* [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating
@ 2019-01-08 15:12 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:12 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
New in this version:
* Final tweaks based on review feedback.
Lionel Landwerlin (1):
tests/gem_ctx_sseu: Dynamic (sub)slice programming tests
Tony Ye (2):
tests/gem_media_vme: Simple test to exercise the VME block
tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on
ICL
Tvrtko Ursulin (1):
headers: bump
include/drm-uapi/drm_fourcc.h | 2 +-
include/drm-uapi/drm_mode.h | 19 +
include/drm-uapi/i915_drm.h | 43 ++
include/drm-uapi/msm_drm.h | 25 +-
include/drm-uapi/v3d_drm.h | 33 ++
lib/gpu_cmds.c | 148 ++++++
lib/gpu_cmds.h | 23 +-
lib/i915/shaders/media/README_media_vme.txt | 65 +++
lib/i915/shaders/media/media_vme.gxa | 51 ++
lib/intel_batchbuffer.c | 9 +
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.am | 1 +
tests/Makefile.sources | 6 +
tests/i915/gem_ctx_param.c | 4 +-
tests/i915/gem_ctx_sseu.c | 541 ++++++++++++++++++++
tests/i915/gem_media_vme.c | 177 +++++++
tests/meson.build | 9 +
20 files changed, 1271 insertions(+), 10 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_ctx_sseu.c
create mode 100644 tests/i915/gem_media_vme.c
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating
@ 2019-01-08 15:12 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:12 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
New in this version:
* Final tweaks based on review feedback.
Lionel Landwerlin (1):
tests/gem_ctx_sseu: Dynamic (sub)slice programming tests
Tony Ye (2):
tests/gem_media_vme: Simple test to exercise the VME block
tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on
ICL
Tvrtko Ursulin (1):
headers: bump
include/drm-uapi/drm_fourcc.h | 2 +-
include/drm-uapi/drm_mode.h | 19 +
include/drm-uapi/i915_drm.h | 43 ++
include/drm-uapi/msm_drm.h | 25 +-
include/drm-uapi/v3d_drm.h | 33 ++
lib/gpu_cmds.c | 148 ++++++
lib/gpu_cmds.h | 23 +-
lib/i915/shaders/media/README_media_vme.txt | 65 +++
lib/i915/shaders/media/media_vme.gxa | 51 ++
lib/intel_batchbuffer.c | 9 +
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.am | 1 +
tests/Makefile.sources | 6 +
tests/i915/gem_ctx_param.c | 4 +-
tests/i915/gem_ctx_sseu.c | 541 ++++++++++++++++++++
tests/i915/gem_media_vme.c | 177 +++++++
tests/meson.build | 9 +
20 files changed, 1271 insertions(+), 10 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_ctx_sseu.c
create mode 100644 tests/i915/gem_media_vme.c
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH i-g-t 1/4] headers: bump
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
@ 2019-01-08 15:13 ` Tvrtko Ursulin
-1 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Sync with latest drm headers from drm-tip.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
---
include/drm-uapi/drm_fourcc.h | 2 +-
include/drm-uapi/drm_mode.h | 19 ++++++++++++++++
include/drm-uapi/i915_drm.h | 43 +++++++++++++++++++++++++++++++++++
include/drm-uapi/msm_drm.h | 25 +++++++++++++++-----
include/drm-uapi/v3d_drm.h | 33 +++++++++++++++++++++++++++
5 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 4ddf754bab09..0b44260a5ee9 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -151,7 +151,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* packed YCbCr420 2x2 tiled formats
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index d3e0fe31efc5..a439c2e67896 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -888,6 +888,25 @@ struct drm_mode_revoke_lease {
__u32 lessee_id;
};
+/**
+ * struct drm_mode_rect - Two dimensional rectangle.
+ * @x1: Horizontal starting coordinate (inclusive).
+ * @y1: Vertical starting coordinate (inclusive).
+ * @x2: Horizontal ending coordinate (exclusive).
+ * @y2: Vertical ending coordinate (exclusive).
+ *
+ * With drm subsystem using struct drm_rect to manage rectangular area this
+ * export it to user-space.
+ *
+ * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.
+ */
+struct drm_mode_rect {
+ __s32 x1;
+ __s32 y1;
+ __s32 x2;
+ __s32 y2;
+};
+
#if defined(__cplusplus)
}
#endif
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index e39b26d4bb3d..bc658583a2b1 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1486,9 +1486,52 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
+ /*
+ * When using the following param, value should be a pointer to
+ * drm_i915_gem_context_param_sseu.
+ */
+#define I915_CONTEXT_PARAM_SSEU 0x7
__u64 value;
};
+struct drm_i915_gem_context_param_sseu {
+ /*
+ * Engine class & instance to be configured or queried.
+ */
+ __u16 class;
+ __u16 instance;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 flags;
+
+ /*
+ * Mask of slices to enable for the context. Valid values are a subset
+ * of the bitmask value returned for I915_PARAM_SLICE_MASK.
+ */
+ __u64 slice_mask;
+
+ /*
+ * Mask of subslices to enable for the context. Valid values are a
+ * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
+ */
+ __u64 subslice_mask;
+
+ /*
+ * Minimum/Maximum number of EUs to enable per subslice for the
+ * context. min_eus_per_subslice must be inferior or equal to
+ * max_eus_per_subslice.
+ */
+ __u16 min_eus_per_subslice;
+ __u16 max_eus_per_subslice;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 rsvd;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h
index c06d0a5bdd80..91a16b333c69 100644
--- a/include/drm-uapi/msm_drm.h
+++ b/include/drm-uapi/msm_drm.h
@@ -105,14 +105,24 @@ struct drm_msm_gem_new {
__u32 handle; /* out */
};
-#define MSM_INFO_IOVA 0x01
-
-#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
+/* Get or set GEM buffer info. The requested value can be passed
+ * directly in 'value', or for data larger than 64b 'value' is a
+ * pointer to userspace buffer, with 'len' specifying the number of
+ * bytes copied into that buffer. For info returned by pointer,
+ * calling the GEM_INFO ioctl with null 'value' will return the
+ * required buffer size in 'len'
+ */
+#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
+#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
+#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
+#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
struct drm_msm_gem_info {
__u32 handle; /* in */
- __u32 flags; /* in - combination of MSM_INFO_* flags */
- __u64 offset; /* out, mmap() offset or iova */
+ __u32 info; /* in - one of MSM_INFO_* */
+ __u64 value; /* in or out */
+ __u32 len; /* in or out */
+ __u32 pad;
};
#define MSM_PREP_READ 0x01
@@ -188,8 +198,11 @@ struct drm_msm_gem_submit_cmd {
*/
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE 0x0002
+#define MSM_SUBMIT_BO_DUMP 0x0004
-#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
+#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
+ MSM_SUBMIT_BO_WRITE | \
+ MSM_SUBMIT_BO_DUMP)
struct drm_msm_gem_submit_bo {
__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h
index b1e5de076b0f..ea70669d2138 100644
--- a/include/drm-uapi/v3d_drm.h
+++ b/include/drm-uapi/v3d_drm.h
@@ -36,6 +36,7 @@ extern "C" {
#define DRM_V3D_MMAP_BO 0x03
#define DRM_V3D_GET_PARAM 0x04
#define DRM_V3D_GET_BO_OFFSET 0x05
+#define DRM_V3D_SUBMIT_TFU 0x06
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -43,6 +44,7 @@ extern "C" {
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
+#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -50,6 +52,14 @@ extern "C" {
*
* This asks the kernel to have the GPU execute an optional binner
* command list, and a render command list.
+ *
+ * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
+ * each CL executes. The VCD cache should be flushed (if necessary)
+ * by the submitted CLs. The TLB writes are guaranteed to have been
+ * flushed by the time the render done IRQ happens, which is the
+ * trigger for out_sync. Any dirtying of cachelines by the job (only
+ * possible using TMU writes) must be flushed by the caller using the
+ * CL's cache flush commands.
*/
struct drm_v3d_submit_cl {
/* Pointer to the binner command list.
@@ -179,6 +189,7 @@ enum drm_v3d_param {
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
+ DRM_V3D_PARAM_SUPPORTS_TFU,
};
struct drm_v3d_get_param {
@@ -197,6 +208,28 @@ struct drm_v3d_get_bo_offset {
__u32 offset;
};
+struct drm_v3d_submit_tfu {
+ __u32 icfg;
+ __u32 iia;
+ __u32 iis;
+ __u32 ica;
+ __u32 iua;
+ __u32 ioa;
+ __u32 ios;
+ __u32 coef[4];
+ /* First handle is the output BO, following are other inputs.
+ * 0 for unused.
+ */
+ __u32 bo_handles[4];
+ /* sync object to block on before running the TFU job. Each TFU
+ * job will execute in the order submitted to its FD. Synchronization
+ * against rendering jobs requires using sync objects.
+ */
+ __u32 in_sync;
+ /* Sync object to signal when the TFU job is done. */
+ __u32 out_sync;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 1/4] headers: bump
@ 2019-01-08 15:13 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Sync with latest drm headers from drm-tip.
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
---
include/drm-uapi/drm_fourcc.h | 2 +-
include/drm-uapi/drm_mode.h | 19 ++++++++++++++++
include/drm-uapi/i915_drm.h | 43 +++++++++++++++++++++++++++++++++++
include/drm-uapi/msm_drm.h | 25 +++++++++++++++-----
include/drm-uapi/v3d_drm.h | 33 +++++++++++++++++++++++++++
5 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 4ddf754bab09..0b44260a5ee9 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -151,7 +151,7 @@ extern "C" {
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
/*
* packed YCbCr420 2x2 tiled formats
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index d3e0fe31efc5..a439c2e67896 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -888,6 +888,25 @@ struct drm_mode_revoke_lease {
__u32 lessee_id;
};
+/**
+ * struct drm_mode_rect - Two dimensional rectangle.
+ * @x1: Horizontal starting coordinate (inclusive).
+ * @y1: Vertical starting coordinate (inclusive).
+ * @x2: Horizontal ending coordinate (exclusive).
+ * @y2: Vertical ending coordinate (exclusive).
+ *
+ * With drm subsystem using struct drm_rect to manage rectangular area this
+ * export it to user-space.
+ *
+ * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.
+ */
+struct drm_mode_rect {
+ __s32 x1;
+ __s32 y1;
+ __s32 x2;
+ __s32 y2;
+};
+
#if defined(__cplusplus)
}
#endif
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index e39b26d4bb3d..bc658583a2b1 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1486,9 +1486,52 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
+ /*
+ * When using the following param, value should be a pointer to
+ * drm_i915_gem_context_param_sseu.
+ */
+#define I915_CONTEXT_PARAM_SSEU 0x7
__u64 value;
};
+struct drm_i915_gem_context_param_sseu {
+ /*
+ * Engine class & instance to be configured or queried.
+ */
+ __u16 class;
+ __u16 instance;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 flags;
+
+ /*
+ * Mask of slices to enable for the context. Valid values are a subset
+ * of the bitmask value returned for I915_PARAM_SLICE_MASK.
+ */
+ __u64 slice_mask;
+
+ /*
+ * Mask of subslices to enable for the context. Valid values are a
+ * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
+ */
+ __u64 subslice_mask;
+
+ /*
+ * Minimum/Maximum number of EUs to enable per subslice for the
+ * context. min_eus_per_subslice must be inferior or equal to
+ * max_eus_per_subslice.
+ */
+ __u16 min_eus_per_subslice;
+ __u16 max_eus_per_subslice;
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 rsvd;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h
index c06d0a5bdd80..91a16b333c69 100644
--- a/include/drm-uapi/msm_drm.h
+++ b/include/drm-uapi/msm_drm.h
@@ -105,14 +105,24 @@ struct drm_msm_gem_new {
__u32 handle; /* out */
};
-#define MSM_INFO_IOVA 0x01
-
-#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
+/* Get or set GEM buffer info. The requested value can be passed
+ * directly in 'value', or for data larger than 64b 'value' is a
+ * pointer to userspace buffer, with 'len' specifying the number of
+ * bytes copied into that buffer. For info returned by pointer,
+ * calling the GEM_INFO ioctl with null 'value' will return the
+ * required buffer size in 'len'
+ */
+#define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
+#define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
+#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
+#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
struct drm_msm_gem_info {
__u32 handle; /* in */
- __u32 flags; /* in - combination of MSM_INFO_* flags */
- __u64 offset; /* out, mmap() offset or iova */
+ __u32 info; /* in - one of MSM_INFO_* */
+ __u64 value; /* in or out */
+ __u32 len; /* in or out */
+ __u32 pad;
};
#define MSM_PREP_READ 0x01
@@ -188,8 +198,11 @@ struct drm_msm_gem_submit_cmd {
*/
#define MSM_SUBMIT_BO_READ 0x0001
#define MSM_SUBMIT_BO_WRITE 0x0002
+#define MSM_SUBMIT_BO_DUMP 0x0004
-#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
+#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
+ MSM_SUBMIT_BO_WRITE | \
+ MSM_SUBMIT_BO_DUMP)
struct drm_msm_gem_submit_bo {
__u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h
index b1e5de076b0f..ea70669d2138 100644
--- a/include/drm-uapi/v3d_drm.h
+++ b/include/drm-uapi/v3d_drm.h
@@ -36,6 +36,7 @@ extern "C" {
#define DRM_V3D_MMAP_BO 0x03
#define DRM_V3D_GET_PARAM 0x04
#define DRM_V3D_GET_BO_OFFSET 0x05
+#define DRM_V3D_SUBMIT_TFU 0x06
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
@@ -43,6 +44,7 @@ extern "C" {
#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
+#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
/**
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
@@ -50,6 +52,14 @@ extern "C" {
*
* This asks the kernel to have the GPU execute an optional binner
* command list, and a render command list.
+ *
+ * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
+ * each CL executes. The VCD cache should be flushed (if necessary)
+ * by the submitted CLs. The TLB writes are guaranteed to have been
+ * flushed by the time the render done IRQ happens, which is the
+ * trigger for out_sync. Any dirtying of cachelines by the job (only
+ * possible using TMU writes) must be flushed by the caller using the
+ * CL's cache flush commands.
*/
struct drm_v3d_submit_cl {
/* Pointer to the binner command list.
@@ -179,6 +189,7 @@ enum drm_v3d_param {
DRM_V3D_PARAM_V3D_CORE0_IDENT0,
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
+ DRM_V3D_PARAM_SUPPORTS_TFU,
};
struct drm_v3d_get_param {
@@ -197,6 +208,28 @@ struct drm_v3d_get_bo_offset {
__u32 offset;
};
+struct drm_v3d_submit_tfu {
+ __u32 icfg;
+ __u32 iia;
+ __u32 iis;
+ __u32 ica;
+ __u32 iua;
+ __u32 ioa;
+ __u32 ios;
+ __u32 coef[4];
+ /* First handle is the output BO, following are other inputs.
+ * 0 for unused.
+ */
+ __u32 bo_handles[4];
+ /* sync object to block on before running the TFU job. Each TFU
+ * job will execute in the order submitted to its FD. Synchronization
+ * against rendering jobs requires using sync objects.
+ */
+ __u32 in_sync;
+ /* Sync object to signal when the TFU job is done. */
+ __u32 out_sync;
+};
+
#if defined(__cplusplus)
}
#endif
--
2.19.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH i-g-t 2/4] tests/gem_ctx_sseu: Dynamic (sub)slice programming tests
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
@ 2019-01-08 15:13 ` Tvrtko Ursulin
-1 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Verify that the per-context dynamic SSEU uAPI works as expected.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
v3: Rename to gem_ctx_rpcs (Lionel)
v4: Update kernel API (Lionel)
Add 0 value test (Lionel)
Exercise invalid values (Lionel)
v5: Add perf tests (Lionel)
v6: Add new sysfs entry tests (Lionel)
v7: Test rsvd fields
Update for kernel series changes
v8: Drop test_no_sseu_support() test (Kelvin)
Drop drm_intel_*() apis (Chris)
v9: by Chris:
Drop all do_ioctl/do_ioctl_err()
Use gem_context_[gs]et_param()
Use gem_read() instead of mapping memory
by Lionel:
Test dynamic sseu on/off more
Tvrtko Ursulin:
v10:
* Various style tweaks and refactorings.
* New test coverage.
v11:
* Change platform support to just Gen11.
* Simplify availability test. (Chris Wilson)
* More invalid pointer tests. (Chris Wilson)
v12:
* Fix MAP_FIXED use (doh!).
* Fix get/set copy&paste errors.
* Drop supported platform test. (Chris Wilson)
* Add mmap__gtt test. (Chris Wilson)
v13:
* Commit message tweaks.
* Added reset/hang/suspend tests. (Chris Wilson)
* Assert spinner is busy. (Chris Wilson)
* Remove some more ABI assumptions. (Chris Wilson)
v14:
* Use default resume time. (Chris Wilson)
* Trigger hang after rpcs read batch has been submitted. (Chris Wilson)
v15:
* Adjust for uAPI restrictions.
v16:
* Build system changes.
v17:
* Remove all subtests which read the RPCS register. (Joonas Lahtinen)
v18:
* Tidy curly braces. (Joonas Lahtinen)
v19:
* Check flags/rsvd MBZ.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v14
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/Makefile.am | 1 +
tests/Makefile.sources | 3 +
tests/i915/gem_ctx_param.c | 4 +-
tests/i915/gem_ctx_sseu.c | 541 +++++++++++++++++++++++++++++++++++++
tests/meson.build | 8 +
5 files changed, 556 insertions(+), 1 deletion(-)
create mode 100644 tests/i915/gem_ctx_sseu.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 48d77535b6bd..42463bde7f30 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -111,6 +111,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_capture_LDADD = $(LDADD) -lz
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index eedde1e817cb..3dfeb5b67274 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -161,6 +161,9 @@ gem_ctx_isolation_SOURCES = i915/gem_ctx_isolation.c
TESTS_progs += gem_ctx_param
gem_ctx_param_SOURCES = i915/gem_ctx_param.c
+TESTS_progs += gem_ctx_sseu
+gem_ctx_sseu_SOURCES = i915/gem_ctx_sseu.c
+
TESTS_progs += gem_ctx_switch
gem_ctx_switch_SOURCES = i915/gem_ctx_switch.c
diff --git a/tests/i915/gem_ctx_param.c b/tests/i915/gem_ctx_param.c
index 0bbc5effbf9f..acc1e6297750 100644
--- a/tests/i915/gem_ctx_param.c
+++ b/tests/i915/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
set_priority(fd);
}
+ /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first.
*/
- arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+ arg.param = I915_CONTEXT_PARAM_SSEU + 1;
igt_subtest("invalid-param-get") {
arg.ctx_id = ctx;
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
new file mode 100644
index 000000000000..52600a928693
--- /dev/null
+++ b/tests/i915/gem_ctx_sseu.c
@@ -0,0 +1,541 @@
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+ *
+ */
+
+#include "igt.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <errno.h>
+#include <time.h>
+#include <sys/mman.h>
+#include <sys/wait.h>
+
+#include "igt_dummyload.h"
+#include "igt_perf.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test context render powergating programming.");
+
+static unsigned int __intel_gen__, __intel_devid__;
+static uint64_t __slice_mask__, __subslice_mask__;
+static unsigned int __slice_count__, __subslice_count__;
+
+static uint64_t mask_minus_one(uint64_t mask)
+{
+ unsigned int i;
+
+ for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+ if ((1ULL << i) & mask)
+ return mask & ~(1ULL << i);
+ }
+
+ igt_assert(0);
+ return 0;
+}
+
+static uint64_t mask_plus_one(uint64_t mask)
+{
+ unsigned int i;
+
+ for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+ if (((1ULL << i) & mask) == 0)
+ return mask | (1ULL << i);
+ }
+
+ igt_assert(0);
+ return 0;
+}
+
+static uint64_t mask_minus(uint64_t mask, int n)
+{
+ unsigned int i;
+
+ for (i = 0; i < n; i++)
+ mask = mask_minus_one(mask);
+
+ return mask;
+}
+
+static uint64_t mask_plus(uint64_t mask, int n)
+{
+ unsigned int i;
+
+ for (i = 0; i < n; i++)
+ mask = mask_plus_one(mask);
+
+ return mask;
+}
+
+static bool
+kernel_has_per_context_sseu_support(int fd)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu),
+ };
+ int ret;
+
+ if (__gem_context_get_param(fd, &arg))
+ return false;
+
+ arg.value = to_user_pointer(&sseu);
+
+ ret = __gem_context_set_param(fd, &arg);
+
+ igt_assert(ret == 0 || ret == -ENODEV || ret == -EINVAL);
+
+ return ret == 0;
+}
+
+static bool has_engine(int fd, unsigned int class, unsigned int instance)
+{
+ int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+
+ if (pmu >= 0)
+ close(pmu);
+
+ return pmu >= 0;
+}
+
+/*
+ * Verify that invalid engines are rejected and valid ones are accepted.
+ */
+static void test_engines(int fd)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu)
+ };
+ unsigned int class, instance;
+ int last_with_engines;
+
+ /* get_param */
+
+ sseu.instance = -1; /* Assumed invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ sseu.class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ sseu.instance = 0; /* Class invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+ sseu.class = I915_ENGINE_CLASS_RENDER;
+
+ last_with_engines = -1;
+ for (class = 0; class < ~0; class++) {
+ for (instance = 0; instance < ~0; instance++) {
+ int ret;
+
+ sseu.class = class;
+ sseu.instance = instance;
+
+ ret = __gem_context_get_param(fd, &arg);
+
+ if (has_engine(fd, class, instance)) {
+ igt_assert_eq(ret, 0);
+ last_with_engines = class;
+ } else {
+ igt_assert_eq(ret, -EINVAL);
+ if (instance > 8) /* Skip over some instance holes. */
+ break;
+ }
+ }
+
+ if (class - last_with_engines > 8) /* Skip over some class holes. */
+ break;
+ }
+
+ /*
+ * Get some proper values before trying to reprogram them onto
+ * an invalid engine.
+ */
+ sseu.class = 0;
+ sseu.instance = 0;
+ gem_context_get_param(fd, &arg);
+
+ /* set_param */
+
+ sseu.instance = -1; /* Assumed invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu.class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu.instance = 0; /* Class invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ last_with_engines = -1;
+ for (class = 0; class < ~0; class++) {
+ for (instance = 0; instance < ~0; instance++) {
+ int ret;
+
+ sseu.class = class;
+ sseu.instance = instance;
+
+ ret = __gem_context_set_param(fd, &arg);
+
+ if (has_engine(fd, class, instance)) {
+ igt_assert(ret == 0 || ret == -ENODEV);
+ last_with_engines = class;
+ } else {
+ igt_assert_eq(ret, -EINVAL);
+ if (instance > 8) /* Skip over some instance holes. */
+ break;
+ }
+ }
+
+ if (class - last_with_engines > 8) /* Skip over some class holes. */
+ break;
+ }
+
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that invalid arguments are rejected.
+ */
+static void
+test_invalid_args(int fd)
+{
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ };
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ unsigned char *page[2];
+ unsigned char *addr;
+ unsigned int sz;
+
+ /* get param */
+
+ /* Invalid size. */
+ arg.size = 1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ /* Query size. */
+ arg.size = 0;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+ sz = arg.size;
+
+ /* Bad pointers. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ arg.value = -1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ arg.value = 1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+
+ /* Unmapped. */
+ page[0] = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ munmap(page[0], 4096);
+ arg.value = to_user_pointer(page[0]);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+
+ /* Straddle into unmapped area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ memset(page[1], 0, sizeof(sseu));
+ munmap(page[1], 4096);
+ arg.value = to_user_pointer(page[1]) -
+ sizeof(struct drm_i915_gem_context_param_sseu) + 4;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+
+ /* Straddle into read-only area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ memset(page[1], 0, sizeof(sseu));
+ igt_assert(mprotect(page[1], 4096, PROT_READ) == 0);
+ arg.value = to_user_pointer(page[1] - sizeof(sseu) + 4);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+ munmap(page[1], 4096);
+
+ /* set param */
+
+ /* Invalid sizes. */
+ arg.size = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ arg.size = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ arg.size = sz;
+
+ /* Bad pointers. */
+ arg.value = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ arg.value = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ arg.value = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+
+ /* Get valid SSEU. */
+ arg.value = to_user_pointer(&sseu);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+
+ /* Invalid MBZ. */
+ sseu.flags = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.rsvd = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.flags = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.rsvd = 0;
+
+ /* Unmapped. */
+ page[0] = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memcpy(page[0], &sseu, sizeof(sseu));
+ munmap(page[0], 4096);
+ arg.value = to_user_pointer(page[0]);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+
+ /* Straddle into unmapped area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ addr = page[1] - sizeof(sseu) + 4;
+ memcpy(addr, &sseu, sizeof(sseu));
+ munmap(page[1], 4096);
+ arg.value = to_user_pointer(addr);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that ggtt mapped area can be used as the sseu pointer.
+ */
+static void
+test_ggtt_args(int fd)
+{
+ struct drm_i915_gem_context_param_sseu *sseu;
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(*sseu),
+ };
+ uint32_t bo;
+
+ bo = gem_create(fd, 4096);
+ arg.value = to_user_pointer(gem_mmap__gtt(fd, bo, 4096,
+ PROT_READ | PROT_WRITE));
+
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), 0);
+
+ munmap((void *)arg.value, 4096);
+ gem_close(fd, bo);
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that invalid SSEU values are rejected.
+ */
+static void
+test_invalid_sseu(int fd)
+{
+ struct drm_i915_gem_context_param_sseu device_sseu = { };
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(sseu),
+ };
+ unsigned int i;
+
+ /* Fetch the device defaults. */
+ arg.value = to_user_pointer(&device_sseu);
+ gem_context_get_param(fd, &arg);
+
+ arg.value = to_user_pointer(&sseu);
+
+ /* Try all slice masks known to be invalid. */
+ sseu = device_sseu;
+ for (i = 1; i <= (8 - __slice_count__); i++) {
+ sseu.slice_mask = mask_plus(__slice_mask__, i);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* 0 slices. */
+ sseu.slice_mask = 0;
+ igt_assert_eq(-EINVAL, __gem_context_set_param(fd, &arg));
+
+ /* Try all subslice masks known to be invalid. */
+ sseu = device_sseu;
+ for (i = 1; i <= (8 - __subslice_count__); i++) {
+ sseu.subslice_mask = mask_plus(__subslice_mask__, i);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* 0 subslices. */
+ sseu.subslice_mask = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Try number of EUs superior to the max available. */
+ sseu = device_sseu;
+ sseu.min_eus_per_subslice = device_sseu.max_eus_per_subslice + 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu = device_sseu;
+ sseu.max_eus_per_subslice = device_sseu.max_eus_per_subslice + 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Try to program 0 max EUs. */
+ sseu = device_sseu;
+ sseu.max_eus_per_subslice = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Min > max */
+ sseu = device_sseu;
+ sseu.min_eus_per_subslice = sseu.max_eus_per_subslice;
+ sseu.max_eus_per_subslice = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ if (__intel_gen__ != 11)
+ goto out;
+
+ /* Subset of subslices but slice mask greater than one. */
+ if (__slice_count__ > 1) {
+ sseu = device_sseu;
+ sseu.subslice_mask = mask_minus_one(sseu.subslice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* Odd subslices above four. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus_one(sseu.subslice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* More than half subslices with one slice. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus(sseu.subslice_mask,
+ __subslice_count__ / 2 - 1);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* VME */
+
+ /* Slice count between one and max. */
+ if (__slice_count__ > 2) {
+ sseu = device_sseu;
+ sseu.slice_mask = mask_minus_one(sseu.slice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* Less than half subslices with one slice. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus(sseu.subslice_mask,
+ __subslice_count__ / 2 + 1);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+out:
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+igt_main
+{
+ int fd;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+
+ __intel_devid__ = intel_get_drm_devid(fd);
+ __intel_gen__ = intel_gen(__intel_devid__);
+
+ igt_require(kernel_has_per_context_sseu_support(fd));
+ }
+
+ igt_subtest_group {
+ igt_fixture {
+ drm_i915_getparam_t gp;
+
+ gp.param = I915_PARAM_SLICE_MASK;
+ gp.value = (int *) &__slice_mask__;
+ do_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ __slice_count__ = __builtin_popcount(__slice_mask__);
+
+ gp.param = I915_PARAM_SUBSLICE_MASK;
+ gp.value = (int *) &__subslice_mask__;
+ do_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ __subslice_count__ =
+ __builtin_popcount(__subslice_mask__);
+ }
+
+ igt_subtest("invalid-args")
+ test_invalid_args(fd);
+
+ igt_subtest("invalid-sseu")
+ test_invalid_sseu(fd);
+
+ igt_subtest("ggtt-args")
+ test_ggtt_args(fd);
+
+ igt_subtest("engines")
+ test_engines(fd);
+ }
+
+ igt_fixture {
+ close(fd);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index b8a6e61b3404..f41f724af8af 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -288,6 +288,14 @@ foreach prog : gem_progs + gen3_progs
test_list += prog
endforeach
+test_executables += executable('gem_ctx_sseu',
+ join_paths('i915', 'gem_ctx_sseu.c'),
+ dependencies : test_deps + [ lib_igt_perf ],
+ install_dir : libexecdir,
+ install_rpath : libexecdir_rpathdir,
+ install : true)
+test_progs += 'gem_ctx_sseu'
+
test_executables += executable('gem_eio',
join_paths('i915', 'gem_eio.c'),
dependencies : test_deps + [ realtime ],
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 2/4] tests/gem_ctx_sseu: Dynamic (sub)slice programming tests
@ 2019-01-08 15:13 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx, Tvrtko Ursulin
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Verify that the per-context dynamic SSEU uAPI works as expected.
v2: Add subslice tests (Lionel)
Use MI_SET_PREDICATE for further verification when available (Lionel)
v3: Rename to gem_ctx_rpcs (Lionel)
v4: Update kernel API (Lionel)
Add 0 value test (Lionel)
Exercise invalid values (Lionel)
v5: Add perf tests (Lionel)
v6: Add new sysfs entry tests (Lionel)
v7: Test rsvd fields
Update for kernel series changes
v8: Drop test_no_sseu_support() test (Kelvin)
Drop drm_intel_*() apis (Chris)
v9: by Chris:
Drop all do_ioctl/do_ioctl_err()
Use gem_context_[gs]et_param()
Use gem_read() instead of mapping memory
by Lionel:
Test dynamic sseu on/off more
Tvrtko Ursulin:
v10:
* Various style tweaks and refactorings.
* New test coverage.
v11:
* Change platform support to just Gen11.
* Simplify availability test. (Chris Wilson)
* More invalid pointer tests. (Chris Wilson)
v12:
* Fix MAP_FIXED use (doh!).
* Fix get/set copy&paste errors.
* Drop supported platform test. (Chris Wilson)
* Add mmap__gtt test. (Chris Wilson)
v13:
* Commit message tweaks.
* Added reset/hang/suspend tests. (Chris Wilson)
* Assert spinner is busy. (Chris Wilson)
* Remove some more ABI assumptions. (Chris Wilson)
v14:
* Use default resume time. (Chris Wilson)
* Trigger hang after rpcs read batch has been submitted. (Chris Wilson)
v15:
* Adjust for uAPI restrictions.
v16:
* Build system changes.
v17:
* Remove all subtests which read the RPCS register. (Joonas Lahtinen)
v18:
* Tidy curly braces. (Joonas Lahtinen)
v19:
* Check flags/rsvd MBZ.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v14
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/Makefile.am | 1 +
tests/Makefile.sources | 3 +
tests/i915/gem_ctx_param.c | 4 +-
tests/i915/gem_ctx_sseu.c | 541 +++++++++++++++++++++++++++++++++++++
tests/meson.build | 8 +
5 files changed, 556 insertions(+), 1 deletion(-)
create mode 100644 tests/i915/gem_ctx_sseu.c
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 48d77535b6bd..42463bde7f30 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -111,6 +111,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_close_race_LDADD = $(LDADD) -lpthread
gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_ctx_thrash_LDADD = $(LDADD) -lpthread
+gem_ctx_sseu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_exec_capture_LDADD = $(LDADD) -lz
gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_exec_parallel_LDADD = $(LDADD) -lpthread
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index eedde1e817cb..3dfeb5b67274 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -161,6 +161,9 @@ gem_ctx_isolation_SOURCES = i915/gem_ctx_isolation.c
TESTS_progs += gem_ctx_param
gem_ctx_param_SOURCES = i915/gem_ctx_param.c
+TESTS_progs += gem_ctx_sseu
+gem_ctx_sseu_SOURCES = i915/gem_ctx_sseu.c
+
TESTS_progs += gem_ctx_switch
gem_ctx_switch_SOURCES = i915/gem_ctx_switch.c
diff --git a/tests/i915/gem_ctx_param.c b/tests/i915/gem_ctx_param.c
index 0bbc5effbf9f..acc1e6297750 100644
--- a/tests/i915/gem_ctx_param.c
+++ b/tests/i915/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
set_priority(fd);
}
+ /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first.
*/
- arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+ arg.param = I915_CONTEXT_PARAM_SSEU + 1;
igt_subtest("invalid-param-get") {
arg.ctx_id = ctx;
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
new file mode 100644
index 000000000000..52600a928693
--- /dev/null
+++ b/tests/i915/gem_ctx_sseu.c
@@ -0,0 +1,541 @@
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+ *
+ */
+
+#include "igt.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <errno.h>
+#include <time.h>
+#include <sys/mman.h>
+#include <sys/wait.h>
+
+#include "igt_dummyload.h"
+#include "igt_perf.h"
+#include "igt_sysfs.h"
+#include "ioctl_wrappers.h"
+
+IGT_TEST_DESCRIPTION("Test context render powergating programming.");
+
+static unsigned int __intel_gen__, __intel_devid__;
+static uint64_t __slice_mask__, __subslice_mask__;
+static unsigned int __slice_count__, __subslice_count__;
+
+static uint64_t mask_minus_one(uint64_t mask)
+{
+ unsigned int i;
+
+ for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+ if ((1ULL << i) & mask)
+ return mask & ~(1ULL << i);
+ }
+
+ igt_assert(0);
+ return 0;
+}
+
+static uint64_t mask_plus_one(uint64_t mask)
+{
+ unsigned int i;
+
+ for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+ if (((1ULL << i) & mask) == 0)
+ return mask | (1ULL << i);
+ }
+
+ igt_assert(0);
+ return 0;
+}
+
+static uint64_t mask_minus(uint64_t mask, int n)
+{
+ unsigned int i;
+
+ for (i = 0; i < n; i++)
+ mask = mask_minus_one(mask);
+
+ return mask;
+}
+
+static uint64_t mask_plus(uint64_t mask, int n)
+{
+ unsigned int i;
+
+ for (i = 0; i < n; i++)
+ mask = mask_plus_one(mask);
+
+ return mask;
+}
+
+static bool
+kernel_has_per_context_sseu_support(int fd)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu),
+ };
+ int ret;
+
+ if (__gem_context_get_param(fd, &arg))
+ return false;
+
+ arg.value = to_user_pointer(&sseu);
+
+ ret = __gem_context_set_param(fd, &arg);
+
+ igt_assert(ret == 0 || ret == -ENODEV || ret == -EINVAL);
+
+ return ret == 0;
+}
+
+static bool has_engine(int fd, unsigned int class, unsigned int instance)
+{
+ int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+
+ if (pmu >= 0)
+ close(pmu);
+
+ return pmu >= 0;
+}
+
+/*
+ * Verify that invalid engines are rejected and valid ones are accepted.
+ */
+static void test_engines(int fd)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu)
+ };
+ unsigned int class, instance;
+ int last_with_engines;
+
+ /* get_param */
+
+ sseu.instance = -1; /* Assumed invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ sseu.class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ sseu.instance = 0; /* Class invalid. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+ sseu.class = I915_ENGINE_CLASS_RENDER;
+
+ last_with_engines = -1;
+ for (class = 0; class < ~0; class++) {
+ for (instance = 0; instance < ~0; instance++) {
+ int ret;
+
+ sseu.class = class;
+ sseu.instance = instance;
+
+ ret = __gem_context_get_param(fd, &arg);
+
+ if (has_engine(fd, class, instance)) {
+ igt_assert_eq(ret, 0);
+ last_with_engines = class;
+ } else {
+ igt_assert_eq(ret, -EINVAL);
+ if (instance > 8) /* Skip over some instance holes. */
+ break;
+ }
+ }
+
+ if (class - last_with_engines > 8) /* Skip over some class holes. */
+ break;
+ }
+
+ /*
+ * Get some proper values before trying to reprogram them onto
+ * an invalid engine.
+ */
+ sseu.class = 0;
+ sseu.instance = 0;
+ gem_context_get_param(fd, &arg);
+
+ /* set_param */
+
+ sseu.instance = -1; /* Assumed invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu.class = I915_ENGINE_CLASS_INVALID; /* Both invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu.instance = 0; /* Class invalid. */
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ last_with_engines = -1;
+ for (class = 0; class < ~0; class++) {
+ for (instance = 0; instance < ~0; instance++) {
+ int ret;
+
+ sseu.class = class;
+ sseu.instance = instance;
+
+ ret = __gem_context_set_param(fd, &arg);
+
+ if (has_engine(fd, class, instance)) {
+ igt_assert(ret == 0 || ret == -ENODEV);
+ last_with_engines = class;
+ } else {
+ igt_assert_eq(ret, -EINVAL);
+ if (instance > 8) /* Skip over some instance holes. */
+ break;
+ }
+ }
+
+ if (class - last_with_engines > 8) /* Skip over some class holes. */
+ break;
+ }
+
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that invalid arguments are rejected.
+ */
+static void
+test_invalid_args(int fd)
+{
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ };
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ unsigned char *page[2];
+ unsigned char *addr;
+ unsigned int sz;
+
+ /* get param */
+
+ /* Invalid size. */
+ arg.size = 1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EINVAL);
+
+ /* Query size. */
+ arg.size = 0;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+ sz = arg.size;
+
+ /* Bad pointers. */
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ arg.value = -1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ arg.value = 1;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+
+ /* Unmapped. */
+ page[0] = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ munmap(page[0], 4096);
+ arg.value = to_user_pointer(page[0]);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+
+ /* Straddle into unmapped area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ memset(page[1], 0, sizeof(sseu));
+ munmap(page[1], 4096);
+ arg.value = to_user_pointer(page[1]) -
+ sizeof(struct drm_i915_gem_context_param_sseu) + 4;
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+
+ /* Straddle into read-only area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memset(page[0], 0, sizeof(sseu));
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ memset(page[1], 0, sizeof(sseu));
+ igt_assert(mprotect(page[1], 4096, PROT_READ) == 0);
+ arg.value = to_user_pointer(page[1] - sizeof(sseu) + 4);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+ munmap(page[1], 4096);
+
+ /* set param */
+
+ /* Invalid sizes. */
+ arg.size = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ arg.size = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ arg.size = sz;
+
+ /* Bad pointers. */
+ arg.value = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ arg.value = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ arg.value = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+
+ /* Get valid SSEU. */
+ arg.value = to_user_pointer(&sseu);
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+
+ /* Invalid MBZ. */
+ sseu.flags = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.rsvd = -1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.flags = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ sseu.rsvd = 0;
+
+ /* Unmapped. */
+ page[0] = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ memcpy(page[0], &sseu, sizeof(sseu));
+ munmap(page[0], 4096);
+ arg.value = to_user_pointer(page[0]);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+
+ /* Straddle into unmapped area. */
+ page[0] = mmap(0, 8192, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ munmap(page[0], 8192);
+ page[0] = mmap(page[0], 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[0] != MAP_FAILED);
+ page[1] = mmap((void *)((unsigned long)page[0] + 4096), 4096,
+ PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_FIXED, -1, 0);
+ igt_assert(page[1] != MAP_FAILED);
+ addr = page[1] - sizeof(sseu) + 4;
+ memcpy(addr, &sseu, sizeof(sseu));
+ munmap(page[1], 4096);
+ arg.value = to_user_pointer(addr);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EFAULT);
+ munmap(page[0], 4096);
+
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that ggtt mapped area can be used as the sseu pointer.
+ */
+static void
+test_ggtt_args(int fd)
+{
+ struct drm_i915_gem_context_param_sseu *sseu;
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(*sseu),
+ };
+ uint32_t bo;
+
+ bo = gem_create(fd, 4096);
+ arg.value = to_user_pointer(gem_mmap__gtt(fd, bo, 4096,
+ PROT_READ | PROT_WRITE));
+
+ igt_assert_eq(__gem_context_get_param(fd, &arg), 0);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), 0);
+
+ munmap((void *)arg.value, 4096);
+ gem_close(fd, bo);
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+/*
+ * Verify that invalid SSEU values are rejected.
+ */
+static void
+test_invalid_sseu(int fd)
+{
+ struct drm_i915_gem_context_param_sseu device_sseu = { };
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = gem_context_create(fd),
+ .size = sizeof(sseu),
+ };
+ unsigned int i;
+
+ /* Fetch the device defaults. */
+ arg.value = to_user_pointer(&device_sseu);
+ gem_context_get_param(fd, &arg);
+
+ arg.value = to_user_pointer(&sseu);
+
+ /* Try all slice masks known to be invalid. */
+ sseu = device_sseu;
+ for (i = 1; i <= (8 - __slice_count__); i++) {
+ sseu.slice_mask = mask_plus(__slice_mask__, i);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* 0 slices. */
+ sseu.slice_mask = 0;
+ igt_assert_eq(-EINVAL, __gem_context_set_param(fd, &arg));
+
+ /* Try all subslice masks known to be invalid. */
+ sseu = device_sseu;
+ for (i = 1; i <= (8 - __subslice_count__); i++) {
+ sseu.subslice_mask = mask_plus(__subslice_mask__, i);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* 0 subslices. */
+ sseu.subslice_mask = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Try number of EUs superior to the max available. */
+ sseu = device_sseu;
+ sseu.min_eus_per_subslice = device_sseu.max_eus_per_subslice + 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ sseu = device_sseu;
+ sseu.max_eus_per_subslice = device_sseu.max_eus_per_subslice + 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Try to program 0 max EUs. */
+ sseu = device_sseu;
+ sseu.max_eus_per_subslice = 0;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* Min > max */
+ sseu = device_sseu;
+ sseu.min_eus_per_subslice = sseu.max_eus_per_subslice;
+ sseu.max_eus_per_subslice = 1;
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ if (__intel_gen__ != 11)
+ goto out;
+
+ /* Subset of subslices but slice mask greater than one. */
+ if (__slice_count__ > 1) {
+ sseu = device_sseu;
+ sseu.subslice_mask = mask_minus_one(sseu.subslice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* Odd subslices above four. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus_one(sseu.subslice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* More than half subslices with one slice. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus(sseu.subslice_mask,
+ __subslice_count__ / 2 - 1);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+ /* VME */
+
+ /* Slice count between one and max. */
+ if (__slice_count__ > 2) {
+ sseu = device_sseu;
+ sseu.slice_mask = mask_minus_one(sseu.slice_mask);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+ }
+
+ /* Less than half subslices with one slice. */
+ sseu = device_sseu;
+ sseu.slice_mask = 0x1;
+ sseu.subslice_mask = mask_minus(sseu.subslice_mask,
+ __subslice_count__ / 2 + 1);
+ igt_assert_eq(__gem_context_set_param(fd, &arg), -EINVAL);
+
+out:
+ gem_context_destroy(fd, arg.ctx_id);
+}
+
+igt_main
+{
+ int fd;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+
+ __intel_devid__ = intel_get_drm_devid(fd);
+ __intel_gen__ = intel_gen(__intel_devid__);
+
+ igt_require(kernel_has_per_context_sseu_support(fd));
+ }
+
+ igt_subtest_group {
+ igt_fixture {
+ drm_i915_getparam_t gp;
+
+ gp.param = I915_PARAM_SLICE_MASK;
+ gp.value = (int *) &__slice_mask__;
+ do_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ __slice_count__ = __builtin_popcount(__slice_mask__);
+
+ gp.param = I915_PARAM_SUBSLICE_MASK;
+ gp.value = (int *) &__subslice_mask__;
+ do_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ __subslice_count__ =
+ __builtin_popcount(__subslice_mask__);
+ }
+
+ igt_subtest("invalid-args")
+ test_invalid_args(fd);
+
+ igt_subtest("invalid-sseu")
+ test_invalid_sseu(fd);
+
+ igt_subtest("ggtt-args")
+ test_ggtt_args(fd);
+
+ igt_subtest("engines")
+ test_engines(fd);
+ }
+
+ igt_fixture {
+ close(fd);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index b8a6e61b3404..f41f724af8af 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -288,6 +288,14 @@ foreach prog : gem_progs + gen3_progs
test_list += prog
endforeach
+test_executables += executable('gem_ctx_sseu',
+ join_paths('i915', 'gem_ctx_sseu.c'),
+ dependencies : test_deps + [ lib_igt_perf ],
+ install_dir : libexecdir,
+ install_rpath : libexecdir_rpathdir,
+ install : true)
+test_progs += 'gem_ctx_sseu'
+
test_executables += executable('gem_eio',
join_paths('i915', 'gem_eio.c'),
dependencies : test_deps + [ realtime ],
--
2.19.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
@ 2019-01-08 15:13 ` Tvrtko Ursulin
-1 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
v6: (Tvrtko Ursulin)
* Replace gem_read with gem_sync. (Chris Wilson)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 117 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 525 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 3dfeb5b67274..6dabb9dbf247 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -302,6 +302,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..8d9fd822b2ee
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+
+ gem_sync(drm_fd, dst.bo->handle);
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index f41f724af8af..e3a4a84ea7cc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -166,6 +166,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
@ 2019-01-08 15:13 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Tony Ye, Intel-gfx, Tvrtko Ursulin
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
v6: (Tvrtko Ursulin)
* Replace gem_read with gem_sync. (Chris Wilson)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 117 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 525 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 3dfeb5b67274..6dabb9dbf247 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -302,6 +302,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..8d9fd822b2ee
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+
+ gem_sync(drm_fd, dst.bo->handle);
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index f41f724af8af..e3a4a84ea7cc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -166,6 +166,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH i-g-t 4/4] tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on ICL
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
@ 2019-01-08 15:13 ` Tvrtko Ursulin
-1 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
On Icelake we need to turn off subslices not containing the VME block or
the VME kernel will hang.
v2: (Tvrtko Ursulin)
* Remove libdrm usage for setting context param.
* Cleanup bitmask operation.
* Only apply the workaround for ICL.
v3: (Tvrtko Ursulin)
* Added hang detector. (Chris Wilson)
v4: (Tvrtko Ursulin)
* Rebase for hang detector moved to previous patch.
* Tidy curly braces.
v5: (Tvrtko Ursulin)
* Whitespace tidy. (Joonas)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 12 ++++++++
lib/gpu_cmds.h | 3 ++
lib/media_fill.c | 2 +-
tests/i915/gem_media_vme.c | 60 ++++++++++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index b490a63bdfef..8d270ee86229 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -36,6 +36,18 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
igt_assert(ret == 0);
}
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+{
+ int ret;
+
+ ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+ if (ret == 0)
+ ret = drm_intel_gem_bo_context_exec(batch->bo, batch->ctx,
+ batch_end, 0);
+ igt_assert(ret == 0);
+}
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color)
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index ca671fb52daf..1321af446161 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -40,6 +40,9 @@
void
gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
diff --git a/lib/media_fill.c b/lib/media_fill.c
index b1e84727394a..03b5e71e101b 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -338,7 +338,7 @@ __gen11_media_vme_func(struct intel_batchbuffer *batch,
batch_end = intel_batchbuffer_align(batch, 8);
assert(batch_end < BATCH_STATE_SPLIT);
- gen7_render_flush(batch, batch_end);
+ gen7_render_context_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
}
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
index 8d9fd822b2ee..d5045ad1d785 100644
--- a/tests/i915/gem_media_vme.c
+++ b/tests/i915/gem_media_vme.c
@@ -81,6 +81,52 @@ static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
buf->stride = 1;
}
+static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n)
+{
+ unsigned int i;
+
+ igt_assert(n > 0 && n <= (sizeof(mask) * 8));
+ igt_assert(n <= __builtin_popcount(mask));
+
+ for (i = 0; n && i < (sizeof(mask) * 8); i++) {
+ uint64_t bit = 1ULL << i;
+
+ if (bit & mask) {
+ mask &= ~bit;
+ n--;
+ }
+ }
+
+ return mask;
+}
+
+static void shut_non_vme_subslices(int drm_fd, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = ctx,
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu),
+ };
+ int ret;
+
+ if (__gem_context_get_param(drm_fd, &arg))
+ return; /* no sseu support */
+
+ ret = __gem_context_set_param(drm_fd, &arg);
+ igt_assert(ret == 0 || ret == -ENODEV || ret == -EINVAL);
+ if (ret)
+ return; /* no sseu support */
+
+ /* shutdown half subslices */
+ sseu.subslice_mask =
+ switch_off_n_bits(sseu.subslice_mask,
+ __builtin_popcount(sseu.subslice_mask) / 2);
+
+ gem_context_set_param(drm_fd, &arg);
+}
+
igt_simple_main
{
int drm_fd;
@@ -107,6 +153,20 @@ igt_simple_main
scratch_buf_init_src(bufmgr, &src);
scratch_buf_init_dst(bufmgr, &dst);
+ batch->ctx = drm_intel_gem_context_create(bufmgr);
+ igt_assert(batch->ctx);
+
+ /* ICL hangs if non-VME enabled slices are enabled with a VME kernel. */
+ if (intel_gen(devid) == 11) {
+ uint32_t ctx_id;
+ int ret;
+
+ ret = drm_intel_gem_context_get_id(batch->ctx, &ctx_id);
+ igt_assert_eq(ret, 0);
+
+ shut_non_vme_subslices(drm_fd, ctx_id);
+ }
+
igt_fork_hang_detector(drm_fd);
media_vme(batch, &src, WIDTH, HEIGHT, &dst);
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 4/4] tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on ICL
@ 2019-01-08 15:13 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 15:13 UTC (permalink / raw)
To: igt-dev; +Cc: Tony Ye, Intel-gfx, Tvrtko Ursulin
From: Tony Ye <tony.ye@intel.com>
On Icelake we need to turn off subslices not containing the VME block or
the VME kernel will hang.
v2: (Tvrtko Ursulin)
* Remove libdrm usage for setting context param.
* Cleanup bitmask operation.
* Only apply the workaround for ICL.
v3: (Tvrtko Ursulin)
* Added hang detector. (Chris Wilson)
v4: (Tvrtko Ursulin)
* Rebase for hang detector moved to previous patch.
* Tidy curly braces.
v5: (Tvrtko Ursulin)
* Whitespace tidy. (Joonas)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 12 ++++++++
lib/gpu_cmds.h | 3 ++
lib/media_fill.c | 2 +-
tests/i915/gem_media_vme.c | 60 ++++++++++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index b490a63bdfef..8d270ee86229 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -36,6 +36,18 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
igt_assert(ret == 0);
}
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+{
+ int ret;
+
+ ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+ if (ret == 0)
+ ret = drm_intel_gem_bo_context_exec(batch->bo, batch->ctx,
+ batch_end, 0);
+ igt_assert(ret == 0);
+}
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color)
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index ca671fb52daf..1321af446161 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -40,6 +40,9 @@
void
gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+void
+gen7_render_context_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
+
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
diff --git a/lib/media_fill.c b/lib/media_fill.c
index b1e84727394a..03b5e71e101b 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -338,7 +338,7 @@ __gen11_media_vme_func(struct intel_batchbuffer *batch,
batch_end = intel_batchbuffer_align(batch, 8);
assert(batch_end < BATCH_STATE_SPLIT);
- gen7_render_flush(batch, batch_end);
+ gen7_render_context_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
}
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
index 8d9fd822b2ee..d5045ad1d785 100644
--- a/tests/i915/gem_media_vme.c
+++ b/tests/i915/gem_media_vme.c
@@ -81,6 +81,52 @@ static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
buf->stride = 1;
}
+static uint64_t switch_off_n_bits(uint64_t mask, unsigned int n)
+{
+ unsigned int i;
+
+ igt_assert(n > 0 && n <= (sizeof(mask) * 8));
+ igt_assert(n <= __builtin_popcount(mask));
+
+ for (i = 0; n && i < (sizeof(mask) * 8); i++) {
+ uint64_t bit = 1ULL << i;
+
+ if (bit & mask) {
+ mask &= ~bit;
+ n--;
+ }
+ }
+
+ return mask;
+}
+
+static void shut_non_vme_subslices(int drm_fd, uint32_t ctx)
+{
+ struct drm_i915_gem_context_param_sseu sseu = { };
+ struct drm_i915_gem_context_param arg = {
+ .param = I915_CONTEXT_PARAM_SSEU,
+ .ctx_id = ctx,
+ .size = sizeof(sseu),
+ .value = to_user_pointer(&sseu),
+ };
+ int ret;
+
+ if (__gem_context_get_param(drm_fd, &arg))
+ return; /* no sseu support */
+
+ ret = __gem_context_set_param(drm_fd, &arg);
+ igt_assert(ret == 0 || ret == -ENODEV || ret == -EINVAL);
+ if (ret)
+ return; /* no sseu support */
+
+ /* shutdown half subslices */
+ sseu.subslice_mask =
+ switch_off_n_bits(sseu.subslice_mask,
+ __builtin_popcount(sseu.subslice_mask) / 2);
+
+ gem_context_set_param(drm_fd, &arg);
+}
+
igt_simple_main
{
int drm_fd;
@@ -107,6 +153,20 @@ igt_simple_main
scratch_buf_init_src(bufmgr, &src);
scratch_buf_init_dst(bufmgr, &dst);
+ batch->ctx = drm_intel_gem_context_create(bufmgr);
+ igt_assert(batch->ctx);
+
+ /* ICL hangs if non-VME enabled slices are enabled with a VME kernel. */
+ if (intel_gen(devid) == 11) {
+ uint32_t ctx_id;
+ int ret;
+
+ ret = drm_intel_gem_context_get_id(batch->ctx, &ctx_id);
+ igt_assert_eq(ret, 0);
+
+ shut_non_vme_subslices(drm_fd, ctx_id);
+ }
+
igt_fork_hang_detector(drm_fd);
media_vme(batch, &src, WIDTH, HEIGHT, &dst);
--
2.19.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for Per context dynamic (sub)slice power-gating (rev11)
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
` (4 preceding siblings ...)
(?)
@ 2019-01-08 15:31 ` Patchwork
-1 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-01-08 15:31 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev11)
URL : https://patchwork.freedesktop.org/series/49190/
State : failure
== Summary ==
Patch is empty.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev12)
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
` (5 preceding siblings ...)
(?)
@ 2019-01-08 17:56 ` Patchwork
-1 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-01-08 17:56 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev12)
URL : https://patchwork.freedesktop.org/series/49190/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5378 -> IGTPW_2202
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_2202 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2202, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/49190/revisions/12/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2202:
### IGT changes ###
#### Warnings ####
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: PASS -> SKIP +36
Known issues
------------
Here are the changes found in IGTPW_2202 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#107341]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_flip@basic-flip-vs-modeset:
- fi-skl-6700hq: PASS -> DMESG-WARN [fdo#105998]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s4-devices:
- fi-bsw-kefka: DMESG-WARN -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: DMESG-FAIL [fdo#109228] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_psr@sprite_plane_onoff:
- fi-skl-6700hq: FAIL [fdo#107383] -> PASS +3
#### Warnings ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: INCOMPLETE [fdo#102657] -> FAIL [fdo#103191] / [fdo#107362]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
[fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108915]: https://bugs.freedesktop.org/show_bug.cgi?id=108915
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109228]: https://bugs.freedesktop.org/show_bug.cgi?id=109228
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
Participating hosts (48 -> 44)
------------------------------
Additional (1): fi-icl-y
Missing (5): fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-cfl-guc
Build changes
-------------
* IGT: IGT_4756 -> IGTPW_2202
CI_DRM_5378: 96b07848e43c024bd6a5a44970371c4866140a1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2202: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2202/
IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_media_vme
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2202/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Per context dynamic (sub)slice power-gating (rev12)
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
` (6 preceding siblings ...)
(?)
@ 2019-01-09 2:28 ` Patchwork
-1 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-01-09 2:28 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
== Series Details ==
Series: Per context dynamic (sub)slice power-gating (rev12)
URL : https://patchwork.freedesktop.org/series/49190/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5378_full -> IGTPW_2202_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/49190/revisions/12/
Known issues
------------
Here are the changes found in IGTPW_2202_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-snb: NOTRUN -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-kbl: NOTRUN -> FAIL [fdo#107725] / [fdo#108145]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145] +1
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-kbl: PASS -> FAIL [fdo#103167] / [fdo#105682]
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@prime_vgem@fence-wait-bsd1:
- shard-snb: NOTRUN -> INCOMPLETE [fdo#105411]
#### Possible fixes ####
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: FAIL [fdo#103232] -> PASS +3
* igt@kms_cursor_crc@cursor-64x21-onscreen:
- shard-glk: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: FAIL [fdo#105454] / [fdo#106509] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: FAIL [fdo#108145] -> PASS
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: FAIL [fdo#108145] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS +3
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-kbl: FAIL [fdo#103166] -> PASS
* igt@kms_setmode@basic:
- shard-glk: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@pm_rps@min-max-config-loaded:
- shard-apl: FAIL [fdo#102250] -> PASS
- shard-glk: FAIL [fdo#102250] -> PASS
#### Warnings ####
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: DMESG-FAIL [fdo#108950] -> DMESG-WARN [fdo#105604]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
[fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#107469]: https://bugs.freedesktop.org/show_bug.cgi?id=107469
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109241]: https://bugs.freedesktop.org/show_bug.cgi?id=109241
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* IGT: IGT_4756 -> IGTPW_2202
* Piglit: piglit_4509 -> None
CI_DRM_5378: 96b07848e43c024bd6a5a44970371c4866140a1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2202: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2202/
IGT_4756: 75081c6bfb9998bd7cbf35a7ac0578c683fe55a8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2202/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-08 15:13 ` [igt-dev] " Tvrtko Ursulin
@ 2019-01-10 14:02 ` Michał Winiarski
-1 siblings, 0 replies; 25+ messages in thread
From: Michał Winiarski @ 2019-01-10 14:02 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx
On Tue, Jan 08, 2019 at 03:13:02PM +0000, Tvrtko Ursulin wrote:
> From: Tony Ye <tony.ye@intel.com>
>
> Simple test which exercises the VME fixed function block.
>
> v2: (Tvrtko Ursulin)
> * Small cleanups like copyright date, tabs, remove unused bits.
>
> v3: (Tony Ye)
> * Added curbe data entry for dst surface.
> * Read the dst surface after the VME kernel being executed.
>
> v4: (Tony Ye)
> * Added the media_vme.gxa kernel source code and compile instructions.
>
> v5: (Tvrtko Ursulin)
> * Added hang detector.
>
> v6: (Tvrtko Ursulin)
> * Replace gem_read with gem_sync. (Chris Wilson)
>
> Signed-off-by: Tony Ye <tony.ye@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> lib/gpu_cmds.c | 136 ++++++++++++++++++++
> lib/gpu_cmds.h | 20 ++-
> lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
> lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
> lib/intel_batchbuffer.c | 9 ++
> lib/intel_batchbuffer.h | 7 +
> lib/media_fill.c | 110 ++++++++++++++++
> lib/media_fill.h | 6 +
> lib/surfaceformat.h | 2 +
> tests/Makefile.sources | 3 +
> tests/i915/gem_media_vme.c | 117 +++++++++++++++++
> tests/meson.build | 1 +
> 12 files changed, 525 insertions(+), 2 deletions(-)
> create mode 100755 lib/i915/shaders/media/README_media_vme.txt
> create mode 100755 lib/i915/shaders/media/media_vme.gxa
> create mode 100644 tests/i915/gem_media_vme.c
>
> diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
> new file mode 100755
> index 000000000000..2470fdd89825
> --- /dev/null
> +++ b/lib/i915/shaders/media/README_media_vme.txt
> @@ -0,0 +1,65 @@
> +Step1: Building IGA (Intel Graphics Assembler)
> +========================================================================
> +
> +1. Download or clone IGC (Intel Graphics Compiler)
> +
> + https://github.com/intel/intel-graphics-compiler.git
> +
> +2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
> +
> + It should read the following folder strucutre:
> +
> + workspace
> + |- visa
> + |- IGC
> + |- inc
> + |- 3d
> + |- skuwa
> +
> +3. Chdir into IGA sub-component
> +
> + cd visa/iga
> +
> +4. Create build directory
> +
> + mkdir build
> +
> +5. Change into build directory
> +
> + cd build
> +
> +6. Run cmake
> +
> + cmake ../
> +
> +7. Run make to build IGA project
> +
> + make
> +
> +8. Get the output executable "iga64" in IGAExe folder
> +
> + usage: ./iga64 OPTIONS ARGS
> + where OPTIONS:
> + -h --help shows help on an option
> + -d --disassemble disassembles the input file
> + -a --assemble assembles the input file
> + -n --numeric-labels use numeric labels
> + -p --platform DEVICE specifies the platform (e.g. "GEN9")
> + -o --output FILE specifies the output file
> +
> + EXAMPLES:
> + ./iga64 file.gxa -p=11 -a -o file.krn
> +
> +Step2: Building ASM code
> +========================================================================
> +1. Command line to convert asm code to binary:
> +
> + iga64 media_vme.gxa -p=11 -a -o media_vme.krn
> +
> +2. Pad 128 bytes zeros to the kernel:
> +
> + dd if=/dev/zero bs=1 count=128 >> media_vme.krn
Why we're padding it with 128B zeroes?
We don't seem to do that for any other shaders.
Could you modify this instruction to use lib/i915/shaders/converter.py and
rather than adding yet another README, update lib/i915/shaders/README instead?
-Michał
> +
> +3. Generate hexdump:
> +
> + hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
@ 2019-01-10 14:02 ` Michał Winiarski
0 siblings, 0 replies; 25+ messages in thread
From: Michał Winiarski @ 2019-01-10 14:02 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Tony Ye, Intel-gfx, Tvrtko Ursulin
On Tue, Jan 08, 2019 at 03:13:02PM +0000, Tvrtko Ursulin wrote:
> From: Tony Ye <tony.ye@intel.com>
>
> Simple test which exercises the VME fixed function block.
>
> v2: (Tvrtko Ursulin)
> * Small cleanups like copyright date, tabs, remove unused bits.
>
> v3: (Tony Ye)
> * Added curbe data entry for dst surface.
> * Read the dst surface after the VME kernel being executed.
>
> v4: (Tony Ye)
> * Added the media_vme.gxa kernel source code and compile instructions.
>
> v5: (Tvrtko Ursulin)
> * Added hang detector.
>
> v6: (Tvrtko Ursulin)
> * Replace gem_read with gem_sync. (Chris Wilson)
>
> Signed-off-by: Tony Ye <tony.ye@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> lib/gpu_cmds.c | 136 ++++++++++++++++++++
> lib/gpu_cmds.h | 20 ++-
> lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
> lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
> lib/intel_batchbuffer.c | 9 ++
> lib/intel_batchbuffer.h | 7 +
> lib/media_fill.c | 110 ++++++++++++++++
> lib/media_fill.h | 6 +
> lib/surfaceformat.h | 2 +
> tests/Makefile.sources | 3 +
> tests/i915/gem_media_vme.c | 117 +++++++++++++++++
> tests/meson.build | 1 +
> 12 files changed, 525 insertions(+), 2 deletions(-)
> create mode 100755 lib/i915/shaders/media/README_media_vme.txt
> create mode 100755 lib/i915/shaders/media/media_vme.gxa
> create mode 100644 tests/i915/gem_media_vme.c
>
> diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
> new file mode 100755
> index 000000000000..2470fdd89825
> --- /dev/null
> +++ b/lib/i915/shaders/media/README_media_vme.txt
> @@ -0,0 +1,65 @@
> +Step1: Building IGA (Intel Graphics Assembler)
> +========================================================================
> +
> +1. Download or clone IGC (Intel Graphics Compiler)
> +
> + https://github.com/intel/intel-graphics-compiler.git
> +
> +2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
> +
> + It should read the following folder strucutre:
> +
> + workspace
> + |- visa
> + |- IGC
> + |- inc
> + |- 3d
> + |- skuwa
> +
> +3. Chdir into IGA sub-component
> +
> + cd visa/iga
> +
> +4. Create build directory
> +
> + mkdir build
> +
> +5. Change into build directory
> +
> + cd build
> +
> +6. Run cmake
> +
> + cmake ../
> +
> +7. Run make to build IGA project
> +
> + make
> +
> +8. Get the output executable "iga64" in IGAExe folder
> +
> + usage: ./iga64 OPTIONS ARGS
> + where OPTIONS:
> + -h --help shows help on an option
> + -d --disassemble disassembles the input file
> + -a --assemble assembles the input file
> + -n --numeric-labels use numeric labels
> + -p --platform DEVICE specifies the platform (e.g. "GEN9")
> + -o --output FILE specifies the output file
> +
> + EXAMPLES:
> + ./iga64 file.gxa -p=11 -a -o file.krn
> +
> +Step2: Building ASM code
> +========================================================================
> +1. Command line to convert asm code to binary:
> +
> + iga64 media_vme.gxa -p=11 -a -o media_vme.krn
> +
> +2. Pad 128 bytes zeros to the kernel:
> +
> + dd if=/dev/zero bs=1 count=128 >> media_vme.krn
Why we're padding it with 128B zeroes?
We don't seem to do that for any other shaders.
Could you modify this instruction to use lib/i915/shaders/converter.py and
rather than adding yet another README, update lib/i915/shaders/README instead?
-Michał
> +
> +3. Generate hexdump:
> +
> + hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-10 14:02 ` Michał Winiarski
@ 2019-01-11 3:18 ` Ye, Tony
-1 siblings, 0 replies; 25+ messages in thread
From: Ye, Tony @ 2019-01-11 3:18 UTC (permalink / raw)
To: Michał Winiarski, Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx
On 1/10/2019 10:02 PM, Michał Winiarski wrote:
> On Tue, Jan 08, 2019 at 03:13:02PM +0000, Tvrtko Ursulin wrote:
>> From: Tony Ye <tony.ye@intel.com>
>>
>> Simple test which exercises the VME fixed function block.
>>
>> v2: (Tvrtko Ursulin)
>> * Small cleanups like copyright date, tabs, remove unused bits.
>>
>> v3: (Tony Ye)
>> * Added curbe data entry for dst surface.
>> * Read the dst surface after the VME kernel being executed.
>>
>> v4: (Tony Ye)
>> * Added the media_vme.gxa kernel source code and compile instructions.
>>
>> v5: (Tvrtko Ursulin)
>> * Added hang detector.
>>
>> v6: (Tvrtko Ursulin)
>> * Replace gem_read with gem_sync. (Chris Wilson)
>>
>> Signed-off-by: Tony Ye <tony.ye@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>> lib/gpu_cmds.c | 136 ++++++++++++++++++++
>> lib/gpu_cmds.h | 20 ++-
>> lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
>> lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
>> lib/intel_batchbuffer.c | 9 ++
>> lib/intel_batchbuffer.h | 7 +
>> lib/media_fill.c | 110 ++++++++++++++++
>> lib/media_fill.h | 6 +
>> lib/surfaceformat.h | 2 +
>> tests/Makefile.sources | 3 +
>> tests/i915/gem_media_vme.c | 117 +++++++++++++++++
>> tests/meson.build | 1 +
>> 12 files changed, 525 insertions(+), 2 deletions(-)
>> create mode 100755 lib/i915/shaders/media/README_media_vme.txt
>> create mode 100755 lib/i915/shaders/media/media_vme.gxa
>> create mode 100644 tests/i915/gem_media_vme.c
>>
>> diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
>> new file mode 100755
>> index 000000000000..2470fdd89825
>> --- /dev/null
>> +++ b/lib/i915/shaders/media/README_media_vme.txt
>> @@ -0,0 +1,65 @@
>> +Step1: Building IGA (Intel Graphics Assembler)
>> +========================================================================
>> +
>> +1. Download or clone IGC (Intel Graphics Compiler)
>> +
>> + https://github.com/intel/intel-graphics-compiler.git
>> +
>> +2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
>> +
>> + It should read the following folder strucutre:
>> +
>> + workspace
>> + |- visa
>> + |- IGC
>> + |- inc
>> + |- 3d
>> + |- skuwa
>> +
>> +3. Chdir into IGA sub-component
>> +
>> + cd visa/iga
>> +
>> +4. Create build directory
>> +
>> + mkdir build
>> +
>> +5. Change into build directory
>> +
>> + cd build
>> +
>> +6. Run cmake
>> +
>> + cmake ../
>> +
>> +7. Run make to build IGA project
>> +
>> + make
>> +
>> +8. Get the output executable "iga64" in IGAExe folder
>> +
>> + usage: ./iga64 OPTIONS ARGS
>> + where OPTIONS:
>> + -h --help shows help on an option
>> + -d --disassemble disassembles the input file
>> + -a --assemble assembles the input file
>> + -n --numeric-labels use numeric labels
>> + -p --platform DEVICE specifies the platform (e.g. "GEN9")
>> + -o --output FILE specifies the output file
>> +
>> + EXAMPLES:
>> + ./iga64 file.gxa -p=11 -a -o file.krn
>> +
>> +Step2: Building ASM code
>> +========================================================================
>> +1. Command line to convert asm code to binary:
>> +
>> + iga64 media_vme.gxa -p=11 -a -o media_vme.krn
>> +
>> +2. Pad 128 bytes zeros to the kernel:
>> +
>> + dd if=/dev/zero bs=1 count=128 >> media_vme.krn
> Why we're padding it with 128B zeroes?
> We don't seem to do that for any other shaders.
>
> Could you modify this instruction to use lib/i915/shaders/converter.py and
> rather than adding yet another README, update lib/i915/shaders/README instead?
>
> -Michał
Padding 128 bytes of zeros are required by Gen HW. It is required for
all shaders unless your compiler did it quietly.
It makes sense to combine the instructions into lib/i915/shaders/README
and use existing python script to dump hex.
But the README seems to be outdated. I could not find intel-gen4asm when
I follow the instructions to build intel-graphics-compiler. Can you
update the README firstly to make it workable with latest
https://github.com/intel/intel-graphics-compiler?
Regards, --Tony
>
>> +
>> +3. Generate hexdump:
>> +
>> + hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
@ 2019-01-11 3:18 ` Ye, Tony
0 siblings, 0 replies; 25+ messages in thread
From: Ye, Tony @ 2019-01-11 3:18 UTC (permalink / raw)
To: Michał Winiarski, Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On 1/10/2019 10:02 PM, Michał Winiarski wrote:
> On Tue, Jan 08, 2019 at 03:13:02PM +0000, Tvrtko Ursulin wrote:
>> From: Tony Ye <tony.ye@intel.com>
>>
>> Simple test which exercises the VME fixed function block.
>>
>> v2: (Tvrtko Ursulin)
>> * Small cleanups like copyright date, tabs, remove unused bits.
>>
>> v3: (Tony Ye)
>> * Added curbe data entry for dst surface.
>> * Read the dst surface after the VME kernel being executed.
>>
>> v4: (Tony Ye)
>> * Added the media_vme.gxa kernel source code and compile instructions.
>>
>> v5: (Tvrtko Ursulin)
>> * Added hang detector.
>>
>> v6: (Tvrtko Ursulin)
>> * Replace gem_read with gem_sync. (Chris Wilson)
>>
>> Signed-off-by: Tony Ye <tony.ye@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>> lib/gpu_cmds.c | 136 ++++++++++++++++++++
>> lib/gpu_cmds.h | 20 ++-
>> lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
>> lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
>> lib/intel_batchbuffer.c | 9 ++
>> lib/intel_batchbuffer.h | 7 +
>> lib/media_fill.c | 110 ++++++++++++++++
>> lib/media_fill.h | 6 +
>> lib/surfaceformat.h | 2 +
>> tests/Makefile.sources | 3 +
>> tests/i915/gem_media_vme.c | 117 +++++++++++++++++
>> tests/meson.build | 1 +
>> 12 files changed, 525 insertions(+), 2 deletions(-)
>> create mode 100755 lib/i915/shaders/media/README_media_vme.txt
>> create mode 100755 lib/i915/shaders/media/media_vme.gxa
>> create mode 100644 tests/i915/gem_media_vme.c
>>
>> diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
>> new file mode 100755
>> index 000000000000..2470fdd89825
>> --- /dev/null
>> +++ b/lib/i915/shaders/media/README_media_vme.txt
>> @@ -0,0 +1,65 @@
>> +Step1: Building IGA (Intel Graphics Assembler)
>> +========================================================================
>> +
>> +1. Download or clone IGC (Intel Graphics Compiler)
>> +
>> + https://github.com/intel/intel-graphics-compiler.git
>> +
>> +2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
>> +
>> + It should read the following folder strucutre:
>> +
>> + workspace
>> + |- visa
>> + |- IGC
>> + |- inc
>> + |- 3d
>> + |- skuwa
>> +
>> +3. Chdir into IGA sub-component
>> +
>> + cd visa/iga
>> +
>> +4. Create build directory
>> +
>> + mkdir build
>> +
>> +5. Change into build directory
>> +
>> + cd build
>> +
>> +6. Run cmake
>> +
>> + cmake ../
>> +
>> +7. Run make to build IGA project
>> +
>> + make
>> +
>> +8. Get the output executable "iga64" in IGAExe folder
>> +
>> + usage: ./iga64 OPTIONS ARGS
>> + where OPTIONS:
>> + -h --help shows help on an option
>> + -d --disassemble disassembles the input file
>> + -a --assemble assembles the input file
>> + -n --numeric-labels use numeric labels
>> + -p --platform DEVICE specifies the platform (e.g. "GEN9")
>> + -o --output FILE specifies the output file
>> +
>> + EXAMPLES:
>> + ./iga64 file.gxa -p=11 -a -o file.krn
>> +
>> +Step2: Building ASM code
>> +========================================================================
>> +1. Command line to convert asm code to binary:
>> +
>> + iga64 media_vme.gxa -p=11 -a -o media_vme.krn
>> +
>> +2. Pad 128 bytes zeros to the kernel:
>> +
>> + dd if=/dev/zero bs=1 count=128 >> media_vme.krn
> Why we're padding it with 128B zeroes?
> We don't seem to do that for any other shaders.
>
> Could you modify this instruction to use lib/i915/shaders/converter.py and
> rather than adding yet another README, update lib/i915/shaders/README instead?
>
> -Michał
Padding 128 bytes of zeros are required by Gen HW. It is required for
all shaders unless your compiler did it quietly.
It makes sense to combine the instructions into lib/i915/shaders/README
and use existing python script to dump hex.
But the README seems to be outdated. I could not find intel-gen4asm when
I follow the instructions to build intel-graphics-compiler. Can you
update the README firstly to make it workable with latest
https://github.com/intel/intel-graphics-compiler?
Regards, --Tony
>
>> +
>> +3. Generate hexdump:
>> +
>> + hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-17 11:01 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2019-01-17 11:01 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-17 11:01 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
v6: (Tvrtko Ursulin)
* Replace gem_read with gem_sync. (Chris Wilson)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 117 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 525 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index b4fe29e2f277..51113685af09 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -304,6 +304,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..8d9fd822b2ee
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+
+ gem_sync(drm_fd, dst.bo->handle);
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index 5852bdc8f59d..180c55a8a283 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -167,6 +167,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-14 10:29 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2019-01-14 10:29 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-14 10:29 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
v6: (Tvrtko Ursulin)
* Replace gem_read with gem_sync. (Chris Wilson)
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 117 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 525 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 3dfeb5b67274..6dabb9dbf247 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -302,6 +302,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..8d9fd822b2ee
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+
+ gem_sync(drm_fd, dst.bo->handle);
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index f41f724af8af..e3a4a84ea7cc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -166,6 +166,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-08 11:24 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
@ 2019-01-08 14:56 ` Joonas Lahtinen
0 siblings, 0 replies; 25+ messages in thread
From: Joonas Lahtinen @ 2019-01-08 14:56 UTC (permalink / raw)
To: Tvrtko Ursulin, igt-dev; +Cc: Intel-gfx
Quoting Tvrtko Ursulin (2019-01-08 13:24:49)
> From: Tony Ye <tony.ye@intel.com>
>
> Simple test which exercises the VME fixed function block.
>
> v2: (Tvrtko Ursulin)
> * Small cleanups like copyright date, tabs, remove unused bits.
>
> v3: (Tony Ye)
> * Added curbe data entry for dst surface.
> * Read the dst surface after the VME kernel being executed.
>
> v4: (Tony Ye)
> * Added the media_vme.gxa kernel source code and compile instructions.
>
> v5: (Tvrtko Ursulin)
> * Added hang detector.
>
> Signed-off-by: Tony Ye <tony.ye@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
One could further improve this by checking some effect of the shader
kernel on the output surface, just to double check that it both executed
and didn't hang as suggested by Chris
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2019-01-08 11:24 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2019-01-08 11:24 ` Tvrtko Ursulin
2019-01-08 14:56 ` Joonas Lahtinen
0 siblings, 1 reply; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-01-08 11:24 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 118 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 526 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 3dfeb5b67274..6dabb9dbf247 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -302,6 +302,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..47e949c781f2
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+ uint8_t dst_linear[OUTPUT_SIZE];
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+ gem_read(drm_fd, dst.bo->handle, 0,
+ dst_linear, sizeof(dst_linear));
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index f41f724af8af..e3a4a84ea7cc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -166,6 +166,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2018-12-13 12:06 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2018-12-13 12:06 ` Tvrtko Ursulin
0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2018-12-13 12:06 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
v4: (Tony Ye)
* Added the media_vme.gxa kernel source code and compile instructions.
v5: (Tvrtko Ursulin)
* Added hang detector.
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
---
lib/gpu_cmds.c | 136 ++++++++++++++++++++
lib/gpu_cmds.h | 20 ++-
lib/i915/shaders/media/README_media_vme.txt | 65 ++++++++++
lib/i915/shaders/media/media_vme.gxa | 51 ++++++++
lib/intel_batchbuffer.c | 9 ++
lib/intel_batchbuffer.h | 7 +
lib/media_fill.c | 110 ++++++++++++++++
lib/media_fill.h | 6 +
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 118 +++++++++++++++++
tests/meson.build | 1 +
12 files changed, 526 insertions(+), 2 deletions(-)
create mode 100755 lib/i915/shaders/media/README_media_vme.txt
create mode 100755 lib/i915/shaders/media/media_vme.gxa
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/i915/shaders/media/README_media_vme.txt b/lib/i915/shaders/media/README_media_vme.txt
new file mode 100755
index 000000000000..2470fdd89825
--- /dev/null
+++ b/lib/i915/shaders/media/README_media_vme.txt
@@ -0,0 +1,65 @@
+Step1: Building IGA (Intel Graphics Assembler)
+========================================================================
+
+1. Download or clone IGC (Intel Graphics Compiler)
+
+ https://github.com/intel/intel-graphics-compiler.git
+
+2. Chdir into 'intel-graphics-compiler' (or any other workspace folder of choice)
+
+ It should read the following folder strucutre:
+
+ workspace
+ |- visa
+ |- IGC
+ |- inc
+ |- 3d
+ |- skuwa
+
+3. Chdir into IGA sub-component
+
+ cd visa/iga
+
+4. Create build directory
+
+ mkdir build
+
+5. Change into build directory
+
+ cd build
+
+6. Run cmake
+
+ cmake ../
+
+7. Run make to build IGA project
+
+ make
+
+8. Get the output executable "iga64" in IGAExe folder
+
+ usage: ./iga64 OPTIONS ARGS
+ where OPTIONS:
+ -h --help shows help on an option
+ -d --disassemble disassembles the input file
+ -a --assemble assembles the input file
+ -n --numeric-labels use numeric labels
+ -p --platform DEVICE specifies the platform (e.g. "GEN9")
+ -o --output FILE specifies the output file
+
+ EXAMPLES:
+ ./iga64 file.gxa -p=11 -a -o file.krn
+
+Step2: Building ASM code
+========================================================================
+1. Command line to convert asm code to binary:
+
+ iga64 media_vme.gxa -p=11 -a -o media_vme.krn
+
+2. Pad 128 bytes zeros to the kernel:
+
+ dd if=/dev/zero bs=1 count=128 >> media_vme.krn
+
+3. Generate hexdump:
+
+ hexdump -v -e '4/4 "0x%08x " "\n"' media_vme.krn > media_vme.hex
diff --git a/lib/i915/shaders/media/media_vme.gxa b/lib/i915/shaders/media/media_vme.gxa
new file mode 100755
index 000000000000..93a0ed2f12d6
--- /dev/null
+++ b/lib/i915/shaders/media/media_vme.gxa
@@ -0,0 +1,51 @@
+/*
+* Copyright (c) 2018, Intel Corporation
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+ mov (8|M0) r1.8<1>:w 0x20000000:v
+ mov (8|M0) r20.0<1>:w 0x1:v
+(W) mov (1|M0) r1.2<1>:f 0x3818000C:f
+ mov (8|M0) r20.8<1>:w 0x10:v
+ mov (8|M0) r21.0<1>:w 0x10000:v
+(W) mov (1|M0) r1.3<1>:f 0x22222222:f
+ add (1|M0) a0.0<1>:d r1.0<0;1,0>:d 276307968:d
+ mov (8|M0) r2.0<1>:f 0x0:f
+ mov (8|M0) r5.0<1>:f 0x0:f
+ mov (8|M0) r6.0<1>:f 0x0:f
+ mov (8|M0) r9.0<1>:f 0x0:f
+ mov (8|M0) r3.0<1>:d r1.8<8;8,1>:w
+ mul (8|M0) r4.0<1>:d r1.2<0;1,0>:d r20.0<8;8,1>:w
+ mul (8|M0) r7.0<1>:d r20.8<8;8,1>:w 256:w
+ mul (8|M0) r8.0<1>:d r1.3<0;1,0>:d r21.0<8;8,1>:w
+(W) mov (1|M0) r17.2<1>:f 0x0:f
+ send (16|M0) r10:uw r2:f 0xD a0.0{NoPreempt}
+ mov (1|M0) r10.14<1>:hf 0xBEEF:hf
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0400:ud
+ mov (1|M0) r10.15<1>:hf 0xDEAD:hf
+(W) mov (1|M0) r18.2<1>:f 0x8:f
+(W) mov (1|M0) r19.2<1>:f 0xC:f
+(W) mov (8|M0) r127.0<1>:f r0.0<8;8,1>:f
+(W) sends (16|M0) null:uw r17 r10 0x10A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0300:ud
+(W) sends (16|M0) null:uw r18 r14 0x8A a0.0
+(W) add (1|M0) a0.0<1>:ud r1.1<0;1,0>:ud 0x20A0200:ud
+(W) sends (8|M0) null:ud r19 r16 0x4A a0.0
+(W) send (8|M0) null r127:f 0x27 0x2000010 {EOT}
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index ad2e718f898c..22697c94fb13 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -873,6 +873,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index ecc23f08da77..e5f6e6d045b8 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -325,6 +325,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..b1e84727394a 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,46 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00600001, 0x20302e68, 0x00000000, 0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000, 0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000, 0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000, 0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000, 0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000, 0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020, 0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000, 0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030, 0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028, 0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290, 0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c, 0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000, 0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040, 0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000, 0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000, 0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000, 0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000, 0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000, 0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242, 0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024, 0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261, 0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0, 0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +285,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 3dfeb5b67274..6dabb9dbf247 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -302,6 +302,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..47e949c781f2
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+ uint8_t dst_linear[OUTPUT_SIZE];
+
+ drm_fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ igt_fork_hang_detector(drm_fd);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+ gem_read(drm_fd, dst.bo->handle, 0,
+ dst_linear, sizeof(dst_linear));
+
+ igt_stop_hang_detector();
+}
diff --git a/tests/meson.build b/tests/meson.build
index f41f724af8af..e3a4a84ea7cc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -166,6 +166,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2018-11-13 14:36 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2018-11-20 13:13 ` Joonas Lahtinen
@ 2018-12-13 10:47 ` Chris Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2018-12-13 10:47 UTC (permalink / raw)
To: Tvrtko Ursulin, igt-dev; +Cc: Intel-gfx
Quoting Tvrtko Ursulin (2018-11-13 14:36:28)
> +igt_vme_func_t igt_get_media_vme_func(int devid)
> +{
> + igt_vme_func_t fill = NULL;
> +
> + if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
> + fill = gen11_media_vme_func;
gen11_media_vme_func implies that this code is only usable from gen11+.
So which is true?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2018-11-13 14:36 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
@ 2018-11-20 13:13 ` Joonas Lahtinen
2018-12-13 10:47 ` Chris Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Joonas Lahtinen @ 2018-11-20 13:13 UTC (permalink / raw)
To: Tvrtko Ursulin, igt-dev, haihao.xiang, chris; +Cc: Intel-gfx
+ Haihaho who's been involved with gem_media_fill test, if you could
provide review, too.
Quoting Tvrtko Ursulin (2018-11-13 16:36:28)
> From: Tony Ye <tony.ye@intel.com>
>
> Simple test which exercises the VME fixed function block.
>
> v2: (Tvrtko Ursulin)
> * Small cleanups like copyright date, tabs, remove unused bits.
>
> v3: (Tony Ye)
> * Added curbe data entry for dst surface.
> * Read the dst surface after the VME kernel being executed.
>
> Signed-off-by: Tony Ye <tony.ye@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
<SNIP>
> +++ b/lib/media_fill.c
> @@ -61,6 +61,53 @@ static const uint32_t gen8_media_kernel[][4] = {
> { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
> };
>
> +static const uint32_t gen11_media_vme_kernel[][4] = {
> + { 0x00000001, 0x00000040, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00600001, 0x20302e68, 0x00000000,0x20000000 },
> + { 0x00600001, 0x22802e68, 0x00000000,0x00000001 },
> + { 0x00000001, 0x20284f2c, 0x00000000,0x3818000c },
> + { 0x00600001, 0x22902e68, 0x00000000,0x00000010 },
> + { 0x00600001, 0x22a02e68, 0x00000000,0x00010000 },
> + { 0x00000001, 0x202c4f2c, 0x00000000,0x22222222 },
> + { 0x00000040, 0x22000a20, 0x0e000020,0x10782000 },
> + { 0x00600001, 0x20404f28, 0x00000000,0x00000000 },
> + { 0x00600001, 0x20a04f28, 0x00000000,0x00000000 },
> + { 0x00600001, 0x20c04f28, 0x00000000,0x00000000 },
> + { 0x00600001, 0x21204f28, 0x00000000,0x00000000 },
> + { 0x00600001, 0x20601a28, 0x008d0030,0x00000000 },
> + { 0x00600041, 0x20800a28, 0x1a000028,0x008d0280 },
> + { 0x00600041, 0x20e01a28, 0x1e8d0290,0x01000100 },
> + { 0x00600041, 0x21000a28, 0x1a00002c,0x008d02a0 },
> + { 0x00000001, 0x22284f2c, 0x00000000,0x00000000 },
> + { 0x0d80c031, 0x21404a48, 0x00000040,0x00000200 },
> + { 0x00000001, 0x215c4708, 0x00000000,0xbeefbeef },
> + { 0x00000040, 0x22000204, 0x06000024,0x020a0400 },
> + { 0x00000001, 0x215e4708, 0x00000000,0xdeaddead },
> + { 0x00000001, 0x22484f2c, 0x00000000,0x00000008 },
> + { 0x00000001, 0x22684f2c, 0x00000000,0x0000000c },
> + { 0x00600001, 0x2fe04b2c, 0x008d0000,0x00000000 },
> + { 0x0a800033, 0x0000a054, 0x00002224,0x00000000 },
> + { 0x00000040, 0x22000204, 0x06000024,0x020a0300 },
> + { 0x0a800033, 0x0000e054, 0x00002242,0x00000000 },
> + { 0x00000040, 0x22000204, 0x06000024,0x020a0200 },
> + { 0x0a600033, 0x00010014, 0x00002261,0x00000000 },
> + { 0x07600031, 0x20004a04, 0x06000fe0,0x82000010 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> + { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
> +};
We need source code and compiling instructions for this, similar
to we have shaders/media/media_fill.gxa
> +static void
> +__gen11_media_vme_func(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned int width, unsigned int height,
> + const struct igt_buf *dst,
> + const uint32_t kernel[][4],
> + size_t kernel_size)
> +{
> + uint32_t curbe_buffer, interface_descriptor;
> + uint32_t batch_end;
> +
> + intel_batchbuffer_flush(batch);
> +
> + /* setup states */
> + batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
> +
> + curbe_buffer = gen11_fill_curbe_buffer_data(batch);
> + interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
> + kernel, kernel_size);
Indent is off here.
Other than these two things, seems reasonable to what I understand of
the test.
Regards, Joonas
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block
2018-11-13 14:36 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
@ 2018-11-13 14:36 ` Tvrtko Ursulin
2018-11-20 13:13 ` Joonas Lahtinen
2018-12-13 10:47 ` Chris Wilson
0 siblings, 2 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2018-11-13 14:36 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-gfx
From: Tony Ye <tony.ye@intel.com>
Simple test which exercises the VME fixed function block.
v2: (Tvrtko Ursulin)
* Small cleanups like copyright date, tabs, remove unused bits.
v3: (Tony Ye)
* Added curbe data entry for dst surface.
* Read the dst surface after the VME kernel being executed.
Signed-off-by: Tony Ye <tony.ye@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
lib/gpu_cmds.c | 136 +++++++++++++++++++++++++++++++++++++
lib/gpu_cmds.h | 20 +++++-
lib/intel_batchbuffer.c | 9 +++
lib/intel_batchbuffer.h | 7 ++
lib/media_fill.c | 117 +++++++++++++++++++++++++++++++
lib/media_fill.h | 6 ++
lib/surfaceformat.h | 2 +
tests/Makefile.sources | 3 +
tests/i915/gem_media_vme.c | 114 +++++++++++++++++++++++++++++++
tests/meson.build | 1 +
10 files changed, 413 insertions(+), 2 deletions(-)
create mode 100644 tests/i915/gem_media_vme.c
diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index 556a94c6f0b6..b490a63bdfef 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -52,6 +52,22 @@ gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch)
+{
+ uint32_t *curbe_buffer;
+ uint32_t offset;
+
+ curbe_buffer = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(uint32_t) * 8,
+ 64);
+ offset = intel_batchbuffer_subdata_offset(batch, curbe_buffer);
+ *curbe_buffer++ = 0;
+ *curbe_buffer = 1;
+
+ return offset;
+}
+
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
@@ -119,6 +135,26 @@ gen7_fill_binding_table(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst)
+{
+ uint32_t *binding_table, offset;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 64, 64);
+ offset = intel_batchbuffer_subdata_offset(batch, binding_table);
+ binding_table[0] = gen11_fill_surface_state(batch, src,
+ SURFACE_1D,SURFACEFORMAT_R32G32B32A32_FLOAT,
+ 0,0,
+ 0);
+ binding_table[1] = gen11_fill_surface_state(batch, dst,
+ SURFACE_BUFFER, SURFACEFORMAT_RAW,
+ 1,1,
+ 1);
+
+ return offset;
+}
+
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
const uint32_t kernel[][4],
@@ -384,6 +420,71 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst)
+{
+ struct gen8_surface_state *ss;
+ uint32_t write_domain, read_domain, offset;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, ss);
+
+ ss->ss0.surface_type = surface_type;
+ ss->ss0.surface_format = format;
+ ss->ss0.render_cache_read_write = 1;
+ ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */
+ ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */
+
+ if (buf->tiling == I915_TILING_X)
+ ss->ss0.tiled_mode = 2;
+ else if (buf->tiling == I915_TILING_Y)
+ ss->ss0.tiled_mode = 3;
+ else
+ ss->ss0.tiled_mode = 0;
+
+ ss->ss8.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4,
+ buf->bo, 0, read_domain, write_domain);
+ igt_assert(ret == 0);
+
+ if (is_dst) {
+ ss->ss1.memory_object_control = 2;
+ ss->ss2.height = 1;
+ ss->ss2.width = 95;
+ ss->ss3.pitch = 0;
+ ss->ss7.shader_chanel_select_r = 4;
+ ss->ss7.shader_chanel_select_g = 5;
+ ss->ss7.shader_chanel_select_b = 6;
+ ss->ss7.shader_chanel_select_a = 7;
+ }
+ else {
+ ss->ss1.qpitch = 4040;
+ ss->ss1.base_mip_level = 31;
+ ss->ss2.height = 9216;
+ ss->ss2.width = 1019;
+ ss->ss3.pitch = 64;
+ ss->ss5.mip_count = 2;
+ }
+
+ return offset;
+}
+
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
@@ -419,6 +520,41 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
return offset;
}
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size)
+{
+ struct gen8_interface_descriptor_data *idd;
+ uint32_t offset;
+ uint32_t binding_table_offset, kernel_offset;
+
+ binding_table_offset = gen11_fill_binding_table(batch, src,dst);
+ kernel_offset = gen7_fill_kernel(batch, kernel, size);
+
+ idd = intel_batchbuffer_subdata_alloc(batch, sizeof(*idd), 64);
+ offset = intel_batchbuffer_subdata_offset(batch, idd);
+
+ idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+ idd->desc2.single_program_flow = 1;
+ idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+ idd->desc3.sampler_count = 0; /* 0 samplers used */
+ idd->desc3.sampler_state_pointer = 0;
+
+ idd->desc4.binding_table_entry_count = 0;
+ idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+ idd->desc5.constant_urb_entry_read_offset = 0;
+ idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+ idd->desc6.num_threads_in_tg = 1;
+
+ return offset;
+}
+
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch)
{
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 79bc4d6473ba..ca671fb52daf 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -43,6 +43,8 @@ gen7_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end);
uint32_t
gen7_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
uint8_t color);
+uint32_t
+gen11_fill_curbe_buffer_data(struct intel_batchbuffer *batch);
uint32_t
gen7_fill_surface_state(struct intel_batchbuffer *batch,
@@ -53,6 +55,9 @@ gen7_fill_surface_state(struct intel_batchbuffer *batch,
uint32_t
gen7_fill_binding_table(struct intel_batchbuffer *batch,
const struct igt_buf *dst);
+uint32_t
+gen11_fill_binding_table(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst);
uint32_t
gen7_fill_kernel(struct intel_batchbuffer *batch,
@@ -99,13 +104,24 @@ gen8_fill_surface_state(struct intel_batchbuffer *batch,
const struct igt_buf *buf,
uint32_t format,
int is_dst);
-
+uint32_t
+gen11_fill_surface_state(struct intel_batchbuffer *batch,
+ const struct igt_buf *buf,
+ uint32_t surface_type,
+ uint32_t format,
+ uint32_t vertical_alignment,
+ uint32_t horizontal_alignment,
+ int is_dst);
uint32_t
gen8_fill_interface_descriptor(struct intel_batchbuffer *batch,
const struct igt_buf *dst,
const uint32_t kernel[][4],
size_t size);
-
+uint32_t
+gen11_fill_interface_descriptor(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t size);
void
gen8_emit_state_base_address(struct intel_batchbuffer *batch);
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index c13b1dc476a3..20453cfa5dec 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -872,6 +872,15 @@ igt_fillfunc_t igt_get_media_fillfunc(int devid)
return fill;
}
+igt_vme_func_t igt_get_media_vme_func(int devid)
+{
+ igt_vme_func_t fill = NULL;
+
+ if (IS_GEN9(devid) || IS_GEN10(devid) || IS_GEN11(devid))
+ fill = gen11_media_vme_func;
+
+ return fill;
+}
/**
* igt_get_gpgpu_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 2dcb09ce8f08..d21fb90ed147 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -323,6 +323,13 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
igt_fillfunc_t igt_get_media_fillfunc(int devid);
igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
+igt_vme_func_t igt_get_media_vme_func(int devid);
+
/**
* igt_media_spinfunc_t:
* @batch: batchbuffer object
diff --git a/lib/media_fill.c b/lib/media_fill.c
index 4942229505ff..ab613b308742 100644
--- a/lib/media_fill.c
+++ b/lib/media_fill.c
@@ -61,6 +61,53 @@ static const uint32_t gen8_media_kernel[][4] = {
{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
};
+static const uint32_t gen11_media_vme_kernel[][4] = {
+ { 0x00000001, 0x00000040, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00600001, 0x20302e68, 0x00000000,0x20000000 },
+ { 0x00600001, 0x22802e68, 0x00000000,0x00000001 },
+ { 0x00000001, 0x20284f2c, 0x00000000,0x3818000c },
+ { 0x00600001, 0x22902e68, 0x00000000,0x00000010 },
+ { 0x00600001, 0x22a02e68, 0x00000000,0x00010000 },
+ { 0x00000001, 0x202c4f2c, 0x00000000,0x22222222 },
+ { 0x00000040, 0x22000a20, 0x0e000020,0x10782000 },
+ { 0x00600001, 0x20404f28, 0x00000000,0x00000000 },
+ { 0x00600001, 0x20a04f28, 0x00000000,0x00000000 },
+ { 0x00600001, 0x20c04f28, 0x00000000,0x00000000 },
+ { 0x00600001, 0x21204f28, 0x00000000,0x00000000 },
+ { 0x00600001, 0x20601a28, 0x008d0030,0x00000000 },
+ { 0x00600041, 0x20800a28, 0x1a000028,0x008d0280 },
+ { 0x00600041, 0x20e01a28, 0x1e8d0290,0x01000100 },
+ { 0x00600041, 0x21000a28, 0x1a00002c,0x008d02a0 },
+ { 0x00000001, 0x22284f2c, 0x00000000,0x00000000 },
+ { 0x0d80c031, 0x21404a48, 0x00000040,0x00000200 },
+ { 0x00000001, 0x215c4708, 0x00000000,0xbeefbeef },
+ { 0x00000040, 0x22000204, 0x06000024,0x020a0400 },
+ { 0x00000001, 0x215e4708, 0x00000000,0xdeaddead },
+ { 0x00000001, 0x22484f2c, 0x00000000,0x00000008 },
+ { 0x00000001, 0x22684f2c, 0x00000000,0x0000000c },
+ { 0x00600001, 0x2fe04b2c, 0x008d0000,0x00000000 },
+ { 0x0a800033, 0x0000a054, 0x00002224,0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024,0x020a0300 },
+ { 0x0a800033, 0x0000e054, 0x00002242,0x00000000 },
+ { 0x00000040, 0x22000204, 0x06000024,0x020a0200 },
+ { 0x0a600033, 0x00010014, 0x00002261,0x00000000 },
+ { 0x07600031, 0x20004a04, 0x06000fe0,0x82000010 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+ { 0x00000000, 0x00000000, 0x00000000,0x00000000 },
+};
+
/*
* This sets up the media pipeline,
*
@@ -245,3 +292,73 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
gen8_media_kernel, sizeof(gen8_media_kernel));
}
+
+static void
+__gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst,
+ const uint32_t kernel[][4],
+ size_t kernel_size)
+{
+ uint32_t curbe_buffer, interface_descriptor;
+ uint32_t batch_end;
+
+ intel_batchbuffer_flush(batch);
+
+ /* setup states */
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ curbe_buffer = gen11_fill_curbe_buffer_data(batch);
+ interface_descriptor = gen11_fill_interface_descriptor(batch, src, dst,
+ kernel, kernel_size);
+ assert(batch->ptr < &batch->buffer[4095]);
+
+ /* media pipeline */
+ batch->ptr = batch->buffer;
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+ GEN9_SAMPLER_DOP_GATE_DISABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+ gen9_emit_state_base_address(batch);
+
+ gen8_emit_vfe_state(batch, THREADS, MEDIA_URB_ENTRIES, MEDIA_URB_SIZE,
+ MEDIA_CURBE_SIZE);
+
+ gen7_emit_curbe_load(batch, curbe_buffer);
+
+ gen7_emit_interface_descriptor_load(batch, interface_descriptor);
+
+ gen7_emit_media_objects(batch, 0, 0, width, height);
+
+ OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+ GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+ GEN9_SAMPLER_DOP_GATE_ENABLE |
+ GEN9_PIPELINE_SELECTION_MASK |
+ GEN9_SAMPLER_DOP_GATE_MASK |
+ GEN9_FORCE_MEDIA_AWAKE_MASK);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ batch_end = intel_batchbuffer_align(batch, 8);
+ assert(batch_end < BATCH_STATE_SPLIT);
+
+ gen7_render_flush(batch, batch_end);
+ intel_batchbuffer_reset(batch);
+}
+
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst)
+{
+ __gen11_media_vme_func(batch,
+ src,
+ width, height,
+ dst,
+ gen11_media_vme_kernel,
+ sizeof(gen11_media_vme_kernel));
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index e365da9e47d2..1d5c5fa826a3 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -49,4 +49,10 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
unsigned int width, unsigned int height,
uint8_t color);
+void
+gen11_media_vme_func(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned int width, unsigned int height,
+ const struct igt_buf *dst);
+
#endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/surfaceformat.h b/lib/surfaceformat.h
index 5d7ed2cadc2d..32ea373262ca 100644
--- a/lib/surfaceformat.h
+++ b/lib/surfaceformat.h
@@ -171,6 +171,8 @@
#define SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define SURFACEFORMAT_R16G16B16_USCALED 0x19F
+#define SURFACEFORMAT_RAW 0x1FF
+
#define SURFACERETURNFORMAT_FLOAT32 0
#define SURFACERETURNFORMAT_S1 1
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index fd99bc15da67..628a28f61364 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -300,6 +300,9 @@ gem_madvise_SOURCES = i915/gem_madvise.c
TESTS_progs += gem_media_fill
gem_media_fill_SOURCES = i915/gem_media_fill.c
+TESTS_progs += gem_media_vme
+gem_media_vme_SOURCES = i915/gem_media_vme.c
+
TESTS_progs += gem_mmap
gem_mmap_SOURCES = i915/gem_mmap.c
diff --git a/tests/i915/gem_media_vme.c b/tests/i915/gem_media_vme.c
new file mode 100644
index 000000000000..1c2f33a45eb5
--- /dev/null
+++ b/tests/i915/gem_media_vme.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "igt.h"
+#include <stdbool.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("A very simple workload for the VME media block.");
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+
+#define INPUT_SIZE (WIDTH * HEIGHT * sizeof(char) * 1.5)
+#define OUTPUT_SIZE (56*sizeof(int))
+
+static void
+scratch_buf_init(drm_intel_bufmgr *bufmgr,
+ struct igt_buf *buf,
+ unsigned int size)
+{
+ drm_intel_bo *bo;
+
+ bo = drm_intel_bo_alloc(bufmgr, "", size, 4096);
+ igt_assert(bo);
+
+ memset(buf, 0, sizeof(*buf));
+
+ buf->bo = bo;
+ buf->tiling = I915_TILING_NONE;
+ buf->size = size;
+}
+
+static void scratch_buf_init_src(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, INPUT_SIZE);
+
+ /*
+ * Ideally we would read src surface from file "SourceFrameI.yu12".
+ * But even without it, we can still triger the rcs0 resetting
+ * with this vme kernel.
+ */
+
+ buf->stride = STRIDE;
+}
+
+static void scratch_buf_init_dst(drm_intel_bufmgr *bufmgr, struct igt_buf *buf)
+{
+ scratch_buf_init(bufmgr, buf, OUTPUT_SIZE);
+
+ buf->stride = 1;
+}
+
+igt_simple_main
+{
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ igt_vme_func_t media_vme;
+ struct intel_batchbuffer *batch;
+ struct igt_buf src, dst;
+ uint8_t dst_linear[OUTPUT_SIZE];
+
+ drm_fd = drm_open_driver_render(DRIVER_INTEL);
+ igt_require_gem(drm_fd);
+
+ devid = intel_get_drm_devid(drm_fd);
+
+ media_vme = igt_get_media_vme_func(devid);
+ igt_require_f(media_vme, "no media-vme function\n");
+
+ bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+ igt_assert(bufmgr);
+
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+ igt_assert(batch);
+
+ scratch_buf_init_src(bufmgr, &src);
+ scratch_buf_init_dst(bufmgr, &dst);
+
+ media_vme(batch, &src, WIDTH, HEIGHT, &dst);
+ gem_read(drm_fd, dst.bo->handle, 0,
+ dst_linear, sizeof(dst_linear));
+}
diff --git a/tests/meson.build b/tests/meson.build
index 1992b0740f35..4ec434776f4c 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -161,6 +161,7 @@ gem_progs = [
'gem_lut_handle',
'gem_madvise',
'gem_media_fill',
+ 'gem_media_vme',
'gem_mmap',
'gem_mmap_gtt',
'gem_mmap_offset_exhaustion',
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2019-01-08 15:12 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2019-01-08 15:12 ` [Intel-gfx] " Tvrtko Ursulin
2019-01-08 15:13 ` [PATCH i-g-t 1/4] headers: bump Tvrtko Ursulin
2019-01-08 15:13 ` [igt-dev] " Tvrtko Ursulin
2019-01-08 15:13 ` [PATCH i-g-t 2/4] tests/gem_ctx_sseu: Dynamic (sub)slice programming tests Tvrtko Ursulin
2019-01-08 15:13 ` [igt-dev] " Tvrtko Ursulin
2019-01-08 15:13 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2019-01-08 15:13 ` [igt-dev] " Tvrtko Ursulin
2019-01-10 14:02 ` Michał Winiarski
2019-01-10 14:02 ` Michał Winiarski
2019-01-11 3:18 ` Ye, Tony
2019-01-11 3:18 ` Ye, Tony
2019-01-08 15:13 ` [PATCH i-g-t 4/4] tests/gem_media_vme: Shut down half of subslices to avoid gpu hang on ICL Tvrtko Ursulin
2019-01-08 15:13 ` [igt-dev] " Tvrtko Ursulin
2019-01-08 15:31 ` [igt-dev] ✗ Fi.CI.BAT: failure for Per context dynamic (sub)slice power-gating (rev11) Patchwork
2019-01-08 17:56 ` [igt-dev] ✓ Fi.CI.BAT: success for Per context dynamic (sub)slice power-gating (rev12) Patchwork
2019-01-09 2:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-01-17 11:01 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2019-01-17 11:01 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2019-01-14 10:29 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2019-01-14 10:29 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2019-01-08 11:24 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2019-01-08 11:24 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2019-01-08 14:56 ` Joonas Lahtinen
2018-12-13 12:06 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2018-12-13 12:06 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2018-11-13 14:36 [PATCH i-g-t 0/4] Per context dynamic (sub)slice power-gating Tvrtko Ursulin
2018-11-13 14:36 ` [PATCH i-g-t 3/4] tests/gem_media_vme: Simple test to exercise the VME block Tvrtko Ursulin
2018-11-20 13:13 ` Joonas Lahtinen
2018-12-13 10:47 ` Chris Wilson
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