From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
Date: Tue, 15 Jan 2019 07:57:27 -0800 [thread overview]
Message-ID: <20190115155727.GD13095@infradead.org> (raw)
In-Reply-To: <20181227111821.80908-6-anup@brainfault.org>
> + if (!force)
> + cpu = cpumask_any_and(mask_val, cpu_online_mask);
> + else
> + cpu = cpumask_first(mask_val);
Any reason for the inverted test?
Otherwise this looks fine to me:
Reviewed-by: Christoph Hellwig <hch@lst.de>
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Thomas Gleixner <tglx@linutronix.de>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v4 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
Date: Tue, 15 Jan 2019 07:57:27 -0800 [thread overview]
Message-ID: <20190115155727.GD13095@infradead.org> (raw)
In-Reply-To: <20181227111821.80908-6-anup@brainfault.org>
> + if (!force)
> + cpu = cpumask_any_and(mask_val, cpu_online_mask);
> + else
> + cpu = cpumask_first(mask_val);
Any reason for the inverted test?
Otherwise this looks fine to me:
Reviewed-by: Christoph Hellwig <hch@lst.de>
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next prev parent reply other threads:[~2019-01-15 15:57 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-27 11:18 [PATCH v4 0/5] IRQ affinity support in PLIC driver Anup Patel
2018-12-27 11:18 ` Anup Patel
2018-12-27 11:18 ` [PATCH v4 1/5] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-12-27 11:18 ` Anup Patel
2018-12-27 11:18 ` [PATCH v4 2/5] irqchip: sifive-plic: Don't inline plic_toggle() and plic_irq_toggle() Anup Patel
2018-12-27 11:18 ` Anup Patel
2019-01-15 15:54 ` Christoph Hellwig
2019-01-15 15:54 ` Christoph Hellwig
2019-01-19 5:00 ` Anup Patel
2019-01-19 5:00 ` Anup Patel
2018-12-27 11:18 ` [PATCH v4 3/5] irqchip: sifive-plic: Add warning in plic_init() if handler already present Anup Patel
2018-12-27 11:18 ` Anup Patel
2019-01-15 15:54 ` Christoph Hellwig
2019-01-15 15:54 ` Christoph Hellwig
2019-01-19 5:03 ` Anup Patel
2019-01-19 5:03 ` Anup Patel
2018-12-27 11:18 ` [PATCH v4 4/5] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-12-27 11:18 ` Anup Patel
2019-01-15 15:56 ` Christoph Hellwig
2019-01-15 15:56 ` Christoph Hellwig
2019-01-19 5:25 ` Anup Patel
2019-01-19 5:25 ` Anup Patel
2018-12-27 11:18 ` [PATCH v4 5/5] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-12-27 11:18 ` Anup Patel
2019-01-15 15:57 ` Christoph Hellwig [this message]
2019-01-15 15:57 ` Christoph Hellwig
2019-01-19 5:26 ` Anup Patel
2019-01-19 5:26 ` Anup Patel
2019-01-08 12:14 ` [PATCH v4 0/5] IRQ affinity support in PLIC driver Anup Patel
2019-01-08 12:14 ` Anup Patel
2019-01-23 18:57 ` Palmer Dabbelt
2019-01-23 18:57 ` Palmer Dabbelt
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