* [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data
@ 2019-01-17 7:53 Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter Cédric Le Goater
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 7:53 UTC (permalink / raw)
To: David Gibson
Cc: Thomas Huth, Greg Kurz, qemu-ppc, qemu-devel, Cédric Le Goater
Hello,
Currently the interrupt presenters of the sPAPR and PowerNV machines
are stored directly under PowerPCCPU which can be problematic as this
model is shared by all PPC machines.
The following patches move the interrupt presenters under the CPU
machine_data pointer which is a private field of the CPU that the
machine can use of its own needs.
To be applied on top of Thomas -std=gnu99 patchset.
Thanks,
C.
Cédric Le Goater (4):
xive: add a get_tctx() method to the XiveRouter
ppc/pnv: introduce a CPU machine_data
spapr: move the interrupt presenters under machine_data
ppc: remove the interrupt presenters from under PowerPCCPU
include/hw/ppc/pnv_core.h | 9 ++++++
include/hw/ppc/spapr_cpu_core.h | 2 ++
include/hw/ppc/xive.h | 57 +++++++++++++++++----------------
target/ppc/cpu.h | 9 ------
hw/intc/spapr_xive.c | 9 ++++++
hw/intc/xics_spapr.c | 11 ++++---
hw/intc/xive.c | 16 +++++----
hw/ppc/pnv.c | 7 ++--
hw/ppc/pnv_core.c | 12 ++++++-
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_cpu_core.c | 8 ++---
hw/ppc/spapr_irq.c | 17 ++++++----
12 files changed, 95 insertions(+), 64 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter
2019-01-17 7:53 [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data Cédric Le Goater
@ 2019-01-17 7:53 ` Cédric Le Goater
2019-01-17 8:12 ` Greg Kurz
2019-01-17 7:53 ` [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data Cédric Le Goater
` (2 subsequent siblings)
3 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 7:53 UTC (permalink / raw)
To: David Gibson
Cc: Thomas Huth, Greg Kurz, qemu-ppc, qemu-devel, Cédric Le Goater
It provides a mean to retrieve the XiveTCTX of a CPU. This will become
necessary with future changes which move the interrupt presenter
object pointers under the PowerPCCPU machine_data.
The PowerNV machine has an extra requirement on TIMA accesses that
this new method addresses. The machine can perform indirect loads and
stores on the TIMA on behalf of another CPU. The PIR being defined in
the controller registers, we need a way to peek in the controller
model to find the PIR value.
The XiveTCTX is moved above the XiveRouter definition to avoid forward
typedef declarations.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 57 ++++++++++++++++++++++---------------------
hw/intc/spapr_xive.c | 8 ++++++
hw/intc/xive.c | 16 +++++++-----
3 files changed, 47 insertions(+), 34 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 5d31c801ee53..ec3bb2aae45a 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
void xive_source_set_irq(void *opaque, int srcno, int val);
+/*
+ * XIVE Thread interrupt Management (TM) context
+ */
+
+#define TYPE_XIVE_TCTX "xive-tctx"
+#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
+
+/*
+ * XIVE Thread interrupt Management register rings :
+ *
+ * QW-0 User event-based exception state
+ * QW-1 O/S OS context for priority management, interrupt acks
+ * QW-2 Pool hypervisor pool context for virtual processors dispatched
+ * QW-3 Physical physical thread context and security context
+ */
+#define XIVE_TM_RING_COUNT 4
+#define XIVE_TM_RING_SIZE 0x10
+
+typedef struct XiveTCTX {
+ DeviceState parent_obj;
+
+ CPUState *cs;
+ qemu_irq output;
+
+ uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
+} XiveTCTX;
+
/*
* XIVE Router
*/
@@ -324,6 +351,7 @@ typedef struct XiveRouterClass {
XiveNVT *nvt);
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
+ XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
} XiveRouterClass;
void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
@@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-
+XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
/*
* XIVE END ESBs
@@ -371,33 +399,6 @@ typedef struct XiveENDSource {
void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
-/*
- * XIVE Thread interrupt Management (TM) context
- */
-
-#define TYPE_XIVE_TCTX "xive-tctx"
-#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
-
-/*
- * XIVE Thread interrupt Management register rings :
- *
- * QW-0 User event-based exception state
- * QW-1 O/S OS context for priority management, interrupt acks
- * QW-2 Pool hypervisor pool context for virtual processors dispatched
- * QW-3 Physical physical thread context and security context
- */
-#define XIVE_TM_RING_COUNT 4
-#define XIVE_TM_RING_SIZE 0x10
-
-typedef struct XiveTCTX {
- DeviceState parent_obj;
-
- CPUState *cs;
- qemu_irq output;
-
- uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
-} XiveTCTX;
-
/*
* XIVE Thread Interrupt Management Aera (TIMA)
*
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index d391177ab81f..136d872f16bc 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
g_assert_not_reached();
}
+static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ return cpu->tctx;
+}
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
xrc->write_nvt = spapr_xive_write_nvt;
+ xrc->get_tctx = spapr_xive_get_tctx;
}
static const TypeInfo spapr_xive_info = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7f567a57d25a..2e9b8efd4342 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
static void xive_tm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto;
/*
@@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
const XiveTmOp *xto;
/*
@@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
}
+XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_tctx(xrtr, cs);
+}
+
/*
* The thread context register words are in big-endian format.
*/
@@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
*/
CPU_FOREACH(cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- XiveTCTX *tctx = cpu->tctx;
+ XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
int ring;
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data
2019-01-17 7:53 [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter Cédric Le Goater
@ 2019-01-17 7:53 ` Cédric Le Goater
2019-01-17 8:13 ` Greg Kurz
2019-01-17 7:53 ` [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU Cédric Le Goater
3 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 7:53 UTC (permalink / raw)
To: David Gibson
Cc: Thomas Huth, Greg Kurz, qemu-ppc, qemu-devel, Cédric Le Goater
Include the interrupt presenter under the machine_data as we plan to
remove it from under PowerPCCPU
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_core.h | 9 +++++++++
hw/ppc/pnv.c | 7 ++++---
hw/ppc/pnv_core.c | 12 +++++++++++-
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 447ae761f7ae..9961ea3a92cd 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -47,4 +47,13 @@ typedef struct PnvCoreClass {
#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
+typedef struct PnvCPUState {
+ struct ICPState *icp;
+} PnvCPUState;
+
+static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
+{
+ return (PnvCPUState *)cpu->machine_data;
+}
+
#endif /* _PPC_PNV_CORE_H */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d84acef55b69..da540860a2b0 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -673,6 +673,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
{
Error *local_err = NULL;
Object *obj;
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
&local_err);
@@ -681,7 +682,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
return;
}
- cpu->icp = ICP(obj);
+ pnv_cpu->icp = ICP(obj);
}
/*
@@ -1099,7 +1100,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
{
PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
- return cpu ? cpu->icp : NULL;
+ return cpu ? pnv_cpu_state(cpu)->icp : NULL;
}
static void pnv_pic_print_info(InterruptStatsProvider *obj,
@@ -1112,7 +1113,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_pic_print_info(cpu->icp, mon);
+ icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon);
}
for (i = 0; i < pnv->num_chips; i++) {
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b98f277f1e02..7c806da720c6 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -155,7 +155,10 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
+ PowerPCCPU *cpu;
+
obj = object_new(typename);
+ cpu = POWERPC_CPU(obj);
pc->threads[i] = POWERPC_CPU(obj);
@@ -163,6 +166,9 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
object_property_add_child(OBJECT(pc), name, obj, &error_abort);
object_property_add_alias(obj, "core-pir", OBJECT(pc),
"pir", &error_abort);
+
+ cpu->machine_data = g_new0(PnvCPUState, 1);
+
object_unref(obj);
}
@@ -189,9 +195,13 @@ err:
static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
qemu_unregister_reset(pnv_cpu_reset, cpu);
- object_unparent(OBJECT(cpu->icp));
+ object_unparent(OBJECT(pnv_cpu_state(cpu)->icp));
cpu_remove_sync(CPU(cpu));
+ cpu->machine_data = NULL;
+ g_free(pnv_cpu);
object_unparent(OBJECT(cpu));
}
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data
2019-01-17 7:53 [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data Cédric Le Goater
@ 2019-01-17 7:53 ` Cédric Le Goater
2019-01-17 8:14 ` Greg Kurz
2019-01-17 7:53 ` [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU Cédric Le Goater
3 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 7:53 UTC (permalink / raw)
To: David Gibson
Cc: Thomas Huth, Greg Kurz, qemu-ppc, qemu-devel, Cédric Le Goater
Next step is to remove them from under the PowerPCCPU
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/spapr_cpu_core.h | 2 ++
hw/intc/spapr_xive.c | 3 ++-
hw/intc/xics_spapr.c | 11 ++++++-----
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_cpu_core.c | 8 ++++----
hw/ppc/spapr_irq.c | 17 ++++++++++-------
6 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index 9e2821e4b31f..d64f86bc284e 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -46,6 +46,8 @@ typedef struct sPAPRCPUState {
uint64_t vpa_addr;
uint64_t slb_shadow_addr, slb_shadow_size;
uint64_t dtl_addr, dtl_size;
+ struct ICPState *icp;
+ struct XiveTCTX *tctx;
} sPAPRCPUState;
static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 136d872f16bc..a0f5ff929447 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -16,6 +16,7 @@
#include "monitor/monitor.h"
#include "hw/ppc/fdt.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_xive.h"
#include "hw/ppc/xive.h"
#include "hw/ppc/xive_regs.h"
@@ -394,7 +395,7 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
- return cpu->tctx;
+ return spapr_cpu_state(cpu)->tctx;
}
static const VMStateDescription vmstate_spapr_xive_end = {
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index de6cc15b6474..e2d8b3818336 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -31,6 +31,7 @@
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
#include "hw/ppc/fdt.h"
@@ -45,7 +46,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
target_ulong cppr = args[0];
- icp_set_cppr(cpu->icp, cppr);
+ icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
return H_SUCCESS;
}
@@ -66,7 +67,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- uint32_t xirr = icp_accept(cpu->icp);
+ uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
args[0] = xirr;
return H_SUCCESS;
@@ -75,7 +76,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- uint32_t xirr = icp_accept(cpu->icp);
+ uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
args[0] = xirr;
args[1] = cpu_get_host_ticks();
@@ -87,7 +88,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
target_ulong xirr = args[0];
- icp_eoi(cpu->icp, xirr);
+ icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
return H_SUCCESS;
}
@@ -95,7 +96,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
uint32_t mfrr;
- uint32_t xirr = icp_ipoll(cpu->icp, &mfrr);
+ uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr);
args[0] = xirr;
args[1] = mfrr;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 83081defde4e..181f994c87a7 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3896,7 +3896,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
{
PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
- return cpu ? cpu->icp : NULL;
+ return cpu ? spapr_cpu_state(cpu)->icp : NULL;
}
static void spapr_pic_print_info(InterruptStatsProvider *obj,
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 0405306d1e59..ef6cbb9c2943 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -194,11 +194,11 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
}
qemu_unregister_reset(spapr_cpu_reset, cpu);
- if (cpu->icp) {
- object_unparent(OBJECT(cpu->icp));
+ if (spapr_cpu_state(cpu)->icp) {
+ object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
}
- if (cpu->tctx) {
- object_unparent(OBJECT(cpu->tctx));
+ if (spapr_cpu_state(cpu)->tctx) {
+ object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
}
cpu_remove_sync(CPU(cpu));
object_unparent(OBJECT(cpu));
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 1da7a32348fc..2d7a7c163876 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -12,6 +12,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/ppc/spapr.h"
+#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_xive.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/xics_spapr.h"
@@ -185,7 +186,7 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_pic_print_info(cpu->icp, mon);
+ icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
}
ics_pic_print_info(spapr->ics, mon);
@@ -196,6 +197,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
{
Error *local_err = NULL;
Object *obj;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
&local_err);
@@ -204,7 +206,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
return;
}
- cpu->icp = ICP(obj);
+ spapr_cpu->icp = ICP(obj);
}
static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
@@ -213,7 +215,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
CPUState *cs;
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- icp_resend(cpu->icp);
+ icp_resend(spapr_cpu_state(cpu)->icp);
}
}
return 0;
@@ -334,7 +336,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
- xive_tctx_pic_print_info(cpu->tctx, mon);
+ xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
}
spapr_xive_pic_print_info(spapr->xive, mon);
@@ -345,6 +347,7 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
{
Error *local_err = NULL;
Object *obj;
+ sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
if (local_err) {
@@ -352,13 +355,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
return;
}
- cpu->tctx = XIVE_TCTX(obj);
+ spapr_cpu->tctx = XIVE_TCTX(obj);
/*
* (TCG) Early setting the OS CAM line for hotplugged CPUs as they
* don't beneficiate from the reset of the XIVE IRQ backend
*/
- spapr_xive_set_tctx_os_cam(cpu->tctx);
+ spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
}
static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
@@ -374,7 +377,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
PowerPCCPU *cpu = POWERPC_CPU(cs);
/* (TCG) Set the OS CAM line of the thread interrupt context. */
- spapr_xive_set_tctx_os_cam(cpu->tctx);
+ spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
}
/* Activate the XIVE MMIOs */
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU
2019-01-17 7:53 [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data Cédric Le Goater
` (2 preceding siblings ...)
2019-01-17 7:53 ` [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data Cédric Le Goater
@ 2019-01-17 7:53 ` Cédric Le Goater
2019-01-17 8:20 ` Greg Kurz
3 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 7:53 UTC (permalink / raw)
To: David Gibson
Cc: Thomas Huth, Greg Kurz, qemu-ppc, qemu-devel, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bde4dff1ba80..2c22292e7f41 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -23,11 +23,6 @@
#include "qemu-common.h"
#include "qemu/int128.h"
-#ifndef CONFIG_USER_ONLY
-#include "hw/ppc/xive.h" /* for XiveTCTX */
-#include "hw/ppc/xics.h" /* for ICPState */
-#endif
-
//#define PPC_EMULATE_32BITS_HYPV
#if defined (TARGET_PPC64)
@@ -1203,10 +1198,6 @@ struct PowerPCCPU {
void *machine_data;
int32_t node_id; /* NUMA node this CPU belongs to */
PPCHash64Options *hash64_opts;
-#ifndef CONFIG_USER_ONLY
- ICPState *icp;
- XiveTCTX *tctx;
-#endif
/* Fields related to migration compatibility hacks */
bool pre_2_8_migration;
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter
2019-01-17 7:53 ` [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter Cédric Le Goater
@ 2019-01-17 8:12 ` Greg Kurz
2019-01-26 2:29 ` David Gibson
0 siblings, 1 reply; 16+ messages in thread
From: Greg Kurz @ 2019-01-17 8:12 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: David Gibson, Thomas Huth, qemu-ppc, qemu-devel
On Thu, 17 Jan 2019 08:53:24 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> It provides a mean to retrieve the XiveTCTX of a CPU. This will become
> necessary with future changes which move the interrupt presenter
> object pointers under the PowerPCCPU machine_data.
>
> The PowerNV machine has an extra requirement on TIMA accesses that
> this new method addresses. The machine can perform indirect loads and
> stores on the TIMA on behalf of another CPU. The PIR being defined in
> the controller registers, we need a way to peek in the controller
> model to find the PIR value.
>
> The XiveTCTX is moved above the XiveRouter definition to avoid forward
> typedef declarations.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> include/hw/ppc/xive.h | 57 ++++++++++++++++++++++---------------------
> hw/intc/spapr_xive.c | 8 ++++++
> hw/intc/xive.c | 16 +++++++-----
> 3 files changed, 47 insertions(+), 34 deletions(-)
>
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index 5d31c801ee53..ec3bb2aae45a 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
>
> void xive_source_set_irq(void *opaque, int srcno, int val);
>
> +/*
> + * XIVE Thread interrupt Management (TM) context
> + */
> +
> +#define TYPE_XIVE_TCTX "xive-tctx"
> +#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> +
> +/*
> + * XIVE Thread interrupt Management register rings :
> + *
> + * QW-0 User event-based exception state
> + * QW-1 O/S OS context for priority management, interrupt acks
> + * QW-2 Pool hypervisor pool context for virtual processors dispatched
> + * QW-3 Physical physical thread context and security context
> + */
> +#define XIVE_TM_RING_COUNT 4
> +#define XIVE_TM_RING_SIZE 0x10
> +
> +typedef struct XiveTCTX {
> + DeviceState parent_obj;
> +
> + CPUState *cs;
> + qemu_irq output;
> +
> + uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> +} XiveTCTX;
> +
> /*
> * XIVE Router
> */
> @@ -324,6 +351,7 @@ typedef struct XiveRouterClass {
> XiveNVT *nvt);
> int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
> } XiveRouterClass;
>
> void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
> @@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt);
> int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> -
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
>
> /*
> * XIVE END ESBs
> @@ -371,33 +399,6 @@ typedef struct XiveENDSource {
> void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
> void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
>
> -/*
> - * XIVE Thread interrupt Management (TM) context
> - */
> -
> -#define TYPE_XIVE_TCTX "xive-tctx"
> -#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> -
> -/*
> - * XIVE Thread interrupt Management register rings :
> - *
> - * QW-0 User event-based exception state
> - * QW-1 O/S OS context for priority management, interrupt acks
> - * QW-2 Pool hypervisor pool context for virtual processors dispatched
> - * QW-3 Physical physical thread context and security context
> - */
> -#define XIVE_TM_RING_COUNT 4
> -#define XIVE_TM_RING_SIZE 0x10
> -
> -typedef struct XiveTCTX {
> - DeviceState parent_obj;
> -
> - CPUState *cs;
> - qemu_irq output;
> -
> - uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> -} XiveTCTX;
> -
> /*
> * XIVE Thread Interrupt Management Aera (TIMA)
> *
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index d391177ab81f..136d872f16bc 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
> g_assert_not_reached();
> }
>
> +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> +
> + return cpu->tctx;
> +}
> +
> static const VMStateDescription vmstate_spapr_xive_end = {
> .name = TYPE_SPAPR_XIVE "/end",
> .version_id = 1,
> @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
> xrc->write_end = spapr_xive_write_end;
> xrc->get_nvt = spapr_xive_get_nvt;
> xrc->write_nvt = spapr_xive_write_nvt;
> + xrc->get_tctx = spapr_xive_get_tctx;
> }
>
> static const TypeInfo spapr_xive_info = {
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 7f567a57d25a..2e9b8efd4342 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
> static void xive_tm_write(void *opaque, hwaddr offset,
> uint64_t value, unsigned size)
> {
> - PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> - XiveTCTX *tctx = cpu->tctx;
> + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> const XiveTmOp *xto;
>
> /*
> @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
>
> static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
> {
> - PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> - XiveTCTX *tctx = cpu->tctx;
> + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> const XiveTmOp *xto;
>
> /*
> @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
> }
>
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +{
> + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
> +
> + return xrc->get_tctx(xrtr, cs);
> +}
> +
> /*
> * The thread context register words are in big-endian format.
> */
> @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
> */
>
> CPU_FOREACH(cs) {
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> - XiveTCTX *tctx = cpu->tctx;
> + XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
> int ring;
>
> /*
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data
2019-01-17 7:53 ` [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data Cédric Le Goater
@ 2019-01-17 8:13 ` Greg Kurz
2019-01-26 2:37 ` David Gibson
0 siblings, 1 reply; 16+ messages in thread
From: Greg Kurz @ 2019-01-17 8:13 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: David Gibson, Thomas Huth, qemu-ppc, qemu-devel
On Thu, 17 Jan 2019 08:53:25 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Include the interrupt presenter under the machine_data as we plan to
> remove it from under PowerPCCPU
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> include/hw/ppc/pnv_core.h | 9 +++++++++
> hw/ppc/pnv.c | 7 ++++---
> hw/ppc/pnv_core.c | 12 +++++++++++-
> 3 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index 447ae761f7ae..9961ea3a92cd 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -47,4 +47,13 @@ typedef struct PnvCoreClass {
> #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
> #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
>
> +typedef struct PnvCPUState {
> + struct ICPState *icp;
> +} PnvCPUState;
> +
> +static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
> +{
> + return (PnvCPUState *)cpu->machine_data;
> +}
> +
> #endif /* _PPC_PNV_CORE_H */
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d84acef55b69..da540860a2b0 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -673,6 +673,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> {
> Error *local_err = NULL;
> Object *obj;
> + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
>
> obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
> &local_err);
> @@ -681,7 +682,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> return;
> }
>
> - cpu->icp = ICP(obj);
> + pnv_cpu->icp = ICP(obj);
> }
>
> /*
> @@ -1099,7 +1100,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
> {
> PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
>
> - return cpu ? cpu->icp : NULL;
> + return cpu ? pnv_cpu_state(cpu)->icp : NULL;
> }
>
> static void pnv_pic_print_info(InterruptStatsProvider *obj,
> @@ -1112,7 +1113,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
> CPU_FOREACH(cs) {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> - icp_pic_print_info(cpu->icp, mon);
> + icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon);
> }
>
> for (i = 0; i < pnv->num_chips; i++) {
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index b98f277f1e02..7c806da720c6 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -155,7 +155,10 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
>
> pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
> for (i = 0; i < cc->nr_threads; i++) {
> + PowerPCCPU *cpu;
> +
> obj = object_new(typename);
> + cpu = POWERPC_CPU(obj);
>
> pc->threads[i] = POWERPC_CPU(obj);
>
> @@ -163,6 +166,9 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
> object_property_add_child(OBJECT(pc), name, obj, &error_abort);
> object_property_add_alias(obj, "core-pir", OBJECT(pc),
> "pir", &error_abort);
> +
> + cpu->machine_data = g_new0(PnvCPUState, 1);
> +
> object_unref(obj);
> }
>
> @@ -189,9 +195,13 @@ err:
>
> static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
> {
> + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> +
> qemu_unregister_reset(pnv_cpu_reset, cpu);
> - object_unparent(OBJECT(cpu->icp));
> + object_unparent(OBJECT(pnv_cpu_state(cpu)->icp));
> cpu_remove_sync(CPU(cpu));
> + cpu->machine_data = NULL;
> + g_free(pnv_cpu);
> object_unparent(OBJECT(cpu));
> }
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data
2019-01-17 7:53 ` [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data Cédric Le Goater
@ 2019-01-17 8:14 ` Greg Kurz
2019-01-26 2:31 ` David Gibson
0 siblings, 1 reply; 16+ messages in thread
From: Greg Kurz @ 2019-01-17 8:14 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: David Gibson, Thomas Huth, qemu-ppc, qemu-devel
On Thu, 17 Jan 2019 08:53:26 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Next step is to remove them from under the PowerPCCPU
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> include/hw/ppc/spapr_cpu_core.h | 2 ++
> hw/intc/spapr_xive.c | 3 ++-
> hw/intc/xics_spapr.c | 11 ++++++-----
> hw/ppc/spapr.c | 2 +-
> hw/ppc/spapr_cpu_core.c | 8 ++++----
> hw/ppc/spapr_irq.c | 17 ++++++++++-------
> 6 files changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
> index 9e2821e4b31f..d64f86bc284e 100644
> --- a/include/hw/ppc/spapr_cpu_core.h
> +++ b/include/hw/ppc/spapr_cpu_core.h
> @@ -46,6 +46,8 @@ typedef struct sPAPRCPUState {
> uint64_t vpa_addr;
> uint64_t slb_shadow_addr, slb_shadow_size;
> uint64_t dtl_addr, dtl_size;
> + struct ICPState *icp;
> + struct XiveTCTX *tctx;
> } sPAPRCPUState;
>
> static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu)
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index 136d872f16bc..a0f5ff929447 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -16,6 +16,7 @@
> #include "monitor/monitor.h"
> #include "hw/ppc/fdt.h"
> #include "hw/ppc/spapr.h"
> +#include "hw/ppc/spapr_cpu_core.h"
> #include "hw/ppc/spapr_xive.h"
> #include "hw/ppc/xive.h"
> #include "hw/ppc/xive_regs.h"
> @@ -394,7 +395,7 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> - return cpu->tctx;
> + return spapr_cpu_state(cpu)->tctx;
> }
>
> static const VMStateDescription vmstate_spapr_xive_end = {
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index de6cc15b6474..e2d8b3818336 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -31,6 +31,7 @@
> #include "trace.h"
> #include "qemu/timer.h"
> #include "hw/ppc/spapr.h"
> +#include "hw/ppc/spapr_cpu_core.h"
> #include "hw/ppc/xics.h"
> #include "hw/ppc/xics_spapr.h"
> #include "hw/ppc/fdt.h"
> @@ -45,7 +46,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> {
> target_ulong cppr = args[0];
>
> - icp_set_cppr(cpu->icp, cppr);
> + icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
> return H_SUCCESS;
> }
>
> @@ -66,7 +67,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> - uint32_t xirr = icp_accept(cpu->icp);
> + uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
>
> args[0] = xirr;
> return H_SUCCESS;
> @@ -75,7 +76,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> - uint32_t xirr = icp_accept(cpu->icp);
> + uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
>
> args[0] = xirr;
> args[1] = cpu_get_host_ticks();
> @@ -87,7 +88,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> {
> target_ulong xirr = args[0];
>
> - icp_eoi(cpu->icp, xirr);
> + icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
> return H_SUCCESS;
> }
>
> @@ -95,7 +96,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> uint32_t mfrr;
> - uint32_t xirr = icp_ipoll(cpu->icp, &mfrr);
> + uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr);
>
> args[0] = xirr;
> args[1] = mfrr;
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 83081defde4e..181f994c87a7 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -3896,7 +3896,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
> {
> PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
>
> - return cpu ? cpu->icp : NULL;
> + return cpu ? spapr_cpu_state(cpu)->icp : NULL;
> }
>
> static void spapr_pic_print_info(InterruptStatsProvider *obj,
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 0405306d1e59..ef6cbb9c2943 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -194,11 +194,11 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
> vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
> }
> qemu_unregister_reset(spapr_cpu_reset, cpu);
> - if (cpu->icp) {
> - object_unparent(OBJECT(cpu->icp));
> + if (spapr_cpu_state(cpu)->icp) {
> + object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
> }
> - if (cpu->tctx) {
> - object_unparent(OBJECT(cpu->tctx));
> + if (spapr_cpu_state(cpu)->tctx) {
> + object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
> }
> cpu_remove_sync(CPU(cpu));
> object_unparent(OBJECT(cpu));
> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
> index 1da7a32348fc..2d7a7c163876 100644
> --- a/hw/ppc/spapr_irq.c
> +++ b/hw/ppc/spapr_irq.c
> @@ -12,6 +12,7 @@
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "hw/ppc/spapr.h"
> +#include "hw/ppc/spapr_cpu_core.h"
> #include "hw/ppc/spapr_xive.h"
> #include "hw/ppc/xics.h"
> #include "hw/ppc/xics_spapr.h"
> @@ -185,7 +186,7 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
> CPU_FOREACH(cs) {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> - icp_pic_print_info(cpu->icp, mon);
> + icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
> }
>
> ics_pic_print_info(spapr->ics, mon);
> @@ -196,6 +197,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> {
> Error *local_err = NULL;
> Object *obj;
> + sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
>
> obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
> &local_err);
> @@ -204,7 +206,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> return;
> }
>
> - cpu->icp = ICP(obj);
> + spapr_cpu->icp = ICP(obj);
> }
>
> static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
> @@ -213,7 +215,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
> CPUState *cs;
> CPU_FOREACH(cs) {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> - icp_resend(cpu->icp);
> + icp_resend(spapr_cpu_state(cpu)->icp);
> }
> }
> return 0;
> @@ -334,7 +336,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
> CPU_FOREACH(cs) {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> - xive_tctx_pic_print_info(cpu->tctx, mon);
> + xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
> }
>
> spapr_xive_pic_print_info(spapr->xive, mon);
> @@ -345,6 +347,7 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> {
> Error *local_err = NULL;
> Object *obj;
> + sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
>
> obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
> if (local_err) {
> @@ -352,13 +355,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> return;
> }
>
> - cpu->tctx = XIVE_TCTX(obj);
> + spapr_cpu->tctx = XIVE_TCTX(obj);
>
> /*
> * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
> * don't beneficiate from the reset of the XIVE IRQ backend
> */
> - spapr_xive_set_tctx_os_cam(cpu->tctx);
> + spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
> }
>
> static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
> @@ -374,7 +377,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> /* (TCG) Set the OS CAM line of the thread interrupt context. */
> - spapr_xive_set_tctx_os_cam(cpu->tctx);
> + spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
> }
>
> /* Activate the XIVE MMIOs */
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU
2019-01-17 7:53 ` [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU Cédric Le Goater
@ 2019-01-17 8:20 ` Greg Kurz
2019-01-17 8:23 ` Thomas Huth
0 siblings, 1 reply; 16+ messages in thread
From: Greg Kurz @ 2019-01-17 8:20 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: David Gibson, Thomas Huth, qemu-ppc, qemu-devel
On Thu, 17 Jan 2019 08:53:27 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
The patch looks good, but I think it would be even better to apply this before
Thomas's -std=c99 patchset. This would allow to get rid of the controversial
"ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode"
patch :)
> target/ppc/cpu.h | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bde4dff1ba80..2c22292e7f41 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -23,11 +23,6 @@
> #include "qemu-common.h"
> #include "qemu/int128.h"
>
> -#ifndef CONFIG_USER_ONLY
> -#include "hw/ppc/xive.h" /* for XiveTCTX */
> -#include "hw/ppc/xics.h" /* for ICPState */
> -#endif
> -
> //#define PPC_EMULATE_32BITS_HYPV
>
> #if defined (TARGET_PPC64)
> @@ -1203,10 +1198,6 @@ struct PowerPCCPU {
> void *machine_data;
> int32_t node_id; /* NUMA node this CPU belongs to */
> PPCHash64Options *hash64_opts;
> -#ifndef CONFIG_USER_ONLY
> - ICPState *icp;
> - XiveTCTX *tctx;
> -#endif
>
> /* Fields related to migration compatibility hacks */
> bool pre_2_8_migration;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU
2019-01-17 8:20 ` Greg Kurz
@ 2019-01-17 8:23 ` Thomas Huth
2019-01-17 8:26 ` Cédric Le Goater
0 siblings, 1 reply; 16+ messages in thread
From: Thomas Huth @ 2019-01-17 8:23 UTC (permalink / raw)
To: Greg Kurz, Cédric Le Goater; +Cc: David Gibson, qemu-ppc, qemu-devel
On 2019-01-17 09:20, Greg Kurz wrote:
> On Thu, 17 Jan 2019 08:53:27 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>
> The patch looks good, but I think it would be even better to apply this before
> Thomas's -std=c99 patchset. This would allow to get rid of the controversial
> "ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode"
> patch :)
Ok, I haven't started to send v3 of my PULL request yet, so I can try to
use these patches here instead...
Thomas
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU
2019-01-17 8:23 ` Thomas Huth
@ 2019-01-17 8:26 ` Cédric Le Goater
2019-01-17 9:00 ` [Qemu-devel] [PATCH v6] ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode Thomas Huth
0 siblings, 1 reply; 16+ messages in thread
From: Cédric Le Goater @ 2019-01-17 8:26 UTC (permalink / raw)
To: Thomas Huth, Greg Kurz; +Cc: David Gibson, qemu-ppc, qemu-devel
On 1/17/19 9:23 AM, Thomas Huth wrote:
> On 2019-01-17 09:20, Greg Kurz wrote:
>> On Thu, 17 Jan 2019 08:53:27 +0100
>> Cédric Le Goater <clg@kaod.org> wrote:
>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>
>> The patch looks good, but I think it would be even better to apply this before
>> Thomas's -std=c99 patchset. This would allow to get rid of the controversial
>> "ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode"
>> patch :)
>
> Ok, I haven't started to send v3 of my PULL request yet, so I can try to
> use these patches here instead...
Yes. that would be nice. Get rid of patch 4 then. And we need David's feedback.
Thanks,
C.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v6] ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode
2019-01-17 8:26 ` Cédric Le Goater
@ 2019-01-17 9:00 ` Thomas Huth
2019-01-17 9:20 ` Greg Kurz
0 siblings, 1 reply; 16+ messages in thread
From: Thomas Huth @ 2019-01-17 9:00 UTC (permalink / raw)
To: qemu-devel, Cédric Le Goater, Greg Kurz; +Cc: qemu-ppc, david
When compiling the ppc code with clang and -std=gnu99, there are a
couple of warnings/errors like this one:
CC ppc64-softmmu/hw/intc/xics.o
In file included from hw/intc/xics.c:35:
include/hw/ppc/xics.h:43:25: error: redefinition of typedef 'ICPState' is a C11 feature
[-Werror,-Wtypedef-redefinition]
typedef struct ICPState ICPState;
^
target/ppc/cpu.h:1181:25: note: previous definition is here
typedef struct ICPState ICPState;
^
Work around the problems by including the proper headers in spapr.h
and by using struct forward declarations in cpu.h.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
As discussed on IRC, Cédric's patches likely should go via David's ppc-
tree, so I'll go with this version here for my gnu99-PULL request.
(v6: Don't use #includes in cpu.h, use forward struct definitions instead)
include/hw/ppc/spapr.h | 5 +++--
include/hw/ppc/spapr_xive.h | 2 --
target/ppc/cpu.h | 9 +++++----
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 9e01a5a..a947a0a 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -8,15 +8,16 @@
#include "hw/mem/pc-dimm.h"
#include "hw/ppc/spapr_ovec.h"
#include "hw/ppc/spapr_irq.h"
+#include "hw/ppc/spapr_xive.h" /* For sPAPRXive */
+#include "hw/ppc/xics.h" /* For ICSState */
struct VIOsPAPRBus;
struct sPAPRPHBState;
struct sPAPRNVRAM;
+
typedef struct sPAPREventLogEntry sPAPREventLogEntry;
typedef struct sPAPREventSource sPAPREventSource;
typedef struct sPAPRPendingHPT sPAPRPendingHPT;
-typedef struct ICSState ICSState;
-typedef struct sPAPRXive sPAPRXive;
#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
#define SPAPR_ENTRY_POINT 0x100
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 7fdc250..9bec919 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -41,8 +41,6 @@ bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi);
bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn);
void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon);
-typedef struct sPAPRMachineState sPAPRMachineState;
-
void spapr_xive_hcall_init(sPAPRMachineState *spapr);
void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt,
uint32_t phandle);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 486abaf..a62ff60 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1177,8 +1177,9 @@ do { \
typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
-typedef struct XiveTCTX XiveTCTX;
-typedef struct ICPState ICPState;
+
+struct XiveTCTX;
+struct ICPState;
/**
* PowerPCCPU:
@@ -1197,8 +1198,8 @@ struct PowerPCCPU {
int vcpu_id;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
- ICPState *icp;
- XiveTCTX *tctx;
+ struct ICPState *icp;
+ struct XiveTCTX *tctx;
void *machine_data;
int32_t node_id; /* NUMA node this CPU belongs to */
PPCHash64Options *hash64_opts;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH v6] ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode
2019-01-17 9:00 ` [Qemu-devel] [PATCH v6] ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode Thomas Huth
@ 2019-01-17 9:20 ` Greg Kurz
0 siblings, 0 replies; 16+ messages in thread
From: Greg Kurz @ 2019-01-17 9:20 UTC (permalink / raw)
To: Thomas Huth; +Cc: qemu-devel, Cédric Le Goater, qemu-ppc, david
On Thu, 17 Jan 2019 10:00:49 +0100
Thomas Huth <thuth@redhat.com> wrote:
> When compiling the ppc code with clang and -std=gnu99, there are a
> couple of warnings/errors like this one:
>
> CC ppc64-softmmu/hw/intc/xics.o
> In file included from hw/intc/xics.c:35:
> include/hw/ppc/xics.h:43:25: error: redefinition of typedef 'ICPState' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> typedef struct ICPState ICPState;
> ^
> target/ppc/cpu.h:1181:25: note: previous definition is here
> typedef struct ICPState ICPState;
> ^
> Work around the problems by including the proper headers in spapr.h
> and by using struct forward declarations in cpu.h.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> ---
> As discussed on IRC, Cédric's patches likely should go via David's ppc-
> tree, so I'll go with this version here for my gnu99-PULL request.
> (v6: Don't use #includes in cpu.h, use forward struct definitions instead)
>
Yeah, now that we know where we're going, I would certainly not hold your
gnu99 work off anymore :)
Reviewed-by: Greg Kurz <groug@kaod.org>
> include/hw/ppc/spapr.h | 5 +++--
> include/hw/ppc/spapr_xive.h | 2 --
> target/ppc/cpu.h | 9 +++++----
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 9e01a5a..a947a0a 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -8,15 +8,16 @@
> #include "hw/mem/pc-dimm.h"
> #include "hw/ppc/spapr_ovec.h"
> #include "hw/ppc/spapr_irq.h"
> +#include "hw/ppc/spapr_xive.h" /* For sPAPRXive */
> +#include "hw/ppc/xics.h" /* For ICSState */
>
> struct VIOsPAPRBus;
> struct sPAPRPHBState;
> struct sPAPRNVRAM;
> +
> typedef struct sPAPREventLogEntry sPAPREventLogEntry;
> typedef struct sPAPREventSource sPAPREventSource;
> typedef struct sPAPRPendingHPT sPAPRPendingHPT;
> -typedef struct ICSState ICSState;
> -typedef struct sPAPRXive sPAPRXive;
>
> #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
> #define SPAPR_ENTRY_POINT 0x100
> diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
> index 7fdc250..9bec919 100644
> --- a/include/hw/ppc/spapr_xive.h
> +++ b/include/hw/ppc/spapr_xive.h
> @@ -41,8 +41,6 @@ bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi);
> bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn);
> void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon);
>
> -typedef struct sPAPRMachineState sPAPRMachineState;
> -
> void spapr_xive_hcall_init(sPAPRMachineState *spapr);
> void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt,
> uint32_t phandle);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 486abaf..a62ff60 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1177,8 +1177,9 @@ do { \
>
> typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
> typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
> -typedef struct XiveTCTX XiveTCTX;
> -typedef struct ICPState ICPState;
> +
> +struct XiveTCTX;
> +struct ICPState;
>
> /**
> * PowerPCCPU:
> @@ -1197,8 +1198,8 @@ struct PowerPCCPU {
> int vcpu_id;
> uint32_t compat_pvr;
> PPCVirtualHypervisor *vhyp;
> - ICPState *icp;
> - XiveTCTX *tctx;
> + struct ICPState *icp;
> + struct XiveTCTX *tctx;
> void *machine_data;
> int32_t node_id; /* NUMA node this CPU belongs to */
> PPCHash64Options *hash64_opts;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter
2019-01-17 8:12 ` Greg Kurz
@ 2019-01-26 2:29 ` David Gibson
0 siblings, 0 replies; 16+ messages in thread
From: David Gibson @ 2019-01-26 2:29 UTC (permalink / raw)
To: Greg Kurz; +Cc: Cédric Le Goater, Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 7517 bytes --]
On Thu, Jan 17, 2019 at 09:12:36AM +0100, Greg Kurz wrote:
65;5403;1c> On Thu, 17 Jan 2019 08:53:24 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
> > It provides a mean to retrieve the XiveTCTX of a CPU. This will become
> > necessary with future changes which move the interrupt presenter
> > object pointers under the PowerPCCPU machine_data.
> >
> > The PowerNV machine has an extra requirement on TIMA accesses that
> > this new method addresses. The machine can perform indirect loads and
> > stores on the TIMA on behalf of another CPU. The PIR being defined in
> > the controller registers, we need a way to peek in the controller
> > model to find the PIR value.
> >
> > The XiveTCTX is moved above the XiveRouter definition to avoid forward
> > typedef declarations.
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
Applied, thanks.
>
> > include/hw/ppc/xive.h | 57 ++++++++++++++++++++++---------------------
> > hw/intc/spapr_xive.c | 8 ++++++
> > hw/intc/xive.c | 16 +++++++-----
> > 3 files changed, 47 insertions(+), 34 deletions(-)
> >
> > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> > index 5d31c801ee53..ec3bb2aae45a 100644
> > --- a/include/hw/ppc/xive.h
> > +++ b/include/hw/ppc/xive.h
> > @@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
> >
> > void xive_source_set_irq(void *opaque, int srcno, int val);
> >
> > +/*
> > + * XIVE Thread interrupt Management (TM) context
> > + */
> > +
> > +#define TYPE_XIVE_TCTX "xive-tctx"
> > +#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> > +
> > +/*
> > + * XIVE Thread interrupt Management register rings :
> > + *
> > + * QW-0 User event-based exception state
> > + * QW-1 O/S OS context for priority management, interrupt acks
> > + * QW-2 Pool hypervisor pool context for virtual processors dispatched
> > + * QW-3 Physical physical thread context and security context
> > + */
> > +#define XIVE_TM_RING_COUNT 4
> > +#define XIVE_TM_RING_SIZE 0x10
> > +
> > +typedef struct XiveTCTX {
> > + DeviceState parent_obj;
> > +
> > + CPUState *cs;
> > + qemu_irq output;
> > +
> > + uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> > +} XiveTCTX;
> > +
> > /*
> > * XIVE Router
> > */
> > @@ -324,6 +351,7 @@ typedef struct XiveRouterClass {
> > XiveNVT *nvt);
> > int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> > XiveNVT *nvt, uint8_t word_number);
> > + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
> > } XiveRouterClass;
> >
> > void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
> > @@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> > XiveNVT *nvt);
> > int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> > XiveNVT *nvt, uint8_t word_number);
> > -
> > +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
> >
> > /*
> > * XIVE END ESBs
> > @@ -371,33 +399,6 @@ typedef struct XiveENDSource {
> > void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
> > void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
> >
> > -/*
> > - * XIVE Thread interrupt Management (TM) context
> > - */
> > -
> > -#define TYPE_XIVE_TCTX "xive-tctx"
> > -#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
> > -
> > -/*
> > - * XIVE Thread interrupt Management register rings :
> > - *
> > - * QW-0 User event-based exception state
> > - * QW-1 O/S OS context for priority management, interrupt acks
> > - * QW-2 Pool hypervisor pool context for virtual processors dispatched
> > - * QW-3 Physical physical thread context and security context
> > - */
> > -#define XIVE_TM_RING_COUNT 4
> > -#define XIVE_TM_RING_SIZE 0x10
> > -
> > -typedef struct XiveTCTX {
> > - DeviceState parent_obj;
> > -
> > - CPUState *cs;
> > - qemu_irq output;
> > -
> > - uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
> > -} XiveTCTX;
> > -
> > /*
> > * XIVE Thread Interrupt Management Aera (TIMA)
> > *
> > diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> > index d391177ab81f..136d872f16bc 100644
> > --- a/hw/intc/spapr_xive.c
> > +++ b/hw/intc/spapr_xive.c
> > @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
> > g_assert_not_reached();
> > }
> >
> > +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> > +{
> > + PowerPCCPU *cpu = POWERPC_CPU(cs);
> > +
> > + return cpu->tctx;
> > +}
> > +
> > static const VMStateDescription vmstate_spapr_xive_end = {
> > .name = TYPE_SPAPR_XIVE "/end",
> > .version_id = 1,
> > @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
> > xrc->write_end = spapr_xive_write_end;
> > xrc->get_nvt = spapr_xive_get_nvt;
> > xrc->write_nvt = spapr_xive_write_nvt;
> > + xrc->get_tctx = spapr_xive_get_tctx;
> > }
> >
> > static const TypeInfo spapr_xive_info = {
> > diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> > index 7f567a57d25a..2e9b8efd4342 100644
> > --- a/hw/intc/xive.c
> > +++ b/hw/intc/xive.c
> > @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
> > static void xive_tm_write(void *opaque, hwaddr offset,
> > uint64_t value, unsigned size)
> > {
> > - PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> > - XiveTCTX *tctx = cpu->tctx;
> > + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> > const XiveTmOp *xto;
> >
> > /*
> > @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset,
> >
> > static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
> > {
> > - PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
> > - XiveTCTX *tctx = cpu->tctx;
> > + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> > const XiveTmOp *xto;
> >
> > /*
> > @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> > return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
> > }
> >
> > +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
> > +{
> > + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
> > +
> > + return xrc->get_tctx(xrtr, cs);
> > +}
> > +
> > /*
> > * The thread context register words are in big-endian format.
> > */
> > @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
> > */
> >
> > CPU_FOREACH(cs) {
> > - PowerPCCPU *cpu = POWERPC_CPU(cs);
> > - XiveTCTX *tctx = cpu->tctx;
> > + XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
> > int ring;
> >
> > /*
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data
2019-01-17 8:14 ` Greg Kurz
@ 2019-01-26 2:31 ` David Gibson
0 siblings, 0 replies; 16+ messages in thread
From: David Gibson @ 2019-01-26 2:31 UTC (permalink / raw)
To: Greg Kurz; +Cc: Cédric Le Goater, Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 9367 bytes --]
On Thu, Jan 17, 2019 at 09:14:26AM +0100, Greg Kurz wrote:
> On Thu, 17 Jan 2019 08:53:26 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
> > Next step is to remove them from under the PowerPCCPU
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
Applied, thanks.
>
> > include/hw/ppc/spapr_cpu_core.h | 2 ++
> > hw/intc/spapr_xive.c | 3 ++-
> > hw/intc/xics_spapr.c | 11 ++++++-----
> > hw/ppc/spapr.c | 2 +-
> > hw/ppc/spapr_cpu_core.c | 8 ++++----
> > hw/ppc/spapr_irq.c | 17 ++++++++++-------
> > 6 files changed, 25 insertions(+), 18 deletions(-)
> >
> > diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
> > index 9e2821e4b31f..d64f86bc284e 100644
> > --- a/include/hw/ppc/spapr_cpu_core.h
> > +++ b/include/hw/ppc/spapr_cpu_core.h
> > @@ -46,6 +46,8 @@ typedef struct sPAPRCPUState {
> > uint64_t vpa_addr;
> > uint64_t slb_shadow_addr, slb_shadow_size;
> > uint64_t dtl_addr, dtl_size;
> > + struct ICPState *icp;
> > + struct XiveTCTX *tctx;
> > } sPAPRCPUState;
> >
> > static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU *cpu)
> > diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> > index 136d872f16bc..a0f5ff929447 100644
> > --- a/hw/intc/spapr_xive.c
> > +++ b/hw/intc/spapr_xive.c
> > @@ -16,6 +16,7 @@
> > #include "monitor/monitor.h"
> > #include "hw/ppc/fdt.h"
> > #include "hw/ppc/spapr.h"
> > +#include "hw/ppc/spapr_cpu_core.h"
> > #include "hw/ppc/spapr_xive.h"
> > #include "hw/ppc/xive.h"
> > #include "hw/ppc/xive_regs.h"
> > @@ -394,7 +395,7 @@ static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> > {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > - return cpu->tctx;
> > + return spapr_cpu_state(cpu)->tctx;
> > }
> >
> > static const VMStateDescription vmstate_spapr_xive_end = {
> > diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> > index de6cc15b6474..e2d8b3818336 100644
> > --- a/hw/intc/xics_spapr.c
> > +++ b/hw/intc/xics_spapr.c
> > @@ -31,6 +31,7 @@
> > #include "trace.h"
> > #include "qemu/timer.h"
> > #include "hw/ppc/spapr.h"
> > +#include "hw/ppc/spapr_cpu_core.h"
> > #include "hw/ppc/xics.h"
> > #include "hw/ppc/xics_spapr.h"
> > #include "hw/ppc/fdt.h"
> > @@ -45,7 +46,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > {
> > target_ulong cppr = args[0];
> >
> > - icp_set_cppr(cpu->icp, cppr);
> > + icp_set_cppr(spapr_cpu_state(cpu)->icp, cppr);
> > return H_SUCCESS;
> > }
> >
> > @@ -66,7 +67,7 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > target_ulong opcode, target_ulong *args)
> > {
> > - uint32_t xirr = icp_accept(cpu->icp);
> > + uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
> >
> > args[0] = xirr;
> > return H_SUCCESS;
> > @@ -75,7 +76,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > target_ulong opcode, target_ulong *args)
> > {
> > - uint32_t xirr = icp_accept(cpu->icp);
> > + uint32_t xirr = icp_accept(spapr_cpu_state(cpu)->icp);
> >
> > args[0] = xirr;
> > args[1] = cpu_get_host_ticks();
> > @@ -87,7 +88,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > {
> > target_ulong xirr = args[0];
> >
> > - icp_eoi(cpu->icp, xirr);
> > + icp_eoi(spapr_cpu_state(cpu)->icp, xirr);
> > return H_SUCCESS;
> > }
> >
> > @@ -95,7 +96,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> > target_ulong opcode, target_ulong *args)
> > {
> > uint32_t mfrr;
> > - uint32_t xirr = icp_ipoll(cpu->icp, &mfrr);
> > + uint32_t xirr = icp_ipoll(spapr_cpu_state(cpu)->icp, &mfrr);
> >
> > args[0] = xirr;
> > args[1] = mfrr;
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 83081defde4e..181f994c87a7 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -3896,7 +3896,7 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
> > {
> > PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
> >
> > - return cpu ? cpu->icp : NULL;
> > + return cpu ? spapr_cpu_state(cpu)->icp : NULL;
> > }
> >
> > static void spapr_pic_print_info(InterruptStatsProvider *obj,
> > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> > index 0405306d1e59..ef6cbb9c2943 100644
> > --- a/hw/ppc/spapr_cpu_core.c
> > +++ b/hw/ppc/spapr_cpu_core.c
> > @@ -194,11 +194,11 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
> > vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
> > }
> > qemu_unregister_reset(spapr_cpu_reset, cpu);
> > - if (cpu->icp) {
> > - object_unparent(OBJECT(cpu->icp));
> > + if (spapr_cpu_state(cpu)->icp) {
> > + object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
> > }
> > - if (cpu->tctx) {
> > - object_unparent(OBJECT(cpu->tctx));
> > + if (spapr_cpu_state(cpu)->tctx) {
> > + object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
> > }
> > cpu_remove_sync(CPU(cpu));
> > object_unparent(OBJECT(cpu));
> > diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
> > index 1da7a32348fc..2d7a7c163876 100644
> > --- a/hw/ppc/spapr_irq.c
> > +++ b/hw/ppc/spapr_irq.c
> > @@ -12,6 +12,7 @@
> > #include "qemu/error-report.h"
> > #include "qapi/error.h"
> > #include "hw/ppc/spapr.h"
> > +#include "hw/ppc/spapr_cpu_core.h"
> > #include "hw/ppc/spapr_xive.h"
> > #include "hw/ppc/xics.h"
> > #include "hw/ppc/xics_spapr.h"
> > @@ -185,7 +186,7 @@ static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
> > CPU_FOREACH(cs) {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > - icp_pic_print_info(cpu->icp, mon);
> > + icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
> > }
> >
> > ics_pic_print_info(spapr->ics, mon);
> > @@ -196,6 +197,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> > {
> > Error *local_err = NULL;
> > Object *obj;
> > + sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
> >
> > obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
> > &local_err);
> > @@ -204,7 +206,7 @@ static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
> > return;
> > }
> >
> > - cpu->icp = ICP(obj);
> > + spapr_cpu->icp = ICP(obj);
> > }
> >
> > static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
> > @@ -213,7 +215,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
> > CPUState *cs;
> > CPU_FOREACH(cs) {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> > - icp_resend(cpu->icp);
> > + icp_resend(spapr_cpu_state(cpu)->icp);
> > }
> > }
> > return 0;
> > @@ -334,7 +336,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
> > CPU_FOREACH(cs) {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > - xive_tctx_pic_print_info(cpu->tctx, mon);
> > + xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
> > }
> >
> > spapr_xive_pic_print_info(spapr->xive, mon);
> > @@ -345,6 +347,7 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> > {
> > Error *local_err = NULL;
> > Object *obj;
> > + sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
> >
> > obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
> > if (local_err) {
> > @@ -352,13 +355,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
> > return;
> > }
> >
> > - cpu->tctx = XIVE_TCTX(obj);
> > + spapr_cpu->tctx = XIVE_TCTX(obj);
> >
> > /*
> > * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
> > * don't beneficiate from the reset of the XIVE IRQ backend
> > */
> > - spapr_xive_set_tctx_os_cam(cpu->tctx);
> > + spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
> > }
> >
> > static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
> > @@ -374,7 +377,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > /* (TCG) Set the OS CAM line of the thread interrupt context. */
> > - spapr_xive_set_tctx_os_cam(cpu->tctx);
> > + spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
> > }
> >
> > /* Activate the XIVE MMIOs */
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data
2019-01-17 8:13 ` Greg Kurz
@ 2019-01-26 2:37 ` David Gibson
0 siblings, 0 replies; 16+ messages in thread
From: David Gibson @ 2019-01-26 2:37 UTC (permalink / raw)
To: Greg Kurz; +Cc: Cédric Le Goater, Thomas Huth, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4278 bytes --]
On Thu, Jan 17, 2019 at 09:13:02AM +0100, Greg Kurz wrote:
> On Thu, 17 Jan 2019 08:53:25 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
> > Include the interrupt presenter under the machine_data as we plan to
> > remove it from under PowerPCCPU
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
Applied, thanks.
>
> > include/hw/ppc/pnv_core.h | 9 +++++++++
> > hw/ppc/pnv.c | 7 ++++---
> > hw/ppc/pnv_core.c | 12 +++++++++++-
> > 3 files changed, 24 insertions(+), 4 deletions(-)
> >
> > diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> > index 447ae761f7ae..9961ea3a92cd 100644
> > --- a/include/hw/ppc/pnv_core.h
> > +++ b/include/hw/ppc/pnv_core.h
> > @@ -47,4 +47,13 @@ typedef struct PnvCoreClass {
> > #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
> > #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
> >
> > +typedef struct PnvCPUState {
> > + struct ICPState *icp;
> > +} PnvCPUState;
> > +
> > +static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
> > +{
> > + return (PnvCPUState *)cpu->machine_data;
> > +}
> > +
> > #endif /* _PPC_PNV_CORE_H */
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index d84acef55b69..da540860a2b0 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -673,6 +673,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> > {
> > Error *local_err = NULL;
> > Object *obj;
> > + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> >
> > obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
> > &local_err);
> > @@ -681,7 +682,7 @@ static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
> > return;
> > }
> >
> > - cpu->icp = ICP(obj);
> > + pnv_cpu->icp = ICP(obj);
> > }
> >
> > /*
> > @@ -1099,7 +1100,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
> > {
> > PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
> >
> > - return cpu ? cpu->icp : NULL;
> > + return cpu ? pnv_cpu_state(cpu)->icp : NULL;
> > }
> >
> > static void pnv_pic_print_info(InterruptStatsProvider *obj,
> > @@ -1112,7 +1113,7 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj,
> > CPU_FOREACH(cs) {
> > PowerPCCPU *cpu = POWERPC_CPU(cs);
> >
> > - icp_pic_print_info(cpu->icp, mon);
> > + icp_pic_print_info(pnv_cpu_state(cpu)->icp, mon);
> > }
> >
> > for (i = 0; i < pnv->num_chips; i++) {
> > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> > index b98f277f1e02..7c806da720c6 100644
> > --- a/hw/ppc/pnv_core.c
> > +++ b/hw/ppc/pnv_core.c
> > @@ -155,7 +155,10 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
> >
> > pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
> > for (i = 0; i < cc->nr_threads; i++) {
> > + PowerPCCPU *cpu;
> > +
> > obj = object_new(typename);
> > + cpu = POWERPC_CPU(obj);
> >
> > pc->threads[i] = POWERPC_CPU(obj);
> >
> > @@ -163,6 +166,9 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
> > object_property_add_child(OBJECT(pc), name, obj, &error_abort);
> > object_property_add_alias(obj, "core-pir", OBJECT(pc),
> > "pir", &error_abort);
> > +
> > + cpu->machine_data = g_new0(PnvCPUState, 1);
> > +
> > object_unref(obj);
> > }
> >
> > @@ -189,9 +195,13 @@ err:
> >
> > static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
> > {
> > + PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
> > +
> > qemu_unregister_reset(pnv_cpu_reset, cpu);
> > - object_unparent(OBJECT(cpu->icp));
> > + object_unparent(OBJECT(pnv_cpu_state(cpu)->icp));
> > cpu_remove_sync(CPU(cpu));
> > + cpu->machine_data = NULL;
> > + g_free(pnv_cpu);
> > object_unparent(OBJECT(cpu));
> > }
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-01-27 1:32 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-17 7:53 [Qemu-devel] [PATCH 0/4] ppc: move the interrupt presenters under the CPU machine_data Cédric Le Goater
2019-01-17 7:53 ` [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter Cédric Le Goater
2019-01-17 8:12 ` Greg Kurz
2019-01-26 2:29 ` David Gibson
2019-01-17 7:53 ` [Qemu-devel] [PATCH 2/4] ppc/pnv: introduce a CPU machine_data Cédric Le Goater
2019-01-17 8:13 ` Greg Kurz
2019-01-26 2:37 ` David Gibson
2019-01-17 7:53 ` [Qemu-devel] [PATCH 3/4] spapr: move the interrupt presenters under machine_data Cédric Le Goater
2019-01-17 8:14 ` Greg Kurz
2019-01-26 2:31 ` David Gibson
2019-01-17 7:53 ` [Qemu-devel] [PATCH 4/4] ppc: remove the interrupt presenters from under PowerPCCPU Cédric Le Goater
2019-01-17 8:20 ` Greg Kurz
2019-01-17 8:23 ` Thomas Huth
2019-01-17 8:26 ` Cédric Le Goater
2019-01-17 9:00 ` [Qemu-devel] [PATCH v6] ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 mode Thomas Huth
2019-01-17 9:20 ` Greg Kurz
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