* [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
@ 2019-01-16 18:03 ` Jordan Crouse
0 siblings, 0 replies; 8+ messages in thread
From: Jordan Crouse @ 2019-01-16 18:03 UTC (permalink / raw)
To: freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dianders-F7+t8E8rja9g9hUCZPvPmw, David Brown, Rob Herring,
Andy Gross
Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
---
This has the following dependencies:
[v11,1/9] dt-bindings: opp: Introduce opp-level bindings
https://patchwork.kernel.org/patch/10755199/
And the following patches already in Rob's msm-next:
msm-next:d1c9cadea6f7 ("drm/msm/gpu: Remove hardcoded interrupt name")
msm-next:b08b92546807 ("drm/msm: drop interrupt-names")
msm-next:24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings")
And finally drm/msm: Fix A6XX support for opp-level
https://patchwork.freedesktop.org/patch/276756/
Which is not merged because it too depends on Rajendra's stack.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index f07c4ca..90766fc 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1618,6 +1618,127 @@
};
};
+
+ gpu@5000000 {
+ compatible = "qcom,adreno-630.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+ /*
+ * Look ma, no clocks! The GPU clocks and power are
+ * controlled entirely by the GMU
+ */
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-710000000 {
+ opp-hz = /bits/ 64 <710000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-675000000 {
+ opp-hz = /bits/ 64 <675000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-596000000 {
+ opp-hz = /bits/ 64 <596000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-520000000 {
+ opp-hz = /bits/ 64 <520000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-414000000 {
+ opp-hz = /bits/ 64 <414000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-257000000 {
+ opp-hz = /bits/ 64 <257000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+ reg = <0x5040000 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>;
+ clock-names = "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+ reg = <0x506a000 0x30000>,
+ <0xb280000 0x10000>,
+ <0xb480000 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x10000>;
--
2.7.4
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
@ 2019-01-16 18:03 ` Jordan Crouse
0 siblings, 0 replies; 8+ messages in thread
From: Jordan Crouse @ 2019-01-16 18:03 UTC (permalink / raw)
To: freedreno
Cc: linux-arm-msm, rnayak, dianders, dri-devel, devicetree,
linux-kernel, Andy Gross, Rob Herring, David Brown, Mark Rutland
Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
---
This has the following dependencies:
[v11,1/9] dt-bindings: opp: Introduce opp-level bindings
https://patchwork.kernel.org/patch/10755199/
And the following patches already in Rob's msm-next:
msm-next:d1c9cadea6f7 ("drm/msm/gpu: Remove hardcoded interrupt name")
msm-next:b08b92546807 ("drm/msm: drop interrupt-names")
msm-next:24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings")
And finally drm/msm: Fix A6XX support for opp-level
https://patchwork.freedesktop.org/patch/276756/
Which is not merged because it too depends on Rajendra's stack.
arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index f07c4ca..90766fc 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1618,6 +1618,127 @@
};
};
+
+ gpu@5000000 {
+ compatible = "qcom,adreno-630.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+ /*
+ * Look ma, no clocks! The GPU clocks and power are
+ * controlled entirely by the GMU
+ */
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-710000000 {
+ opp-hz = /bits/ 64 <710000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-675000000 {
+ opp-hz = /bits/ 64 <675000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-596000000 {
+ opp-hz = /bits/ 64 <596000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-520000000 {
+ opp-hz = /bits/ 64 <520000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-414000000 {
+ opp-hz = /bits/ 64 <414000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-257000000 {
+ opp-hz = /bits/ 64 <257000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+ reg = <0x5040000 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>;
+ clock-names = "bus", "iface";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
+
+ reg = <0x506a000 0x30000>,
+ <0xb280000 0x10000>,
+ <0xb480000 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x10000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
2019-01-16 18:03 ` Jordan Crouse
@ 2019-01-16 19:13 ` Doug Anderson
-1 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2019-01-16 19:13 UTC (permalink / raw)
To: Jordan Crouse
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Rajendra Nayak,
linux-arm-msm, LKML, dri-devel, David Brown, Rob Herring,
Andy Gross, freedreno
Hi,
On Wed, Jan 16, 2019 at 10:03 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
> ---
> This has the following dependencies:
>
> [v11,1/9] dt-bindings: opp: Introduce opp-level bindings
> https://patchwork.kernel.org/patch/10755199/
>
> And the following patches already in Rob's msm-next:
> msm-next:d1c9cadea6f7 ("drm/msm/gpu: Remove hardcoded interrupt name")
> msm-next:b08b92546807 ("drm/msm: drop interrupt-names")
> msm-next:24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings")
>
> And finally drm/msm: Fix A6XX support for opp-level
> https://patchwork.freedesktop.org/patch/276756/
>
> Which is not merged because it too depends on Rajendra's stack.
Newer version:
https://lore.kernel.org/patchwork/patch/1032724/
...that one should be able to land earlier since it's simpler.
---
Don't forget that your patch also depends on:
https://lkml.kernel.org/r/20181128185743.75328-2-dianders@chromium.org
...because you won't compile unless gpucc is there.
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++++++++++
> 1 file changed, 121 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index f07c4ca..90766fc 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1618,6 +1618,127 @@
> };
> };
>
> +
> + gpu@5000000 {
Heads up to Andy that when this lands it should be re-sorted to be
right before gpucc so that the unit addresses are sorted. :-) ...and
while doing that we can make sure there's not an extra blank line.
-Doug
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
@ 2019-01-16 19:13 ` Doug Anderson
0 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2019-01-16 19:13 UTC (permalink / raw)
To: Jordan Crouse
Cc: freedreno, linux-arm-msm, Rajendra Nayak, dri-devel, devicetree,
LKML, Andy Gross, Rob Herring, David Brown, Mark Rutland
Hi,
On Wed, Jan 16, 2019 at 10:03 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
>
> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
> ---
> This has the following dependencies:
>
> [v11,1/9] dt-bindings: opp: Introduce opp-level bindings
> https://patchwork.kernel.org/patch/10755199/
>
> And the following patches already in Rob's msm-next:
> msm-next:d1c9cadea6f7 ("drm/msm/gpu: Remove hardcoded interrupt name")
> msm-next:b08b92546807 ("drm/msm: drop interrupt-names")
> msm-next:24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings")
>
> And finally drm/msm: Fix A6XX support for opp-level
> https://patchwork.freedesktop.org/patch/276756/
>
> Which is not merged because it too depends on Rajendra's stack.
Newer version:
https://lore.kernel.org/patchwork/patch/1032724/
...that one should be able to land earlier since it's simpler.
---
Don't forget that your patch also depends on:
https://lkml.kernel.org/r/20181128185743.75328-2-dianders@chromium.org
...because you won't compile unless gpucc is there.
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++++++++++
> 1 file changed, 121 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index f07c4ca..90766fc 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1618,6 +1618,127 @@
> };
> };
>
> +
> + gpu@5000000 {
Heads up to Andy that when this lands it should be re-sorted to be
right before gpucc so that the unit addresses are sorted. :-) ...and
while doing that we can make sure there's not an extra blank line.
-Doug
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
2019-01-16 18:03 ` Jordan Crouse
@ 2019-01-17 23:15 ` Doug Anderson
-1 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2019-01-17 23:15 UTC (permalink / raw)
To: Jordan Crouse, Andy Gross, Bjorn Andersson
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Rajendra Nayak,
linux-arm-msm, LKML, dri-devel, David Brown, Rob Herring,
freedreno
Hi,
On Wed, Jan 16, 2019 at 10:03 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> + gpu@5000000 {
> + compatible = "qcom,adreno-630.2", "qcom,adreno";
> + #stream-id-cells = <16>;
> +
> + reg = <0x5000000 0x40000>, <0x509e000 0x10>;
This will now need to be adjusted to:
reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
This fixes things up to deal with the patch ("arm64: dts: qcom:
sdm845: Increase address and size cells for soc"), AKA:
- https://patchwork.kernel.org/patch/10767511/
- https://lkml.kernel.org/r/20190117042940.25487-2-bjorn.andersson@linaro.org
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
> + reg = <0x5040000 0x10000>;
This one to:
reg = <0 0x05040000 0 0x10000>;
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
> +
> + reg = <0x506a000 0x30000>,
> + <0xb280000 0x10000>,
> + <0xb480000 0x10000>;
This one to:
reg = <0 0x0506a000 0 0x30000>,
<0 0x0b280000 0 0x10000>,
<0 0x0b480000 0 0x10000>;
In the email:
https://lkml.kernel.org/r/20190117192955.16515-1-bjorn.andersson@linaro.org
...Bjorn provided a link to a github tree that should be OK to use as
a basis for sending a new patch. Specifically
<https://github.com/andersson/kernel/commits/for-andy/arm64-for-5.1>.
That tree not only has the address-cells / size-cells change but also
has gpucc.
-Doug
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
@ 2019-01-17 23:15 ` Doug Anderson
0 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2019-01-17 23:15 UTC (permalink / raw)
To: Jordan Crouse, Andy Gross, Bjorn Andersson
Cc: freedreno, linux-arm-msm, Rajendra Nayak, dri-devel, devicetree,
LKML, Rob Herring, David Brown, Mark Rutland
Hi,
On Wed, Jan 16, 2019 at 10:03 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
> + gpu@5000000 {
> + compatible = "qcom,adreno-630.2", "qcom,adreno";
> + #stream-id-cells = <16>;
> +
> + reg = <0x5000000 0x40000>, <0x509e000 0x10>;
This will now need to be adjusted to:
reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
This fixes things up to deal with the patch ("arm64: dts: qcom:
sdm845: Increase address and size cells for soc"), AKA:
- https://patchwork.kernel.org/patch/10767511/
- https://lkml.kernel.org/r/20190117042940.25487-2-bjorn.andersson@linaro.org
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
> + reg = <0x5040000 0x10000>;
This one to:
reg = <0 0x05040000 0 0x10000>;
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
> +
> + reg = <0x506a000 0x30000>,
> + <0xb280000 0x10000>,
> + <0xb480000 0x10000>;
This one to:
reg = <0 0x0506a000 0 0x30000>,
<0 0x0b280000 0 0x10000>,
<0 0x0b480000 0 0x10000>;
In the email:
https://lkml.kernel.org/r/20190117192955.16515-1-bjorn.andersson@linaro.org
...Bjorn provided a link to a github tree that should be OK to use as
a basis for sending a new patch. Specifically
<https://github.com/andersson/kernel/commits/for-andy/arm64-for-5.1>.
That tree not only has the address-cells / size-cells change but also
has gpucc.
-Doug
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
2019-01-16 18:03 ` Jordan Crouse
@ 2019-01-21 1:49 ` kbuild test robot
-1 siblings, 0 replies; 8+ messages in thread
From: kbuild test robot @ 2019-01-21 1:49 UTC (permalink / raw)
To: Jordan Crouse
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dianders-F7+t8E8rja9g9hUCZPvPmw, David Brown, Rob Herring,
kbuild-all-JC7UmRfGjtg, Andy Gross,
freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi Jordan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v5.0-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jordan-Crouse/arm64-dts-sdm845-Add-gpu-and-gmu-device-nodes/20190118-051651
config: arm64-allyesconfig
compiler: aarch64-linux-gnu-gcc (Debian 8.2.0-11) 8.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
GCC_VERSION=8.2.0 make.cross ARCH=arm64 allyesconfig
GCC_VERSION=8.2.0 make.cross ARCH=arm64
All errors (new ones prefixed by >>):
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes
@ 2019-01-21 1:49 ` kbuild test robot
0 siblings, 0 replies; 8+ messages in thread
From: kbuild test robot @ 2019-01-21 1:49 UTC (permalink / raw)
To: Jordan Crouse
Cc: kbuild-all, freedreno, Mark Rutland, devicetree, rnayak,
linux-arm-msm, linux-kernel, dri-devel, dianders, David Brown,
Rob Herring, Andy Gross
Hi Jordan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v5.0-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jordan-Crouse/arm64-dts-sdm845-Add-gpu-and-gmu-device-nodes/20190118-051651
config: arm64-allyesconfig
compiler: aarch64-linux-gnu-gcc (Debian 8.2.0-11) 8.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
GCC_VERSION=8.2.0 make.cross ARCH=arm64 allyesconfig
GCC_VERSION=8.2.0 make.cross ARCH=arm64
All errors (new ones prefixed by >>):
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-01-21 7:11 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-16 18:03 [PATCH v8] arm64: dts: sdm845: Add gpu and gmu device nodes Jordan Crouse
2019-01-16 18:03 ` Jordan Crouse
[not found] ` <1547661809-31184-1-git-send-email-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2019-01-16 19:13 ` Doug Anderson
2019-01-16 19:13 ` Doug Anderson
2019-01-17 23:15 ` Doug Anderson
2019-01-17 23:15 ` Doug Anderson
2019-01-21 1:49 ` kbuild test robot
2019-01-21 1:49 ` kbuild test robot
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