[PATCH v3 0/5] net: Add support for Qualcomm ethqos

[PATCH v3 0/5] net: Add support for Qualcomm ethqos

[Vinod Koul]

Some Qualcomm SoCs sport a ethqos controller which use DW ip, so add
the glue driver which uses stmmac driver along with DT bindings for
this device.

This controller supports rgmii mode and doesn't work with existing
phy drivers as they do not remove the phy delay delay in this mode,
so fix the two phy drivers tested with this.

Changes in v3:
 - Add description in DT and rename the file and compatible as suggested by
   Rob
 - Update changelog for QCA8K driver
 - Update AT803x phy disable delay for all RGMxx modes

Changes in v2:
 - Fix the example in dt-binding
 - Remove DT property for disable the delay and disable delay for RGMII mode
   in AT803x and QCA8K PHY drivers

Vinod Koul (5):
  dt-bindings: net: Add Qualcomm ethqos binding
  net: stmmac: Add driver for Qualcomm ethqos
  MAINTAINER: Add entry for Qualcomm ETHQOS ethernet driver
  net: phy: at803x: Disable phy delay for RGMII mode
  net: dsa: qca8k: disable delay for RGMII mode

 .../devicetree/bindings/net/qcom,ethqos.txt   |  64 ++
 MAINTAINERS                                   |   8 +
 drivers/net/dsa/qca8k.c                       |  16 +-
 drivers/net/ethernet/stmicro/stmmac/Kconfig   |  10 +
 drivers/net/ethernet/stmicro/stmmac/Makefile  |   1 +
 .../stmicro/stmmac/dwmac-qcom-ethqos.c        | 545 ++++++++++++++++++
 drivers/net/phy/at803x.c                      |  22 +-
 7 files changed, 644 insertions(+), 22 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/qcom,ethqos.txt
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

-- 
2.20.1

[PATCH v3 1/5] dt-bindings: net: Add Qualcomm ethqos binding

[Vinod Koul]

Add support for Qualcomm ethqos found in some SoCs like QCS404.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 .../devicetree/bindings/net/qcom,ethqos.txt   | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/qcom,ethqos.txt

diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.txt b/Documentation/devicetree/bindings/net/qcom,ethqos.txt
new file mode 100644
index 000000000000..fcf5035810b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qcom,ethqos.txt
@@ -0,0 +1,64 @@
+Qualcomm Ethernet ETHQOS device
+
+This documents dwmmac based ethernet device which supports Gigabit
+ethernet for version v2.3.0 onwards.
+
+This device has following properties:
+
+Required properties:
+
+- compatible: Should be qcom,qcs404-ethqos"
+
+- reg: Address and length of the register set for the device
+
+- reg-names: Should contain register names "stmmaceth", "rgmii"
+
+- clocks: Should contain phandle to clocks
+
+- clock-names: Should contain clock names "stmmaceth", "pclk",
+		"ptp_ref", "rgmii"
+
+- interrupts: Should contain phandle to interrupts
+
+- interrupt-names: Should contain interrupt names "macirq", "eth_lpi"
+
+Rest of the properties are defined in stmmac.txt file in same directory
+
+
+Example:
+
+ethernet: ethernet@7a80000 {
+	compatible = "qcom,qcs404-ethqos";
+	reg = <0x07a80000 0x10000>,
+		<0x07a96000 0x100>;
+	reg-names = "stmmaceth", "rgmii";
+	clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+	clocks = <&gcc GCC_ETH_AXI_CLK>,
+		<&gcc GCC_ETH_SLAVE_AHB_CLK>,
+		<&gcc GCC_ETH_PTP_CLK>,
+		<&gcc GCC_ETH_RGMII_CLK>;
+	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "macirq", "eth_lpi";
+	snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+
+	snps,txpbl = <8>;
+	snps,rxpbl = <2>;
+	snps,aal;
+	snps,tso;
+
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii";
+
+	mdio {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		compatible = "snps,dwmac-mdio";
+		phy1: phy@4 {
+			device_type = "ethernet-phy";
+			reg = <0x4>;
+		};
+	};
+
+};
-- 
2.20.1

[PATCH v3 2/5] net: stmmac: Add driver for Qualcomm ethqos

[Vinod Koul]

Add glue driver to support Qualcomm ETHQOS using stmmac driver.

This is based on downstream driver written by Siddarth Gupta, Sunil
Kumar Paidimarri, Rahul Ankushrao Kawadgave, Nisha Menon, Jagadeesh
Babu Challagundla, Chaitanya Pratapa, Lakshit Tyagi, Suraj Jaiswal,
Sneh Shah and Ventrapragada Ravi Kanth

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/Kconfig   |  10 +
 drivers/net/ethernet/stmicro/stmmac/Makefile  |   1 +
 .../stmicro/stmmac/dwmac-qcom-ethqos.c        | 545 ++++++++++++++++++
 3 files changed, 556 insertions(+)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 6209cc1fb305..f194235153f9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -105,6 +105,16 @@ config DWMAC_OXNAS
 	  This selects the Oxford Semiconductor OXNASSoC glue layer support for
 	  the stmmac device driver. This driver is used for OX820.
 
+config DWMAC_QCOM_ETHQOS
+	tristate "Qualcomm ETHQOS support"
+	default ARCH_QCOM
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
+	help
+	  Support for the Qualcomm ETHQOS core.
+
+	  This selects the Qualcomm ETHQOS glue layer support for the
+	  stmmac device driver.
+
 config DWMAC_ROCKCHIP
 	tristate "Rockchip dwmac support"
 	default ARCH_ROCKCHIP
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index bf09701d2623..c529c21e9bdd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_LPC18XX)	+= dwmac-lpc18xx.o
 obj-$(CONFIG_DWMAC_MEDIATEK)	+= dwmac-mediatek.o
 obj-$(CONFIG_DWMAC_MESON)	+= dwmac-meson.o dwmac-meson8b.o
 obj-$(CONFIG_DWMAC_OXNAS)	+= dwmac-oxnas.o
+obj-$(CONFIG_DWMAC_QCOM_ETHQOS)	+= dwmac-qcom-ethqos.o
 obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rk.o
 obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
 obj-$(CONFIG_DWMAC_STI)		+= dwmac-sti.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
new file mode 100644
index 000000000000..30724bd330f4
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-19, Linaro Limited
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+#include "stmmac.h"
+#include "stmmac_platform.h"
+
+#define RGMII_IO_MACRO_CONFIG		0x0
+#define SDCC_HC_REG_DLL_CONFIG		0x4
+#define SDCC_HC_REG_DDR_CONFIG		0xC
+#define SDCC_HC_REG_DLL_CONFIG2		0x10
+#define SDC4_STATUS			0x14
+#define SDCC_USR_CTL			0x18
+#define RGMII_IO_MACRO_CONFIG2		0x1C
+#define RGMII_IO_MACRO_DEBUG1		0x20
+#define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28
+
+/* RGMII_IO_MACRO_CONFIG fields */
+#define RGMII_CONFIG_FUNC_CLK_EN		BIT(30)
+#define RGMII_CONFIG_POS_NEG_DATA_SEL		BIT(23)
+#define RGMII_CONFIG_GPIO_CFG_RX_INT		GENMASK(21, 20)
+#define RGMII_CONFIG_GPIO_CFG_TX_INT		GENMASK(19, 17)
+#define RGMII_CONFIG_MAX_SPD_PRG_9		GENMASK(16, 8)
+#define RGMII_CONFIG_MAX_SPD_PRG_2		GENMASK(7, 6)
+#define RGMII_CONFIG_INTF_SEL			GENMASK(5, 4)
+#define RGMII_CONFIG_BYPASS_TX_ID_EN		BIT(3)
+#define RGMII_CONFIG_LOOPBACK_EN		BIT(2)
+#define RGMII_CONFIG_PROG_SWAP			BIT(1)
+#define RGMII_CONFIG_DDR_MODE			BIT(0)
+
+/* SDCC_HC_REG_DLL_CONFIG fields */
+#define SDCC_DLL_CONFIG_DLL_RST			BIT(30)
+#define SDCC_DLL_CONFIG_PDN			BIT(29)
+#define SDCC_DLL_CONFIG_MCLK_FREQ		GENMASK(26, 24)
+#define SDCC_DLL_CONFIG_CDR_SELEXT		GENMASK(23, 20)
+#define SDCC_DLL_CONFIG_CDR_EXT_EN		BIT(19)
+#define SDCC_DLL_CONFIG_CK_OUT_EN		BIT(18)
+#define SDCC_DLL_CONFIG_CDR_EN			BIT(17)
+#define SDCC_DLL_CONFIG_DLL_EN			BIT(16)
+#define SDCC_DLL_MCLK_GATING_EN			BIT(5)
+#define SDCC_DLL_CDR_FINE_PHASE			GENMASK(3, 2)
+
+/* SDCC_HC_REG_DDR_CONFIG fields */
+#define SDCC_DDR_CONFIG_PRG_DLY_EN		BIT(31)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	GENMASK(26, 21)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	GENMASK(29, 27)
+#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN	BIT(30)
+#define SDCC_DDR_CONFIG_PRG_RCLK_DLY		GENMASK(8, 0)
+
+/* SDCC_HC_REG_DLL_CONFIG2 fields */
+#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS		BIT(21)
+#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC		GENMASK(17, 10)
+#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	GENMASK(3, 2)
+#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW	BIT(1)
+#define SDCC_DLL_CONFIG2_DDR_CAL_EN		BIT(0)
+
+/* SDC4_STATUS bits */
+#define SDC4_STATUS_DLL_LOCK			BIT(7)
+
+/* RGMII_IO_MACRO_CONFIG2 fields */
+#define RGMII_CONFIG2_RSVD_CONFIG15		GENMASK(31, 17)
+#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG		BIT(16)
+#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN	BIT(13)
+#define RGMII_CONFIG2_CLK_DIVIDE_SEL		BIT(12)
+#define RGMII_CONFIG2_RX_PROG_SWAP		BIT(7)
+#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	BIT(6)
+#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	BIT(5)
+
+struct ethqos_emac_por {
+	unsigned int offset;
+	unsigned int value;
+};
+
+struct qcom_ethqos {
+	struct platform_device *pdev;
+	void __iomem *rgmii_base;
+
+	unsigned int rgmii_clk_rate;
+	struct clk *rgmii_clk;
+	unsigned int speed;
+
+	const struct ethqos_emac_por *por;
+	unsigned int num_por;
+};
+
+static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
+{
+	return readl(ethqos->rgmii_base + offset);
+}
+
+static void rgmii_writel(struct qcom_ethqos *ethqos,
+			 int value, unsigned int offset)
+{
+	writel(value, ethqos->rgmii_base + offset);
+}
+
+static void rgmii_updatel(struct qcom_ethqos *ethqos,
+			  int mask, int val, unsigned int offset)
+{
+	unsigned int temp;
+
+	temp =  rgmii_readl(ethqos, offset);
+	temp = (temp & ~(mask)) | val;
+	rgmii_writel(ethqos, temp, offset);
+}
+
+static void rgmii_dump(struct qcom_ethqos *ethqos)
+{
+	dev_dbg(&ethqos->pdev->dev, "Rgmii register dump\n");
+	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
+		rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
+	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
+		rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
+	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
+		rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
+	dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
+		rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
+	dev_dbg(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
+		rgmii_readl(ethqos, SDC4_STATUS));
+	dev_dbg(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
+		rgmii_readl(ethqos, SDCC_USR_CTL));
+	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
+		rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
+	dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
+		rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
+	dev_dbg(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
+		rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
+}
+
+/* Clock rates */
+#define RGMII_1000_NOM_CLK_FREQ			(250 * 1000 * 1000UL)
+#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ	 (50 * 1000 * 1000UL)
+#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ	  (5 * 1000 * 1000UL)
+
+static void
+ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
+{
+	switch (speed) {
+	case SPEED_1000:
+		ethqos->rgmii_clk_rate =  RGMII_1000_NOM_CLK_FREQ;
+		break;
+
+	case SPEED_100:
+		ethqos->rgmii_clk_rate =  RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
+		break;
+
+	case SPEED_10:
+		ethqos->rgmii_clk_rate =  RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
+		break;
+	}
+
+	clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
+}
+
+static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
+{
+	rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
+		      RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
+}
+
+static const struct ethqos_emac_por emac_v2_3_0_por[] = {
+	{ .offset = RGMII_IO_MACRO_CONFIG,	.value = 0x00C01343 },
+	{ .offset = SDCC_HC_REG_DLL_CONFIG,	.value = 0x2004642C },
+	{ .offset = SDCC_HC_REG_DDR_CONFIG,	.value = 0x00000000 },
+	{ .offset = SDCC_HC_REG_DLL_CONFIG2,	.value = 0x00200000 },
+	{ .offset = SDCC_USR_CTL,		.value = 0x00010800 },
+	{ .offset = RGMII_IO_MACRO_CONFIG2,	.value = 0x00002060 },
+};
+
+static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
+{
+	unsigned int val;
+	int retry = 1000;
+
+	/* Set CDR_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
+		      SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Set CDR_EXT_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
+		      SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Clear CK_OUT_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
+		      0, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Set DLL_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
+		      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
+
+	rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
+		      0, SDCC_HC_REG_DLL_CONFIG);
+
+	rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
+		      0, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Wait for CK_OUT_EN clear */
+	do {
+		val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
+		val &= SDCC_DLL_CONFIG_CK_OUT_EN;
+		if (!val)
+			break;
+		mdelay(1);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		dev_err(&ethqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
+
+	/* Set CK_OUT_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
+		      SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Wait for CK_OUT_EN set */
+	retry = 1000;
+	do {
+		val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
+		val &= SDCC_DLL_CONFIG_CK_OUT_EN;
+		if (val)
+			break;
+		mdelay(1);
+		retry--;
+	} while (retry > 0);
+	if (!retry)
+		dev_err(&ethqos->pdev->dev, "Set CK_OUT_EN timedout\n");
+
+	/* Set DDR_CAL_EN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
+		      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
+
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
+		      0, SDCC_HC_REG_DLL_CONFIG2);
+
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
+		      0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
+
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
+		      BIT(2), SDCC_HC_REG_DLL_CONFIG2);
+
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
+		      SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
+		      SDCC_HC_REG_DLL_CONFIG2);
+
+	return 0;
+}
+
+static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
+{
+	/* Disable loopback mode */
+	rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
+		      0, RGMII_IO_MACRO_CONFIG2);
+
+	/* Select RGMII, write 0 to interface select */
+	rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
+		      0, RGMII_IO_MACRO_CONFIG);
+
+	switch (ethqos->speed) {
+	case SPEED_1000:
+		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
+			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+			      0, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
+			      RGMII_CONFIG_POS_NEG_DATA_SEL,
+			      RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
+			      RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
+			      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
+			      RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
+			      RGMII_CONFIG2_RX_PROG_SWAP,
+			      RGMII_IO_MACRO_CONFIG2);
+
+		/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
+			      57, SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
+			      SDCC_DDR_CONFIG_PRG_DLY_EN,
+			      SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+		break;
+
+	case SPEED_100:
+		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
+			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+			      RGMII_CONFIG_BYPASS_TX_ID_EN,
+			      RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
+			      0, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
+			      0, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
+			      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
+			      RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
+			      BIT(6), RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		/* Write 0x5 to PRG_RCLK_DLY_CODE */
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+			      SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+			      SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+		break;
+
+	case SPEED_10:
+		rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
+			      RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+			      RGMII_CONFIG_BYPASS_TX_ID_EN,
+			      RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
+			      0, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
+			      0, RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
+			      BIT(12) | GENMASK(9, 8),
+			      RGMII_IO_MACRO_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
+			      0, RGMII_IO_MACRO_CONFIG2);
+		/* Write 0x5 to PRG_RCLK_DLY_CODE */
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+			      (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+			      SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+			      SDCC_HC_REG_DDR_CONFIG);
+		rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+			      RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+		break;
+	default:
+		dev_err(&ethqos->pdev->dev,
+			"Invalid speed %d\n", ethqos->speed);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ethqos_configure(struct qcom_ethqos *ethqos)
+{
+	volatile unsigned int dll_lock;
+	unsigned int i, retry = 1000;
+
+	/* Reset to POR values and enable clk */
+	for (i = 0; i < ethqos->num_por; i++)
+		rgmii_writel(ethqos, ethqos->por[i].value,
+			     ethqos->por[i].offset);
+	ethqos_set_func_clk_en(ethqos);
+
+	/* Initialize the DLL first */
+
+	/* Set DLL_RST */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
+		      SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Set PDN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
+		      SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
+
+	/* Clear DLL_RST */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
+		      SDCC_HC_REG_DLL_CONFIG);
+
+	/* Clear PDN */
+	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
+		      SDCC_HC_REG_DLL_CONFIG);
+
+	if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
+		/* Set DLL_EN */
+		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
+			      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
+
+		/* Set CK_OUT_EN */
+		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
+			      SDCC_DLL_CONFIG_CK_OUT_EN,
+			      SDCC_HC_REG_DLL_CONFIG);
+
+		/* Set USR_CTL bit 26 with mask of 3 bits */
+		rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
+
+		/* wait for DLL LOCK */
+		do {
+			mdelay(1);
+			dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
+			if (dll_lock & SDC4_STATUS_DLL_LOCK)
+				break;
+		} while (retry > 0);
+		if (!retry)
+			dev_err(&ethqos->pdev->dev,
+				"Timeout while waiting for DLL lock\n");
+	}
+
+	if (ethqos->speed == SPEED_1000)
+		ethqos_dll_configure(ethqos);
+
+	ethqos_rgmii_macro_init(ethqos);
+
+	return 0;
+}
+
+static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
+{
+	struct qcom_ethqos *ethqos = priv;
+
+	ethqos->speed = speed;
+	ethqos_update_rgmii_clk(ethqos, speed);
+	ethqos_configure(ethqos);
+}
+
+static int qcom_ethqos_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct plat_stmmacenet_data *plat_dat;
+	struct stmmac_resources stmmac_res;
+	struct qcom_ethqos *ethqos;
+	struct resource *res;
+	int ret;
+
+	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+	if (ret)
+		return ret;
+
+	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
+	if (IS_ERR(plat_dat)) {
+		dev_err(&pdev->dev, "dt configuration failed\n");
+		return PTR_ERR(plat_dat);
+	}
+
+	ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
+	if (!ethqos) {
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	ethqos->pdev = pdev;
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rgmii");
+	ethqos->rgmii_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(ethqos->rgmii_base)) {
+		dev_err(&pdev->dev, "Can't get rgmii base\n");
+		ret = PTR_ERR(ethqos->rgmii_base);
+		goto err_mem;
+	}
+
+	ethqos->por = of_device_get_match_data(&pdev->dev);
+
+	ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
+	if (!ethqos->rgmii_clk) {
+		ret = -ENOMEM;
+		goto err_mem;
+	}
+
+	ret = clk_prepare_enable(ethqos->rgmii_clk);
+	if (ret)
+		goto err_mem;
+
+	ethqos->speed = SPEED_1000;
+	ethqos_update_rgmii_clk(ethqos, SPEED_1000);
+	ethqos_set_func_clk_en(ethqos);
+
+	plat_dat->bsp_priv = ethqos;
+	plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
+	plat_dat->has_gmac4 = 1;
+	plat_dat->pmt = 1;
+	plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
+
+	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+	if (ret)
+		goto err_clk;
+
+	rgmii_dump(ethqos);
+
+	return ret;
+
+err_clk:
+	clk_disable_unprepare(ethqos->rgmii_clk);
+
+err_mem:
+	stmmac_remove_config_dt(pdev, plat_dat);
+
+	return ret;
+}
+
+static int qcom_ethqos_remove(struct platform_device *pdev)
+{
+	struct qcom_ethqos *ethqos;
+	int ret;
+
+	ethqos = get_stmmac_bsp_priv(&pdev->dev);
+	if (!ethqos)
+		return -ENODEV;
+
+	ret = stmmac_pltfr_remove(pdev);
+	clk_disable_unprepare(ethqos->rgmii_clk);
+
+	return ret;
+}
+
+static const struct of_device_id qcom_ethqos_match[] = {
+	{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_por},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
+
+static struct platform_driver qcom_ethqos_driver = {
+	.probe  = qcom_ethqos_probe,
+	.remove = qcom_ethqos_remove,
+	.driver = {
+		.name           = "qcom-ethqos",
+		.pm		= &stmmac_pltfr_pm_ops,
+		.of_match_table = of_match_ptr(qcom_ethqos_match),
+	},
+};
+module_platform_driver(qcom_ethqos_driver);
+
+MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
+MODULE_LICENSE("GPL v2");
-- 
2.20.1

[PATCH v3 3/5] MAINTAINER: Add entry for Qualcomm ETHQOS ethernet driver

[Vinod Koul]

Add myself and Niklas as maintainers for this driver

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 32d444476a90..b0af43cda327 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12605,6 +12605,14 @@ L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/qualcomm/emac/
 
+QUALCOMM ETHQOS ETHERNET DRIVER
+M:	Vinod Koul <vkoul@kernel.org>
+M:	Niklas Cassel <niklas.cassel@linaro.org>
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+F:	Documentation/devicetree/bindings/net/qcom,dwmac.txt
+
 QUALCOMM GENERIC INTERFACE I2C DRIVER
 M:	Alok Chauhan <alokc@codeaurora.org>
 M:	Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
-- 
2.20.1

[PATCH v3 4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Vinod Koul]

For RGMII mode, phy delay should be disabled. Add this case along
with disable delay routines.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/net/phy/at803x.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
index f9432d053a22..8ff12938ab47 100644
--- a/drivers/net/phy/at803x.c
+++ b/drivers/net/phy/at803x.c
@@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
 	return phy_write(phydev, AT803X_DEBUG_DATA, val);
 }
 
-static inline int at803x_enable_rx_delay(struct phy_device *phydev)
+static inline int at803x_disable_rx_delay(struct phy_device *phydev)
 {
-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
-					AT803X_DEBUG_RX_CLK_DLY_EN);
+	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
+				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 }
 
-static inline int at803x_enable_tx_delay(struct phy_device *phydev)
+static inline int at803x_disable_tx_delay(struct phy_device *phydev)
 {
-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
-					AT803X_DEBUG_TX_CLK_DLY_EN);
+	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
+				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 }
 
 /* save relevant PHY registers to private copy */
@@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
 		return ret;
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-		ret = at803x_enable_rx_delay(phydev);
+			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+		ret = at803x_disable_rx_delay(phydev);
 		if (ret < 0)
 			return ret;
 	}
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
-			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-		ret = at803x_enable_tx_delay(phydev);
+			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+		ret = at803x_disable_tx_delay(phydev);
 		if (ret < 0)
 			return ret;
 	}
-- 
2.20.1

[PATCH v3 5/5] net: dsa: qca8k: disable delay for RGMII mode

[Vinod Koul]

In RGMII mode we should not have any delay in port MAC, so disable
the delay.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/net/dsa/qca8k.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7e97e620bd44..a4b6cda38016 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -420,7 +420,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
 static int
 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 {
-	u32 reg;
+	u32 reg, val;
 
 	switch (port) {
 	case 0:
@@ -439,17 +439,9 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 	 */
 	switch (mode) {
 	case PHY_INTERFACE_MODE_RGMII:
-		qca8k_write(priv, reg,
-			    QCA8K_PORT_PAD_RGMII_EN |
-			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
-
-		/* According to the datasheet, RGMII delay is enabled through
-		 * PORT5_PAD_CTRL for all ports, rather than individual port
-		 * registers
-		 */
-		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
+		/* RGMII mode means no delay so don't enable the delay */
+		val = QCA8K_PORT_PAD_RGMII_EN;
+		qca8k_write(priv, reg, val);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
-- 
2.20.1

Re: [PATCH v3 1/5] dt-bindings: net: Add Qualcomm ethqos binding

[Rob Herring]

On Mon, 21 Jan 2019 14:43:14 +0530, Vinod Koul wrote:
> Add support for Qualcomm ethqos found in some SoCs like QCS404.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../devicetree/bindings/net/qcom,ethqos.txt   | 64 +++++++++++++++++++
>  1 file changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/qcom,ethqos.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 1/5] dt-bindings: net: Add Qualcomm ethqos binding

[Rob Herring]

On Mon, 21 Jan 2019 14:43:14 +0530, Vinod Koul wrote:
> Add support for Qualcomm ethqos found in some SoCs like QCS404.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../devicetree/bindings/net/qcom,ethqos.txt   | 64 +++++++++++++++++++
>  1 file changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/qcom,ethqos.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 0/5] net: Add support for Qualcomm ethqos

[David Miller]

From: Vinod Koul <vkoul@kernel.org>
Date: Mon, 21 Jan 2019 14:43:13 +0530

> Some Qualcomm SoCs sport a ethqos controller which use DW ip, so add
> the glue driver which uses stmmac driver along with DT bindings for
> this device.
> 
> This controller supports rgmii mode and doesn't work with existing
> phy drivers as they do not remove the phy delay delay in this mode,
> so fix the two phy drivers tested with this.
> 
> Changes in v3:
>  - Add description in DT and rename the file and compatible as suggested by
>    Rob
>  - Update changelog for QCA8K driver
>  - Update AT803x phy disable delay for all RGMxx modes
> 
> Changes in v2:
>  - Fix the example in dt-binding
>  - Remove DT property for disable the delay and disable delay for RGMII mode
>    in AT803x and QCA8K PHY drivers

Series applied, thanks.

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Peter Ujfalusi]

Vinod,

On 21/01/2019 11.13, Vinod Koul wrote:
> For RGMII mode, phy delay should be disabled. Add this case along
> with disable delay routines.

In next-20190211 I need to revert this patch to get cpsw networking to work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled by the phy/at803x.c

On next-20190211:
[    3.374601] net eth0: initializing cpsw version 1.12 (0)
[    3.384484] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[    3.400041] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    3.410813] mmc1: new SDIO card at address 0001
[    3.439362] IP-Config: Complete:
[    3.442649]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
[    3.452840]      host=10.0.0.90, domain=, nis-domain=(none)
[    3.458462]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
[    3.466296] vwl1271: disabling
[    3.470195] ALSA device list:
[    3.473189]   #0: AM335x-EVMSK

After reverting this patch:
[    3.374636] net eth0: initializing cpsw version 1.12 (0)
[    3.384534] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[    3.400125] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    3.410866] mmc1: new SDIO card at address 0001
[    3.439379] IP-Config: Complete:
[    3.442666]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
[    3.452865]      host=10.0.0.90, domain=, nis-domain=(none)
[    3.458482]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
[    3.466334] vwl1271: disabling
[    3.470245] ALSA device list:
[    3.473241]   #0: AM335x-EVMSK
[    3.501052] VFS: Mounted root (nfs filesystem) readonly on device 0:15.
[    3.508694] devtmpfs: mounted
[    3.514546] Freeing unused kernel memory: 1024K
[    3.520567] Run /sbin/init as init process

and the board boots to nfsroot fine.

 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/net/phy/at803x.c | 22 ++++++++++++----------
>  1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> index f9432d053a22..8ff12938ab47 100644
> --- a/drivers/net/phy/at803x.c
> +++ b/drivers/net/phy/at803x.c
> @@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
>  	return phy_write(phydev, AT803X_DEBUG_DATA, val);
>  }
>  
> -static inline int at803x_enable_rx_delay(struct phy_device *phydev)
> +static inline int at803x_disable_rx_delay(struct phy_device *phydev)
>  {
> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
> -					AT803X_DEBUG_RX_CLK_DLY_EN);
> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
> +				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
>  }
>  
> -static inline int at803x_enable_tx_delay(struct phy_device *phydev)
> +static inline int at803x_disable_tx_delay(struct phy_device *phydev)
>  {
> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
> -					AT803X_DEBUG_TX_CLK_DLY_EN);
> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
> +				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
>  }
>  
>  /* save relevant PHY registers to private copy */
> @@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
>  		return ret;
>  
>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> -		ret = at803x_enable_rx_delay(phydev);
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> +		ret = at803x_disable_rx_delay(phydev);
>  		if (ret < 0)
>  			return ret;
>  	}
>  
>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> -		ret = at803x_enable_tx_delay(phydev);
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> +		ret = at803x_disable_tx_delay(phydev);
>  		if (ret < 0)
>  			return ret;
>  	}
> 

- Péter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Peter Ujfalusi]

Vinod,

On 21/01/2019 11.13, Vinod Koul wrote:
> For RGMII mode, phy delay should be disabled. Add this case along
> with disable delay routines.

In next-20190211 I need to revert this patch to get cpsw networking to work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled by the phy/at803x.c

On next-20190211:
[    3.374601] net eth0: initializing cpsw version 1.12 (0)
[    3.384484] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[    3.400041] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    3.410813] mmc1: new SDIO card at address 0001
[    3.439362] IP-Config: Complete:
[    3.442649]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
[    3.452840]      host=10.0.0.90, domain=, nis-domain=(none)
[    3.458462]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
[    3.466296] vwl1271: disabling
[    3.470195] ALSA device list:
[    3.473189]   #0: AM335x-EVMSK

After reverting this patch:
[    3.374636] net eth0: initializing cpsw version 1.12 (0)
[    3.384534] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[    3.400125] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    3.410866] mmc1: new SDIO card at address 0001
[    3.439379] IP-Config: Complete:
[    3.442666]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
[    3.452865]      host=10.0.0.90, domain=, nis-domain=(none)
[    3.458482]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
[    3.466334] vwl1271: disabling
[    3.470245] ALSA device list:
[    3.473241]   #0: AM335x-EVMSK
[    3.501052] VFS: Mounted root (nfs filesystem) readonly on device 0:15.
[    3.508694] devtmpfs: mounted
[    3.514546] Freeing unused kernel memory: 1024K
[    3.520567] Run /sbin/init as init process

and the board boots to nfsroot fine.

 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/net/phy/at803x.c | 22 ++++++++++++----------
>  1 file changed, 12 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> index f9432d053a22..8ff12938ab47 100644
> --- a/drivers/net/phy/at803x.c
> +++ b/drivers/net/phy/at803x.c
> @@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
>  	return phy_write(phydev, AT803X_DEBUG_DATA, val);
>  }
>  
> -static inline int at803x_enable_rx_delay(struct phy_device *phydev)
> +static inline int at803x_disable_rx_delay(struct phy_device *phydev)
>  {
> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
> -					AT803X_DEBUG_RX_CLK_DLY_EN);
> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
> +				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
>  }
>  
> -static inline int at803x_enable_tx_delay(struct phy_device *phydev)
> +static inline int at803x_disable_tx_delay(struct phy_device *phydev)
>  {
> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
> -					AT803X_DEBUG_TX_CLK_DLY_EN);
> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
> +				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
>  }
>  
>  /* save relevant PHY registers to private copy */
> @@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
>  		return ret;
>  
>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> -		ret = at803x_enable_rx_delay(phydev);
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> +		ret = at803x_disable_rx_delay(phydev);
>  		if (ret < 0)
>  			return ret;
>  	}
>  
>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> -		ret = at803x_enable_tx_delay(phydev);
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> +		ret = at803x_disable_tx_delay(phydev);
>  		if (ret < 0)
>  			return ret;
>  	}
> 

- Péter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Vinod Koul]

Hi Peter,

On 12-02-19, 12:55, Peter Ujfalusi wrote:
> Vinod,
> 
> On 21/01/2019 11.13, Vinod Koul wrote:
> > For RGMII mode, phy delay should be disabled. Add this case along
> > with disable delay routines.
> 
> In next-20190211 I need to revert this patch to get cpsw networking to
> work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled
> by the phy/at803x.c

I see that DTS specifies that you are using phy-mode = "rgmii-txid".
RGMII mode implies that we should not have any delay in the
phy, so this patch does the right thing.

In the previous version of the patch I did propose to add a DT entry so
that current users who are wrongly using this would not be impacted but
the suggestion was to get them fixed.

So in you case do you need rgmii-txd mode if so why should the delay be
enabled for this? We can add a patch that enabled delay for your
controller but that cant be rgmii mode.

Thanks


> 
> On next-20190211:
> [    3.374601] net eth0: initializing cpsw version 1.12 (0)
> [    3.384484] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
> [    3.400041] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
> [    3.410813] mmc1: new SDIO card at address 0001
> [    3.439362] IP-Config: Complete:
> [    3.442649]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
> [    3.452840]      host=10.0.0.90, domain=, nis-domain=(none)
> [    3.458462]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
> [    3.466296] vwl1271: disabling
> [    3.470195] ALSA device list:
> [    3.473189]   #0: AM335x-EVMSK
> 
> After reverting this patch:
> [    3.374636] net eth0: initializing cpsw version 1.12 (0)
> [    3.384534] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
> [    3.400125] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
> [    3.410866] mmc1: new SDIO card at address 0001
> [    3.439379] IP-Config: Complete:
> [    3.442666]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
> [    3.452865]      host=10.0.0.90, domain=, nis-domain=(none)
> [    3.458482]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
> [    3.466334] vwl1271: disabling
> [    3.470245] ALSA device list:
> [    3.473241]   #0: AM335x-EVMSK
> [    3.501052] VFS: Mounted root (nfs filesystem) readonly on device 0:15.
> [    3.508694] devtmpfs: mounted
> [    3.514546] Freeing unused kernel memory: 1024K
> [    3.520567] Run /sbin/init as init process
> 
> and the board boots to nfsroot fine.
> 
>  
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  drivers/net/phy/at803x.c | 22 ++++++++++++----------
> >  1 file changed, 12 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
> > index f9432d053a22..8ff12938ab47 100644
> > --- a/drivers/net/phy/at803x.c
> > +++ b/drivers/net/phy/at803x.c
> > @@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
> >  	return phy_write(phydev, AT803X_DEBUG_DATA, val);
> >  }
> >  
> > -static inline int at803x_enable_rx_delay(struct phy_device *phydev)
> > +static inline int at803x_disable_rx_delay(struct phy_device *phydev)
> >  {
> > -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
> > -					AT803X_DEBUG_RX_CLK_DLY_EN);
> > +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
> > +				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
> >  }
> >  
> > -static inline int at803x_enable_tx_delay(struct phy_device *phydev)
> > +static inline int at803x_disable_tx_delay(struct phy_device *phydev)
> >  {
> > -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
> > -					AT803X_DEBUG_TX_CLK_DLY_EN);
> > +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
> > +				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
> >  }
> >  
> >  /* save relevant PHY registers to private copy */
> > @@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
> >  		return ret;
> >  
> >  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
> > -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> > -		ret = at803x_enable_rx_delay(phydev);
> > +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> > +		ret = at803x_disable_rx_delay(phydev);
> >  		if (ret < 0)
> >  			return ret;
> >  	}
> >  
> >  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
> > -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
> > -		ret = at803x_enable_tx_delay(phydev);
> > +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
> > +		ret = at803x_disable_tx_delay(phydev);
> >  		if (ret < 0)
> >  			return ret;
> >  	}
> > 
> 
> - Péter
> 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

-- 
~Vinod

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Peter Ujfalusi]

Hi Vinod,

On 12/02/2019 13.31, Vinod Koul wrote:
> Hi Peter,
> 
> On 12-02-19, 12:55, Peter Ujfalusi wrote:
>> Vinod,
>>
>> On 21/01/2019 11.13, Vinod Koul wrote:
>>> For RGMII mode, phy delay should be disabled. Add this case along
>>> with disable delay routines.
>>
>> In next-20190211 I need to revert this patch to get cpsw networking to
>> work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled
>> by the phy/at803x.c
> 
> I see that DTS specifies that you are using phy-mode = "rgmii-txid".
> RGMII mode implies that we should not have any delay in the
> phy, so this patch does the right thing.

Right, on am335x-evmsk:
[    3.393406] at803x_config_init: phydev->interface: 11
So PHY_INTERFACE_MODE_RGMII_TXID.

> In the previous version of the patch I did propose to add a DT entry so
> that current users who are wrongly using this would not be impacted but
> the suggestion was to get them fixed.
> 
> So in you case do you need rgmii-txd mode if so why should the delay be
> enabled for this? We can add a patch that enabled delay for your
> controller but that cant be rgmii mode.

I'm not too familiar with the networking, but the AR8031 datasheet does
tell that the debug_5:bit8 is 0 by default (rgmii tx clock delay disable).

In the errata document of am335x (http://www.ti.com/lit/pdf/sprz360),
1.0.10 I believe tells that the delay needs to be enabled on the rgmii
ethernet PHY because the internal delay is not working (?) and advises
that the delay might need to be enabled on the rgmii PHY.

The PHY_INTERFACE_MODE_RGMII_TXID delay was enabled in the PHY driver
since 2013 (1ca6d1b1aef4628ff0fe458135ddb008d134ad8f)

To me it looks like that when AR8031 is used with am335x the 'rgmii tx
clock delay' needs to be enabled.

Sekhar, Roger: any insights, thoughts?

> 
> Thanks
> 
> 
>>
>> On next-20190211:
>> [    3.374601] net eth0: initializing cpsw version 1.12 (0)
>> [    3.384484] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
>> [    3.400041] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
>> [    3.410813] mmc1: new SDIO card at address 0001
>> [    3.439362] IP-Config: Complete:
>> [    3.442649]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
>> [    3.452840]      host=10.0.0.90, domain=, nis-domain=(none)
>> [    3.458462]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
>> [    3.466296] vwl1271: disabling
>> [    3.470195] ALSA device list:
>> [    3.473189]   #0: AM335x-EVMSK
>>
>> After reverting this patch:
>> [    3.374636] net eth0: initializing cpsw version 1.12 (0)
>> [    3.384534] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
>> [    3.400125] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
>> [    3.410866] mmc1: new SDIO card at address 0001
>> [    3.439379] IP-Config: Complete:
>> [    3.442666]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
>> [    3.452865]      host=10.0.0.90, domain=, nis-domain=(none)
>> [    3.458482]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
>> [    3.466334] vwl1271: disabling
>> [    3.470245] ALSA device list:
>> [    3.473241]   #0: AM335x-EVMSK
>> [    3.501052] VFS: Mounted root (nfs filesystem) readonly on device 0:15.
>> [    3.508694] devtmpfs: mounted
>> [    3.514546] Freeing unused kernel memory: 1024K
>> [    3.520567] Run /sbin/init as init process
>>
>> and the board boots to nfsroot fine.
>>
>>  
>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>> ---
>>>  drivers/net/phy/at803x.c | 22 ++++++++++++----------
>>>  1 file changed, 12 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
>>> index f9432d053a22..8ff12938ab47 100644
>>> --- a/drivers/net/phy/at803x.c
>>> +++ b/drivers/net/phy/at803x.c
>>> @@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
>>>  	return phy_write(phydev, AT803X_DEBUG_DATA, val);
>>>  }
>>>  
>>> -static inline int at803x_enable_rx_delay(struct phy_device *phydev)
>>> +static inline int at803x_disable_rx_delay(struct phy_device *phydev)
>>>  {
>>> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
>>> -					AT803X_DEBUG_RX_CLK_DLY_EN);
>>> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
>>> +				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
>>>  }
>>>  
>>> -static inline int at803x_enable_tx_delay(struct phy_device *phydev)
>>> +static inline int at803x_disable_tx_delay(struct phy_device *phydev)
>>>  {
>>> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
>>> -					AT803X_DEBUG_TX_CLK_DLY_EN);
>>> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
>>> +				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
>>>  }
>>>  
>>>  /* save relevant PHY registers to private copy */
>>> @@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
>>>  		return ret;
>>>  
>>>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
>>> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
>>> -		ret = at803x_enable_rx_delay(phydev);
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
>>> +		ret = at803x_disable_rx_delay(phydev);
>>>  		if (ret < 0)
>>>  			return ret;
>>>  	}
>>>  
>>>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
>>> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
>>> -		ret = at803x_enable_tx_delay(phydev);
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
>>> +		ret = at803x_disable_tx_delay(phydev);
>>>  		if (ret < 0)
>>>  			return ret;
>>>  	}
>>>
>>
>> - Péter
>>
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 

- Péter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Peter Ujfalusi]

Hi Vinod,

On 12/02/2019 13.31, Vinod Koul wrote:
> Hi Peter,
> 
> On 12-02-19, 12:55, Peter Ujfalusi wrote:
>> Vinod,
>>
>> On 21/01/2019 11.13, Vinod Koul wrote:
>>> For RGMII mode, phy delay should be disabled. Add this case along
>>> with disable delay routines.
>>
>> In next-20190211 I need to revert this patch to get cpsw networking to
>> work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled
>> by the phy/at803x.c
> 
> I see that DTS specifies that you are using phy-mode = "rgmii-txid".
> RGMII mode implies that we should not have any delay in the
> phy, so this patch does the right thing.

Right, on am335x-evmsk:
[    3.393406] at803x_config_init: phydev->interface: 11
So PHY_INTERFACE_MODE_RGMII_TXID.

> In the previous version of the patch I did propose to add a DT entry so
> that current users who are wrongly using this would not be impacted but
> the suggestion was to get them fixed.
> 
> So in you case do you need rgmii-txd mode if so why should the delay be
> enabled for this? We can add a patch that enabled delay for your
> controller but that cant be rgmii mode.

I'm not too familiar with the networking, but the AR8031 datasheet does
tell that the debug_5:bit8 is 0 by default (rgmii tx clock delay disable).

In the errata document of am335x (http://www.ti.com/lit/pdf/sprz360),
1.0.10 I believe tells that the delay needs to be enabled on the rgmii
ethernet PHY because the internal delay is not working (?) and advises
that the delay might need to be enabled on the rgmii PHY.

The PHY_INTERFACE_MODE_RGMII_TXID delay was enabled in the PHY driver
since 2013 (1ca6d1b1aef4628ff0fe458135ddb008d134ad8f)

To me it looks like that when AR8031 is used with am335x the 'rgmii tx
clock delay' needs to be enabled.

Sekhar, Roger: any insights, thoughts?

> 
> Thanks
> 
> 
>>
>> On next-20190211:
>> [    3.374601] net eth0: initializing cpsw version 1.12 (0)
>> [    3.384484] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
>> [    3.400041] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
>> [    3.410813] mmc1: new SDIO card at address 0001
>> [    3.439362] IP-Config: Complete:
>> [    3.442649]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
>> [    3.452840]      host=10.0.0.90, domain=, nis-domain=(none)
>> [    3.458462]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
>> [    3.466296] vwl1271: disabling
>> [    3.470195] ALSA device list:
>> [    3.473189]   #0: AM335x-EVMSK
>>
>> After reverting this patch:
>> [    3.374636] net eth0: initializing cpsw version 1.12 (0)
>> [    3.384534] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
>> [    3.400125] cpsw 4a100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
>> [    3.410866] mmc1: new SDIO card at address 0001
>> [    3.439379] IP-Config: Complete:
>> [    3.442666]      device=eth0, hwaddr=bc:6a:29:7d:2c:a9, ipaddr=10.0.0.90, mask=255.255.255.0, gw=10.0.0.1
>> [    3.452865]      host=10.0.0.90, domain=, nis-domain=(none)
>> [    3.458482]      bootserver=10.0.0.30, rootserver=10.0.0.30, rootpath=
>> [    3.466334] vwl1271: disabling
>> [    3.470245] ALSA device list:
>> [    3.473241]   #0: AM335x-EVMSK
>> [    3.501052] VFS: Mounted root (nfs filesystem) readonly on device 0:15.
>> [    3.508694] devtmpfs: mounted
>> [    3.514546] Freeing unused kernel memory: 1024K
>> [    3.520567] Run /sbin/init as init process
>>
>> and the board boots to nfsroot fine.
>>
>>  
>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>> ---
>>>  drivers/net/phy/at803x.c | 22 ++++++++++++----------
>>>  1 file changed, 12 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
>>> index f9432d053a22..8ff12938ab47 100644
>>> --- a/drivers/net/phy/at803x.c
>>> +++ b/drivers/net/phy/at803x.c
>>> @@ -110,16 +110,16 @@ static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
>>>  	return phy_write(phydev, AT803X_DEBUG_DATA, val);
>>>  }
>>>  
>>> -static inline int at803x_enable_rx_delay(struct phy_device *phydev)
>>> +static inline int at803x_disable_rx_delay(struct phy_device *phydev)
>>>  {
>>> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
>>> -					AT803X_DEBUG_RX_CLK_DLY_EN);
>>> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
>>> +				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
>>>  }
>>>  
>>> -static inline int at803x_enable_tx_delay(struct phy_device *phydev)
>>> +static inline int at803x_disable_tx_delay(struct phy_device *phydev)
>>>  {
>>> -	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
>>> -					AT803X_DEBUG_TX_CLK_DLY_EN);
>>> +	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
>>> +				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
>>>  }
>>>  
>>>  /* save relevant PHY registers to private copy */
>>> @@ -256,15 +256,17 @@ static int at803x_config_init(struct phy_device *phydev)
>>>  		return ret;
>>>  
>>>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
>>> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
>>> -		ret = at803x_enable_rx_delay(phydev);
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
>>> +		ret = at803x_disable_rx_delay(phydev);
>>>  		if (ret < 0)
>>>  			return ret;
>>>  	}
>>>  
>>>  	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
>>> -			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
>>> -		ret = at803x_enable_tx_delay(phydev);
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
>>> +			phydev->interface == PHY_INTERFACE_MODE_RGMII) {
>>> +		ret = at803x_disable_tx_delay(phydev);
>>>  		if (ret < 0)
>>>  			return ret;
>>>  	}
>>>
>>
>> - Péter
>>
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 

- Péter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Vinod Koul]

Hi again,

On 12-02-19, 17:01, Vinod Koul wrote:
> Hi Peter,
> 
> On 12-02-19, 12:55, Peter Ujfalusi wrote:
> > Vinod,
> > 
> > On 21/01/2019 11.13, Vinod Koul wrote:
> > > For RGMII mode, phy delay should be disabled. Add this case along
> > > with disable delay routines.
> > 
> > In next-20190211 I need to revert this patch to get cpsw networking to
> > work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is handled
> > by the phy/at803x.c
> 
> I see that DTS specifies that you are using phy-mode = "rgmii-txid".
> RGMII mode implies that we should not have any delay in the
> phy, so this patch does the right thing.
> 
> In the previous version of the patch I did propose to add a DT entry so
> that current users who are wrongly using this would not be impacted but
> the suggestion was to get them fixed.
> 
> So in you case do you need rgmii-txd mode if so why should the delay be
> enabled for this? We can add a patch that enabled delay for your
> controller but that cant be rgmii mode.

Relooking at this again and seeing the mode definitions in
Documentation/devicetree/bindings/net/ethernet.txt,
I think I have got it wrong.. (thanks to Niklas for discussion)

So in case of rgmii mode delay should be disabled and in case of
rgmii-id/rxid/txid it should be enabled. I will send a patch to address
this shortly, please do test.

Thanks
-- 
~Vinod

Re: [v3,4/5] net: phy: at803x: Disable phy delay for RGMII mode

[Marc Gonzalez]

On 12/02/2019 11:55, Peter Ujfalusi wrote:

> On 21/01/2019 11.13, Vinod Koul wrote:
> 
>> For RGMII mode, phy delay should be disabled. Add this case along 
>> with disable delay routines.
> 
> In next-20190211 I need to revert this patch to get cpsw networking
> to work on am335x-evmsk. The board uses AR8031_AL1A PHY, which is
> handled by the phy/at803x.c

I'm having flashbacks:

[PATCH 1/2] net: phy: at803x: Fix RGMII RX and TX clock delays setup
https://www.spinics.net/lists/netdev/msg445053.html

Quirks of the Atheros 8035 PHY
https://www.spinics.net/lists/netdev/msg444527.html

See also
http://patchwork.ozlabs.org/project/netdev/list/?submitter=67482&state=*

Regards.