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From: Patchwork <patchwork@emeril.freedesktop.org>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for Define MOCS table for Icelake (rev2)
Date: Tue, 22 Jan 2019 05:22:31 -0000	[thread overview]
Message-ID: <20190122052231.12974.74608@emeril.freedesktop.org> (raw)
In-Reply-To: <20190122051227.8329-1-lucas.demarchi@intel.com>

== Series Details ==

Series: Define MOCS table for Icelake (rev2)
URL   : https://patchwork.freedesktop.org/series/54070/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
42a8e03cdfa2 drm/i915: initialize unused MOCS entries to PTE
392416ee2864 drm/i915: Simplify MOCS table definition
d732afcb4803 drm/i915/skl: Rework MOCS tables to keep common part in a define
75c2a9d1ab5d drm/i915: use a macro to define MOCS entries
-:63: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#63: FILE: drivers/gpu/drm/i915/intel_mocs.c:111:
+	MOCS_ENTRY(I915_MOCS_CACHED,	LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+					L3_3_WB)

-:76: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#76: FILE: drivers/gpu/drm/i915/intel_mocs.c:118:
+	MOCS_ENTRY(I915_MOCS_CACHED,	LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
+					L3_3_WB)

total: 0 errors, 0 warnings, 2 checks, 60 lines checked
c0f65453147a drm/i915: keep track of used entries in MOCS table
9ace3442d5cf drm/i915: cache number of MOCS entries
d4f7316f00e2 drm/i915/icl: Define MOCS table for Icelake
-:92: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#92: FILE: drivers/gpu/drm/i915/intel_mocs.c:131:
+#define GEN11_MOCS_ENTRIES \
+	/* Base - Uncached (Deprecated) */ \
+	MOCS_ENTRY(I915_MOCS_UNCACHED,	LE_1_UC | LE_TC_1_LLC, \
+					L3_1_UC), \
+	/* Base - L3 + LeCC:PAT (Deprecated) */ \
+	MOCS_ENTRY(I915_MOCS_PTE,	LE_0_PAGETABLE | LE_TC_1_LLC, \
+					L3_3_WB), \
+	/* Base - L3 + LLC */ \
+	MOCS_ENTRY(2,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+			L3_3_WB), \
+	/* Base - Uncached */ \
+	MOCS_ENTRY(3,	LE_1_UC | LE_TC_1_LLC, \
+			L3_1_UC), \
+	/* Base - L3 */ \
+	MOCS_ENTRY(4,	LE_1_UC | LE_TC_1_LLC, \
+			L3_3_WB), \
+	/* Base - LLC */ \
+	MOCS_ENTRY(5,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+			L3_1_UC), \
+	/* Age 0 - LLC */ \
+	MOCS_ENTRY(6,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
+			L3_1_UC), \
+	/* Age 0 - L3 + LLC */ \
+	MOCS_ENTRY(7,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
+			L3_3_WB), \
+	/* Age: Don't Chg. - LLC */ \
+	MOCS_ENTRY(8,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
+			L3_1_UC), \
+	/* Age: Don't Chg. - L3 + LLC */ \
+	MOCS_ENTRY(9,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
+			L3_3_WB), \
+	/* No AOM - LLC */ \
+	MOCS_ENTRY(10,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
+			L3_1_UC), \
+	/* No AOM - L3 + LLC */ \
+	MOCS_ENTRY(11,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
+			L3_3_WB), \
+	/* No AOM; Age 0 - LLC */ \
+	MOCS_ENTRY(12,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
+			L3_1_UC), \
+	/* No AOM; Age 0 - L3 + LLC */ \
+	MOCS_ENTRY(13,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
+			L3_3_WB), \
+	/* No AOM; Age:DC - LLC */ \
+	MOCS_ENTRY(14,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
+			L3_1_UC), \
+	/* No AOM; Age:DC - L3 + LLC */ \
+	MOCS_ENTRY(15,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
+			L3_3_WB), \
+	/* Self-Snoop - L3 + LLC */ \
+	MOCS_ENTRY(18,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
+			L3_3_WB), \
+	/* Skip Caching - L3 + LLC(12.5%) */ \
+	MOCS_ENTRY(19,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
+			L3_3_WB), \
+	/* Skip Caching - L3 + LLC(25%) */ \
+	MOCS_ENTRY(20,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
+			L3_3_WB), \
+	/* Skip Caching - L3 + LLC(50%) */ \
+	MOCS_ENTRY(21,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
+			L3_3_WB), \
+	/* Skip Caching - L3 + LLC(75%) */ \
+	MOCS_ENTRY(22,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
+			L3_3_WB), \
+	/* Skip Caching - L3 + LLC(87.5%) */ \
+	MOCS_ENTRY(23,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
+			L3_3_WB), \
+	/* HW Reserved - SW program but never use */ \
+	MOCS_ENTRY(62,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+			L3_1_UC), \
+	/* HW Reserved - SW program but never use */ \
+	MOCS_ENTRY(63,	LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+			L3_1_UC), \
+

total: 1 errors, 0 warnings, 0 checks, 142 lines checked

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  parent reply	other threads:[~2019-01-22  5:22 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-22  5:12 [PATCH v8 0/7] Define MOCS table for Icelake Lucas De Marchi
2019-01-22  5:12 ` [PATCH v8 1/7] drm/i915: initialize unused MOCS entries to PTE Lucas De Marchi
2019-01-22 14:28   ` Chris Wilson
2019-01-23 18:33   ` Lis, Tomasz
2019-01-23 18:39     ` Lucas De Marchi
2019-01-22  5:12 ` [PATCH v8 2/7] drm/i915: Simplify MOCS table definition Lucas De Marchi
2019-01-23 18:34   ` Lis, Tomasz
2019-01-22  5:12 ` [PATCH v8 3/7] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
2019-01-22 14:30   ` Chris Wilson
2019-01-23 18:34   ` Lis, Tomasz
2019-01-22  5:12 ` [PATCH v8 4/7] drm/i915: use a macro to define MOCS entries Lucas De Marchi
2019-01-22 14:32   ` Chris Wilson
2019-01-22 21:33     ` Lucas De Marchi
2019-01-22 21:37       ` Chris Wilson
2019-01-23 18:51         ` Lucas De Marchi
2019-01-23 18:43   ` Lis, Tomasz
2019-01-22  5:12 ` [PATCH v8 5/7] drm/i915: keep track of used entries in MOCS table Lucas De Marchi
2019-01-22 14:40   ` Chris Wilson
2019-01-23 21:50     ` Lucas De Marchi
2019-01-23 18:48   ` Lis, Tomasz
2019-01-22  5:12 ` [PATCH v8 6/7] drm/i915: cache number of MOCS entries Lucas De Marchi
2019-01-22 14:34   ` Chris Wilson
2019-01-23 19:02   ` Lis, Tomasz
2019-01-22  5:12 ` [PATCH v8 7/7] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
2019-01-23 19:07   ` Lis, Tomasz
2019-01-22  5:22 ` Patchwork [this message]
2019-01-22  5:40 ` ✓ Fi.CI.BAT: success for Define MOCS table for Icelake (rev2) Patchwork
2019-01-22  6:49 ` ✓ Fi.CI.IGT: " Patchwork

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