* [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit
@ 2019-01-22 15:59 Ram Pai
2019-01-22 23:36 ` Paul Mackerras
0 siblings, 1 reply; 2+ messages in thread
From: Ram Pai @ 2019-01-22 15:59 UTC (permalink / raw)
To: kvm-ppc
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
MSR_S bit enables access to secure memory.
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1c98ef1..3c3588a 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@
#define MSR_TM_LG 32 /* Trans Mem Available */
#define MSR_VEC_LG 25 /* Enable AltiVec */
#define MSR_VSX_LG 23 /* Enable VSX */
+#define MSR_S_LG 22 /* Secure VM bit */
#define MSR_POW_LG 18 /* Enable Power Management */
#define MSR_WE_LG 18 /* Wait State Enable */
#define MSR_TGPR_LG 17 /* TLB Update registers in use */
@@ -71,11 +72,13 @@
#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
+#define MSR_S __MASK(MSR_S_LG) /* Secure state */
#else
/* so tests for these bits fail on 32-bit */
#define MSR_SF 0
#define MSR_ISF 0
#define MSR_HV 0
+#define MSR_S 0
#endif
/*
--
1.8.3.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit
2019-01-22 15:59 [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit Ram Pai
@ 2019-01-22 23:36 ` Paul Mackerras
0 siblings, 0 replies; 2+ messages in thread
From: Paul Mackerras @ 2019-01-22 23:36 UTC (permalink / raw)
To: kvm-ppc
On Tue, Jan 22, 2019 at 07:59:34AM -0800, Ram Pai wrote:
> From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>
> MSR_S bit enables access to secure memory.
I would like to see a bit more commentary here that explains that the
hypervisor doesn't (and can't) run with the MSR_S bit set, but a
secure guest and the ultravisor do.
> Signed-off-by: Ram Pai <linuxram@us.ibm.com>
> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Nit: signoffs are in the wrong order.
Paul.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-01-22 23:36 ` Paul Mackerras
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