* [PATCH] drm/i915/gvt: switch to kernel types
@ 2019-01-21 9:51 Jani Nikula
2019-01-21 10:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Jani Nikula @ 2019-01-21 9:51 UTC (permalink / raw)
To: intel-gvt-dev; +Cc: jani.nikula, intel-gfx
Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +++++++-------
drivers/gpu/drm/i915/gvt/handlers.c | 6 +++---
drivers/gpu/drm/i915/gvt/kvmgt.c | 24 ++++++++++++------------
drivers/gpu/drm/i915/gvt/mmio.c | 6 +++---
drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
6 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 77ae634eb11c..bac014031c4b 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -399,10 +399,10 @@ struct cmd_info {
#define R_VECS (1 << VECS)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
- uint16_t rings;
+ u16 rings;
/* devices that support this cmd: SNB/IVB/HSW/... */
- uint16_t devices;
+ u16 devices;
/* which DWords are address that need fix up.
* bit 0 means a 32-bit non address operand in command
@@ -412,13 +412,13 @@ struct cmd_info {
* No matter the address length, each address only takes
* one bit in the bitmap.
*/
- uint16_t addr_bitmap;
+ u16 addr_bitmap;
/* flag == F_LEN_CONST : command length
* flag == F_LEN_VAR : length bias bits
* Note: length is in DWord
*/
- uint8_t len;
+ u8 len;
parser_cmd_handler handler;
};
@@ -1644,7 +1644,7 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
{
unsigned long gma = 0;
struct cmd_info *info;
- uint32_t cmd_len = 0;
+ u32 cmd_len = 0;
bool bb_end = false;
struct intel_vgpu *vgpu = s->vgpu;
u32 cmd;
@@ -2683,7 +2683,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
I915_GTT_PAGE_SIZE)))
return -EINVAL;
- ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
+ ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
PAGE_SIZE);
gma_head = wa_ctx->indirect_ctx.guest_gma;
@@ -2850,7 +2850,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
{
- uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
+ u32 per_ctx_start[CACHELINE_DWORDS] = {0};
unsigned char *bb_start_sva;
if (!wa_ctx->per_ctx.valid)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e9f343b124b0..2837baa55128 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -276,7 +276,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
u32 old, new;
- uint32_t ack_reg_offset;
+ u32 ack_reg_offset;
old = vgpu_vreg(vgpu, offset);
new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
@@ -833,7 +833,7 @@ static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
}
static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
- uint8_t t)
+ u8 t)
{
if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
/* training pattern 1 for CR */
@@ -919,7 +919,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
if (op == GVT_AUX_NATIVE_WRITE) {
int t;
- uint8_t buf[16];
+ u8 buf[16];
if ((addr + len + 1) >= DPCD_SIZE) {
/*
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index dd3dfd00f4e6..413c6a13ec02 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -703,7 +703,7 @@ static void intel_vgpu_release_work(struct work_struct *work)
__intel_vgpu_release(vgpu);
}
-static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
+static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
{
u32 start_lo, start_hi;
u32 mem_type;
@@ -730,10 +730,10 @@ static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
return ((u64)start_hi << 32) | start_lo;
}
-static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
+static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off,
void *buf, unsigned int count, bool is_write)
{
- uint64_t bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
+ u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
int ret;
if (is_write)
@@ -745,13 +745,13 @@ static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
return ret;
}
-static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)
+static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off)
{
return off >= vgpu_aperture_offset(vgpu) &&
off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);
}
-static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,
+static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,
void *buf, unsigned long count, bool is_write)
{
void *aperture_va;
@@ -783,7 +783,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
{
struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);
unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
- uint64_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+ u64 pos = *ppos & VFIO_PCI_OFFSET_MASK;
int ret = -EINVAL;
@@ -1039,7 +1039,7 @@ static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type)
static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
unsigned int index, unsigned int start,
- unsigned int count, uint32_t flags,
+ unsigned int count, u32 flags,
void *data)
{
return 0;
@@ -1047,21 +1047,21 @@ static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu,
unsigned int index, unsigned int start,
- unsigned int count, uint32_t flags, void *data)
+ unsigned int count, u32 flags, void *data)
{
return 0;
}
static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu,
unsigned int index, unsigned int start, unsigned int count,
- uint32_t flags, void *data)
+ u32 flags, void *data)
{
return 0;
}
static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
unsigned int index, unsigned int start, unsigned int count,
- uint32_t flags, void *data)
+ u32 flags, void *data)
{
struct eventfd_ctx *trigger;
@@ -1080,12 +1080,12 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
return 0;
}
-static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, uint32_t flags,
+static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags,
unsigned int index, unsigned int start, unsigned int count,
void *data)
{
int (*func)(struct intel_vgpu *vgpu, unsigned int index,
- unsigned int start, unsigned int count, uint32_t flags,
+ unsigned int start, unsigned int count, u32 flags,
void *data) = NULL;
switch (index) {
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 43f65848ecd6..ed4df2f6d60b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -57,7 +57,7 @@ int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
(reg >= gvt->device_info.gtt_start_offset \
&& reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
-static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
+static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes, bool read)
{
struct intel_gvt *gvt = NULL;
@@ -99,7 +99,7 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
* Returns:
* Zero on success, negative error code if failed
*/
-int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
+int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
struct intel_gvt *gvt = vgpu->gvt;
@@ -171,7 +171,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
* Returns:
* Zero on success, negative error code if failed
*/
-int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
+int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
{
struct intel_gvt *gvt = vgpu->gvt;
diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c
index f04b3b965bfc..1c763a27a412 100644
--- a/drivers/gpu/drm/i915/gvt/sched_policy.c
+++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
@@ -94,7 +94,7 @@ static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
{
struct vgpu_sched_data *vgpu_data;
struct list_head *pos;
- static uint64_t stage_check;
+ static u64 stage_check;
int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
/* The timeslice accumulation reset at stage 0, which is
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 2065cba59aab..0635b2c4bed7 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -61,7 +61,7 @@ struct shadow_indirect_ctx {
unsigned long guest_gma;
unsigned long shadow_gma;
void *shadow_va;
- uint32_t size;
+ u32 size;
};
#define PER_CTX_ADDR_MASK 0xfffff000
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gvt: switch to kernel types
2019-01-21 9:51 [PATCH] drm/i915/gvt: switch to kernel types Jani Nikula
@ 2019-01-21 10:55 ` Patchwork
2019-01-21 11:14 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-01-21 10:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gvt: switch to kernel types
URL : https://patchwork.freedesktop.org/series/55503/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
65ac07a75479 drm/i915/gvt: switch to kernel types
-:142: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#142: FILE: drivers/gpu/drm/i915/gvt/kvmgt.c:755:
+static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,
void *buf, unsigned long count, bool is_write)
-:194: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#194: FILE: drivers/gpu/drm/i915/gvt/kvmgt.c:1084:
+static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags,
unsigned int index, unsigned int start, unsigned int count,
-:213: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#213: FILE: drivers/gpu/drm/i915/gvt/mmio.c:61:
+static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes, bool read)
-:222: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#222: FILE: drivers/gpu/drm/i915/gvt/mmio.c:103:
+int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/gvt/mmio.c:175:
+int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
void *p_data, unsigned int bytes)
total: 0 errors, 0 warnings, 5 checks, 204 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/gvt: switch to kernel types
2019-01-21 9:51 [PATCH] drm/i915/gvt: switch to kernel types Jani Nikula
2019-01-21 10:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-01-21 11:14 ` Patchwork
2019-01-21 15:29 ` ✓ Fi.CI.IGT: " Patchwork
2019-01-23 5:44 ` [PATCH] " Zhenyu Wang
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-01-21 11:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gvt: switch to kernel types
URL : https://patchwork.freedesktop.org/series/55503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458 -> Patchwork_11993
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55503/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_11993 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: PASS -> FAIL [fdo#103167]
#### Possible fixes ####
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160: INCOMPLETE -> PASS
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#108767] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (46 -> 40)
------------------------------
Missing (6): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-pnv-d510
Build changes
-------------
* Linux: CI_DRM_5458 -> Patchwork_11993
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11993: 65ac07a754799ac1b91daae24db602479bd7d6f7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
65ac07a75479 drm/i915/gvt: switch to kernel types
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11993/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/gvt: switch to kernel types
2019-01-21 9:51 [PATCH] drm/i915/gvt: switch to kernel types Jani Nikula
2019-01-21 10:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-01-21 11:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-01-21 15:29 ` Patchwork
2019-01-23 5:44 ` [PATCH] " Zhenyu Wang
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-01-21 15:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gvt: switch to kernel types
URL : https://patchwork.freedesktop.org/series/55503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5458_full -> Patchwork_11993_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_11993_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_interruptible@universal-setplane-primary:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +4
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] / [fdo#105602]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
#### Possible fixes ####
* igt@gem_exec_reuse@contexts:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: FAIL [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
#### Warnings ####
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> FAIL [fdo#109381]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109381]: https://bugs.freedesktop.org/show_bug.cgi?id=109381
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5458 -> Patchwork_11993
CI_DRM_5458: 74ec7792af09018594097356ddc79d87cb9504f9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4779: d4199510374514489b1ab56e3416f53f6c1d6291 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11993: 65ac07a754799ac1b91daae24db602479bd7d6f7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11993/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/gvt: switch to kernel types
2019-01-21 9:51 [PATCH] drm/i915/gvt: switch to kernel types Jani Nikula
` (2 preceding siblings ...)
2019-01-21 15:29 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-01-23 5:44 ` Zhenyu Wang
3 siblings, 0 replies; 5+ messages in thread
From: Zhenyu Wang @ 2019-01-23 5:44 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-gvt-dev
[-- Attachment #1.1: Type: text/plain, Size: 10634 bytes --]
On 2019.01.21 11:51:41 +0200, Jani Nikula wrote:
> Mixed C99 and kernel types use is getting ugly. Prefer kernel types.
>
> sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g'
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Looks good to me.
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Will queue this up. Thanks!
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +++++++-------
> drivers/gpu/drm/i915/gvt/handlers.c | 6 +++---
> drivers/gpu/drm/i915/gvt/kvmgt.c | 24 ++++++++++++------------
> drivers/gpu/drm/i915/gvt/mmio.c | 6 +++---
> drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
> 6 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 77ae634eb11c..bac014031c4b 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -399,10 +399,10 @@ struct cmd_info {
> #define R_VECS (1 << VECS)
> #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
> /* rings that support this cmd: BLT/RCS/VCS/VECS */
> - uint16_t rings;
> + u16 rings;
>
> /* devices that support this cmd: SNB/IVB/HSW/... */
> - uint16_t devices;
> + u16 devices;
>
> /* which DWords are address that need fix up.
> * bit 0 means a 32-bit non address operand in command
> @@ -412,13 +412,13 @@ struct cmd_info {
> * No matter the address length, each address only takes
> * one bit in the bitmap.
> */
> - uint16_t addr_bitmap;
> + u16 addr_bitmap;
>
> /* flag == F_LEN_CONST : command length
> * flag == F_LEN_VAR : length bias bits
> * Note: length is in DWord
> */
> - uint8_t len;
> + u8 len;
>
> parser_cmd_handler handler;
> };
> @@ -1644,7 +1644,7 @@ static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
> {
> unsigned long gma = 0;
> struct cmd_info *info;
> - uint32_t cmd_len = 0;
> + u32 cmd_len = 0;
> bool bb_end = false;
> struct intel_vgpu *vgpu = s->vgpu;
> u32 cmd;
> @@ -2683,7 +2683,7 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
> I915_GTT_PAGE_SIZE)))
> return -EINVAL;
>
> - ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
> + ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
> ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
> PAGE_SIZE);
> gma_head = wa_ctx->indirect_ctx.guest_gma;
> @@ -2850,7 +2850,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
>
> static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
> {
> - uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
> + u32 per_ctx_start[CACHELINE_DWORDS] = {0};
> unsigned char *bb_start_sva;
>
> if (!wa_ctx->per_ctx.valid)
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index e9f343b124b0..2837baa55128 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -276,7 +276,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
> unsigned int offset, void *p_data, unsigned int bytes)
> {
> u32 old, new;
> - uint32_t ack_reg_offset;
> + u32 ack_reg_offset;
>
> old = vgpu_vreg(vgpu, offset);
> new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
> @@ -833,7 +833,7 @@ static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
> }
>
> static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
> - uint8_t t)
> + u8 t)
> {
> if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
> /* training pattern 1 for CR */
> @@ -919,7 +919,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
>
> if (op == GVT_AUX_NATIVE_WRITE) {
> int t;
> - uint8_t buf[16];
> + u8 buf[16];
>
> if ((addr + len + 1) >= DPCD_SIZE) {
> /*
> diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
> index dd3dfd00f4e6..413c6a13ec02 100644
> --- a/drivers/gpu/drm/i915/gvt/kvmgt.c
> +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
> @@ -703,7 +703,7 @@ static void intel_vgpu_release_work(struct work_struct *work)
> __intel_vgpu_release(vgpu);
> }
>
> -static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> +static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> {
> u32 start_lo, start_hi;
> u32 mem_type;
> @@ -730,10 +730,10 @@ static uint64_t intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar)
> return ((u64)start_hi << 32) | start_lo;
> }
>
> -static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
> +static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off,
> void *buf, unsigned int count, bool is_write)
> {
> - uint64_t bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
> + u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar);
> int ret;
>
> if (is_write)
> @@ -745,13 +745,13 @@ static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, uint64_t off,
> return ret;
> }
>
> -static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, uint64_t off)
> +static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off)
> {
> return off >= vgpu_aperture_offset(vgpu) &&
> off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu);
> }
>
> -static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t off,
> +static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,
> void *buf, unsigned long count, bool is_write)
> {
> void *aperture_va;
> @@ -783,7 +783,7 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
> {
> struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);
> unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
> - uint64_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
> + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK;
> int ret = -EINVAL;
>
>
> @@ -1039,7 +1039,7 @@ static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type)
>
> static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start,
> - unsigned int count, uint32_t flags,
> + unsigned int count, u32 flags,
> void *data)
> {
> return 0;
> @@ -1047,21 +1047,21 @@ static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu,
>
> static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start,
> - unsigned int count, uint32_t flags, void *data)
> + unsigned int count, u32 flags, void *data)
> {
> return 0;
> }
>
> static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start, unsigned int count,
> - uint32_t flags, void *data)
> + u32 flags, void *data)
> {
> return 0;
> }
>
> static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
> unsigned int index, unsigned int start, unsigned int count,
> - uint32_t flags, void *data)
> + u32 flags, void *data)
> {
> struct eventfd_ctx *trigger;
>
> @@ -1080,12 +1080,12 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu,
> return 0;
> }
>
> -static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, uint32_t flags,
> +static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags,
> unsigned int index, unsigned int start, unsigned int count,
> void *data)
> {
> int (*func)(struct intel_vgpu *vgpu, unsigned int index,
> - unsigned int start, unsigned int count, uint32_t flags,
> + unsigned int start, unsigned int count, u32 flags,
> void *data) = NULL;
>
> switch (index) {
> diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
> index 43f65848ecd6..ed4df2f6d60b 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio.c
> @@ -57,7 +57,7 @@ int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
> (reg >= gvt->device_info.gtt_start_offset \
> && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
>
> -static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
> +static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes, bool read)
> {
> struct intel_gvt *gvt = NULL;
> @@ -99,7 +99,7 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
> * Returns:
> * Zero on success, negative error code if failed
> */
> -int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
> +int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes)
> {
> struct intel_gvt *gvt = vgpu->gvt;
> @@ -171,7 +171,7 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
> * Returns:
> * Zero on success, negative error code if failed
> */
> -int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
> +int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
> void *p_data, unsigned int bytes)
> {
> struct intel_gvt *gvt = vgpu->gvt;
> diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c
> index f04b3b965bfc..1c763a27a412 100644
> --- a/drivers/gpu/drm/i915/gvt/sched_policy.c
> +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c
> @@ -94,7 +94,7 @@ static void gvt_balance_timeslice(struct gvt_sched_data *sched_data)
> {
> struct vgpu_sched_data *vgpu_data;
> struct list_head *pos;
> - static uint64_t stage_check;
> + static u64 stage_check;
> int stage = stage_check++ % GVT_TS_BALANCE_STAGE_NUM;
>
> /* The timeslice accumulation reset at stage 0, which is
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
> index 2065cba59aab..0635b2c4bed7 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.h
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.h
> @@ -61,7 +61,7 @@ struct shadow_indirect_ctx {
> unsigned long guest_gma;
> unsigned long shadow_gma;
> void *shadow_va;
> - uint32_t size;
> + u32 size;
> };
>
> #define PER_CTX_ADDR_MASK 0xfffff000
> --
> 2.20.1
>
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-01-23 5:44 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-21 9:51 [PATCH] drm/i915/gvt: switch to kernel types Jani Nikula
2019-01-21 10:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-01-21 11:14 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-21 15:29 ` ✓ Fi.CI.IGT: " Patchwork
2019-01-23 5:44 ` [PATCH] " Zhenyu Wang
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