* [PATCH v3 1/8] drm/i915: Add a new "remapped" gtt_view
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-30 19:06 ` Daniel Vetter
2019-01-18 15:27 ` [PATCH v3 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
` (18 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
v2: Use intel_remapped_plane_info base type
s/unused/unused_mbz/ (Chris)
Separate BUILD_BUG_ON()s (Chris)
Use I915_GTT_PAGE_SIZE (Chris)
v3: Use i915_gem_object_get_dma_address() (Chris)
Trim the sg (Tvrtko)
v4: Actually trim this time. Limit the max length
to one row of pages to keep things simple
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gem.c | 17 ++++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +++++--
drivers/gpu/drm/i915/i915_vma.c | 6 +-
drivers/gpu/drm/i915/i915_vma.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 6 +-
10 files changed, 163 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 24d6d4ce14ef..b7c6b06cf2f3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -198,6 +198,18 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
vma->ggtt_view.rotated.plane[1].offset);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
+ vma->ggtt_view.remapped.plane[0].width,
+ vma->ggtt_view.remapped.plane[0].height,
+ vma->ggtt_view.remapped.plane[0].stride,
+ vma->ggtt_view.remapped.plane[0].offset,
+ vma->ggtt_view.remapped.plane[1].width,
+ vma->ggtt_view.remapped.plane[1].height,
+ vma->ggtt_view.remapped.plane[1].stride,
+ vma->ggtt_view.remapped.plane[1].offset);
+ break;
+
default:
MISSING_CASE(vma->ggtt_view.type);
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 310d9e1e1620..4cb0c9b756d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2855,6 +2855,10 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
unsigned int n);
dma_addr_t
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len);
+dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
unsigned long n);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b359390ba22c..1e7c95d0fea1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5660,16 +5660,29 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
}
dma_addr_t
-i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
- unsigned long n)
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len)
{
struct scatterlist *sg;
unsigned int offset;
sg = i915_gem_object_get_sg(obj, n, &offset);
+
+ if (len)
+ *len = sg_dma_len(sg) - (offset << PAGE_SHIFT);
+
return sg_dma_address(sg) + (offset << PAGE_SHIFT);
}
+dma_addr_t
+i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ return i915_gem_object_get_dma_address_len(obj, n, NULL);
+}
+
+
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
{
struct sg_table *pages;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9081e3bc5a59..64e278c9479b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3612,6 +3612,89 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
return ERR_PTR(ret);
}
+static struct scatterlist *
+remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
+ unsigned int width, unsigned int height,
+ unsigned int stride,
+ struct sg_table *st, struct scatterlist *sg)
+{
+ unsigned int row;
+
+ for (row = 0; row < height; row++) {
+ unsigned int left = width * I915_GTT_PAGE_SIZE;
+
+ while (left) {
+ dma_addr_t addr;
+ unsigned int length;
+
+ /* We don't need the pages, but need to initialize
+ * the entries so the sg list can be happily traversed.
+ * The only thing we need are DMA addresses.
+ */
+
+ addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
+
+ length = min(left, length);
+
+ st->nents++;
+
+ sg_set_page(sg, NULL, length, 0);
+ sg_dma_address(sg) = addr;
+ sg_dma_len(sg) = length;
+ sg = sg_next(sg);
+
+ offset += length / I915_GTT_PAGE_SIZE;
+ left -= length;
+ }
+
+ offset += stride - width;
+ }
+
+ return sg;
+}
+
+static noinline struct sg_table *
+intel_remap_pages(struct intel_remapped_info *rem_info,
+ struct drm_i915_gem_object *obj)
+{
+ unsigned int size = intel_remapped_info_size(rem_info);
+ struct sg_table *st;
+ struct scatterlist *sg;
+ int ret = -ENOMEM;
+ int i;
+
+ /* Allocate target SG list. */
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ goto err_st_alloc;
+
+ ret = sg_alloc_table(st, size, GFP_KERNEL);
+ if (ret)
+ goto err_sg_alloc;
+
+ st->nents = 0;
+ sg = st->sgl;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
+ sg = remap_pages(obj, rem_info->plane[i].offset,
+ rem_info->plane[i].width, rem_info->plane[i].height,
+ rem_info->plane[i].stride, st, sg);
+ }
+
+ i915_sg_trim(st);
+
+ return st;
+
+err_sg_alloc:
+ kfree(st);
+err_st_alloc:
+
+ DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size);
+
+ return ERR_PTR(ret);
+}
+
static noinline struct sg_table *
intel_partial_pages(const struct i915_ggtt_view *view,
struct drm_i915_gem_object *obj)
@@ -3690,6 +3773,11 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ vma->pages =
+ intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
+ break;
+
case I915_GGTT_VIEW_PARTIAL:
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9229b03d629b..7892e5467c6a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -162,11 +162,18 @@ typedef u64 gen8_ppgtt_pml4e_t;
struct sg_table;
+struct intel_remapped_plane_info {
+ /* in gtt pages */
+ unsigned int width, height, stride, offset;
+} __packed;
+
+struct intel_remapped_info {
+ struct intel_remapped_plane_info plane[2];
+ unsigned int unused_mbz;
+} __packed;
+
struct intel_rotation_info {
- struct intel_rotation_plane_info {
- /* tiles */
- unsigned int width, height, stride, offset;
- } plane[2];
+ struct intel_remapped_plane_info plane[2];
} __packed;
struct intel_partial_info {
@@ -178,12 +185,20 @@ enum i915_ggtt_view_type {
I915_GGTT_VIEW_NORMAL = 0,
I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
+ I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
};
static inline void assert_i915_gem_gtt_types(void)
{
BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
+
+ /* Check that rotation/remapped shares offsets for simplicity */
+ BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
+ offsetof(struct intel_rotation_info, plane[0]));
+ BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
+ offsetofend(struct intel_rotation_info, plane[1]));
/* As we encode the size of each branch inside the union into its type,
* we have to be careful that each branch has a unique size.
@@ -192,6 +207,7 @@ static inline void assert_i915_gem_gtt_types(void)
case I915_GGTT_VIEW_NORMAL:
case I915_GGTT_VIEW_PARTIAL:
case I915_GGTT_VIEW_ROTATED:
+ case I915_GGTT_VIEW_REMAPPED:
/* gcc complains if these are identical cases */
break;
}
@@ -203,6 +219,7 @@ struct i915_ggtt_view {
/* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
+ struct intel_remapped_info remapped;
};
};
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5b4d78cdb4ca..9a039c36dc0c 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -164,6 +164,9 @@ vma_create(struct drm_i915_gem_object *obj,
} else if (view->type == I915_GGTT_VIEW_ROTATED) {
vma->size = intel_rotation_info_size(&view->rotated);
vma->size <<= PAGE_SHIFT;
+ } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
+ vma->size = intel_remapped_info_size(&view->remapped);
+ vma->size <<= PAGE_SHIFT;
}
}
@@ -464,7 +467,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
* Explicitly disable for rotated VMA since the display does not
* need the fence and the VMA is not accessible to other users.
*/
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
+ vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
return;
fenceable = (vma->node.size >= vma->fence_size &&
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 4f7c1c7599f4..64cf029c028a 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -265,8 +265,11 @@ i915_vma_compare(struct i915_vma *vma,
*/
BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
+ BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
offsetof(typeof(*view), partial));
+ BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
+ offsetof(typeof(*view), remapped));
return memcmp(&vma->ggtt_view.partial, &view->partial, view->type);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b087ed285cc1..6e5ce084b244 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1947,6 +1947,17 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
return size;
}
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
+{
+ unsigned int size = 0;
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
+ size += rem_info->plane[i].width * rem_info->plane[i].height;
+
+ return size;
+}
+
static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e5a436c33307..d025821a71d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1604,6 +1604,7 @@ unsigned int intel_fb_xy_to_linear(int x, int y,
void intel_add_fb_offsets(int *x, int *y,
const struct intel_plane_state *state, int plane);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
void intel_mark_busy(struct drm_i915_private *dev_priv);
void intel_mark_idle(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index ffa74290e054..4fc49c27f13c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -395,8 +395,8 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
-static unsigned int rotated_size(const struct intel_rotation_plane_info *a,
- const struct intel_rotation_plane_info *b)
+static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
+ const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
@@ -406,7 +406,7 @@ static int igt_vma_rotate(void *arg)
struct drm_i915_private *i915 = arg;
struct i915_address_space *vm = &i915->ggtt.vm;
struct drm_i915_gem_object *obj;
- const struct intel_rotation_plane_info planes[] = {
+ const struct intel_remapped_plane_info planes[] = {
{ .width = 1, .height = 1, .stride = 1 },
{ .width = 2, .height = 2, .stride = 2 },
{ .width = 4, .height = 4, .stride = 4 },
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v3 1/8] drm/i915: Add a new "remapped" gtt_view
2019-01-18 15:27 ` [PATCH v3 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
@ 2019-01-30 19:06 ` Daniel Vetter
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 19:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jan 18, 2019 at 05:27:13PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To overcome display engine stride limits we'll want to remap the
> pages in the GTT. To that end we need a new gtt_view type which
> is just like the "rotated" type except not rotated.
>
> v2: Use intel_remapped_plane_info base type
> s/unused/unused_mbz/ (Chris)
> Separate BUILD_BUG_ON()s (Chris)
> Use I915_GTT_PAGE_SIZE (Chris)
> v3: Use i915_gem_object_get_dma_address() (Chris)
> Trim the sg (Tvrtko)
> v4: Actually trim this time. Limit the max length
> to one row of pages to keep things simple
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++
> drivers/gpu/drm/i915/i915_drv.h | 4 ++
> drivers/gpu/drm/i915/i915_gem.c | 17 ++++-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +++++--
> drivers/gpu/drm/i915/i915_vma.c | 6 +-
> drivers/gpu/drm/i915/i915_vma.h | 3 +
> drivers/gpu/drm/i915/intel_display.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/selftests/i915_vma.c | 6 +-
> 10 files changed, 163 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 24d6d4ce14ef..b7c6b06cf2f3 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -198,6 +198,18 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> vma->ggtt_view.rotated.plane[1].offset);
> break;
>
> + case I915_GGTT_VIEW_REMAPPED:
> + seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
> + vma->ggtt_view.remapped.plane[0].width,
> + vma->ggtt_view.remapped.plane[0].height,
> + vma->ggtt_view.remapped.plane[0].stride,
> + vma->ggtt_view.remapped.plane[0].offset,
> + vma->ggtt_view.remapped.plane[1].width,
> + vma->ggtt_view.remapped.plane[1].height,
> + vma->ggtt_view.remapped.plane[1].stride,
> + vma->ggtt_view.remapped.plane[1].offset);
> + break;
> +
> default:
> MISSING_CASE(vma->ggtt_view.type);
> break;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 310d9e1e1620..4cb0c9b756d4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2855,6 +2855,10 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
> unsigned int n);
>
> dma_addr_t
> +i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
> + unsigned long n,
> + unsigned int *len);
> +dma_addr_t
> i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
> unsigned long n);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b359390ba22c..1e7c95d0fea1 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5660,16 +5660,29 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
> }
>
> dma_addr_t
> -i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
> - unsigned long n)
> +i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
> + unsigned long n,
> + unsigned int *len)
> {
> struct scatterlist *sg;
> unsigned int offset;
>
> sg = i915_gem_object_get_sg(obj, n, &offset);
> +
> + if (len)
> + *len = sg_dma_len(sg) - (offset << PAGE_SHIFT);
> +
> return sg_dma_address(sg) + (offset << PAGE_SHIFT);
> }
>
> +dma_addr_t
> +i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
> + unsigned long n)
> +{
> + return i915_gem_object_get_dma_address_len(obj, n, NULL);
> +}
> +
> +
> int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
> {
> struct sg_table *pages;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 9081e3bc5a59..64e278c9479b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3612,6 +3612,89 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
> return ERR_PTR(ret);
> }
>
> +static struct scatterlist *
> +remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
> + unsigned int width, unsigned int height,
> + unsigned int stride,
> + struct sg_table *st, struct scatterlist *sg)
> +{
> + unsigned int row;
> +
> + for (row = 0; row < height; row++) {
> + unsigned int left = width * I915_GTT_PAGE_SIZE;
> +
> + while (left) {
> + dma_addr_t addr;
> + unsigned int length;
> +
> + /* We don't need the pages, but need to initialize
> + * the entries so the sg list can be happily traversed.
> + * The only thing we need are DMA addresses.
> + */
> +
> + addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
> +
> + length = min(left, length);
> +
> + st->nents++;
> +
> + sg_set_page(sg, NULL, length, 0);
> + sg_dma_address(sg) = addr;
> + sg_dma_len(sg) = length;
> + sg = sg_next(sg);
> +
> + offset += length / I915_GTT_PAGE_SIZE;
> + left -= length;
> + }
> +
> + offset += stride - width;
Not sure trying to keep the compacted sg list is worth all the code, but
can't hurt really either. lgtm, and I trust Chris to have fully reviewed
test coverage for all the corner cases :-)
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> + }
> +
> + return sg;
> +}
> +
> +static noinline struct sg_table *
> +intel_remap_pages(struct intel_remapped_info *rem_info,
> + struct drm_i915_gem_object *obj)
> +{
> + unsigned int size = intel_remapped_info_size(rem_info);
> + struct sg_table *st;
> + struct scatterlist *sg;
> + int ret = -ENOMEM;
> + int i;
> +
> + /* Allocate target SG list. */
> + st = kmalloc(sizeof(*st), GFP_KERNEL);
> + if (!st)
> + goto err_st_alloc;
> +
> + ret = sg_alloc_table(st, size, GFP_KERNEL);
> + if (ret)
> + goto err_sg_alloc;
> +
> + st->nents = 0;
> + sg = st->sgl;
> +
> + for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
> + sg = remap_pages(obj, rem_info->plane[i].offset,
> + rem_info->plane[i].width, rem_info->plane[i].height,
> + rem_info->plane[i].stride, st, sg);
> + }
> +
> + i915_sg_trim(st);
> +
> + return st;
> +
> +err_sg_alloc:
> + kfree(st);
> +err_st_alloc:
> +
> + DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
> + obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size);
> +
> + return ERR_PTR(ret);
> +}
> +
> static noinline struct sg_table *
> intel_partial_pages(const struct i915_ggtt_view *view,
> struct drm_i915_gem_object *obj)
> @@ -3690,6 +3773,11 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
> intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
> break;
>
> + case I915_GGTT_VIEW_REMAPPED:
> + vma->pages =
> + intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
> + break;
> +
> case I915_GGTT_VIEW_PARTIAL:
> vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
> break;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 9229b03d629b..7892e5467c6a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -162,11 +162,18 @@ typedef u64 gen8_ppgtt_pml4e_t;
>
> struct sg_table;
>
> +struct intel_remapped_plane_info {
> + /* in gtt pages */
> + unsigned int width, height, stride, offset;
> +} __packed;
> +
> +struct intel_remapped_info {
> + struct intel_remapped_plane_info plane[2];
> + unsigned int unused_mbz;
> +} __packed;
> +
> struct intel_rotation_info {
> - struct intel_rotation_plane_info {
> - /* tiles */
> - unsigned int width, height, stride, offset;
> - } plane[2];
> + struct intel_remapped_plane_info plane[2];
> } __packed;
>
> struct intel_partial_info {
> @@ -178,12 +185,20 @@ enum i915_ggtt_view_type {
> I915_GGTT_VIEW_NORMAL = 0,
> I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
> I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
> + I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
> };
>
> static inline void assert_i915_gem_gtt_types(void)
> {
> BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
> BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
> + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
> +
> + /* Check that rotation/remapped shares offsets for simplicity */
> + BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
> + offsetof(struct intel_rotation_info, plane[0]));
> + BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
> + offsetofend(struct intel_rotation_info, plane[1]));
>
> /* As we encode the size of each branch inside the union into its type,
> * we have to be careful that each branch has a unique size.
> @@ -192,6 +207,7 @@ static inline void assert_i915_gem_gtt_types(void)
> case I915_GGTT_VIEW_NORMAL:
> case I915_GGTT_VIEW_PARTIAL:
> case I915_GGTT_VIEW_ROTATED:
> + case I915_GGTT_VIEW_REMAPPED:
> /* gcc complains if these are identical cases */
> break;
> }
> @@ -203,6 +219,7 @@ struct i915_ggtt_view {
> /* Members need to contain no holes/padding */
> struct intel_partial_info partial;
> struct intel_rotation_info rotated;
> + struct intel_remapped_info remapped;
> };
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 5b4d78cdb4ca..9a039c36dc0c 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -164,6 +164,9 @@ vma_create(struct drm_i915_gem_object *obj,
> } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> vma->size = intel_rotation_info_size(&view->rotated);
> vma->size <<= PAGE_SHIFT;
> + } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
> + vma->size = intel_remapped_info_size(&view->remapped);
> + vma->size <<= PAGE_SHIFT;
> }
> }
>
> @@ -464,7 +467,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> * Explicitly disable for rotated VMA since the display does not
> * need the fence and the VMA is not accessible to other users.
> */
> - if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
> + if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
> + vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
> return;
>
> fenceable = (vma->node.size >= vma->fence_size &&
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 4f7c1c7599f4..64cf029c028a 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -265,8 +265,11 @@ i915_vma_compare(struct i915_vma *vma,
> */
> BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
> BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
> + BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
> BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
> offsetof(typeof(*view), partial));
> + BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
> + offsetof(typeof(*view), remapped));
> return memcmp(&vma->ggtt_view.partial, &view->partial, view->type);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b087ed285cc1..6e5ce084b244 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1947,6 +1947,17 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
> return size;
> }
>
> +unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
> +{
> + unsigned int size = 0;
> + int i;
> +
> + for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
> + size += rem_info->plane[i].width * rem_info->plane[i].height;
> +
> + return size;
> +}
> +
> static void
> intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e5a436c33307..d025821a71d5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1604,6 +1604,7 @@ unsigned int intel_fb_xy_to_linear(int x, int y,
> void intel_add_fb_offsets(int *x, int *y,
> const struct intel_plane_state *state, int plane);
> unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
> +unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
> bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
> void intel_mark_busy(struct drm_i915_private *dev_priv);
> void intel_mark_idle(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
> index ffa74290e054..4fc49c27f13c 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_vma.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
> @@ -395,8 +395,8 @@ assert_rotated(struct drm_i915_gem_object *obj,
> return sg;
> }
>
> -static unsigned int rotated_size(const struct intel_rotation_plane_info *a,
> - const struct intel_rotation_plane_info *b)
> +static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
> + const struct intel_remapped_plane_info *b)
> {
> return a->width * a->height + b->width * b->height;
> }
> @@ -406,7 +406,7 @@ static int igt_vma_rotate(void *arg)
> struct drm_i915_private *i915 = arg;
> struct i915_address_space *vm = &i915->ggtt.vm;
> struct drm_i915_gem_object *obj;
> - const struct intel_rotation_plane_info planes[] = {
> + const struct intel_remapped_plane_info planes[] = {
> { .width = 1, .height = 1, .stride = 1 },
> { .width = 2, .height = 2, .stride = 2 },
> { .width = 4, .height = 4, .stride = 4 },
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-24 18:58 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
` (17 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
v3: Deal with trimmed sg
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 105 ++++++++++++++++++++--
1 file changed, 97 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 4fc49c27f13c..063143fa51bf 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -58,7 +58,7 @@ static bool assert_vma(struct i915_vma *vma,
static struct i915_vma *
checked_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
- struct i915_ggtt_view *view)
+ const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
bool ok = true;
@@ -395,13 +395,81 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
+static unsigned long remapped_index(const struct intel_remapped_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * y +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_remapped(struct drm_i915_gem_object *obj,
+ const struct intel_remapped_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+ unsigned int left = 0;
+ unsigned int offset;
+
+ for (y = 0; y < r->plane[n].height; y++) {
+ for (x = 0; x < r->plane[n].width; x++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane %d, (%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+ if (!left) {
+ offset = 0;
+ left = sg_dma_len(sg);
+ }
+
+ DRM_DEBUG_KMS("sg %p start left %d\n", sg, left);
+
+ src_idx = remapped_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ DRM_DEBUG_KMS("sg %p %d %d %d %llx\n", sg, n, x, y, src);
+
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
+ pr_err("Invalid sg.length, found %d, expected %lu for remapped page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ DRM_DEBUG_KMS("sg %p dma %llx off = %d\n", sg, sg_dma_address(sg), offset);
+
+ if (sg_dma_address(sg) + offset != src) {
+ pr_err("Invalid address for remapped page (%d, %d) [src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+ DRM_DEBUG_KMS("sg %p end left %d\n", sg, left);
+
+ left -= PAGE_SIZE;
+ offset += PAGE_SIZE;
+
+
+ if (!left)
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
-static int igt_vma_rotate(void *arg)
+static int igt_vma_rotate_remap(void *arg)
{
struct drm_i915_private *i915 = arg;
struct i915_address_space *vm = &i915->ggtt.vm;
@@ -424,6 +492,11 @@ static int igt_vma_rotate(void *arg)
{ .width = 6, .height = 4, .stride = 6 },
{ }
}, *a, *b;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
const unsigned int max_pages = 64;
int err = -ENOMEM;
@@ -435,6 +508,7 @@ static int igt_vma_rotate(void *arg)
if (IS_ERR(obj))
goto out;
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
struct i915_ggtt_view view;
@@ -445,7 +519,7 @@ static int igt_vma_rotate(void *arg)
GEM_BUG_ON(max_offset > max_pages);
max_offset = max_pages - max_offset;
- view.type = I915_GGTT_VIEW_ROTATED;
+ view.type = *t;
view.rotated.plane[0] = *a;
view.rotated.plane[1] = *b;
@@ -466,14 +540,23 @@ static int igt_vma_rotate(void *arg)
goto out_object;
}
- if (vma->size != rotated_size(a, b) * PAGE_SIZE) {
+ if (view.type == I915_GGTT_VIEW_ROTATED &&
+ vma->size != rotated_size(a, b) * PAGE_SIZE) {
pr_err("VMA is wrong size, expected %lu, found %llu\n",
PAGE_SIZE * rotated_size(a, b), vma->size);
err = -EINVAL;
goto out_object;
}
- if (vma->pages->nents != rotated_size(a, b)) {
+ if (view.type == I915_GGTT_VIEW_REMAPPED &&
+ vma->size > rotated_size(a, b) * PAGE_SIZE) {
+ pr_err("VMA is wrong size, expected %lu, found %llu\n",
+ PAGE_SIZE * rotated_size(a, b), vma->size);
+ err = -EINVAL;
+ goto out_object;
+ }
+
+ if (vma->pages->nents > rotated_size(a, b)) {
pr_err("sg table is wrong sizeo, expected %u, found %u nents\n",
rotated_size(a, b), vma->pages->nents);
err = -EINVAL;
@@ -495,9 +578,14 @@ static int igt_vma_rotate(void *arg)
sg = vma->pages->sgl;
for (n = 0; n < ARRAY_SIZE(view.rotated.plane); n++) {
- sg = assert_rotated(obj, &view.rotated, n, sg);
+ if (view.type == I915_GGTT_VIEW_ROTATED)
+ sg = assert_rotated(obj, &view.rotated, n, sg);
+ else
+ sg = assert_remapped(obj, &view.remapped, n, sg);
if (IS_ERR(sg)) {
- pr_err("Inconsistent VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n", n,
+ pr_err("Inconsistent %s VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n",
+ view.type == I915_GGTT_VIEW_ROTATED ?
+ "rotated" : "remapped", n,
view.rotated.plane[0].width,
view.rotated.plane[0].height,
view.rotated.plane[0].stride,
@@ -516,6 +604,7 @@ static int igt_vma_rotate(void *arg)
}
}
}
+ }
out_object:
i915_gem_object_put(obj);
@@ -719,7 +808,7 @@ int i915_vma_mock_selftests(void)
static const struct i915_subtest tests[] = {
SUBTEST(igt_vma_create),
SUBTEST(igt_vma_pin1),
- SUBTEST(igt_vma_rotate),
+ SUBTEST(igt_vma_rotate_remap),
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
2019-01-18 15:27 ` [PATCH v3 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
@ 2019-01-24 18:58 ` Ville Syrjala
2019-01-24 23:22 ` Chris Wilson
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-24 18:58 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
v3: Deal with trimmed sg
v4: Drop leftover debugs
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 98 +++++++++++++++++++++--
1 file changed, 90 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 06bbed7920b9..653a9b6c514e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -59,7 +59,7 @@ static bool assert_vma(struct i915_vma *vma,
static struct i915_vma *
checked_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
- struct i915_ggtt_view *view)
+ const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
bool ok = true;
@@ -397,13 +397,74 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
+static unsigned long remapped_index(const struct intel_remapped_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * y +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_remapped(struct drm_i915_gem_object *obj,
+ const struct intel_remapped_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+ unsigned int left = 0;
+ unsigned int offset;
+
+ for (y = 0; y < r->plane[n].height; y++) {
+ for (x = 0; x < r->plane[n].width; x++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane %d, (%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+ if (!left) {
+ offset = 0;
+ left = sg_dma_len(sg);
+ }
+
+ src_idx = remapped_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
+ pr_err("Invalid sg.length, found %d, expected %lu for remapped page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (sg_dma_address(sg) + offset != src) {
+ pr_err("Invalid address for remapped page (%d, %d) [src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ left -= PAGE_SIZE;
+ offset += PAGE_SIZE;
+
+
+ if (!left)
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
-static int igt_vma_rotate(void *arg)
+static int igt_vma_rotate_remap(void *arg)
{
struct i915_ggtt *ggtt = arg;
struct i915_address_space *vm = &ggtt->vm;
@@ -426,6 +487,11 @@ static int igt_vma_rotate(void *arg)
{ .width = 6, .height = 4, .stride = 6 },
{ }
}, *a, *b;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
const unsigned int max_pages = 64;
int err = -ENOMEM;
@@ -437,6 +503,7 @@ static int igt_vma_rotate(void *arg)
if (IS_ERR(obj))
goto out;
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
struct i915_ggtt_view view;
@@ -447,7 +514,7 @@ static int igt_vma_rotate(void *arg)
GEM_BUG_ON(max_offset > max_pages);
max_offset = max_pages - max_offset;
- view.type = I915_GGTT_VIEW_ROTATED;
+ view.type = *t;
view.rotated.plane[0] = *a;
view.rotated.plane[1] = *b;
@@ -468,14 +535,23 @@ static int igt_vma_rotate(void *arg)
goto out_object;
}
- if (vma->size != rotated_size(a, b) * PAGE_SIZE) {
+ if (view.type == I915_GGTT_VIEW_ROTATED &&
+ vma->size != rotated_size(a, b) * PAGE_SIZE) {
pr_err("VMA is wrong size, expected %lu, found %llu\n",
PAGE_SIZE * rotated_size(a, b), vma->size);
err = -EINVAL;
goto out_object;
}
- if (vma->pages->nents != rotated_size(a, b)) {
+ if (view.type == I915_GGTT_VIEW_REMAPPED &&
+ vma->size > rotated_size(a, b) * PAGE_SIZE) {
+ pr_err("VMA is wrong size, expected %lu, found %llu\n",
+ PAGE_SIZE * rotated_size(a, b), vma->size);
+ err = -EINVAL;
+ goto out_object;
+ }
+
+ if (vma->pages->nents > rotated_size(a, b)) {
pr_err("sg table is wrong sizeo, expected %u, found %u nents\n",
rotated_size(a, b), vma->pages->nents);
err = -EINVAL;
@@ -497,9 +573,14 @@ static int igt_vma_rotate(void *arg)
sg = vma->pages->sgl;
for (n = 0; n < ARRAY_SIZE(view.rotated.plane); n++) {
- sg = assert_rotated(obj, &view.rotated, n, sg);
+ if (view.type == I915_GGTT_VIEW_ROTATED)
+ sg = assert_rotated(obj, &view.rotated, n, sg);
+ else
+ sg = assert_remapped(obj, &view.remapped, n, sg);
if (IS_ERR(sg)) {
- pr_err("Inconsistent VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n", n,
+ pr_err("Inconsistent %s VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n",
+ view.type == I915_GGTT_VIEW_ROTATED ?
+ "rotated" : "remapped", n,
view.rotated.plane[0].width,
view.rotated.plane[0].height,
view.rotated.plane[0].stride,
@@ -518,6 +599,7 @@ static int igt_vma_rotate(void *arg)
}
}
}
+ }
out_object:
i915_gem_object_put(obj);
@@ -721,7 +803,7 @@ int i915_vma_mock_selftests(void)
static const struct i915_subtest tests[] = {
SUBTEST(igt_vma_create),
SUBTEST(igt_vma_pin1),
- SUBTEST(igt_vma_rotate),
+ SUBTEST(igt_vma_rotate_remap),
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
2019-01-24 18:58 ` [PATCH v4 " Ville Syrjala
@ 2019-01-24 23:22 ` Chris Wilson
0 siblings, 0 replies; 44+ messages in thread
From: Chris Wilson @ 2019-01-24 23:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2019-01-24 18:58:02)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extend the rotated vma mock selftest to cover remapped vmas as
> well.
>
> TODO: reindent the loops I guess? Left like this for now to
> ease review
Probably leave it as is for the moment. Looks like we need to split the
loops up into their functions for us to be able to recover enough
columns.
Not a task worth holding up this series for.
> v2: Include the vma type in the error message (Chris)
> v3: Deal with trimmed sg
> v4: Drop leftover debugs
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 3/8] drm/i915/selftests: Add live vma selftest
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-24 19:11 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 4/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
` (16 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable would be, hence I just hacked it in the test.
v2: Grab rpm reference (Chris)
GEM_BUG_ON(view.type not as expected) (Chris)
Allow CAN_FENCE for rotated/remapped vmas (Chris)
Update intel_plane_uses_fence() to ask for a fence
only for normal vmas on gen4+
v3: Deal with intel_wakeref_t
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_vma.c | 8 -
drivers/gpu/drm/i915/intel_display.c | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 141 ++++++++++++++++++
4 files changed, 145 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 9a039c36dc0c..865290751633 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -463,14 +463,6 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- /*
- * Explicitly disable for rotated VMA since the display does not
- * need the fence and the VMA is not accessible to other users.
- */
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
- vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
- return;
-
fenceable = (vma->node.size >= vma->fence_size &&
IS_ALIGNED(vma->node.start, vma->fence_alignment));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e5ce084b244..0d5526ec34b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2027,7 +2027,9 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+ return INTEL_GEN(dev_priv) < 4 ||
+ (plane->has_fbc &&
+ plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a15713cae3b3..095e25e92a36 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -15,6 +15,7 @@ selftest(workarounds, intel_workarounds_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(dmabuf, i915_gem_dmabuf_live_selftests)
+selftest(vma, i915_vma_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(gem, i915_gem_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 063143fa51bf..a9a0e3155c94 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -826,3 +826,144 @@ int i915_vma_mock_selftests(void)
return err;
}
+static int igt_vma_remapped_gtt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct intel_remapped_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *p;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
+ struct drm_i915_gem_object *obj;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ for (t = types; *t; t++) {
+ for (p = planes; p->width; p++) {
+ struct i915_ggtt_view view = {
+ .type = *t,
+ .rotated.plane[0] = *p,
+ };
+ struct i915_vma *vma;
+ u32 __iomem *map;
+ unsigned int x, y;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (err)
+ goto out;
+
+ vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != *t);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset;
+ u32 val = y << 16 | x;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ offset = (x * p->height + y) * PAGE_SIZE;
+ else
+ offset = (y * p->width + x) * PAGE_SIZE;
+
+ iowrite32(val, &map[offset / sizeof(*map)]);
+ }
+ }
+
+ i915_vma_unpin_iomap(vma);
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset, src_idx;
+ u32 exp = y << 16 | x;
+ u32 val;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ src_idx = rotated_index(&view.rotated, 0, x, y);
+ else
+ src_idx = remapped_index(&view.remapped, 0, x, y);
+ offset = src_idx * PAGE_SIZE;
+
+ val = ioread32(&map[offset / sizeof(*map)]);
+ if (val != exp) {
+ pr_err("%s VMA write test failed, expected 0x%x, found 0x%x\n",
+ *t == I915_GGTT_VIEW_ROTATED ? "Rotated" : "Remapped",
+ val, exp);
+ i915_vma_unpin_iomap(vma);
+ goto out;
+ }
+ }
+ }
+ i915_vma_unpin_iomap(vma);
+ }
+ }
+
+out:
+ intel_runtime_pm_put(i915, wakeref);
+ mutex_unlock(&i915->drm.struct_mutex);
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
+int i915_vma_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_vma_remapped_gtt),
+ };
+
+ return i915_subtests(tests, i915);
+}
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest
2019-01-18 15:27 ` [PATCH v3 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
@ 2019-01-24 19:11 ` Ville Syrjala
2019-01-24 23:20 ` Chris Wilson
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-24 19:11 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable would be, hence I just hacked it in the test.
v2: Grab rpm reference (Chris)
GEM_BUG_ON(view.type not as expected) (Chris)
Allow CAN_FENCE for rotated/remapped vmas (Chris)
Update intel_plane_uses_fence() to ask for a fence
only for normal vmas on gen4+
v3: Deal with intel_wakeref_t
v4: Rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_vma.c | 8 -
drivers/gpu/drm/i915/intel_display.c | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 142 ++++++++++++++++++
4 files changed, 146 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 9a039c36dc0c..865290751633 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -463,14 +463,6 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- /*
- * Explicitly disable for rotated VMA since the display does not
- * need the fence and the VMA is not accessible to other users.
- */
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
- vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
- return;
-
fenceable = (vma->node.size >= vma->fence_size &&
IS_ALIGNED(vma->node.start, vma->fence_alignment));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84efbf892c65..17c7edee9584 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2027,7 +2027,9 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+ return INTEL_GEN(dev_priv) < 4 ||
+ (plane->has_fbc &&
+ plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a15713cae3b3..095e25e92a36 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -15,6 +15,7 @@ selftest(workarounds, intel_workarounds_live_selftests)
selftest(requests, i915_request_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(dmabuf, i915_gem_dmabuf_live_selftests)
+selftest(vma, i915_vma_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(gem, i915_gem_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 653a9b6c514e..d8fa169e2775 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -828,3 +828,145 @@ int i915_vma_mock_selftests(void)
return err;
}
+
+static int igt_vma_remapped_gtt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct intel_remapped_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *p;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
+ struct drm_i915_gem_object *obj;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ for (t = types; *t; t++) {
+ for (p = planes; p->width; p++) {
+ struct i915_ggtt_view view = {
+ .type = *t,
+ .rotated.plane[0] = *p,
+ };
+ struct i915_vma *vma;
+ u32 __iomem *map;
+ unsigned int x, y;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (err)
+ goto out;
+
+ vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != *t);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset;
+ u32 val = y << 16 | x;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ offset = (x * p->height + y) * PAGE_SIZE;
+ else
+ offset = (y * p->width + x) * PAGE_SIZE;
+
+ iowrite32(val, &map[offset / sizeof(*map)]);
+ }
+ }
+
+ i915_vma_unpin_iomap(vma);
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset, src_idx;
+ u32 exp = y << 16 | x;
+ u32 val;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ src_idx = rotated_index(&view.rotated, 0, x, y);
+ else
+ src_idx = remapped_index(&view.remapped, 0, x, y);
+ offset = src_idx * PAGE_SIZE;
+
+ val = ioread32(&map[offset / sizeof(*map)]);
+ if (val != exp) {
+ pr_err("%s VMA write test failed, expected 0x%x, found 0x%x\n",
+ *t == I915_GGTT_VIEW_ROTATED ? "Rotated" : "Remapped",
+ val, exp);
+ i915_vma_unpin_iomap(vma);
+ goto out;
+ }
+ }
+ }
+ i915_vma_unpin_iomap(vma);
+ }
+ }
+
+out:
+ intel_runtime_pm_put(i915, wakeref);
+ mutex_unlock(&i915->drm.struct_mutex);
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
+int i915_vma_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_vma_remapped_gtt),
+ };
+
+ return i915_subtests(tests, i915);
+}
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest
2019-01-24 19:11 ` [PATCH v4 " Ville Syrjala
@ 2019-01-24 23:20 ` Chris Wilson
0 siblings, 0 replies; 44+ messages in thread
From: Chris Wilson @ 2019-01-24 23:20 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2019-01-24 19:11:57)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a live selftest to excercise rotated/remapped vmas. We simply
> write through the rotated/remapped vma, and confirm that the data
> appears in the right page when read through the normal vma.
>
> Not sure what the fallout of making all rotated/remapped vmas
> mappable/fenceable would be, hence I just hacked it in the test.
>
> v2: Grab rpm reference (Chris)
> GEM_BUG_ON(view.type not as expected) (Chris)
> Allow CAN_FENCE for rotated/remapped vmas (Chris)
> Update intel_plane_uses_fence() to ask for a fence
> only for normal vmas on gen4+
> v3: Deal with intel_wakeref_t
> v4: Rebase
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (2 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-24 18:58 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
` (15 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have. Need to deal with the
fence POT requirements, and do something about the gen2
gtt page size vs tile size difference
v2: Rebase due to is_ccs_modifier()
Fix up the skl+ stride_mult mess
memset() the gtt_view because otherwise we could leave
junk in plane[1] when going from 2 plane to 1 plane format
v3: intel_check_plane_stride() was split out
v4: Drop the aligned viewport stuff, it was meant for ccs which
can't be remapped anyway
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 332 ++++++++++++++++++++-------
1 file changed, 255 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d5526ec34b4..86847cee833a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN(dev_priv, 2))
return 128;
@@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2459,6 +2448,82 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
+static
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+ * We assume the primary plane for pipe A has
+ * the highest stride limits of them all.
+ */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+ DRM_MODE_ROTATE_0);
+}
+
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ u32 max_stride = intel_plane_fb_max_stride(dev_priv,
+ fb->format->format,
+ fb->modifier);
+
+ /*
+ * To make remapping with linear generally feasible
+ * we need the stride to be page aligned.
+ */
+ if (fb->pitches[color_plane] > max_stride)
+ return intel_tile_size(dev_priv);
+ else
+ return 64;
+ } else {
+ return intel_tile_width_bytes(fb, color_plane);
+ }
+}
+
+static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride, max_stride;
+
+ /* We don't want to deal with remapping with cursors */
+ if (plane->id == PLANE_CURSOR)
+ return false;
+
+ /* No fence for the remapped vma */
+ if (INTEL_GEN(dev_priv) < 4)
+ return false;
+
+ /* New CCS hash mode makes remapping impossible */
+ if (is_ccs_modifier(fb->modifier))
+ return false;
+
+ /* FIXME other color planes? */
+ stride = intel_fb_pitch(fb, 0, rotation);
+ max_stride = plane->max_stride(plane, fb->format->format,
+ fb->modifier, rotation);
+
+ return stride > max_stride;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2624,6 +2689,167 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return 0;
}
+static void
+intel_plane_remap_gtt(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct intel_rotation_info *info = &plane_state->view.rotated;
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->format->num_planes;
+ unsigned int tile_size = intel_tile_size(dev_priv);
+ unsigned int src_x, src_y;
+ unsigned int src_w, src_h;
+ u32 gtt_offset = 0;
+
+ memset(&plane_state->view, 0, sizeof(plane_state->view));
+ plane_state->view.type = drm_rotation_90_or_270(rotation) ?
+ I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+
+ WARN_ON(is_ccs_modifier(fb->modifier));
+
+ /* Make src coordinates relative to the viewport */
+ drm_rect_translate(&plane_state->base.src,
+ -(src_x << 16), -(src_y << 16));
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ src_w << 16, src_h << 16,
+ DRM_MODE_ROTATE_270);
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int hsub = i ? fb->format->hsub : 1;
+ unsigned int vsub = i ? fb->format->vsub : 1;
+ unsigned int cpp = fb->format->cpp[i];
+ unsigned int tile_width, tile_height;
+ unsigned int width, height;
+ unsigned int pitch_tiles;
+ unsigned int x, y;
+ u32 offset;
+
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+
+ x = src_x / hsub;
+ y = src_y / vsub;
+ width = src_w / hsub;
+ height = src_h / vsub;
+
+ /*
+ * First pixel of the src viewport from the
+ * start of the normal gtt mapping.
+ */
+ x += intel_fb->normal[i].x;
+ y += intel_fb->normal[i].y;
+
+ offset = intel_compute_aligned_offset(dev_priv, &x, &y,
+ fb, i, fb->pitches[i],
+ DRM_MODE_ROTATE_0, tile_size);
+ offset /= tile_size;
+
+ info->plane[i].offset = offset;
+ info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
+ tile_width * cpp);
+ info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
+ info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
+
+ if (drm_rotation_90_or_270(rotation)) {
+ struct drm_rect r;
+
+ /* rotate the x/y offsets to match the GTT view */
+ r.x1 = x;
+ r.y1 = y;
+ r.x2 = x + width;
+ r.y2 = y + height;
+ drm_rect_rotate(&r,
+ info->plane[i].width * tile_width,
+ info->plane[i].height * tile_height,
+ DRM_MODE_ROTATE_270);
+ x = r.x1;
+ y = r.y1;
+
+ pitch_tiles = info->plane[i].height;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_height;
+
+ /* rotate the tile dimensions to match the GTT view */
+ swap(tile_width, tile_height);
+ } else {
+ pitch_tiles = info->plane[i].width;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
+ }
+
+ /*
+ * We only keep the x/y offsets, so push all of the
+ * gtt offset into the x/y offsets.
+ */
+ intel_adjust_tile_offset(&x, &y,
+ tile_width, tile_height,
+ tile_size, pitch_tiles,
+ gtt_offset * tile_size, 0);
+
+ gtt_offset += info->plane[i].width * info->plane[i].height;
+
+ plane_state->color_plane[i].offset = 0;
+ plane_state->color_plane[i].x = x;
+ plane_state->color_plane[i].y = y;
+ }
+}
+
+static int
+intel_plane_compute_gtt(struct intel_plane_state *plane_state)
+{
+ const struct intel_framebuffer *fb =
+ to_intel_framebuffer(plane_state->base.fb);
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->base.format->num_planes;
+ int ret;
+
+ if (intel_plane_needs_remap(plane_state)) {
+ intel_plane_remap_gtt(plane_state);
+
+ /* Remapping should take care of this always */
+ ret = intel_plane_check_stride(plane_state);
+ if (WARN_ON(ret))
+ return ret;
+
+ return 0;
+ }
+
+ intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
+
+ for (i = 0; i < num_planes; i++) {
+ plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
+ plane_state->color_plane[i].offset = 0;
+
+ if (drm_rotation_90_or_270(rotation)) {
+ plane_state->color_plane[i].x = fb->rotated[i].x;
+ plane_state->color_plane[i].y = fb->rotated[i].y;
+ } else {
+ plane_state->color_plane[i].x = fb->normal[i].x;
+ plane_state->color_plane[i].y = fb->normal[i].y;
+ }
+ }
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ fb->base.width << 16, fb->base.height << 16,
+ DRM_MODE_ROTATE_270);
+
+ ret = intel_plane_check_stride(plane_state);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
@@ -3127,26 +3353,12 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
- plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
- if (!plane_state->base.visible)
- return 0;
-
- /* Rotate src coordinates to match rotated GTT view */
- if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
- fb->width << 16, fb->height << 16,
- DRM_MODE_ROTATE_270);
-
/*
* Handle the AUX surface first since
* the main surface setup depends on it.
@@ -3265,20 +3477,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int src_x = plane_state->base.src.x1 >> 16;
- int src_y = plane_state->base.src.y1 >> 16;
+ int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -3289,6 +3498,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
+ unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3459,15 +3669,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static u32
-intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
-{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 64;
- else
- return intel_tile_width_bytes(fb, color_plane);
-}
-
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -9829,16 +10030,11 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
@@ -14571,31 +14767,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
.dirty = intel_user_framebuffer_dirty,
};
-static
-u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
- u32 pixel_format, u64 fb_modifier)
-{
- struct intel_crtc *crtc;
- struct intel_plane *plane;
-
- /*
- * We assume the primary plane for pipe A has
- * the highest stride limits of them all.
- */
- crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
- plane = to_intel_plane(crtc->base.primary);
-
- return plane->max_stride(plane, pixel_format, fb_modifier,
- DRM_MODE_ROTATE_0);
-}
-
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_framebuffer *fb = &intel_fb->base;
- u32 pitch_limit;
+ u32 max_stride;
unsigned int tiling, stride;
int ret = -EINVAL;
int i;
@@ -14647,13 +14825,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
- mode_cmd->modifier[0]);
- if (mode_cmd->pitches[0] > pitch_limit) {
+ max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
+ mode_cmd->modifier[0]);
+ if (mode_cmd->pitches[0] > max_stride) {
DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
"tiled" : "linear",
- mode_cmd->pitches[0], pitch_limit);
+ mode_cmd->pitches[0], max_stride);
goto err;
}
--
2.19.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-01-18 15:27 ` [PATCH v3 4/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
@ 2019-01-24 18:58 ` Ville Syrjala
2019-01-30 19:01 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-24 18:58 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have. Need to deal with the
fence POT requirements, and do something about the gen2
gtt page size vs tile size difference
v2: Rebase due to is_ccs_modifier()
Fix up the skl+ stride_mult mess
memset() the gtt_view because otherwise we could leave
junk in plane[1] when going from 2 plane to 1 plane format
v3: intel_check_plane_stride() was split out
v4: Drop the aligned viewport stuff, it was meant for ccs which
can't be remapped anyway
v5: Introduce intel_plane_can_remap()
Reorder the code so that plane_state->view gets filled
even for invisible planes, otherwise we'd keep using
stale values and could explode during remapping. The new
logic never remaps invisible planes since we don't have
a viewport, and instead pins the full fb instead
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 393 +++++++++++++++++++++------
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
3 files changed, 334 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 17c7edee9584..3713b6f1796e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN(dev_priv, 2))
return 128;
@@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2459,6 +2448,119 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
+static
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+ * We assume the primary plane for pipe A has
+ * the highest stride limits of them all.
+ */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+ DRM_MODE_ROTATE_0);
+}
+
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ u32 max_stride = intel_plane_fb_max_stride(dev_priv,
+ fb->format->format,
+ fb->modifier);
+
+ /*
+ * To make remapping with linear generally feasible
+ * we need the stride to be page aligned.
+ */
+ if (fb->pitches[color_plane] > max_stride)
+ return intel_tile_size(dev_priv);
+ else
+ return 64;
+ } else {
+ return intel_tile_width_bytes(fb, color_plane);
+ }
+}
+
+bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ int i;
+
+ /* We don't want to deal with remapping with cursors */
+ if (plane->id == PLANE_CURSOR)
+ return false;
+
+ /*
+ * The dsplay engine limits already match the render
+ * engine limits, so not much point in remapping.
+ * Would also need to deal with the fence POT alignment
+ * and gen2 2KiB GTT tile size.
+ */
+ if (INTEL_GEN(dev_priv) < 4)
+ return false;
+
+ /*
+ * The new CCS hash mode isn't compatible with remapping as
+ * the virtual address of the pages affects the compressed data.
+ */
+ if (is_ccs_modifier(fb->modifier))
+ return false;
+
+ /* Linear needs a page aligned stride for remapping */
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ unsigned int alignment = intel_tile_size(dev_priv) - 1;
+
+ for (i = 0; i < fb->format->num_planes; i++) {
+ if (fb->pitches[i] & alignment)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride, max_stride;
+
+ /*
+ * No remapping for invisible planes since we don't have
+ * an actual source viewport to remap.
+ */
+ if (!plane_state->base.visible)
+ return false;
+
+ if (!intel_plane_can_remap(plane_state))
+ return false;
+
+ /* FIXME other color planes? */
+ stride = intel_fb_pitch(fb, 0, rotation);
+ max_stride = plane->max_stride(plane, fb->format->format,
+ fb->modifier, rotation);
+
+ return stride > max_stride;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2624,6 +2726,172 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return 0;
}
+static void
+intel_plane_remap_gtt(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct intel_rotation_info *info = &plane_state->view.rotated;
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->format->num_planes;
+ unsigned int tile_size = intel_tile_size(dev_priv);
+ unsigned int src_x, src_y;
+ unsigned int src_w, src_h;
+ u32 gtt_offset = 0;
+
+ memset(&plane_state->view, 0, sizeof(plane_state->view));
+ plane_state->view.type = drm_rotation_90_or_270(rotation) ?
+ I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+
+ WARN_ON(is_ccs_modifier(fb->modifier));
+
+ /* Make src coordinates relative to the viewport */
+ drm_rect_translate(&plane_state->base.src,
+ -(src_x << 16), -(src_y << 16));
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ src_w << 16, src_h << 16,
+ DRM_MODE_ROTATE_270);
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int hsub = i ? fb->format->hsub : 1;
+ unsigned int vsub = i ? fb->format->vsub : 1;
+ unsigned int cpp = fb->format->cpp[i];
+ unsigned int tile_width, tile_height;
+ unsigned int width, height;
+ unsigned int pitch_tiles;
+ unsigned int x, y;
+ u32 offset;
+
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+
+ x = src_x / hsub;
+ y = src_y / vsub;
+ width = src_w / hsub;
+ height = src_h / vsub;
+
+ /*
+ * First pixel of the src viewport from the
+ * start of the normal gtt mapping.
+ */
+ x += intel_fb->normal[i].x;
+ y += intel_fb->normal[i].y;
+
+ offset = intel_compute_aligned_offset(dev_priv, &x, &y,
+ fb, i, fb->pitches[i],
+ DRM_MODE_ROTATE_0, tile_size);
+ offset /= tile_size;
+
+ info->plane[i].offset = offset;
+ info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
+ tile_width * cpp);
+ info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
+ info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
+
+ if (drm_rotation_90_or_270(rotation)) {
+ struct drm_rect r;
+
+ /* rotate the x/y offsets to match the GTT view */
+ r.x1 = x;
+ r.y1 = y;
+ r.x2 = x + width;
+ r.y2 = y + height;
+ drm_rect_rotate(&r,
+ info->plane[i].width * tile_width,
+ info->plane[i].height * tile_height,
+ DRM_MODE_ROTATE_270);
+ x = r.x1;
+ y = r.y1;
+
+ pitch_tiles = info->plane[i].height;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_height;
+
+ /* rotate the tile dimensions to match the GTT view */
+ swap(tile_width, tile_height);
+ } else {
+ pitch_tiles = info->plane[i].width;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
+ }
+
+ /*
+ * We only keep the x/y offsets, so push all of the
+ * gtt offset into the x/y offsets.
+ */
+ intel_adjust_tile_offset(&x, &y,
+ tile_width, tile_height,
+ tile_size, pitch_tiles,
+ gtt_offset * tile_size, 0);
+
+ gtt_offset += info->plane[i].width * info->plane[i].height;
+
+ plane_state->color_plane[i].offset = 0;
+ plane_state->color_plane[i].x = x;
+ plane_state->color_plane[i].y = y;
+ }
+}
+
+static int
+intel_plane_compute_gtt(struct intel_plane_state *plane_state)
+{
+ const struct intel_framebuffer *fb =
+ to_intel_framebuffer(plane_state->base.fb);
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes;
+ int ret;
+
+ if (!fb)
+ return 0;
+
+ num_planes = fb->base.format->num_planes;
+
+ if (intel_plane_needs_remap(plane_state)) {
+ intel_plane_remap_gtt(plane_state);
+
+ /* Remapping should take care of this always */
+ ret = intel_plane_check_stride(plane_state);
+ if (WARN_ON(ret))
+ return ret;
+
+ return 0;
+ }
+
+ intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
+
+ for (i = 0; i < num_planes; i++) {
+ plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
+ plane_state->color_plane[i].offset = 0;
+
+ if (drm_rotation_90_or_270(rotation)) {
+ plane_state->color_plane[i].x = fb->rotated[i].x;
+ plane_state->color_plane[i].y = fb->rotated[i].y;
+ } else {
+ plane_state->color_plane[i].x = fb->normal[i].x;
+ plane_state->color_plane[i].y = fb->normal[i].y;
+ }
+ }
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ fb->base.width << 16, fb->base.height << 16,
+ DRM_MODE_ROTATE_270);
+
+ ret = intel_plane_check_stride(plane_state);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
@@ -3127,26 +3395,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
- plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
if (!plane_state->base.visible)
return 0;
- /* Rotate src coordinates to match rotated GTT view */
- if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
- fb->width << 16, fb->height << 16,
- DRM_MODE_ROTATE_270);
-
/*
* Handle the AUX surface first since
* the main surface setup depends on it.
@@ -3265,20 +3522,20 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int src_x = plane_state->base.src.x1 >> 16;
- int src_y = plane_state->base.src.y1 >> 16;
+ int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
+ if (!plane_state->base.visible)
+ return 0;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -3289,6 +3546,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
+ unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3325,6 +3583,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -3332,10 +3594,6 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
return 0;
@@ -3459,15 +3717,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static u32
-intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
-{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 64;
- else
- return intel_tile_width_bytes(fb, color_plane);
-}
-
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -9830,19 +10079,17 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
+ if (!plane_state->base.visible)
+ return 0;
+
src_x = plane_state->base.src_x >> 16;
src_y = plane_state->base.src_y >> 16;
@@ -9879,6 +10126,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = intel_cursor_check_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -9886,10 +10137,6 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = intel_cursor_check_surface(plane_state);
- if (ret)
- return ret;
-
return 0;
}
@@ -14591,31 +14838,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
.dirty = intel_user_framebuffer_dirty,
};
-static
-u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
- u32 pixel_format, u64 fb_modifier)
-{
- struct intel_crtc *crtc;
- struct intel_plane *plane;
-
- /*
- * We assume the primary plane for pipe A has
- * the highest stride limits of them all.
- */
- crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
- plane = to_intel_plane(crtc->base.primary);
-
- return plane->max_stride(plane, pixel_format, fb_modifier,
- DRM_MODE_ROTATE_0);
-}
-
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_framebuffer *fb = &intel_fb->base;
- u32 pitch_limit;
+ u32 max_stride;
unsigned int tiling, stride;
int ret = -EINVAL;
int i;
@@ -14667,13 +14896,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
- mode_cmd->modifier[0]);
- if (mode_cmd->pitches[0] > pitch_limit) {
+ max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
+ mode_cmd->modifier[0]);
+ if (mode_cmd->pitches[0] > max_stride) {
DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
"tiled" : "linear",
- mode_cmd->pitches[0], pitch_limit);
+ mode_cmd->pitches[0], max_stride);
goto err;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 813626322fa3..0ee73f9dea7c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1586,6 +1586,7 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
const char *context);
/* intel_display.c */
+bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index b02d3d9809e3..517747d08962 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -237,6 +237,16 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
unsigned int rotation = plane_state->base.rotation;
u32 stride, max_stride;
+ /*
+ * We ignore stride for all invisible planes that
+ * can be remapped. Otherwise we could end up
+ * with a false positive when the remapping didn't
+ * kick in due the plane being invisible.
+ */
+ if (intel_plane_can_remap(plane_state) &&
+ !plane_state->base.visible)
+ return 0;
+
/* FIXME other color planes? */
stride = plane_state->color_plane[0].stride;
max_stride = plane->max_stride(plane, fb->format->format,
@@ -1341,6 +1351,10 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1352,10 +1366,6 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
if (INTEL_GEN(dev_priv) >= 7)
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
else
@@ -1399,6 +1409,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1406,10 +1420,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
return 0;
@@ -1556,6 +1566,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = skl_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1571,10 +1585,6 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = skl_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
/* HW only has 8 bits pixel precision, disable plane if invisible */
if (!(plane_state->base.alpha >> 8))
plane_state->base.visible = false;
--
2.19.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v4 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-01-24 18:58 ` [PATCH v4 " Ville Syrjala
@ 2019-01-30 19:01 ` Daniel Vetter
2019-01-30 20:59 ` Ville Syrjälä
0 siblings, 1 reply; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 19:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2019 at 08:58:49PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The display engine stride limits are getting in our way. On SKL+
> we are limited to 8k pixels, which is easily exceeded with three
> 4k displays. To overcome this limitation we can remap the pages
> in the GTT to provide the display engine with a view of memory
> with a smaller stride.
>
> The code is mostly already there as We already play tricks with
> the plane surface address and x/y offsets.
>
> A few caveats apply:
> * linear buffers need the fb stride to be page aligned, as
> otherwise the remapped lines wouldn't start at the same
> spot
> * compressed buffers can't be remapped due to the new
> ccs hash mode causing the virtual address of the pages
> to affect the interpretation of the compressed data. IIRC
> the old hash was limited to the low 12 bits so if we were
> using that mode we could remap. As it stands we just refuse
> to remapp with compressed fbs.
> * no remapping gen2/3 as we'd need a fence for the remapped
> vma, which we currently don't have. Need to deal with the
> fence POT requirements, and do something about the gen2
> gtt page size vs tile size difference
>
> v2: Rebase due to is_ccs_modifier()
> Fix up the skl+ stride_mult mess
> memset() the gtt_view because otherwise we could leave
> junk in plane[1] when going from 2 plane to 1 plane format
> v3: intel_check_plane_stride() was split out
> v4: Drop the aligned viewport stuff, it was meant for ccs which
> can't be remapped anyway
> v5: Introduce intel_plane_can_remap()
> Reorder the code so that plane_state->view gets filled
> even for invisible planes, otherwise we'd keep using
> stale values and could explode during remapping. The new
> logic never remaps invisible planes since we don't have
> a viewport, and instead pins the full fb instead
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 393 +++++++++++++++++++++------
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
> 3 files changed, 334 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 17c7edee9584..3713b6f1796e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>
> switch (fb->modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> - return cpp;
> + return intel_tile_size(dev_priv);
> case I915_FORMAT_MOD_X_TILED:
> if (IS_GEN(dev_priv, 2))
> return 128;
> @@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> static unsigned int
> intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> {
> - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> - return 1;
> - else
> - return intel_tile_size(to_i915(fb->dev)) /
> - intel_tile_width_bytes(fb, color_plane);
> + return intel_tile_size(to_i915(fb->dev)) /
> + intel_tile_width_bytes(fb, color_plane);
> }
>
> /* Return the tile dimensions in pixel units */
> @@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
> int color_plane)
>
> {
> - const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> - unsigned int rotation = state->base.rotation;
> -
> - if (drm_rotation_90_or_270(rotation)) {
> - *x += intel_fb->rotated[color_plane].x;
> - *y += intel_fb->rotated[color_plane].y;
> - } else {
> - *x += intel_fb->normal[color_plane].x;
> - *y += intel_fb->normal[color_plane].y;
> - }
> + *x += state->color_plane[color_plane].x;
> + *y += state->color_plane[color_plane].y;
> }
>
> static u32 intel_adjust_tile_offset(int *x, int *y,
> @@ -2459,6 +2448,119 @@ bool is_ccs_modifier(u64 modifier)
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
>
> +static
> +u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> + u32 pixel_format, u64 modifier)
> +{
> + struct intel_crtc *crtc;
> + struct intel_plane *plane;
> +
> + /*
> + * We assume the primary plane for pipe A has
> + * the highest stride limits of them all.
> + */
> + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> + plane = to_intel_plane(crtc->base.primary);
> +
> + return plane->max_stride(plane, pixel_format, modifier,
> + DRM_MODE_ROTATE_0);
> +}
> +
> +static
> +u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> + u32 pixel_format, u64 modifier)
> +{
> + return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
> +}
> +
> +static u32
> +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +
> + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> + u32 max_stride = intel_plane_fb_max_stride(dev_priv,
> + fb->format->format,
> + fb->modifier);
> +
> + /*
> + * To make remapping with linear generally feasible
> + * we need the stride to be page aligned.
> + */
> + if (fb->pitches[color_plane] > max_stride)
> + return intel_tile_size(dev_priv);
> + else
> + return 64;
> + } else {
> + return intel_tile_width_bytes(fb, color_plane);
> + }
> +}
> +
> +bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + int i;
> +
> + /* We don't want to deal with remapping with cursors */
> + if (plane->id == PLANE_CURSOR)
> + return false;
They should be caught in the stride check below anyway ... why special
case?
> +
> + /*
> + * The dsplay engine limits already match the render
> + * engine limits, so not much point in remapping.
> + * Would also need to deal with the fence POT alignment
> + * and gen2 2KiB GTT tile size.
> + */
> + if (INTEL_GEN(dev_priv) < 4)
> + return false;
> +
> + /*
> + * The new CCS hash mode isn't compatible with remapping as
> + * the virtual address of the pages affects the compressed data.
> + */
> + if (is_ccs_modifier(fb->modifier))
> + return false;
> +
> + /* Linear needs a page aligned stride for remapping */
> + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
Not sure whether cramming linear formats into the same macheniry is really
clever in a good way or bad way (because too tricky). I guess it works,
and this is not something that's well explaing in some comments sprinkled
all over.
*shrug*
> + unsigned int alignment = intel_tile_size(dev_priv) - 1;
> +
> + for (i = 0; i < fb->format->num_planes; i++) {
> + if (fb->pitches[i] & alignment)
> + return false;
> + }
> + }
> +
> + return true;
> +}
> +
> +static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + unsigned int rotation = plane_state->base.rotation;
> + u32 stride, max_stride;
> +
> + /*
> + * No remapping for invisible planes since we don't have
> + * an actual source viewport to remap.
> + */
> + if (!plane_state->base.visible)
> + return false;
> +
> + if (!intel_plane_can_remap(plane_state))
> + return false;
> +
> + /* FIXME other color planes? */
Should be simple to fix if we do a similar loop like in can_remap above.
Just true if any of them are bigger than max stride.
> + stride = intel_fb_pitch(fb, 0, rotation);
> + max_stride = plane->max_stride(plane, fb->format->format,
> + fb->modifier, rotation);
> +
> + return stride > max_stride;
> +}
> +
> static int
> intel_fill_fb_info(struct drm_i915_private *dev_priv,
> struct drm_framebuffer *fb)
> @@ -2624,6 +2726,172 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> return 0;
> }
>
> +static void
> +intel_plane_remap_gtt(struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct drm_framebuffer *fb = plane_state->base.fb;
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> + struct intel_rotation_info *info = &plane_state->view.rotated;
> + unsigned int rotation = plane_state->base.rotation;
> + int i, num_planes = fb->format->num_planes;
> + unsigned int tile_size = intel_tile_size(dev_priv);
> + unsigned int src_x, src_y;
> + unsigned int src_w, src_h;
> + u32 gtt_offset = 0;
> +
> + memset(&plane_state->view, 0, sizeof(plane_state->view));
> + plane_state->view.type = drm_rotation_90_or_270(rotation) ?
> + I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
> +
> + src_x = plane_state->base.src.x1 >> 16;
> + src_y = plane_state->base.src.y1 >> 16;
> + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> +
> + WARN_ON(is_ccs_modifier(fb->modifier));
> +
> + /* Make src coordinates relative to the viewport */
> + drm_rect_translate(&plane_state->base.src,
> + -(src_x << 16), -(src_y << 16));
> +
> + /* Rotate src coordinates to match rotated GTT view */
> + if (drm_rotation_90_or_270(rotation))
> + drm_rect_rotate(&plane_state->base.src,
> + src_w << 16, src_h << 16,
> + DRM_MODE_ROTATE_270);
> +
> + for (i = 0; i < num_planes; i++) {
> + unsigned int hsub = i ? fb->format->hsub : 1;
> + unsigned int vsub = i ? fb->format->vsub : 1;
> + unsigned int cpp = fb->format->cpp[i];
> + unsigned int tile_width, tile_height;
> + unsigned int width, height;
> + unsigned int pitch_tiles;
> + unsigned int x, y;
> + u32 offset;
> +
> + intel_tile_dims(fb, i, &tile_width, &tile_height);
> +
> + x = src_x / hsub;
> + y = src_y / vsub;
> + width = src_w / hsub;
> + height = src_h / vsub;
> +
> + /*
> + * First pixel of the src viewport from the
> + * start of the normal gtt mapping.
> + */
> + x += intel_fb->normal[i].x;
> + y += intel_fb->normal[i].y;
> +
> + offset = intel_compute_aligned_offset(dev_priv, &x, &y,
> + fb, i, fb->pitches[i],
> + DRM_MODE_ROTATE_0, tile_size);
> + offset /= tile_size;
> +
> + info->plane[i].offset = offset;
> + info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
> + tile_width * cpp);
> + info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
> + info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
> +
> + if (drm_rotation_90_or_270(rotation)) {
> + struct drm_rect r;
> +
> + /* rotate the x/y offsets to match the GTT view */
> + r.x1 = x;
> + r.y1 = y;
> + r.x2 = x + width;
> + r.y2 = y + height;
> + drm_rect_rotate(&r,
> + info->plane[i].width * tile_width,
> + info->plane[i].height * tile_height,
> + DRM_MODE_ROTATE_270);
> + x = r.x1;
> + y = r.y1;
> +
> + pitch_tiles = info->plane[i].height;
> + plane_state->color_plane[i].stride = pitch_tiles * tile_height;
> +
> + /* rotate the tile dimensions to match the GTT view */
> + swap(tile_width, tile_height);
> + } else {
> + pitch_tiles = info->plane[i].width;
> + plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
> + }
> +
> + /*
> + * We only keep the x/y offsets, so push all of the
> + * gtt offset into the x/y offsets.
> + */
> + intel_adjust_tile_offset(&x, &y,
> + tile_width, tile_height,
> + tile_size, pitch_tiles,
> + gtt_offset * tile_size, 0);
> +
> + gtt_offset += info->plane[i].width * info->plane[i].height;
> +
> + plane_state->color_plane[i].offset = 0;
> + plane_state->color_plane[i].x = x;
> + plane_state->color_plane[i].y = y;
> + }
> +}
Validating this freaks me out. Keeping it working freaks me out even more,
there's pretty much a guarantee that we don't.
Also, I'm not sure CI exercises this much even with your hacks. Most of
our kms tests use single-crtc buffers, so no massive overallocation, so no
real need for views. The selftests are good, but they don't cover the
massive pile of pixel/coordination frobbing above.
I think only thing that can validate this is:
- a pile of igts that make sure we overallocate plentiful, while still
exercising all the major fb layouts (rotated, all the different cpp,
tiling formats, and throw in a ccs for lols to make sure nothing blows
up).
- kernel patch to prefer remmaped over normal. Don't move your buffers
around too much though :-)
Now the second part isn't really a real world thing, since even with
y-tiled that means remapping the view every 32 pixels (on average, worse
if your edges aren't aligned to 32 pixels, then it's twice as much).
So I think the only thing that works for validating this beast is a pile
of new igts that allocate dumb&tiled buffers at the size limit, and do all
the rotations/scaling/moving tests we already have.
Yes this is painful.
> +
> +static int
> +intel_plane_compute_gtt(struct intel_plane_state *plane_state)
> +{
> + const struct intel_framebuffer *fb =
> + to_intel_framebuffer(plane_state->base.fb);
> + unsigned int rotation = plane_state->base.rotation;
> + int i, num_planes;
> + int ret;
> +
> + if (!fb)
> + return 0;
> +
> + num_planes = fb->base.format->num_planes;
> +
> + if (intel_plane_needs_remap(plane_state)) {
> + intel_plane_remap_gtt(plane_state);
> +
> + /* Remapping should take care of this always */
> + ret = intel_plane_check_stride(plane_state);
> + if (WARN_ON(ret))
> + return ret;
> +
> + return 0;
> + }
> +
> + intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
> +
> + for (i = 0; i < num_planes; i++) {
> + plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
> + plane_state->color_plane[i].offset = 0;
> +
> + if (drm_rotation_90_or_270(rotation)) {
> + plane_state->color_plane[i].x = fb->rotated[i].x;
> + plane_state->color_plane[i].y = fb->rotated[i].y;
> + } else {
> + plane_state->color_plane[i].x = fb->normal[i].x;
> + plane_state->color_plane[i].y = fb->normal[i].y;
> + }
> + }
> +
> + /* Rotate src coordinates to match rotated GTT view */
> + if (drm_rotation_90_or_270(rotation))
> + drm_rect_rotate(&plane_state->base.src,
> + fb->base.width << 16, fb->base.height << 16,
> + DRM_MODE_ROTATE_270);
> +
> + ret = intel_plane_check_stride(plane_state);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
Splitting the refactoring from the actual feature adding would be nice.
> +
> static int i9xx_format_to_fourcc(int format)
> {
> switch (format) {
> @@ -3127,26 +3395,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> int skl_check_plane_surface(struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> - unsigned int rotation = plane_state->base.rotation;
> int ret;
>
> - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> - plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
> -
> - ret = intel_plane_check_stride(plane_state);
> + ret = intel_plane_compute_gtt(plane_state);
> if (ret)
> return ret;
>
> if (!plane_state->base.visible)
> return 0;
>
> - /* Rotate src coordinates to match rotated GTT view */
> - if (drm_rotation_90_or_270(rotation))
> - drm_rect_rotate(&plane_state->base.src,
> - fb->width << 16, fb->height << 16,
> - DRM_MODE_ROTATE_270);
> -
> /*
> * Handle the AUX surface first since
> * the main surface setup depends on it.
> @@ -3265,20 +3522,20 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> - unsigned int rotation = plane_state->base.rotation;
> - int src_x = plane_state->base.src.x1 >> 16;
> - int src_y = plane_state->base.src.y1 >> 16;
> + int src_x, src_y;
> u32 offset;
> int ret;
>
> - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> -
> - ret = intel_plane_check_stride(plane_state);
> + ret = intel_plane_compute_gtt(plane_state);
> if (ret)
> return ret;
>
> + if (!plane_state->base.visible)
> + return 0;
> +
> + src_x = plane_state->base.src.x1 >> 16;
> + src_y = plane_state->base.src.y1 >> 16;
> +
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>
> if (INTEL_GEN(dev_priv) >= 4)
> @@ -3289,6 +3546,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
>
> /* HSW/BDW do this automagically in hardware */
> if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> + unsigned int rotation = plane_state->base.rotation;
> int src_w = drm_rect_width(&plane_state->base.src) >> 16;
> int src_h = drm_rect_height(&plane_state->base.src) >> 16;
>
> @@ -3325,6 +3583,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> if (!plane_state->base.visible)
> return 0;
>
> @@ -3332,10 +3594,6 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = i9xx_check_plane_surface(plane_state);
> - if (ret)
> - return ret;
> -
> plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
>
> return 0;
> @@ -3459,15 +3717,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> return ret;
> }
>
> -static u32
> -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> -{
> - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> - return 64;
> - else
> - return intel_tile_width_bytes(fb, color_plane);
> -}
> -
> static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> {
> struct drm_device *dev = intel_crtc->base.dev;
> @@ -9830,19 +10079,17 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
>
> static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> {
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> - unsigned int rotation = plane_state->base.rotation;
> int src_x, src_y;
> u32 offset;
> int ret;
>
> - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> -
> - ret = intel_plane_check_stride(plane_state);
> + ret = intel_plane_compute_gtt(plane_state);
> if (ret)
> return ret;
>
> + if (!plane_state->base.visible)
> + return 0;
> +
> src_x = plane_state->base.src_x >> 16;
> src_y = plane_state->base.src_y >> 16;
>
> @@ -9879,6 +10126,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + ret = intel_cursor_check_surface(plane_state);
> + if (ret)
> + return ret;
> +
> if (!plane_state->base.visible)
> return 0;
>
> @@ -9886,10 +10137,6 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = intel_cursor_check_surface(plane_state);
> - if (ret)
> - return ret;
> -
> return 0;
> }
>
> @@ -14591,31 +14838,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> .dirty = intel_user_framebuffer_dirty,
> };
>
> -static
> -u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> - u32 pixel_format, u64 fb_modifier)
> -{
> - struct intel_crtc *crtc;
> - struct intel_plane *plane;
> -
> - /*
> - * We assume the primary plane for pipe A has
> - * the highest stride limits of them all.
> - */
> - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> - plane = to_intel_plane(crtc->base.primary);
> -
> - return plane->max_stride(plane, pixel_format, fb_modifier,
> - DRM_MODE_ROTATE_0);
> -}
> -
> static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd)
> {
> struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> struct drm_framebuffer *fb = &intel_fb->base;
> - u32 pitch_limit;
> + u32 max_stride;
> unsigned int tiling, stride;
> int ret = -EINVAL;
> int i;
> @@ -14667,13 +14896,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
>
> - pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
> - mode_cmd->modifier[0]);
> - if (mode_cmd->pitches[0] > pitch_limit) {
> + max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
> + mode_cmd->modifier[0]);
> + if (mode_cmd->pitches[0] > max_stride) {
> DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
> mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
> "tiled" : "linear",
> - mode_cmd->pitches[0], pitch_limit);
> + mode_cmd->pitches[0], max_stride);
> goto err;
> }
>
We need an intel_framebuffer|plane.c. And a metric pile of other extracted
files, probably also per major platforms and stuff like that :-/
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 813626322fa3..0ee73f9dea7c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1586,6 +1586,7 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> const char *context);
>
> /* intel_display.c */
> +bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index b02d3d9809e3..517747d08962 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -237,6 +237,16 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
> unsigned int rotation = plane_state->base.rotation;
> u32 stride, max_stride;
>
> + /*
> + * We ignore stride for all invisible planes that
> + * can be remapped. Otherwise we could end up
> + * with a false positive when the remapping didn't
> + * kick in due the plane being invisible.
> + */
> + if (intel_plane_can_remap(plane_state) &&
> + !plane_state->base.visible)
> + return 0;
> +
> /* FIXME other color planes? */
> stride = plane_state->color_plane[0].stride;
> max_stride = plane->max_stride(plane, fb->format->format,
> @@ -1341,6 +1351,10 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> if (!plane_state->base.visible)
> return 0;
>
> @@ -1352,10 +1366,6 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = i9xx_check_plane_surface(plane_state);
> - if (ret)
> - return ret;
> -
> if (INTEL_GEN(dev_priv) >= 7)
> plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
> else
> @@ -1399,6 +1409,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> if (!plane_state->base.visible)
> return 0;
>
> @@ -1406,10 +1420,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = i9xx_check_plane_surface(plane_state);
> - if (ret)
> - return ret;
> -
> plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
>
> return 0;
> @@ -1556,6 +1566,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> + ret = skl_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> if (!plane_state->base.visible)
> return 0;
>
> @@ -1571,10 +1585,6 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - ret = skl_check_plane_surface(plane_state);
> - if (ret)
> - return ret;
> -
> /* HW only has 8 bits pixel precision, disable plane if invisible */
> if (!(plane_state->base.alpha >> 8))
> plane_state->base.visible = false;
Code looks good, but the testing freaks me out. Needs lots of igt, I'd say
at least similar amounts to what we've all added for the original
kms_rotation tests.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-01-30 19:01 ` Daniel Vetter
@ 2019-01-30 20:59 ` Ville Syrjälä
2019-01-30 21:55 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjälä @ 2019-01-30 20:59 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 08:01:21PM +0100, Daniel Vetter wrote:
> On Thu, Jan 24, 2019 at 08:58:49PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The display engine stride limits are getting in our way. On SKL+
> > we are limited to 8k pixels, which is easily exceeded with three
> > 4k displays. To overcome this limitation we can remap the pages
> > in the GTT to provide the display engine with a view of memory
> > with a smaller stride.
> >
> > The code is mostly already there as We already play tricks with
> > the plane surface address and x/y offsets.
> >
> > A few caveats apply:
> > * linear buffers need the fb stride to be page aligned, as
> > otherwise the remapped lines wouldn't start at the same
> > spot
> > * compressed buffers can't be remapped due to the new
> > ccs hash mode causing the virtual address of the pages
> > to affect the interpretation of the compressed data. IIRC
> > the old hash was limited to the low 12 bits so if we were
> > using that mode we could remap. As it stands we just refuse
> > to remapp with compressed fbs.
> > * no remapping gen2/3 as we'd need a fence for the remapped
> > vma, which we currently don't have. Need to deal with the
> > fence POT requirements, and do something about the gen2
> > gtt page size vs tile size difference
> >
> > v2: Rebase due to is_ccs_modifier()
> > Fix up the skl+ stride_mult mess
> > memset() the gtt_view because otherwise we could leave
> > junk in plane[1] when going from 2 plane to 1 plane format
> > v3: intel_check_plane_stride() was split out
> > v4: Drop the aligned viewport stuff, it was meant for ccs which
> > can't be remapped anyway
> > v5: Introduce intel_plane_can_remap()
> > Reorder the code so that plane_state->view gets filled
> > even for invisible planes, otherwise we'd keep using
> > stale values and could explode during remapping. The new
> > logic never remaps invisible planes since we don't have
> > a viewport, and instead pins the full fb instead
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 393 +++++++++++++++++++++------
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
> > 3 files changed, 334 insertions(+), 94 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 17c7edee9584..3713b6f1796e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >
> > switch (fb->modifier) {
> > case DRM_FORMAT_MOD_LINEAR:
> > - return cpp;
> > + return intel_tile_size(dev_priv);
> > case I915_FORMAT_MOD_X_TILED:
> > if (IS_GEN(dev_priv, 2))
> > return 128;
> > @@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > static unsigned int
> > intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> > {
> > - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > - return 1;
> > - else
> > - return intel_tile_size(to_i915(fb->dev)) /
> > - intel_tile_width_bytes(fb, color_plane);
> > + return intel_tile_size(to_i915(fb->dev)) /
> > + intel_tile_width_bytes(fb, color_plane);
> > }
> >
> > /* Return the tile dimensions in pixel units */
> > @@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
> > int color_plane)
> >
> > {
> > - const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> > - unsigned int rotation = state->base.rotation;
> > -
> > - if (drm_rotation_90_or_270(rotation)) {
> > - *x += intel_fb->rotated[color_plane].x;
> > - *y += intel_fb->rotated[color_plane].y;
> > - } else {
> > - *x += intel_fb->normal[color_plane].x;
> > - *y += intel_fb->normal[color_plane].y;
> > - }
> > + *x += state->color_plane[color_plane].x;
> > + *y += state->color_plane[color_plane].y;
> > }
> >
> > static u32 intel_adjust_tile_offset(int *x, int *y,
> > @@ -2459,6 +2448,119 @@ bool is_ccs_modifier(u64 modifier)
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > }
> >
> > +static
> > +u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > + u32 pixel_format, u64 modifier)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_plane *plane;
> > +
> > + /*
> > + * We assume the primary plane for pipe A has
> > + * the highest stride limits of them all.
> > + */
> > + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > + plane = to_intel_plane(crtc->base.primary);
> > +
> > + return plane->max_stride(plane, pixel_format, modifier,
> > + DRM_MODE_ROTATE_0);
> > +}
> > +
> > +static
> > +u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> > + u32 pixel_format, u64 modifier)
> > +{
> > + return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
> > +}
> > +
> > +static u32
> > +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > +
> > + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> > + u32 max_stride = intel_plane_fb_max_stride(dev_priv,
> > + fb->format->format,
> > + fb->modifier);
> > +
> > + /*
> > + * To make remapping with linear generally feasible
> > + * we need the stride to be page aligned.
> > + */
> > + if (fb->pitches[color_plane] > max_stride)
> > + return intel_tile_size(dev_priv);
> > + else
> > + return 64;
> > + } else {
> > + return intel_tile_width_bytes(fb, color_plane);
> > + }
> > +}
> > +
> > +bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + int i;
> > +
> > + /* We don't want to deal with remapping with cursors */
> > + if (plane->id == PLANE_CURSOR)
> > + return false;
>
> They should be caught in the stride check below anyway ... why special
> case?
I guess we could just drop this. Hmm, yeah even i845/i865 with
their max cursor stride of 2k should get rejected later.
>
> > +
> > + /*
> > + * The dsplay engine limits already match the render
> > + * engine limits, so not much point in remapping.
> > + * Would also need to deal with the fence POT alignment
> > + * and gen2 2KiB GTT tile size.
> > + */
> > + if (INTEL_GEN(dev_priv) < 4)
> > + return false;
> > +
> > + /*
> > + * The new CCS hash mode isn't compatible with remapping as
> > + * the virtual address of the pages affects the compressed data.
> > + */
> > + if (is_ccs_modifier(fb->modifier))
> > + return false;
> > +
> > + /* Linear needs a page aligned stride for remapping */
> > + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
>
> Not sure whether cramming linear formats into the same macheniry is really
> clever in a good way or bad way (because too tricky). I guess it works,
> and this is not something that's well explaing in some comments sprinkled
> all over.
>
> *shrug*
>
> > + unsigned int alignment = intel_tile_size(dev_priv) - 1;
> > +
> > + for (i = 0; i < fb->format->num_planes; i++) {
> > + if (fb->pitches[i] & alignment)
> > + return false;
> > + }
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + unsigned int rotation = plane_state->base.rotation;
> > + u32 stride, max_stride;
> > +
> > + /*
> > + * No remapping for invisible planes since we don't have
> > + * an actual source viewport to remap.
> > + */
> > + if (!plane_state->base.visible)
> > + return false;
> > +
> > + if (!intel_plane_can_remap(plane_state))
> > + return false;
> > +
> > + /* FIXME other color planes? */
>
> Should be simple to fix if we do a similar loop like in can_remap above.
> Just true if any of them are bigger than max stride.
That's assuming the max stride for each plane is the same. Which
it might not be. IIRC the skl+ docs didn't really say what the max
aux stride is.
>
> > + stride = intel_fb_pitch(fb, 0, rotation);
> > + max_stride = plane->max_stride(plane, fb->format->format,
> > + fb->modifier, rotation);
> > +
> > + return stride > max_stride;
> > +}
> > +
> > static int
> > intel_fill_fb_info(struct drm_i915_private *dev_priv,
> > struct drm_framebuffer *fb)
> > @@ -2624,6 +2726,172 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> > return 0;
> > }
> >
> > +static void
> > +intel_plane_remap_gtt(struct intel_plane_state *plane_state)
> > +{
> > + struct drm_i915_private *dev_priv =
> > + to_i915(plane_state->base.plane->dev);
> > + struct drm_framebuffer *fb = plane_state->base.fb;
> > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > + struct intel_rotation_info *info = &plane_state->view.rotated;
> > + unsigned int rotation = plane_state->base.rotation;
> > + int i, num_planes = fb->format->num_planes;
> > + unsigned int tile_size = intel_tile_size(dev_priv);
> > + unsigned int src_x, src_y;
> > + unsigned int src_w, src_h;
> > + u32 gtt_offset = 0;
> > +
> > + memset(&plane_state->view, 0, sizeof(plane_state->view));
> > + plane_state->view.type = drm_rotation_90_or_270(rotation) ?
> > + I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
> > +
> > + src_x = plane_state->base.src.x1 >> 16;
> > + src_y = plane_state->base.src.y1 >> 16;
> > + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > +
> > + WARN_ON(is_ccs_modifier(fb->modifier));
> > +
> > + /* Make src coordinates relative to the viewport */
> > + drm_rect_translate(&plane_state->base.src,
> > + -(src_x << 16), -(src_y << 16));
> > +
> > + /* Rotate src coordinates to match rotated GTT view */
> > + if (drm_rotation_90_or_270(rotation))
> > + drm_rect_rotate(&plane_state->base.src,
> > + src_w << 16, src_h << 16,
> > + DRM_MODE_ROTATE_270);
> > +
> > + for (i = 0; i < num_planes; i++) {
> > + unsigned int hsub = i ? fb->format->hsub : 1;
> > + unsigned int vsub = i ? fb->format->vsub : 1;
> > + unsigned int cpp = fb->format->cpp[i];
> > + unsigned int tile_width, tile_height;
> > + unsigned int width, height;
> > + unsigned int pitch_tiles;
> > + unsigned int x, y;
> > + u32 offset;
> > +
> > + intel_tile_dims(fb, i, &tile_width, &tile_height);
> > +
> > + x = src_x / hsub;
> > + y = src_y / vsub;
> > + width = src_w / hsub;
> > + height = src_h / vsub;
> > +
> > + /*
> > + * First pixel of the src viewport from the
> > + * start of the normal gtt mapping.
> > + */
> > + x += intel_fb->normal[i].x;
> > + y += intel_fb->normal[i].y;
> > +
> > + offset = intel_compute_aligned_offset(dev_priv, &x, &y,
> > + fb, i, fb->pitches[i],
> > + DRM_MODE_ROTATE_0, tile_size);
> > + offset /= tile_size;
> > +
> > + info->plane[i].offset = offset;
> > + info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
> > + tile_width * cpp);
> > + info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
> > + info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
> > +
> > + if (drm_rotation_90_or_270(rotation)) {
> > + struct drm_rect r;
> > +
> > + /* rotate the x/y offsets to match the GTT view */
> > + r.x1 = x;
> > + r.y1 = y;
> > + r.x2 = x + width;
> > + r.y2 = y + height;
> > + drm_rect_rotate(&r,
> > + info->plane[i].width * tile_width,
> > + info->plane[i].height * tile_height,
> > + DRM_MODE_ROTATE_270);
> > + x = r.x1;
> > + y = r.y1;
> > +
> > + pitch_tiles = info->plane[i].height;
> > + plane_state->color_plane[i].stride = pitch_tiles * tile_height;
> > +
> > + /* rotate the tile dimensions to match the GTT view */
> > + swap(tile_width, tile_height);
> > + } else {
> > + pitch_tiles = info->plane[i].width;
> > + plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
> > + }
> > +
> > + /*
> > + * We only keep the x/y offsets, so push all of the
> > + * gtt offset into the x/y offsets.
> > + */
> > + intel_adjust_tile_offset(&x, &y,
> > + tile_width, tile_height,
> > + tile_size, pitch_tiles,
> > + gtt_offset * tile_size, 0);
> > +
> > + gtt_offset += info->plane[i].width * info->plane[i].height;
> > +
> > + plane_state->color_plane[i].offset = 0;
> > + plane_state->color_plane[i].x = x;
> > + plane_state->color_plane[i].y = y;
> > + }
> > +}
>
> Validating this freaks me out. Keeping it working freaks me out even more,
> there's pretty much a guarantee that we don't.
>
> Also, I'm not sure CI exercises this much even with your hacks. Most of
> our kms tests use single-crtc buffers, so no massive overallocation, so no
> real need for views. The selftests are good, but they don't cover the
> massive pile of pixel/coordination frobbing above.
>
> I think only thing that can validate this is:
> - a pile of igts that make sure we overallocate plentiful, while still
> exercising all the major fb layouts (rotated, all the different cpp,
> tiling formats, and throw in a ccs for lols to make sure nothing blows
> up).
> - kernel patch to prefer remmaped over normal. Don't move your buffers
> around too much though :-)
>
> Now the second part isn't really a real world thing, since even with
> y-tiled that means remapping the view every 32 pixels (on average, worse
> if your edges aren't aligned to 32 pixels, then it's twice as much).
>
> So I think the only thing that works for validating this beast is a pile
> of new igts that allocate dumb&tiled buffers at the size limit, and do all
> the rotations/scaling/moving tests we already have.
>
> Yes this is painful.
One test that I did write was kms_big_fb, which allocates a huge fb and
pans around it with all rotations and modifiers. But the version I
posted was pretty old and I need to look into cleaning up any later
changes I had. The other annoying thing is that generating that huge
fb is pretty slow. Should maybe look into minimizing the stuff we render
to it to speed it up.
>
> > +
> > +static int
> > +intel_plane_compute_gtt(struct intel_plane_state *plane_state)
> > +{
> > + const struct intel_framebuffer *fb =
> > + to_intel_framebuffer(plane_state->base.fb);
> > + unsigned int rotation = plane_state->base.rotation;
> > + int i, num_planes;
> > + int ret;
> > +
> > + if (!fb)
> > + return 0;
> > +
> > + num_planes = fb->base.format->num_planes;
> > +
> > + if (intel_plane_needs_remap(plane_state)) {
> > + intel_plane_remap_gtt(plane_state);
> > +
> > + /* Remapping should take care of this always */
> > + ret = intel_plane_check_stride(plane_state);
> > + if (WARN_ON(ret))
> > + return ret;
> > +
> > + return 0;
> > + }
> > +
> > + intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
> > +
> > + for (i = 0; i < num_planes; i++) {
> > + plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
> > + plane_state->color_plane[i].offset = 0;
> > +
> > + if (drm_rotation_90_or_270(rotation)) {
> > + plane_state->color_plane[i].x = fb->rotated[i].x;
> > + plane_state->color_plane[i].y = fb->rotated[i].y;
> > + } else {
> > + plane_state->color_plane[i].x = fb->normal[i].x;
> > + plane_state->color_plane[i].y = fb->normal[i].y;
> > + }
> > + }
> > +
> > + /* Rotate src coordinates to match rotated GTT view */
> > + if (drm_rotation_90_or_270(rotation))
> > + drm_rect_rotate(&plane_state->base.src,
> > + fb->base.width << 16, fb->base.height << 16,
> > + DRM_MODE_ROTATE_270);
> > +
> > + ret = intel_plane_check_stride(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
>
> Splitting the refactoring from the actual feature adding would be nice.
Aye. This patch did end up accumulating a bit too many changes.
>
> > +
> > static int i9xx_format_to_fourcc(int format)
> > {
> > switch (format) {
> > @@ -3127,26 +3395,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> > int skl_check_plane_surface(struct intel_plane_state *plane_state)
> > {
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > - unsigned int rotation = plane_state->base.rotation;
> > int ret;
> >
> > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > - plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
> > -
> > - ret = intel_plane_check_stride(plane_state);
> > + ret = intel_plane_compute_gtt(plane_state);
> > if (ret)
> > return ret;
> >
> > if (!plane_state->base.visible)
> > return 0;
> >
> > - /* Rotate src coordinates to match rotated GTT view */
> > - if (drm_rotation_90_or_270(rotation))
> > - drm_rect_rotate(&plane_state->base.src,
> > - fb->width << 16, fb->height << 16,
> > - DRM_MODE_ROTATE_270);
> > -
> > /*
> > * Handle the AUX surface first since
> > * the main surface setup depends on it.
> > @@ -3265,20 +3522,20 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > to_i915(plane_state->base.plane->dev);
> > - const struct drm_framebuffer *fb = plane_state->base.fb;
> > - unsigned int rotation = plane_state->base.rotation;
> > - int src_x = plane_state->base.src.x1 >> 16;
> > - int src_y = plane_state->base.src.y1 >> 16;
> > + int src_x, src_y;
> > u32 offset;
> > int ret;
> >
> > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > -
> > - ret = intel_plane_check_stride(plane_state);
> > + ret = intel_plane_compute_gtt(plane_state);
> > if (ret)
> > return ret;
> >
> > + if (!plane_state->base.visible)
> > + return 0;
> > +
> > + src_x = plane_state->base.src.x1 >> 16;
> > + src_y = plane_state->base.src.y1 >> 16;
> > +
> > intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> >
> > if (INTEL_GEN(dev_priv) >= 4)
> > @@ -3289,6 +3546,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> >
> > /* HSW/BDW do this automagically in hardware */
> > if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> > + unsigned int rotation = plane_state->base.rotation;
> > int src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > int src_h = drm_rect_height(&plane_state->base.src) >> 16;
> >
> > @@ -3325,6 +3583,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -3332,10 +3594,6 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = i9xx_check_plane_surface(plane_state);
> > - if (ret)
> > - return ret;
> > -
> > plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
> >
> > return 0;
> > @@ -3459,15 +3717,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> > return ret;
> > }
> >
> > -static u32
> > -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> > -{
> > - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > - return 64;
> > - else
> > - return intel_tile_width_bytes(fb, color_plane);
> > -}
> > -
> > static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> > {
> > struct drm_device *dev = intel_crtc->base.dev;
> > @@ -9830,19 +10079,17 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
> >
> > static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> > {
> > - const struct drm_framebuffer *fb = plane_state->base.fb;
> > - unsigned int rotation = plane_state->base.rotation;
> > int src_x, src_y;
> > u32 offset;
> > int ret;
> >
> > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > -
> > - ret = intel_plane_check_stride(plane_state);
> > + ret = intel_plane_compute_gtt(plane_state);
> > if (ret)
> > return ret;
> >
> > + if (!plane_state->base.visible)
> > + return 0;
> > +
> > src_x = plane_state->base.src_x >> 16;
> > src_y = plane_state->base.src_y >> 16;
> >
> > @@ -9879,6 +10126,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > + ret = intel_cursor_check_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -9886,10 +10137,6 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = intel_cursor_check_surface(plane_state);
> > - if (ret)
> > - return ret;
> > -
> > return 0;
> > }
> >
> > @@ -14591,31 +14838,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> > .dirty = intel_user_framebuffer_dirty,
> > };
> >
> > -static
> > -u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> > - u32 pixel_format, u64 fb_modifier)
> > -{
> > - struct intel_crtc *crtc;
> > - struct intel_plane *plane;
> > -
> > - /*
> > - * We assume the primary plane for pipe A has
> > - * the highest stride limits of them all.
> > - */
> > - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > - plane = to_intel_plane(crtc->base.primary);
> > -
> > - return plane->max_stride(plane, pixel_format, fb_modifier,
> > - DRM_MODE_ROTATE_0);
> > -}
> > -
> > static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > struct drm_i915_gem_object *obj,
> > struct drm_mode_fb_cmd2 *mode_cmd)
> > {
> > struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> > struct drm_framebuffer *fb = &intel_fb->base;
> > - u32 pitch_limit;
> > + u32 max_stride;
> > unsigned int tiling, stride;
> > int ret = -EINVAL;
> > int i;
> > @@ -14667,13 +14896,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > goto err;
> > }
> >
> > - pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
> > - mode_cmd->modifier[0]);
> > - if (mode_cmd->pitches[0] > pitch_limit) {
> > + max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
> > + mode_cmd->modifier[0]);
> > + if (mode_cmd->pitches[0] > max_stride) {
> > DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
> > mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
> > "tiled" : "linear",
> > - mode_cmd->pitches[0], pitch_limit);
> > + mode_cmd->pitches[0], max_stride);
> > goto err;
> > }
> >
>
> We need an intel_framebuffer|plane.c. And a metric pile of other extracted
> files, probably also per major platforms and stuff like that :-/
Yeah, I've been thinking about skl_universal_plane.c + i9xx_plane.c +
maybe intel_plane.c for generic stuff for a while now. Also maybe
intel_cursor.c. But I've been putting it off to avoid rebase pain.
But I think we're probably in a good enough state now that it should
be fine to take the plunge.
>
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 813626322fa3..0ee73f9dea7c 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1586,6 +1586,7 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> > const char *context);
> >
> > /* intel_display.c */
> > +bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> > void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> > enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index b02d3d9809e3..517747d08962 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -237,6 +237,16 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
> > unsigned int rotation = plane_state->base.rotation;
> > u32 stride, max_stride;
> >
> > + /*
> > + * We ignore stride for all invisible planes that
> > + * can be remapped. Otherwise we could end up
> > + * with a false positive when the remapping didn't
> > + * kick in due the plane being invisible.
> > + */
> > + if (intel_plane_can_remap(plane_state) &&
> > + !plane_state->base.visible)
> > + return 0;
> > +
> > /* FIXME other color planes? */
> > stride = plane_state->color_plane[0].stride;
> > max_stride = plane->max_stride(plane, fb->format->format,
> > @@ -1341,6 +1351,10 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -1352,10 +1366,6 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = i9xx_check_plane_surface(plane_state);
> > - if (ret)
> > - return ret;
> > -
> > if (INTEL_GEN(dev_priv) >= 7)
> > plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
> > else
> > @@ -1399,6 +1409,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -1406,10 +1420,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = i9xx_check_plane_surface(plane_state);
> > - if (ret)
> > - return ret;
> > -
> > plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
> >
> > return 0;
> > @@ -1556,6 +1566,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > + ret = skl_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > if (!plane_state->base.visible)
> > return 0;
> >
> > @@ -1571,10 +1585,6 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - ret = skl_check_plane_surface(plane_state);
> > - if (ret)
> > - return ret;
> > -
> > /* HW only has 8 bits pixel precision, disable plane if invisible */
> > if (!(plane_state->base.alpha >> 8))
> > plane_state->base.visible = false;
>
> Code looks good, but the testing freaks me out. Needs lots of igt, I'd say
> at least similar amounts to what we've all added for the original
> kms_rotation tests.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 4/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-01-30 20:59 ` Ville Syrjälä
@ 2019-01-30 21:55 ` Daniel Vetter
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 21:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 10:59:04PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 30, 2019 at 08:01:21PM +0100, Daniel Vetter wrote:
> > On Thu, Jan 24, 2019 at 08:58:49PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The display engine stride limits are getting in our way. On SKL+
> > > we are limited to 8k pixels, which is easily exceeded with three
> > > 4k displays. To overcome this limitation we can remap the pages
> > > in the GTT to provide the display engine with a view of memory
> > > with a smaller stride.
> > >
> > > The code is mostly already there as We already play tricks with
> > > the plane surface address and x/y offsets.
> > >
> > > A few caveats apply:
> > > * linear buffers need the fb stride to be page aligned, as
> > > otherwise the remapped lines wouldn't start at the same
> > > spot
> > > * compressed buffers can't be remapped due to the new
> > > ccs hash mode causing the virtual address of the pages
> > > to affect the interpretation of the compressed data. IIRC
> > > the old hash was limited to the low 12 bits so if we were
> > > using that mode we could remap. As it stands we just refuse
> > > to remapp with compressed fbs.
> > > * no remapping gen2/3 as we'd need a fence for the remapped
> > > vma, which we currently don't have. Need to deal with the
> > > fence POT requirements, and do something about the gen2
> > > gtt page size vs tile size difference
> > >
> > > v2: Rebase due to is_ccs_modifier()
> > > Fix up the skl+ stride_mult mess
> > > memset() the gtt_view because otherwise we could leave
> > > junk in plane[1] when going from 2 plane to 1 plane format
> > > v3: intel_check_plane_stride() was split out
> > > v4: Drop the aligned viewport stuff, it was meant for ccs which
> > > can't be remapped anyway
> > > v5: Introduce intel_plane_can_remap()
> > > Reorder the code so that plane_state->view gets filled
> > > even for invisible planes, otherwise we'd keep using
> > > stale values and could explode during remapping. The new
> > > logic never remaps invisible planes since we don't have
> > > a viewport, and instead pins the full fb instead
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 393 +++++++++++++++++++++------
> > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
> > > 3 files changed, 334 insertions(+), 94 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 17c7edee9584..3713b6f1796e 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -1865,7 +1865,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > >
> > > switch (fb->modifier) {
> > > case DRM_FORMAT_MOD_LINEAR:
> > > - return cpp;
> > > + return intel_tile_size(dev_priv);
> > > case I915_FORMAT_MOD_X_TILED:
> > > if (IS_GEN(dev_priv, 2))
> > > return 128;
> > > @@ -1908,11 +1908,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > static unsigned int
> > > intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> > > {
> > > - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > > - return 1;
> > > - else
> > > - return intel_tile_size(to_i915(fb->dev)) /
> > > - intel_tile_width_bytes(fb, color_plane);
> > > + return intel_tile_size(to_i915(fb->dev)) /
> > > + intel_tile_width_bytes(fb, color_plane);
> > > }
> > >
> > > /* Return the tile dimensions in pixel units */
> > > @@ -2170,16 +2167,8 @@ void intel_add_fb_offsets(int *x, int *y,
> > > int color_plane)
> > >
> > > {
> > > - const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> > > - unsigned int rotation = state->base.rotation;
> > > -
> > > - if (drm_rotation_90_or_270(rotation)) {
> > > - *x += intel_fb->rotated[color_plane].x;
> > > - *y += intel_fb->rotated[color_plane].y;
> > > - } else {
> > > - *x += intel_fb->normal[color_plane].x;
> > > - *y += intel_fb->normal[color_plane].y;
> > > - }
> > > + *x += state->color_plane[color_plane].x;
> > > + *y += state->color_plane[color_plane].y;
> > > }
> > >
> > > static u32 intel_adjust_tile_offset(int *x, int *y,
> > > @@ -2459,6 +2448,119 @@ bool is_ccs_modifier(u64 modifier)
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > }
> > >
> > > +static
> > > +u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > > + u32 pixel_format, u64 modifier)
> > > +{
> > > + struct intel_crtc *crtc;
> > > + struct intel_plane *plane;
> > > +
> > > + /*
> > > + * We assume the primary plane for pipe A has
> > > + * the highest stride limits of them all.
> > > + */
> > > + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > > + plane = to_intel_plane(crtc->base.primary);
> > > +
> > > + return plane->max_stride(plane, pixel_format, modifier,
> > > + DRM_MODE_ROTATE_0);
> > > +}
> > > +
> > > +static
> > > +u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> > > + u32 pixel_format, u64 modifier)
> > > +{
> > > + return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
> > > +}
> > > +
> > > +static u32
> > > +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > > +
> > > + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> > > + u32 max_stride = intel_plane_fb_max_stride(dev_priv,
> > > + fb->format->format,
> > > + fb->modifier);
> > > +
> > > + /*
> > > + * To make remapping with linear generally feasible
> > > + * we need the stride to be page aligned.
> > > + */
> > > + if (fb->pitches[color_plane] > max_stride)
> > > + return intel_tile_size(dev_priv);
> > > + else
> > > + return 64;
> > > + } else {
> > > + return intel_tile_width_bytes(fb, color_plane);
> > > + }
> > > +}
> > > +
> > > +bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
> > > +{
> > > + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > > + int i;
> > > +
> > > + /* We don't want to deal with remapping with cursors */
> > > + if (plane->id == PLANE_CURSOR)
> > > + return false;
> >
> > They should be caught in the stride check below anyway ... why special
> > case?
>
> I guess we could just drop this. Hmm, yeah even i845/i865 with
> their max cursor stride of 2k should get rejected later.
>
> >
> > > +
> > > + /*
> > > + * The dsplay engine limits already match the render
> > > + * engine limits, so not much point in remapping.
> > > + * Would also need to deal with the fence POT alignment
> > > + * and gen2 2KiB GTT tile size.
> > > + */
> > > + if (INTEL_GEN(dev_priv) < 4)
> > > + return false;
> > > +
> > > + /*
> > > + * The new CCS hash mode isn't compatible with remapping as
> > > + * the virtual address of the pages affects the compressed data.
> > > + */
> > > + if (is_ccs_modifier(fb->modifier))
> > > + return false;
> > > +
> > > + /* Linear needs a page aligned stride for remapping */
> > > + if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> >
> > Not sure whether cramming linear formats into the same macheniry is really
> > clever in a good way or bad way (because too tricky). I guess it works,
> > and this is not something that's well explaing in some comments sprinkled
> > all over.
> >
> > *shrug*
> >
> > > + unsigned int alignment = intel_tile_size(dev_priv) - 1;
> > > +
> > > + for (i = 0; i < fb->format->num_planes; i++) {
> > > + if (fb->pitches[i] & alignment)
> > > + return false;
> > > + }
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
> > > +{
> > > + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> > > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > > + unsigned int rotation = plane_state->base.rotation;
> > > + u32 stride, max_stride;
> > > +
> > > + /*
> > > + * No remapping for invisible planes since we don't have
> > > + * an actual source viewport to remap.
> > > + */
> > > + if (!plane_state->base.visible)
> > > + return false;
> > > +
> > > + if (!intel_plane_can_remap(plane_state))
> > > + return false;
> > > +
> > > + /* FIXME other color planes? */
> >
> > Should be simple to fix if we do a similar loop like in can_remap above.
> > Just true if any of them are bigger than max stride.
>
> That's assuming the max stride for each plane is the same. Which
> it might not be. IIRC the skl+ docs didn't really say what the max
> aux stride is.
Ugh. In that case probably better to make that clear in the comment, e.g.
/* FIXME: aux plane limits on gen9+ are unclear in Bspec, for now
* no checking. */
Otoh there's no reasonable scenario where they're wider, so might still be
better to at least check for that.
> > > + stride = intel_fb_pitch(fb, 0, rotation);
> > > + max_stride = plane->max_stride(plane, fb->format->format,
> > > + fb->modifier, rotation);
> > > +
> > > + return stride > max_stride;
> > > +}
> > > +
> > > static int
> > > intel_fill_fb_info(struct drm_i915_private *dev_priv,
> > > struct drm_framebuffer *fb)
> > > @@ -2624,6 +2726,172 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
> > > return 0;
> > > }
> > >
> > > +static void
> > > +intel_plane_remap_gtt(struct intel_plane_state *plane_state)
> > > +{
> > > + struct drm_i915_private *dev_priv =
> > > + to_i915(plane_state->base.plane->dev);
> > > + struct drm_framebuffer *fb = plane_state->base.fb;
> > > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > > + struct intel_rotation_info *info = &plane_state->view.rotated;
> > > + unsigned int rotation = plane_state->base.rotation;
> > > + int i, num_planes = fb->format->num_planes;
> > > + unsigned int tile_size = intel_tile_size(dev_priv);
> > > + unsigned int src_x, src_y;
> > > + unsigned int src_w, src_h;
> > > + u32 gtt_offset = 0;
> > > +
> > > + memset(&plane_state->view, 0, sizeof(plane_state->view));
> > > + plane_state->view.type = drm_rotation_90_or_270(rotation) ?
> > > + I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
> > > +
> > > + src_x = plane_state->base.src.x1 >> 16;
> > > + src_y = plane_state->base.src.y1 >> 16;
> > > + src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > > + src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > > +
> > > + WARN_ON(is_ccs_modifier(fb->modifier));
> > > +
> > > + /* Make src coordinates relative to the viewport */
> > > + drm_rect_translate(&plane_state->base.src,
> > > + -(src_x << 16), -(src_y << 16));
> > > +
> > > + /* Rotate src coordinates to match rotated GTT view */
> > > + if (drm_rotation_90_or_270(rotation))
> > > + drm_rect_rotate(&plane_state->base.src,
> > > + src_w << 16, src_h << 16,
> > > + DRM_MODE_ROTATE_270);
> > > +
> > > + for (i = 0; i < num_planes; i++) {
> > > + unsigned int hsub = i ? fb->format->hsub : 1;
> > > + unsigned int vsub = i ? fb->format->vsub : 1;
> > > + unsigned int cpp = fb->format->cpp[i];
> > > + unsigned int tile_width, tile_height;
> > > + unsigned int width, height;
> > > + unsigned int pitch_tiles;
> > > + unsigned int x, y;
> > > + u32 offset;
> > > +
> > > + intel_tile_dims(fb, i, &tile_width, &tile_height);
> > > +
> > > + x = src_x / hsub;
> > > + y = src_y / vsub;
> > > + width = src_w / hsub;
> > > + height = src_h / vsub;
> > > +
> > > + /*
> > > + * First pixel of the src viewport from the
> > > + * start of the normal gtt mapping.
> > > + */
> > > + x += intel_fb->normal[i].x;
> > > + y += intel_fb->normal[i].y;
> > > +
> > > + offset = intel_compute_aligned_offset(dev_priv, &x, &y,
> > > + fb, i, fb->pitches[i],
> > > + DRM_MODE_ROTATE_0, tile_size);
> > > + offset /= tile_size;
> > > +
> > > + info->plane[i].offset = offset;
> > > + info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
> > > + tile_width * cpp);
> > > + info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
> > > + info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
> > > +
> > > + if (drm_rotation_90_or_270(rotation)) {
> > > + struct drm_rect r;
> > > +
> > > + /* rotate the x/y offsets to match the GTT view */
> > > + r.x1 = x;
> > > + r.y1 = y;
> > > + r.x2 = x + width;
> > > + r.y2 = y + height;
> > > + drm_rect_rotate(&r,
> > > + info->plane[i].width * tile_width,
> > > + info->plane[i].height * tile_height,
> > > + DRM_MODE_ROTATE_270);
> > > + x = r.x1;
> > > + y = r.y1;
> > > +
> > > + pitch_tiles = info->plane[i].height;
> > > + plane_state->color_plane[i].stride = pitch_tiles * tile_height;
> > > +
> > > + /* rotate the tile dimensions to match the GTT view */
> > > + swap(tile_width, tile_height);
> > > + } else {
> > > + pitch_tiles = info->plane[i].width;
> > > + plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
> > > + }
> > > +
> > > + /*
> > > + * We only keep the x/y offsets, so push all of the
> > > + * gtt offset into the x/y offsets.
> > > + */
> > > + intel_adjust_tile_offset(&x, &y,
> > > + tile_width, tile_height,
> > > + tile_size, pitch_tiles,
> > > + gtt_offset * tile_size, 0);
> > > +
> > > + gtt_offset += info->plane[i].width * info->plane[i].height;
> > > +
> > > + plane_state->color_plane[i].offset = 0;
> > > + plane_state->color_plane[i].x = x;
> > > + plane_state->color_plane[i].y = y;
> > > + }
> > > +}
> >
> > Validating this freaks me out. Keeping it working freaks me out even more,
> > there's pretty much a guarantee that we don't.
> >
> > Also, I'm not sure CI exercises this much even with your hacks. Most of
> > our kms tests use single-crtc buffers, so no massive overallocation, so no
> > real need for views. The selftests are good, but they don't cover the
> > massive pile of pixel/coordination frobbing above.
> >
> > I think only thing that can validate this is:
> > - a pile of igts that make sure we overallocate plentiful, while still
> > exercising all the major fb layouts (rotated, all the different cpp,
> > tiling formats, and throw in a ccs for lols to make sure nothing blows
> > up).
> > - kernel patch to prefer remmaped over normal. Don't move your buffers
> > around too much though :-)
> >
> > Now the second part isn't really a real world thing, since even with
> > y-tiled that means remapping the view every 32 pixels (on average, worse
> > if your edges aren't aligned to 32 pixels, then it's twice as much).
> >
> > So I think the only thing that works for validating this beast is a pile
> > of new igts that allocate dumb&tiled buffers at the size limit, and do all
> > the rotations/scaling/moving tests we already have.
> >
> > Yes this is painful.
>
> One test that I did write was kms_big_fb, which allocates a huge fb and
> pans around it with all rotations and modifiers. But the version I
> posted was pretty old and I need to look into cleaning up any later
> changes I had. The other annoying thing is that generating that huge
> fb is pretty slow. Should maybe look into minimizing the stuff we render
> to it to speed it up.
16*16 is just 1GB, that should still be ok to clflush and all that. As
long as we don't use pixman to render to it.
What I had in mind is just kms_rotation, but added big_fb subtests for at
least some of them, with the only difference that we allocate a huge fb.
But still render only into the fairly tiny visible portion. Iirc we even
have a few of those "bigger than necessary fb" tests in kms_rotation, to
make sure the remapping isn't broken in these corner-cases.
Since remapped view/fb is exactly the same problem as rotated, except not
rotated, I think reusing that test as much as possible simplifies the
reviewing.
Another thing: If we do the dumb_create change I recommend then it should
Just Work: MODIFIER_NONE is allocated through dumb, so should pick up the
stride restrictions automatically, and other modifiers work automatically
because tiles. I think that should be the quickest way to get good enough
test coverage without having to review an entire new igt.
Only gap would be a test for dumb_create to check it does the right thing,
but I'm ok with shrugging that one off.
-Daniel
>
> >
> > > +
> > > +static int
> > > +intel_plane_compute_gtt(struct intel_plane_state *plane_state)
> > > +{
> > > + const struct intel_framebuffer *fb =
> > > + to_intel_framebuffer(plane_state->base.fb);
> > > + unsigned int rotation = plane_state->base.rotation;
> > > + int i, num_planes;
> > > + int ret;
> > > +
> > > + if (!fb)
> > > + return 0;
> > > +
> > > + num_planes = fb->base.format->num_planes;
> > > +
> > > + if (intel_plane_needs_remap(plane_state)) {
> > > + intel_plane_remap_gtt(plane_state);
> > > +
> > > + /* Remapping should take care of this always */
> > > + ret = intel_plane_check_stride(plane_state);
> > > + if (WARN_ON(ret))
> > > + return ret;
> > > +
> > > + return 0;
> > > + }
> > > +
> > > + intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
> > > +
> > > + for (i = 0; i < num_planes; i++) {
> > > + plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
> > > + plane_state->color_plane[i].offset = 0;
> > > +
> > > + if (drm_rotation_90_or_270(rotation)) {
> > > + plane_state->color_plane[i].x = fb->rotated[i].x;
> > > + plane_state->color_plane[i].y = fb->rotated[i].y;
> > > + } else {
> > > + plane_state->color_plane[i].x = fb->normal[i].x;
> > > + plane_state->color_plane[i].y = fb->normal[i].y;
> > > + }
> > > + }
> > > +
> > > + /* Rotate src coordinates to match rotated GTT view */
> > > + if (drm_rotation_90_or_270(rotation))
> > > + drm_rect_rotate(&plane_state->base.src,
> > > + fb->base.width << 16, fb->base.height << 16,
> > > + DRM_MODE_ROTATE_270);
> > > +
> > > + ret = intel_plane_check_stride(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return 0;
> > > +}
> >
> > Splitting the refactoring from the actual feature adding would be nice.
>
> Aye. This patch did end up accumulating a bit too many changes.
>
> >
> > > +
> > > static int i9xx_format_to_fourcc(int format)
> > > {
> > > switch (format) {
> > > @@ -3127,26 +3395,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> > > int skl_check_plane_surface(struct intel_plane_state *plane_state)
> > > {
> > > const struct drm_framebuffer *fb = plane_state->base.fb;
> > > - unsigned int rotation = plane_state->base.rotation;
> > > int ret;
> > >
> > > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > > - plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
> > > -
> > > - ret = intel_plane_check_stride(plane_state);
> > > + ret = intel_plane_compute_gtt(plane_state);
> > > if (ret)
> > > return ret;
> > >
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > - /* Rotate src coordinates to match rotated GTT view */
> > > - if (drm_rotation_90_or_270(rotation))
> > > - drm_rect_rotate(&plane_state->base.src,
> > > - fb->width << 16, fb->height << 16,
> > > - DRM_MODE_ROTATE_270);
> > > -
> > > /*
> > > * Handle the AUX surface first since
> > > * the main surface setup depends on it.
> > > @@ -3265,20 +3522,20 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> > > {
> > > struct drm_i915_private *dev_priv =
> > > to_i915(plane_state->base.plane->dev);
> > > - const struct drm_framebuffer *fb = plane_state->base.fb;
> > > - unsigned int rotation = plane_state->base.rotation;
> > > - int src_x = plane_state->base.src.x1 >> 16;
> > > - int src_y = plane_state->base.src.y1 >> 16;
> > > + int src_x, src_y;
> > > u32 offset;
> > > int ret;
> > >
> > > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > > -
> > > - ret = intel_plane_check_stride(plane_state);
> > > + ret = intel_plane_compute_gtt(plane_state);
> > > if (ret)
> > > return ret;
> > >
> > > + if (!plane_state->base.visible)
> > > + return 0;
> > > +
> > > + src_x = plane_state->base.src.x1 >> 16;
> > > + src_y = plane_state->base.src.y1 >> 16;
> > > +
> > > intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> > >
> > > if (INTEL_GEN(dev_priv) >= 4)
> > > @@ -3289,6 +3546,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
> > >
> > > /* HSW/BDW do this automagically in hardware */
> > > if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int src_w = drm_rect_width(&plane_state->base.src) >> 16;
> > > int src_h = drm_rect_height(&plane_state->base.src) >> 16;
> > >
> > > @@ -3325,6 +3583,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > + ret = i9xx_check_plane_surface(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > @@ -3332,10 +3594,6 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - ret = i9xx_check_plane_surface(plane_state);
> > > - if (ret)
> > > - return ret;
> > > -
> > > plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
> > >
> > > return 0;
> > > @@ -3459,15 +3717,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> > > return ret;
> > > }
> > >
> > > -static u32
> > > -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> > > -{
> > > - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > > - return 64;
> > > - else
> > > - return intel_tile_width_bytes(fb, color_plane);
> > > -}
> > > -
> > > static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> > > {
> > > struct drm_device *dev = intel_crtc->base.dev;
> > > @@ -9830,19 +10079,17 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
> > >
> > > static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
> > > {
> > > - const struct drm_framebuffer *fb = plane_state->base.fb;
> > > - unsigned int rotation = plane_state->base.rotation;
> > > int src_x, src_y;
> > > u32 offset;
> > > int ret;
> > >
> > > - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > > - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
> > > -
> > > - ret = intel_plane_check_stride(plane_state);
> > > + ret = intel_plane_compute_gtt(plane_state);
> > > if (ret)
> > > return ret;
> > >
> > > + if (!plane_state->base.visible)
> > > + return 0;
> > > +
> > > src_x = plane_state->base.src_x >> 16;
> > > src_y = plane_state->base.src_y >> 16;
> > >
> > > @@ -9879,6 +10126,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > + ret = intel_cursor_check_surface(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > @@ -9886,10 +10137,6 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - ret = intel_cursor_check_surface(plane_state);
> > > - if (ret)
> > > - return ret;
> > > -
> > > return 0;
> > > }
> > >
> > > @@ -14591,31 +14838,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> > > .dirty = intel_user_framebuffer_dirty,
> > > };
> > >
> > > -static
> > > -u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> > > - u32 pixel_format, u64 fb_modifier)
> > > -{
> > > - struct intel_crtc *crtc;
> > > - struct intel_plane *plane;
> > > -
> > > - /*
> > > - * We assume the primary plane for pipe A has
> > > - * the highest stride limits of them all.
> > > - */
> > > - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> > > - plane = to_intel_plane(crtc->base.primary);
> > > -
> > > - return plane->max_stride(plane, pixel_format, fb_modifier,
> > > - DRM_MODE_ROTATE_0);
> > > -}
> > > -
> > > static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > > struct drm_i915_gem_object *obj,
> > > struct drm_mode_fb_cmd2 *mode_cmd)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> > > struct drm_framebuffer *fb = &intel_fb->base;
> > > - u32 pitch_limit;
> > > + u32 max_stride;
> > > unsigned int tiling, stride;
> > > int ret = -EINVAL;
> > > int i;
> > > @@ -14667,13 +14896,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > > goto err;
> > > }
> > >
> > > - pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
> > > - mode_cmd->modifier[0]);
> > > - if (mode_cmd->pitches[0] > pitch_limit) {
> > > + max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
> > > + mode_cmd->modifier[0]);
> > > + if (mode_cmd->pitches[0] > max_stride) {
> > > DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
> > > mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
> > > "tiled" : "linear",
> > > - mode_cmd->pitches[0], pitch_limit);
> > > + mode_cmd->pitches[0], max_stride);
> > > goto err;
> > > }
> > >
> >
> > We need an intel_framebuffer|plane.c. And a metric pile of other extracted
> > files, probably also per major platforms and stuff like that :-/
>
> Yeah, I've been thinking about skl_universal_plane.c + i9xx_plane.c +
> maybe intel_plane.c for generic stuff for a while now. Also maybe
> intel_cursor.c. But I've been putting it off to avoid rebase pain.
> But I think we're probably in a good enough state now that it should
> be fine to take the plunge.
>
> >
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 813626322fa3..0ee73f9dea7c 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1586,6 +1586,7 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
> > > const char *context);
> > >
> > > /* intel_display.c */
> > > +bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> > > void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> > > void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
> > > enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index b02d3d9809e3..517747d08962 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -237,6 +237,16 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
> > > unsigned int rotation = plane_state->base.rotation;
> > > u32 stride, max_stride;
> > >
> > > + /*
> > > + * We ignore stride for all invisible planes that
> > > + * can be remapped. Otherwise we could end up
> > > + * with a false positive when the remapping didn't
> > > + * kick in due the plane being invisible.
> > > + */
> > > + if (intel_plane_can_remap(plane_state) &&
> > > + !plane_state->base.visible)
> > > + return 0;
> > > +
> > > /* FIXME other color planes? */
> > > stride = plane_state->color_plane[0].stride;
> > > max_stride = plane->max_stride(plane, fb->format->format,
> > > @@ -1341,6 +1351,10 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > + ret = i9xx_check_plane_surface(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > @@ -1352,10 +1366,6 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - ret = i9xx_check_plane_surface(plane_state);
> > > - if (ret)
> > > - return ret;
> > > -
> > > if (INTEL_GEN(dev_priv) >= 7)
> > > plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
> > > else
> > > @@ -1399,6 +1409,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > + ret = i9xx_check_plane_surface(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > @@ -1406,10 +1420,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - ret = i9xx_check_plane_surface(plane_state);
> > > - if (ret)
> > > - return ret;
> > > -
> > > plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
> > >
> > > return 0;
> > > @@ -1556,6 +1566,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > + ret = skl_check_plane_surface(plane_state);
> > > + if (ret)
> > > + return ret;
> > > +
> > > if (!plane_state->base.visible)
> > > return 0;
> > >
> > > @@ -1571,10 +1585,6 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > > if (ret)
> > > return ret;
> > >
> > > - ret = skl_check_plane_surface(plane_state);
> > > - if (ret)
> > > - return ret;
> > > -
> > > /* HW only has 8 bits pixel precision, disable plane if invisible */
> > > if (!(plane_state->base.alpha >> 8))
> > > plane_state->base.visible = false;
> >
> > Code looks good, but the testing freaks me out. Needs lots of igt, I'd say
> > at least similar amounts to what we've all added for the original
> > kms_rotation tests.
> > -Daniel
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Ville Syrjälä
> Intel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (3 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 4/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-24 18:59 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
` (14 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no remapping
on gen2/3 due to lack of fence on the remapped vma.
v2: Rebase due to is_ccs_modifier()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 86847cee833a..f7c4456220cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2470,6 +2470,19 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+ * Arbitrary limit for gen4+. We can deal with any page
+ * aligned stride via GTT remapping. Gen2/3 need a fence
+ * for tiled scanout which the remapped vma won't have,
+ * so we don't allow remapping on those platforms.
+ *
+ * Also the new hash mode we use for CCS isn't compatible
+ * with remapping as the virtual address of the pages
+ * affects the compressed data.
+ */
+ if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+ return 256*1024;
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.19.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
2019-01-18 15:27 ` [PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
@ 2019-01-24 18:59 ` Ville Syrjala
2019-01-30 9:58 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-24 18:59 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just pick the limit to match the render
engine max stride (256KiB).
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
remapping on gen2/3 due extra complications from fence alignment
and gen2 2KiB GTT tile size. Also no real benefit since the
display engine limits already match the other limits.
v2: Rebase due to is_ccs_modifier()
v3: Tweak the comment and commit msg
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3713b6f1796e..e0cf43336b62 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2470,6 +2470,15 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+ * Arbitrary limit for gen4+ chosen to match the
+ * render engine max stride.
+ *
+ * The new CCS hash mode makes remapping impossible
+ */
+ if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
+ return 256*1024;
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
2019-01-24 18:59 ` [PATCH v4 " Ville Syrjala
@ 2019-01-30 9:58 ` Daniel Vetter
2019-01-30 10:01 ` Chris Wilson
0 siblings, 1 reply; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 9:58 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With gtt remapping plugged in we can simply raise the stride
> limit on gen4+. Let's just pick the limit to match the render
> engine max stride (256KiB).
>
> No remapping CCS because the virtual address of each page actually
> matters due to the new hash mode
> (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
> remapping on gen2/3 due extra complications from fence alignment
> and gen2 2KiB GTT tile size. Also no real benefit since the
> display engine limits already match the other limits.
>
> v2: Rebase due to is_ccs_modifier()
> v3: Tweak the comment and commit msg
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3713b6f1796e..e0cf43336b62 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2470,6 +2470,15 @@ static
> u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier)
> {
> + /*
> + * Arbitrary limit for gen4+ chosen to match the
> + * render engine max stride.
> + *
> + * The new CCS hash mode makes remapping impossible
> + */
> + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
> + return 256*1024;
bikeshed: KB(256) but I'm not sure how much we use these really.
-Daniel
> +
> return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
> }
>
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
2019-01-30 9:58 ` Daniel Vetter
@ 2019-01-30 10:01 ` Chris Wilson
2019-01-30 14:33 ` Ville Syrjälä
0 siblings, 1 reply; 44+ messages in thread
From: Chris Wilson @ 2019-01-30 10:01 UTC (permalink / raw)
To: Daniel Vetter, Ville Syrjala; +Cc: intel-gfx
Quoting Daniel Vetter (2019-01-30 09:58:56)
> On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > With gtt remapping plugged in we can simply raise the stride
> > limit on gen4+. Let's just pick the limit to match the render
> > engine max stride (256KiB).
> >
> > No remapping CCS because the virtual address of each page actually
> > matters due to the new hash mode
> > (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
> > remapping on gen2/3 due extra complications from fence alignment
> > and gen2 2KiB GTT tile size. Also no real benefit since the
> > display engine limits already match the other limits.
> >
> > v2: Rebase due to is_ccs_modifier()
> > v3: Tweak the comment and commit msg
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3713b6f1796e..e0cf43336b62 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2470,6 +2470,15 @@ static
> > u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> > u32 pixel_format, u64 modifier)
> > {
> > + /*
> > + * Arbitrary limit for gen4+ chosen to match the
> > + * render engine max stride.
> > + *
> > + * The new CCS hash mode makes remapping impossible
> > + */
> > + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
> > + return 256*1024;
>
> bikeshed: KB(256) but I'm not sure how much we use these really.
Polka-dot bikeshed: SZ_256K
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB
2019-01-30 10:01 ` Chris Wilson
@ 2019-01-30 14:33 ` Ville Syrjälä
0 siblings, 0 replies; 44+ messages in thread
From: Ville Syrjälä @ 2019-01-30 14:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 10:01:04AM +0000, Chris Wilson wrote:
> Quoting Daniel Vetter (2019-01-30 09:58:56)
> > On Thu, Jan 24, 2019 at 08:59:36PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > With gtt remapping plugged in we can simply raise the stride
> > > limit on gen4+. Let's just pick the limit to match the render
> > > engine max stride (256KiB).
> > >
> > > No remapping CCS because the virtual address of each page actually
> > > matters due to the new hash mode
> > > (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
> > > remapping on gen2/3 due extra complications from fence alignment
> > > and gen2 2KiB GTT tile size. Also no real benefit since the
> > > display engine limits already match the other limits.
> > >
> > > v2: Rebase due to is_ccs_modifier()
> > > v3: Tweak the comment and commit msg
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 3713b6f1796e..e0cf43336b62 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2470,6 +2470,15 @@ static
> > > u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> > > u32 pixel_format, u64 modifier)
> > > {
> > > + /*
> > > + * Arbitrary limit for gen4+ chosen to match the
> > > + * render engine max stride.
> > > + *
> > > + * The new CCS hash mode makes remapping impossible
> > > + */
> > > + if (INTEL_GEN(dev_priv) >= 4 && !is_ccs_modifier(modifier))
> > > + return 256*1024;
> >
> > bikeshed: KB(256) but I'm not sure how much we use these really.
>
> Polka-dot bikeshed: SZ_256K
I tried a cocci conversion to these, but ended up being slightly
annoyed by the fact that we only have defines for POT sizes, and
there are quite a few non-POT sizes in the code.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (4 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 5/8] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-30 10:01 ` Daniel Vetter
2019-01-18 15:27 ` [PATCH v3 7/8] hack: drm/i915: Always remap gtt Ville Syrjala
` (13 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping in place we can use arbitrarily large
framebuffers. Let's bump the limits to 16kx16k on gen7+.
The limit was chosen to match the maximum 2D surface size
of the 3D engine.
With the remapping we could easily go higher than that for the
display engine. However the modesetting ddx will blindly assume
it can handle whatever is reported via kms. The oversized
buffer dimensions are not caught by glamor nor Mesa until
finally an assert will trip when genxml attempts to pack the
SURFACE_STATE. So we pick a safe limit to avoid the X server
from crashing (or potentially misbehaving if the genxml asserts
are compiled out).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f7c4456220cd..4053ed93e73c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15366,16 +15366,22 @@ int intel_modeset_init(struct drm_device *dev)
}
}
- /* maximum framebuffer dimensions */
- if (IS_GEN(dev_priv, 2)) {
- dev->mode_config.max_width = 2048;
- dev->mode_config.max_height = 2048;
+ /*
+ * Maximum framebuffer dimensions, chosen to match
+ * the maximum render engine surface size on gen4+.
+ */
+ if (INTEL_GEN(dev_priv) >= 7) {
+ dev->mode_config.max_width = 16384;
+ dev->mode_config.max_height = 16384;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ dev->mode_config.max_width = 8192;
+ dev->mode_config.max_height = 8192;
} else if (IS_GEN(dev_priv, 3)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
- dev->mode_config.max_width = 8192;
- dev->mode_config.max_height = 8192;
+ dev->mode_config.max_width = 2048;
+ dev->mode_config.max_height = 2048;
}
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-01-18 15:27 ` [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
@ 2019-01-30 10:01 ` Daniel Vetter
2019-01-30 14:35 ` Ville Syrjälä
0 siblings, 1 reply; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 10:01 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jan 18, 2019 at 05:27:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With gtt remapping in place we can use arbitrarily large
> framebuffers. Let's bump the limits to 16kx16k on gen7+.
> The limit was chosen to match the maximum 2D surface size
> of the 3D engine.
>
> With the remapping we could easily go higher than that for the
> display engine. However the modesetting ddx will blindly assume
> it can handle whatever is reported via kms. The oversized
> buffer dimensions are not caught by glamor nor Mesa until
> finally an assert will trip when genxml attempts to pack the
> SURFACE_STATE. So we pick a safe limit to avoid the X server
> from crashing (or potentially misbehaving if the genxml asserts
> are compiled out).
So -modesetting is still fireworks on gen3, which has 4k x 4k buffer
limit, but 2k x 2k render limit? I thought the tiled rendering stuff
landed ...
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Matches my mesa here.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f7c4456220cd..4053ed93e73c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15366,16 +15366,22 @@ int intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - /* maximum framebuffer dimensions */
> - if (IS_GEN(dev_priv, 2)) {
> - dev->mode_config.max_width = 2048;
> - dev->mode_config.max_height = 2048;
> + /*
> + * Maximum framebuffer dimensions, chosen to match
> + * the maximum render engine surface size on gen4+.
> + */
> + if (INTEL_GEN(dev_priv) >= 7) {
> + dev->mode_config.max_width = 16384;
> + dev->mode_config.max_height = 16384;
> + } else if (INTEL_GEN(dev_priv) >= 4) {
> + dev->mode_config.max_width = 8192;
> + dev->mode_config.max_height = 8192;
> } else if (IS_GEN(dev_priv, 3)) {
> dev->mode_config.max_width = 4096;
> dev->mode_config.max_height = 4096;
> } else {
> - dev->mode_config.max_width = 8192;
> - dev->mode_config.max_height = 8192;
> + dev->mode_config.max_width = 2048;
> + dev->mode_config.max_height = 2048;
> }
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-01-30 10:01 ` Daniel Vetter
@ 2019-01-30 14:35 ` Ville Syrjälä
0 siblings, 0 replies; 44+ messages in thread
From: Ville Syrjälä @ 2019-01-30 14:35 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 11:01:50AM +0100, Daniel Vetter wrote:
> On Fri, Jan 18, 2019 at 05:27:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > With gtt remapping in place we can use arbitrarily large
> > framebuffers. Let's bump the limits to 16kx16k on gen7+.
> > The limit was chosen to match the maximum 2D surface size
> > of the 3D engine.
> >
> > With the remapping we could easily go higher than that for the
> > display engine. However the modesetting ddx will blindly assume
> > it can handle whatever is reported via kms. The oversized
> > buffer dimensions are not caught by glamor nor Mesa until
> > finally an assert will trip when genxml attempts to pack the
> > SURFACE_STATE. So we pick a safe limit to avoid the X server
> > from crashing (or potentially misbehaving if the genxml asserts
> > are compiled out).
>
> So -modesetting is still fireworks on gen3, which has 4k x 4k buffer
> limit, but 2k x 2k render limit?
Not sure. Does anyone seriously expect -modesetting to work with
gen3? I've never even tried it myself.
> I thought the tiled rendering stuff
> landed ...
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Matches my mesa here.
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f7c4456220cd..4053ed93e73c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15366,16 +15366,22 @@ int intel_modeset_init(struct drm_device *dev)
> > }
> > }
> >
> > - /* maximum framebuffer dimensions */
> > - if (IS_GEN(dev_priv, 2)) {
> > - dev->mode_config.max_width = 2048;
> > - dev->mode_config.max_height = 2048;
> > + /*
> > + * Maximum framebuffer dimensions, chosen to match
> > + * the maximum render engine surface size on gen4+.
> > + */
> > + if (INTEL_GEN(dev_priv) >= 7) {
> > + dev->mode_config.max_width = 16384;
> > + dev->mode_config.max_height = 16384;
> > + } else if (INTEL_GEN(dev_priv) >= 4) {
> > + dev->mode_config.max_width = 8192;
> > + dev->mode_config.max_height = 8192;
> > } else if (IS_GEN(dev_priv, 3)) {
> > dev->mode_config.max_width = 4096;
> > dev->mode_config.max_height = 4096;
> > } else {
> > - dev->mode_config.max_width = 8192;
> > - dev->mode_config.max_height = 8192;
> > + dev->mode_config.max_width = 2048;
> > + dev->mode_config.max_height = 2048;
> > }
> >
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> > --
> > 2.19.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 7/8] hack: drm/i915: Always remap gtt
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (5 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-24 19:31 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:27 ` [PATCH v3 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
` (12 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4053ed93e73c..fbe71fb23c9e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2509,6 +2509,25 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
}
}
+static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int alignment = intel_tile_size(dev_priv) - 1;
+ int i;
+
+ if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+ return true;
+
+ for (i = 0; i < fb->format->num_planes; i++) {
+ if (fb->pitches[i] & alignment)
+ return false;
+ }
+
+ return true;
+}
+
static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
@@ -2529,6 +2548,10 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
if (is_ccs_modifier(fb->modifier))
return false;
+ /* HACK: always remap */
+ if (intel_plane_can_remap(plane_state))
+ return true;
+
/* FIXME other color planes? */
stride = intel_fb_pitch(fb, 0, rotation);
max_stride = plane->max_stride(plane, fb->format->format,
--
2.19.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 7/8] hack: drm/i915: Always remap gtt
2019-01-18 15:27 ` [PATCH v3 7/8] hack: drm/i915: Always remap gtt Ville Syrjala
@ 2019-01-24 19:31 ` Ville Syrjala
2019-01-30 9:58 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-24 19:31 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
v2: Rebase due to can_remap()
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c6f59bfb4744..c720891b31c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2562,6 +2562,9 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
if (!intel_plane_can_remap(plane_state))
return false;
+ /* HACK: always remap */
+ return true;
+
/* FIXME other color planes? */
stride = intel_fb_pitch(fb, 0, rotation);
max_stride = plane->max_stride(plane, fb->format->format,
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v4 7/8] hack: drm/i915: Always remap gtt
2019-01-24 19:31 ` [PATCH v4 " Ville Syrjala
@ 2019-01-30 9:58 ` Daniel Vetter
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 9:58 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jan 24, 2019 at 09:31:01PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Rebase due to can_remap()
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c6f59bfb4744..c720891b31c9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2562,6 +2562,9 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
> if (!intel_plane_can_remap(plane_state))
> return false;
>
> + /* HACK: always remap */
> + return true;
Mildly silly idea, but what if we always do this when we can? Could help a
bit with ggtt fragmentation, since we wouldn't need the big view anymore,
just a few smaller ones. Just an idea really, which would have the side
benefit of making sure we don't break this too often. Of only remap when
there's an actual benefit, i.e. remapping stride/size smaller than full
buffer size.
-Daniel
> +
> /* FIXME other color planes? */
> stride = intel_fb_pitch(fb, 0, rotation);
> max_stride = plane->max_stride(plane, fb->format->format,
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v3 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (6 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 7/8] hack: drm/i915: Always remap gtt Ville Syrjala
@ 2019-01-18 15:27 ` Ville Syrjala
2019-01-18 17:11 ` [PATCH v4 " Ville Syrjala
2019-01-18 15:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
` (11 subsequent siblings)
19 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 15:27 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1e7c95d0fea1..365125c6683b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -745,7 +745,7 @@ i915_gem_dumb_create(struct drm_file *file,
struct drm_mode_create_dumb *args)
{
/* have to work out size/pitch and return them */
- args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
+ args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
args->size = args->pitch * args->height;
return i915_gem_create(file, to_i915(dev),
args->size, &args->handle);
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH v4 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-18 15:27 ` [PATCH v3 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
@ 2019-01-18 17:11 ` Ville Syrjala
2019-01-30 9:54 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjala @ 2019-01-18 17:11 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
v2: Leave the stride alone for buffers that look to be for the cursor
---
drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1e7c95d0fea1..b4b34519af80 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -745,7 +745,12 @@ i915_gem_dumb_create(struct drm_file *file,
struct drm_mode_create_dumb *args)
{
/* have to work out size/pitch and return them */
- args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
+ if (args->bpp == 32 && (args->width == 64 ||
+ args->width == 128 ||
+ args->width == 256))
+ args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
+ else
+ args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
args->size = args->pitch * args->height;
return i915_gem_create(file, to_i915(dev),
args->size, &args->handle);
--
2.19.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH v4 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-18 17:11 ` [PATCH v4 " Ville Syrjala
@ 2019-01-30 9:54 ` Daniel Vetter
2019-01-30 10:06 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 9:54 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jan 18, 2019 at 07:11:06PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> v2: Leave the stride alone for buffers that look to be for the cursor
> ---
> drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1e7c95d0fea1..b4b34519af80 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -745,7 +745,12 @@ i915_gem_dumb_create(struct drm_file *file,
> struct drm_mode_create_dumb *args)
> {
> /* have to work out size/pitch and return them */
> - args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> + if (args->bpp == 32 && (args->width == 64 ||
> + args->width == 128 ||
> + args->width == 256))
> + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> + else
> + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
Shouldn't we convert this into a non-hack and just do it anytime the pitch
is too wide for the display to handle?
Or am I missing something somewhere? -modesetting et all will dtrt
because tiling, but this should help with boot splashes and stuff like
that (but those tend to not do side-by-side, so maybe that's why the get
away with it).
-Daniel
> args->size = args->pitch * args->height;
> return i915_gem_create(file, to_i915(dev),
> args->size, &args->handle);
> --
> 2.19.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-30 9:54 ` Daniel Vetter
@ 2019-01-30 10:06 ` Daniel Vetter
2019-01-30 15:38 ` Ville Syrjälä
0 siblings, 1 reply; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 10:06 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 10:54:15AM +0100, Daniel Vetter wrote:
> On Fri, Jan 18, 2019 at 07:11:06PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > v2: Leave the stride alone for buffers that look to be for the cursor
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 1e7c95d0fea1..b4b34519af80 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -745,7 +745,12 @@ i915_gem_dumb_create(struct drm_file *file,
> > struct drm_mode_create_dumb *args)
> > {
> > /* have to work out size/pitch and return them */
> > - args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > + if (args->bpp == 32 && (args->width == 64 ||
> > + args->width == 128 ||
> > + args->width == 256))
> > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > + else
> > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
>
> Shouldn't we convert this into a non-hack and just do it anytime the pitch
> is too wide for the display to handle?
>
> Or am I missing something somewhere? -modesetting et all will dtrt
> because tiling, but this should help with boot splashes and stuff like
> that (but those tend to not do side-by-side, so maybe that's why the get
> away with it).
Correction: We need this, and before we start bumping the limits. Any dumb
buffer you create (within the limits) we must be able to scan out. So we
definitely need to have this for super-big buffers on gen7+. Even if it's
fairly theoretical.
I think we should even have an igt which creates a max size buffer (using
dumb create) and then makes sure we can scan that out.
-Daniel
> -Daniel
>
> > args->size = args->pitch * args->height;
> > return i915_gem_create(file, to_i915(dev),
> > args->size, &args->handle);
> > --
> > 2.19.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-30 10:06 ` Daniel Vetter
@ 2019-01-30 15:38 ` Ville Syrjälä
2019-01-30 18:26 ` Daniel Vetter
0 siblings, 1 reply; 44+ messages in thread
From: Ville Syrjälä @ 2019-01-30 15:38 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 11:06:07AM +0100, Daniel Vetter wrote:
> On Wed, Jan 30, 2019 at 10:54:15AM +0100, Daniel Vetter wrote:
> > On Fri, Jan 18, 2019 at 07:11:06PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > v2: Leave the stride alone for buffers that look to be for the cursor
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
> > > 1 file changed, 6 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index 1e7c95d0fea1..b4b34519af80 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -745,7 +745,12 @@ i915_gem_dumb_create(struct drm_file *file,
> > > struct drm_mode_create_dumb *args)
> > > {
> > > /* have to work out size/pitch and return them */
> > > - args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > > + if (args->bpp == 32 && (args->width == 64 ||
> > > + args->width == 128 ||
> > > + args->width == 256))
> > > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > > + else
> > > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
> >
> > Shouldn't we convert this into a non-hack and just do it anytime the pitch
> > is too wide for the display to handle?
> >
> > Or am I missing something somewhere? -modesetting et all will dtrt
> > because tiling, but this should help with boot splashes and stuff like
> > that (but those tend to not do side-by-side, so maybe that's why the get
> > away with it).
>
> Correction: We need this, and before we start bumping the limits. Any dumb
> buffer you create (within the limits) we must be able to scan out. So we
> definitely need to have this for super-big buffers on gen7+. Even if it's
> fairly theoretical.
Is there some userpsace that actually wants to create a huge dumb
buffer like that?
Looks like we don't even check against the max fb dimensions in
dumb_create so you can create any sized dumb buffer you want.
So even now there is no guarantee that the addfb will actually
succeed.
>
> I think we should even have an igt which creates a max size buffer (using
> dumb create) and then makes sure we can scan that out.
> -Daniel
>
> > -Daniel
> >
> > > args->size = args->pitch * args->height;
> > > return i915_gem_create(file, to_i915(dev),
> > > args->size, &args->handle);
> > > --
> > > 2.19.2
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH v4 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping
2019-01-30 15:38 ` Ville Syrjälä
@ 2019-01-30 18:26 ` Daniel Vetter
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Vetter @ 2019-01-30 18:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jan 30, 2019 at 05:38:03PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 30, 2019 at 11:06:07AM +0100, Daniel Vetter wrote:
> > On Wed, Jan 30, 2019 at 10:54:15AM +0100, Daniel Vetter wrote:
> > > On Fri, Jan 18, 2019 at 07:11:06PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > v2: Leave the stride alone for buffers that look to be for the cursor
> > > > ---
> > > > drivers/gpu/drm/i915/i915_gem.c | 7 ++++++-
> > > > 1 file changed, 6 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > > index 1e7c95d0fea1..b4b34519af80 100644
> > > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > > @@ -745,7 +745,12 @@ i915_gem_dumb_create(struct drm_file *file,
> > > > struct drm_mode_create_dumb *args)
> > > > {
> > > > /* have to work out size/pitch and return them */
> > > > - args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > > > + if (args->bpp == 32 && (args->width == 64 ||
> > > > + args->width == 128 ||
> > > > + args->width == 256))
> > > > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> > > > + else
> > > > + args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 4096);
> > >
> > > Shouldn't we convert this into a non-hack and just do it anytime the pitch
> > > is too wide for the display to handle?
> > >
> > > Or am I missing something somewhere? -modesetting et all will dtrt
> > > because tiling, but this should help with boot splashes and stuff like
> > > that (but those tend to not do side-by-side, so maybe that's why the get
> > > away with it).
> >
> > Correction: We need this, and before we start bumping the limits. Any dumb
> > buffer you create (within the limits) we must be able to scan out. So we
> > definitely need to have this for super-big buffers on gen7+. Even if it's
> > fairly theoretical.
>
> Is there some userpsace that actually wants to create a huge dumb
> buffer like that?
Given that the core drm_mode_dumb_create doesn't check anything, I guess
not. Would be good to add.
> Looks like we don't even check against the max fb dimensions in
> dumb_create so you can create any sized dumb buffer you want.
> So even now there is no guarantee that the addfb will actually
> succeed.
Well we do tell userspace up to what limit we expect it to succeed, and
dumb_create is supposed to come up with the correct stride. I think
there's no good reason to give userspace a stride that doesn't work at
all, and it's essentially this patch, but with a slightly different if
condition.
-Daniel
>
> >
> > I think we should even have an igt which creates a max size buffer (using
> > dumb create) and then makes sure we can scan that out.
> > -Daniel
> >
> > > -Daniel
> > >
> > > > args->size = args->pitch * args->height;
> > > > return i915_gem_create(file, to_i915(dev),
> > > > args->size, &args->handle);
> > > > --
> > > > 2.19.2
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Ville Syrjälä
> Intel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (7 preceding siblings ...)
2019-01-18 15:27 ` [PATCH v3 8/8] hack: align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
@ 2019-01-18 15:41 ` Patchwork
2019-01-18 15:44 ` ✗ Fi.CI.SPARSE: " Patchwork
` (10 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 15:41 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6c45cc6e9157 drm/i915: Add a new "remapped" gtt_view
-:96: CHECK:LINE_SPACING: Please don't use multiple blank lines
#96: FILE: drivers/gpu/drm/i915/i915_gem.c:5685:
+
+
-:244: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#244: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:195:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
e5cab34e27df drm/i915/selftests: Add mock selftest for remapped vmas
-:78: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#78: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:438:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:97: CHECK:LINE_SPACING: Please don't use multiple blank lines
#97: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:457:
+
+
-:133: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#133: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:511:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:177: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#177: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:581:
+ if (view.type == I915_GGTT_VIEW_ROTATED)
-:178: WARNING:LONG_LINE: line over 100 characters
#178: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:582:
+ sg = assert_rotated(obj, &view.rotated, n, sg);
-:179: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#179: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:583:
+ else
-:180: WARNING:LONG_LINE: line over 100 characters
#180: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:584:
+ sg = assert_remapped(obj, &view.remapped, n, sg);
total: 0 errors, 5 warnings, 2 checks, 172 lines checked
2fe756c3f657 drm/i915/selftests: Add live vma selftest
6d769ecac679 drm/i915: Overcome display engine stride limits via GTT remapping
67f25d52d1f2 drm/i915: Bump gen4+ fb stride limit to 256KiB
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:2484:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
3203cda3c436 drm/i915: Bump gen7+ fb size limits to 16kx16k
792906e7f600 hack: drm/i915: Always remap gtt
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:47: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 35 lines checked
796dff7bd3da hack: align dumb buffer stride to 4k to allow for gtt remapping
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:20: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (8 preceding siblings ...)
2019-01-18 15:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
@ 2019-01-18 15:44 ` Patchwork
2019-01-18 16:05 ` ✗ Fi.CI.BAT: failure " Patchwork
` (9 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 15:44 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add a new "remapped" gtt_view
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void)
Commit: drm/i915/selftests: Add mock selftest for remapped vmas
Okay!
Commit: drm/i915/selftests: Add live vma selftest
Okay!
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB
Okay!
Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k
Okay!
Commit: hack: drm/i915: Always remap gtt
Okay!
Commit: hack: align dumb buffer stride to 4k to allow for gtt remapping
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (9 preceding siblings ...)
2019-01-18 15:44 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-01-18 16:05 ` Patchwork
2019-01-18 17:18 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2) Patchwork
` (8 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 16:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55415/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5449 -> Patchwork_11984
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_11984 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11984, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55415/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11984:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: PASS -> FAIL +7
- fi-byt-j1900: PASS -> FAIL +8
- fi-byt-clapper: PASS -> FAIL +7
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-hsw-4770r: PASS -> FAIL +7
- fi-hsw-peppy: PASS -> FAIL +7
- fi-cfl-8700k: PASS -> FAIL +7
- fi-apl-guc: PASS -> FAIL +7
- fi-bdw-5557u: PASS -> FAIL +7
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-byt-n2820: PASS -> FAIL +7
- fi-ivb-3770: PASS -> FAIL +8
- fi-bxt-j4205: PASS -> FAIL +7
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-snb-2600: PASS -> FAIL +8
- fi-ivb-3520m: PASS -> FAIL +8
- fi-cfl-8109u: PASS -> FAIL +7
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-snb-2520m: PASS -> FAIL +8
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-ilk-650: PASS -> FAIL +8
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-bsw-n3050: PASS -> FAIL +7
- fi-hsw-4770: PASS -> FAIL +7
- fi-cfl-guc: PASS -> FAIL +7
- fi-bdw-gvtdvm: PASS -> FAIL +7
* igt@kms_force_connector_basic@force-load-detect:
- fi-hsw-4770: PASS -> INCOMPLETE
- fi-bwr-2160: PASS -> FAIL
- fi-elk-e7500: PASS -> FAIL
- fi-pnv-d510: PASS -> FAIL
- fi-gdg-551: PASS -> FAIL
Known issues
------------
Here are the changes found in Patchwork_11984 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#107341]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: PASS -> DMESG-FAIL [fdo#103841]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-icl-u2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-kbl-7567u: PASS -> FAIL [fdo#103841] / [fdo#108767]
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-7560u: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: PASS -> FAIL [fdo#109052] +7
- fi-kbl-x1275: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u3: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-skl-6770hq: PASS -> FAIL [fdo#109052] +7
- fi-skl-gvtdvm: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-skl-guc: PASS -> FAIL [fdo#109052] +7
- fi-whl-u: PASS -> FAIL [fdo#109052] +7
- fi-skl-6260u: PASS -> FAIL [fdo#109052] +7
- fi-kbl-r: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: PASS -> FAIL [fdo#109052] +7
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-skl-6700k2: PASS -> FAIL [fdo#109052] +7
- fi-skl-iommu: PASS -> FAIL [fdo#109052] +7
- fi-skl-6700hq: PASS -> FAIL [fdo#109052] +7
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: WARN [fdo#109380] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> PASS +25
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
#### Warnings ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> FAIL [fdo#109052] +7
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
Participating hosts (48 -> 43)
------------------------------
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
Build changes
-------------
* Linux: CI_DRM_5449 -> Patchwork_11984
CI_DRM_5449: d187a189c76898b9ba2e74262703ad797538cbc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4778: 0c80bd7f2a964605f307e0220c6bb756685582b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11984: 796dff7bd3da80ff7dffb589c0c444d5c98d99aa @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11984/build_32bit.log
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_vma.o
In file included from ./include/drm/drm_mm.h:49:0,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/i915_vma.c:25:
drivers/gpu/drm/i915/selftests/i915_vma.c: In function ‘assert_remapped’:
drivers/gpu/drm/i915/selftests/i915_vma.c:436:18: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 7 has type ‘dma_addr_t {aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p %d %d %d %llx\n", sg, n, x, y, src);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
drivers/gpu/drm/i915/selftests/i915_vma.c:445:18: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘dma_addr_t {aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p dma %llx off = %d\n", sg, sg_dma_address(sg), offset);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/i915_vma.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_vma.o] Error 1
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1042: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Linux commits ==
796dff7bd3da hack: align dumb buffer stride to 4k to allow for gtt remapping
792906e7f600 hack: drm/i915: Always remap gtt
3203cda3c436 drm/i915: Bump gen7+ fb size limits to 16kx16k
67f25d52d1f2 drm/i915: Bump gen4+ fb stride limit to 256KiB
6d769ecac679 drm/i915: Overcome display engine stride limits via GTT remapping
2fe756c3f657 drm/i915/selftests: Add live vma selftest
e5cab34e27df drm/i915/selftests: Add mock selftest for remapped vmas
6c45cc6e9157 drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11984/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (10 preceding siblings ...)
2019-01-18 16:05 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-01-18 17:18 ` Patchwork
2019-01-18 17:21 ` ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 17:18 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
08b5a861466d drm/i915: Add a new "remapped" gtt_view
-:96: CHECK:LINE_SPACING: Please don't use multiple blank lines
#96: FILE: drivers/gpu/drm/i915/i915_gem.c:5685:
+
+
-:244: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#244: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:195:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
48e2be95ad44 drm/i915/selftests: Add mock selftest for remapped vmas
-:78: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#78: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:438:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:97: CHECK:LINE_SPACING: Please don't use multiple blank lines
#97: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:457:
+
+
-:133: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#133: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:511:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:177: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#177: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:581:
+ if (view.type == I915_GGTT_VIEW_ROTATED)
-:178: WARNING:LONG_LINE: line over 100 characters
#178: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:582:
+ sg = assert_rotated(obj, &view.rotated, n, sg);
-:179: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#179: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:583:
+ else
-:180: WARNING:LONG_LINE: line over 100 characters
#180: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:584:
+ sg = assert_remapped(obj, &view.remapped, n, sg);
total: 0 errors, 5 warnings, 2 checks, 172 lines checked
31c281758b75 drm/i915/selftests: Add live vma selftest
dd914fe9943f drm/i915: Overcome display engine stride limits via GTT remapping
2883c9d21fd3 drm/i915: Bump gen4+ fb stride limit to 256KiB
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:2484:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
32ab0d5da81a drm/i915: Bump gen7+ fb size limits to 16kx16k
a3ea0c0f5a1f hack: drm/i915: Always remap gtt
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:47: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 35 lines checked
e70492ee3f5e hack: align dumb buffer stride to 4k to allow for gtt remapping
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:26: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 13 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display (rev2)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (11 preceding siblings ...)
2019-01-18 17:18 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2) Patchwork
@ 2019-01-18 17:21 ` Patchwork
2019-01-18 17:51 ` ✗ Fi.CI.BAT: failure " Patchwork
` (6 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 17:21 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add a new "remapped" gtt_view
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void)
Commit: drm/i915/selftests: Add mock selftest for remapped vmas
Okay!
Commit: drm/i915/selftests: Add live vma selftest
Okay!
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB
Okay!
Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k
Okay!
Commit: hack: drm/i915: Always remap gtt
Okay!
Commit: hack: align dumb buffer stride to 4k to allow for gtt remapping
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev2)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (12 preceding siblings ...)
2019-01-18 17:21 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-01-18 17:51 ` Patchwork
2019-01-24 19:03 ` ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev5) Patchwork
` (5 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-18 17:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/55415/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5449 -> Patchwork_11985
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_11985 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11985, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55415/revisions/2/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11985:
### IGT changes ###
#### Possible regressions ####
* igt@kms_force_connector_basic@force-load-detect:
- fi-hsw-4770: PASS -> INCOMPLETE
- fi-ivb-3770: PASS -> INCOMPLETE
- fi-ivb-3520m: PASS -> INCOMPLETE
Known issues
------------
Here are the changes found in Patchwork_11985 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#107341]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> DMESG-WARN [fdo#108622]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: PASS -> DMESG-FAIL [fdo#103841]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-icl-u2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-kbl-7567u: PASS -> FAIL [fdo#103841] / [fdo#108767]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: WARN [fdo#109380] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: {SKIP} [fdo#109271] -> PASS +33
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107341]: https://bugs.freedesktop.org/show_bug.cgi?id=107341
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
Participating hosts (48 -> 43)
------------------------------
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-pnv-d510
Build changes
-------------
* Linux: CI_DRM_5449 -> Patchwork_11985
CI_DRM_5449: d187a189c76898b9ba2e74262703ad797538cbc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4778: 0c80bd7f2a964605f307e0220c6bb756685582b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11985: e70492ee3f5e3ad93de54feedae5d30d0b45b566 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11985/build_32bit.log
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_vma.o
In file included from ./include/drm/drm_mm.h:49:0,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/i915_vma.c:25:
drivers/gpu/drm/i915/selftests/i915_vma.c: In function ‘assert_remapped’:
drivers/gpu/drm/i915/selftests/i915_vma.c:436:18: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 7 has type ‘dma_addr_t {aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p %d %d %d %llx\n", sg, n, x, y, src);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
drivers/gpu/drm/i915/selftests/i915_vma.c:445:18: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘dma_addr_t {aka unsigned int}’ [-Werror=format=]
DRM_DEBUG_KMS("sg %p dma %llx off = %d\n", sg, sg_dma_address(sg), offset);
^
./include/drm/drm_print.h:362:22: note: in definition of macro ‘DRM_DEBUG_KMS’
drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/i915_vma.o' failed
make[4]: *** [drivers/gpu/drm/i915/i915_vma.o] Error 1
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1042: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Linux commits ==
e70492ee3f5e hack: align dumb buffer stride to 4k to allow for gtt remapping
a3ea0c0f5a1f hack: drm/i915: Always remap gtt
32ab0d5da81a drm/i915: Bump gen7+ fb size limits to 16kx16k
2883c9d21fd3 drm/i915: Bump gen4+ fb stride limit to 256KiB
dd914fe9943f drm/i915: Overcome display engine stride limits via GTT remapping
31c281758b75 drm/i915/selftests: Add live vma selftest
48e2be95ad44 drm/i915/selftests: Add mock selftest for remapped vmas
08b5a861466d drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11985/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev5)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (13 preceding siblings ...)
2019-01-18 17:51 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-01-24 19:03 ` Patchwork
2019-01-24 19:28 ` ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev6) Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 19:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev5)
URL : https://patchwork.freedesktop.org/series/55415/
State : failure
== Summary ==
Applying: drm/i915: Add a new "remapped" gtt_view
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_debugfs.c
M drivers/gpu/drm/i915/i915_drv.h
M drivers/gpu/drm/i915/i915_gem.c
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_drv.h
M drivers/gpu/drm/i915/selftests/i915_vma.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c
Auto-merging drivers/gpu/drm/i915/intel_drv.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_gem.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/i915_debugfs.c
Applying: drm/i915/selftests: Add mock selftest for remapped vmas
Applying: drm/i915/selftests: Add live vma selftest
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/selftests/i915_vma.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/selftests/i915_vma.c
Auto-merging drivers/gpu/drm/i915/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0003 drm/i915/selftests: Add live vma selftest
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev6)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (14 preceding siblings ...)
2019-01-24 19:03 ` ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev5) Patchwork
@ 2019-01-24 19:28 ` Patchwork
2019-01-24 19:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev7) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 19:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev6)
URL : https://patchwork.freedesktop.org/series/55415/
State : failure
== Summary ==
Applying: drm/i915: Add a new "remapped" gtt_view
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_debugfs.c
M drivers/gpu/drm/i915/i915_drv.h
M drivers/gpu/drm/i915/i915_gem.c
M drivers/gpu/drm/i915/intel_display.c
M drivers/gpu/drm/i915/intel_drv.h
M drivers/gpu/drm/i915/selftests/i915_vma.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/selftests/i915_vma.c
Auto-merging drivers/gpu/drm/i915/intel_drv.h
Auto-merging drivers/gpu/drm/i915/intel_display.c
Auto-merging drivers/gpu/drm/i915/i915_gem.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/i915_debugfs.c
Applying: drm/i915/selftests: Add mock selftest for remapped vmas
Applying: drm/i915/selftests: Add live vma selftest
Applying: drm/i915: Overcome display engine stride limits via GTT remapping
Applying: drm/i915: Bump gen4+ fb stride limit to 256KiB
Applying: drm/i915: Bump gen7+ fb size limits to 16kx16k
Applying: hack: drm/i915: Always remap gtt
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_display.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0007 hack: drm/i915: Always remap gtt
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev7)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (15 preceding siblings ...)
2019-01-24 19:28 ` ✗ Fi.CI.BAT: failure for drm/i915: GTT remapping for display (rev6) Patchwork
@ 2019-01-24 19:48 ` Patchwork
2019-01-24 19:52 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 19:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
02b1fe191700 drm/i915: Add a new "remapped" gtt_view
-:96: CHECK:LINE_SPACING: Please don't use multiple blank lines
#96: FILE: drivers/gpu/drm/i915/i915_gem.c:5687:
+
+
-:244: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#244: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:195:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
2264b41f8fa4 drm/i915/selftests: Add mock selftest for remapped vmas
-:75: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#75: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:436:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:91: CHECK:LINE_SPACING: Please don't use multiple blank lines
#91: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:452:
+
+
-:127: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#127: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:506:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:171: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#171: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:576:
+ if (view.type == I915_GGTT_VIEW_ROTATED)
-:172: WARNING:LONG_LINE: line over 100 characters
#172: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:577:
+ sg = assert_rotated(obj, &view.rotated, n, sg);
-:173: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#173: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:578:
+ else
-:174: WARNING:LONG_LINE: line over 100 characters
#174: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:579:
+ sg = assert_remapped(obj, &view.remapped, n, sg);
total: 0 errors, 5 warnings, 2 checks, 165 lines checked
b4401cf43d11 drm/i915/selftests: Add live vma selftest
a31fbb99b1ce drm/i915: Overcome display engine stride limits via GTT remapping
77a6058e039f drm/i915: Bump gen4+ fb stride limit to 256KiB
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:2480:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 15 lines checked
9044b091f79e drm/i915: Bump gen7+ fb size limits to 16kx16k
a0fc50b1d3bf hack: drm/i915: Always remap gtt
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:21: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 9 lines checked
e35f31943952 hack: align dumb buffer stride to 4k to allow for gtt remapping
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:26: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 1 errors, 1 warnings, 0 checks, 13 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display (rev7)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (16 preceding siblings ...)
2019-01-24 19:48 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev7) Patchwork
@ 2019-01-24 19:52 ` Patchwork
2019-01-24 20:16 ` ✓ Fi.CI.BAT: success " Patchwork
2019-01-24 21:09 ` ✓ Fi.CI.IGT: " Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 19:52 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add a new "remapped" gtt_view
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:3637:34: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3546:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3550:16: warning: expression using sizeof(void)
Commit: drm/i915/selftests: Add mock selftest for remapped vmas
Okay!
Commit: drm/i915/selftests: Add live vma selftest
Okay!
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB
Okay!
Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k
Okay!
Commit: hack: drm/i915: Always remap gtt
Okay!
Commit: hack: align dumb buffer stride to 4k to allow for gtt remapping
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display (rev7)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (17 preceding siblings ...)
2019-01-24 19:52 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-01-24 20:16 ` Patchwork
2019-01-24 21:09 ` ✓ Fi.CI.IGT: " Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 20:16 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5475 -> Patchwork_12033
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/55415/revisions/7/mbox/
Known issues
------------
Here are the changes found in Patchwork_12033 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: PASS -> DMESG-FAIL [fdo#108735]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: PASS -> DMESG-FAIL [fdo#103841]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: PASS -> FAIL [fdo#103841] / [fdo#108767]
- fi-kbl-7567u: PASS -> FAIL [fdo#103841] / [fdo#108767]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
#### Possible fixes ####
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (45 -> 41)
------------------------------
Missing (4): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_5475 -> Patchwork_12033
CI_DRM_5475: 9ced33eacb10c4ec1f03010d6efd9f21c6cf3ef7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4788: 3f77380fabd4083f9857daa6cd454d0937077901 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12033: e35f319439521868732c6a8a1502fcc2b86385fc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e35f31943952 hack: align dumb buffer stride to 4k to allow for gtt remapping
a0fc50b1d3bf hack: drm/i915: Always remap gtt
9044b091f79e drm/i915: Bump gen7+ fb size limits to 16kx16k
77a6058e039f drm/i915: Bump gen4+ fb stride limit to 256KiB
a31fbb99b1ce drm/i915: Overcome display engine stride limits via GTT remapping
b4401cf43d11 drm/i915/selftests: Add live vma selftest
2264b41f8fa4 drm/i915/selftests: Add mock selftest for remapped vmas
02b1fe191700 drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12033/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: GTT remapping for display (rev7)
2019-01-18 15:27 [PATCH v3 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (18 preceding siblings ...)
2019-01-24 20:16 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-01-24 21:09 ` Patchwork
19 siblings, 0 replies; 44+ messages in thread
From: Patchwork @ 2019-01-24 21:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev7)
URL : https://patchwork.freedesktop.org/series/55415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5475_full -> Patchwork_12033_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12033_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +4
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@all-pipes-single-bo:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
- shard-apl: PASS -> FAIL [fdo#103166] +2
#### Possible fixes ####
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-apl: FAIL [fdo#106641] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +4
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109381] -> PASS
- shard-glk: DMESG-FAIL [fdo#105763] / [fdo#106538] -> PASS
- shard-apl: DMESG-FAIL [fdo#108950] -> PASS
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
* igt@pm_rpm@system-suspend:
- shard-glk: FAIL [fdo#103375] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109381]: https://bugs.freedesktop.org/show_bug.cgi?id=109381
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 5)
------------------------------
Missing (2): shard-skl shard-iclb
Build changes
-------------
* Linux: CI_DRM_5475 -> Patchwork_12033
CI_DRM_5475: 9ced33eacb10c4ec1f03010d6efd9f21c6cf3ef7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4788: 3f77380fabd4083f9857daa6cd454d0937077901 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12033: e35f319439521868732c6a8a1502fcc2b86385fc @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12033/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 44+ messages in thread