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From: Paul Cercueil <paul@crapouillou.net>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock
Date: Fri, 25 Jan 2019 12:34:36 -0300	[thread overview]
Message-ID: <20190125153436.13517-1-paul@crapouillou.net> (raw)

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
---
 drivers/clk/ingenic/jz4740-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index d8ac7f2e183a..5d0d5be1e6a7 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 		.mux = { CGU_REG_CPCCR, 29, 1 },
 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-		.gate = { CGU_REG_SCR, 6 },
+		.gate = { CGU_REG_SCR, 6, true },
 	},
 
 	/* Gate-only clocks */
-- 
2.20.1


             reply	other threads:[~2019-01-25 15:34 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-25 15:34 Paul Cercueil [this message]
2019-01-25 18:55 ` [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock Stephen Boyd
2019-01-25 19:24   ` Paul Cercueil
2019-01-29 18:13     ` Stephen Boyd
2019-01-29 19:22       ` Paul Cercueil
2019-01-29 21:16         ` Stephen Boyd
2019-02-05 21:32 ` Stephen Boyd

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