[U-Boot] [PATCH v1 0/5] db820: Add missing initialization for uart

[U-Boot] [PATCH v1 0/5] db820: Add missing initialization for uart

[Ramon Fried]

Uart was lacking initialization of pinctrl & PLL's and
relied on previous initialization from LK.
Fix that.


Ramon Fried (5):
  arm: mach-snapdragon: db820c: Actually init PLL for serial
  arm: mach-snapdragon: add pinctrl driver for db820c
  configs: dragonboard820c: Enable pinctrl/mux config
  arm: mach-snapdragon: pinctrl: clarify gpio disable bit
  dts: 820c: Add pinctrl node and uart mux

 arch/arm/dts/dragonboard820c-uboot.dtsi       | 10 +++-
 arch/arm/dts/dragonboard820c.dts              | 29 +++++++---
 arch/arm/mach-snapdragon/Makefile             |  5 +-
 arch/arm/mach-snapdragon/clock-apq8096.c      | 34 +++++++++++
 .../include/mach/sysmap-apq8096.h             |  9 +++
 arch/arm/mach-snapdragon/pinctrl-apq8096.c    | 56 +++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  6 +-
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 configs/dragonboard820c_defconfig             |  2 +
 9 files changed, 139 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8096.c

-- 
2.20.1

[U-Boot] [PATCH v1 1/5] arm: mach-snapdragon: db820c: Actually init PLL for serial

[Ramon Fried]

The PLL for the UART was not set, and relied on previous
initializtion made by LK. add the appropriate initialization.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

 arch/arm/mach-snapdragon/clock-apq8096.c      | 34 +++++++++++++++++++
 .../include/mach/sysmap-apq8096.h             |  9 +++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c
index 628c38785b..e5011be8f2 100644
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ b/arch/arm/mach-snapdragon/clock-apq8096.c
@@ -34,6 +34,12 @@ static const struct pll_vote_clk gpll0_vote_clk = {
 	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
 };
 
+static struct vote_clk gcc_blsp2_ahb_clk = {
+	.cbcr_reg = BLSP2_AHB_CBCR,
+	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.vote_bit = BIT(15),
+};
+
 static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 {
 	int div = 3;
@@ -47,6 +53,32 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
 	return rate;
 }
 
+static const struct bcr_regs uart2_regs = {
+	.cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
+	.cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
+	.M = BLSP2_UART2_APPS_M,
+	.N = BLSP2_UART2_APPS_N,
+	.D = BLSP2_UART2_APPS_D,
+};
+
+static int clk_init_uart(struct msm_clk_priv *priv)
+{
+	/* Enable AHB clock */
+	clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
+
+	/* 7372800 uart block clock @ GPLL0 */
+	clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
+			     CFG_CLK_SRC_GPLL0);
+
+	/* Vote for gpll0 clock */
+	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+
+	/* Enable core clk */
+	clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
+
+	return 0;
+}
+
 ulong msm_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -55,6 +87,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
 	case 0: /* SDC1 */
 		return clk_init_sdc(priv, rate);
 		break;
+	case 4: /*UART2*/
+		return clk_init_uart(priv);
 	default:
 		return 0;
 	}
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
index 14febb6487..36a902bd92 100644
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
@@ -15,6 +15,7 @@
 /* Clocks: (from CLK_CTL_BASE)  */
 #define GPLL0_STATUS			(0x0000)
 #define APCS_GPLL_ENA_VOTE		(0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x52004)
 
 #define SDCC2_BCR			(0x14000) /* block reset */
 #define SDCC2_APPS_CBCR			(0x14004) /* branch control */
@@ -25,4 +26,12 @@
 #define SDCC2_N				(0x1401C)
 #define SDCC2_D				(0x14020)
 
+#define BLSP2_AHB_CBCR			(0x25004)
+#define BLSP2_UART2_APPS_CBCR		(0x29004)
+#define BLSP2_UART2_APPS_CMD_RCGR	(0x2900C)
+#define BLSP2_UART2_APPS_CFG_RCGR	(0x29010)
+#define BLSP2_UART2_APPS_M		(0x29014)
+#define BLSP2_UART2_APPS_N		(0x29018)
+#define BLSP2_UART2_APPS_D		(0x2901C)
+
 #endif
-- 
2.20.1

[U-Boot] [PATCH v1 2/5] arm: mach-snapdragon: add pinctrl driver for db820c

[Ramon Fried]

Add pinctrl driver for Dragonboard820c, currently with only
one mux func to initialize pins for serial console.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

 arch/arm/mach-snapdragon/Makefile             |  5 +-
 arch/arm/mach-snapdragon/pinctrl-apq8096.c    | 56 +++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  2 +-
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 4 files changed, 61 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8096.c

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 2d94083600..709919fce4 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -6,8 +6,9 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o
 obj-y += misc.o
 obj-y += clock-snapdragon.o
 obj-y += dram.o
+obj-y += pinctrl-snapdragon.o
+obj-y += pinctrl-apq8016.o
+obj-y += pinctrl-apq8096.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/arch/arm/mach-snapdragon/pinctrl-apq8096.c
new file mode 100644
index 0000000000..20a71c319b
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-apq8096.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm APQ8096 pinctrl
+ *
+ * (C) Copyright 2019 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN];
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+	"SDC1_RCLK",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart8", 2},
+};
+
+static const char *apq8096_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *apq8096_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 150) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 150];
+	}
+}
+
+static unsigned int apq8096_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data apq8096_data = {
+	.pin_count = 157,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = apq8096_get_function_name,
+	.get_function_mux = apq8096_get_function_mux,
+	.get_pin_name = apq8096_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index 5365ccdb70..ac511d9ee5 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -113,8 +113,8 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 };
 
 static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data },
 	{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+	{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
 	{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index c47d988af4..24f8863f59 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -26,5 +26,6 @@ struct pinctrl_function {
 };
 
 extern struct msm_pinctrl_data apq8016_data;
+extern struct msm_pinctrl_data apq8096_data;
 
 #endif
-- 
2.20.1

[U-Boot] [PATCH v1 3/5] configs: dragonboard820c: Enable pinctrl/mux config

[Ramon Fried]

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

 configs/dragonboard820c_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index d1e0b77717..20a6ba9b61 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -31,6 +31,8 @@ CONFIG_PM8916_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_PM8916=y
 CONFIG_MSM_SERIAL=y
-- 
2.20.1

[U-Boot] [PATCH v1 4/5] arm: mach-snapdragon: pinctrl: clarify gpio disable bit

[Ramon Fried]

The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

 arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index ac511d9ee5..9ba8fdd729 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -22,7 +22,7 @@ struct msm_pinctrl_priv {
 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_ENABLE BIT(9)
+#define TLMM_GPIO_DISABLE BIT(9)
 
 static const struct pinconf_param msm_conf_params[] = {
 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
@@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
 	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
 			priv->data->get_function_mux(func_selector) << 2);
 	return 0;
 }
-- 
2.20.1

[U-Boot] [PATCH v1 5/5] dts: 820c: Add pinctrl node and uart mux

[Ramon Fried]

* Add pinctrl node for TLMM and add mux request for uart node.
* Rename uart to the actual board uart port.
* Fix indentendation of sdhc2 node.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
---

 arch/arm/dts/dragonboard820c-uboot.dtsi | 10 ++++++++-
 arch/arm/dts/dragonboard820c.dts        | 29 +++++++++++++++++++------
 2 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
index d60aa04494..8610d7ec37 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -13,14 +13,22 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
+		qcom,tlmm at 1010000 {
+			u-boot,dm-pre-reloc;
+
+			uart {
+				u-boot,dm-pre-reloc;
+			};
+		};
+
 		clock-controller at 300000 {
 			u-boot,dm-pre-reloc;
 		};
 
 		serial at 75b0000 {
 			u-boot,dm-pre-reloc;
-			};
 		};
+	};
 };
 
 &pm8994_pon {
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 34abbc9110..dac15775dd 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "skeleton64.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. DB820c";
@@ -16,7 +17,7 @@
 	#size-cells = <2>;
 
 	aliases {
-		serial0 = &blsp2_uart1;
+		serial0 = &blsp2_uart2;
 	};
 
 	chosen {
@@ -63,18 +64,32 @@
 			reg = <0x300000 0x90000>;
 		};
 
-		blsp2_uart1: serial at 75b0000 {
+		pinctrl: qcom,tlmm at 1010000 {
+			compatible = "qcom,tlmm-apq8096";
+			reg = <0x1010000 0x400000>;
+
+			blsp8_uart: uart {
+				function = "blsp_uart8";
+				pins = "GPIO_4", "GPIO_5";
+				drive-strength = <DRIVE_STRENGTH_8MA>;
+				bias-disable;
+			};
+		};
+
+		blsp2_uart2: serial at 75b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x75b0000 0x1000>;
 			clock = <&gcc 4>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp8_uart>;
 		};
 
 		sdhc2: sdhci at 74a4900 {
-			 compatible = "qcom,sdhci-msm-v4";
-			 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
-			 index = <0x0>;
-			 bus-width = <4>;
-			 clock = <&gcc 0>;
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+			index = <0x0>;
+			bus-width = <4>;
+			clock = <&gcc 0>;
 			clock-frequency = <200000000>;
 		 };
 
-- 
2.20.1

[U-Boot] [U-Boot, v1, 1/5] arm: mach-snapdragon: db820c: Actually init PLL for serial

[Tom Rini]

On Sat, Jan 12, 2019 at 11:47:24AM +0200, Ramon Fried wrote:

> The PLL for the UART was not set, and relied on previous
> initializtion made by LK. add the appropriate initialization.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 2/5] arm: mach-snapdragon: add pinctrl driver for db820c

[Tom Rini]

On Sat, Jan 12, 2019 at 11:47:25AM +0200, Ramon Fried wrote:

> Add pinctrl driver for Dragonboard820c, currently with only
> one mux func to initialize pins for serial console.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 3/5] configs: dragonboard820c: Enable pinctrl/mux config

[Tom Rini]

On Sat, Jan 12, 2019 at 11:47:26AM +0200, Ramon Fried wrote:

> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 4/5] arm: mach-snapdragon: pinctrl: clarify gpio disable bit

[Tom Rini]

On Sat, Jan 12, 2019 at 11:47:27AM +0200, Ramon Fried wrote:

> The TLMM_GPIO_ENABLE bit is actually use to disable
> the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, v1, 5/5] dts: 820c: Add pinctrl node and uart mux

[Tom Rini]

On Sat, Jan 12, 2019 at 11:47:28AM +0200, Ramon Fried wrote:

> * Add pinctrl node for TLMM and add mux request for uart node.
> * Rename uart to the actual board uart port.
> * Fix indentendation of sdhc2 node.
> 
> Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

Applied to u-boot/master, thanks!

-- 
Tom
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