From: Maxime Chevallier <maxime.chevallier@bootlin.com> To: davem@davemloft.net Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>, Heiner Kallweit <hkallweit1@gmail.com>, Russell King <linux@armlinux.org.uk>, linux-arm-kernel@lists.infradead.org, Antoine Tenart <antoine.tenart@bootlin.com>, thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com, miquel.raynal@bootlin.com, nadavh@marvell.com, stefanc@marvell.com, mw@semihalf.com Subject: [PATCH net-next v2 04/10] net: phy: Automatically fill the generic TP, FIBRE and Backplane modes Date: Thu, 7 Feb 2019 10:49:33 +0100 [thread overview] Message-ID: <20190207094939.27369-5-maxime.chevallier@bootlin.com> (raw) In-Reply-To: <20190207094939.27369-1-maxime.chevallier@bootlin.com> PHY advertised and supported linkmodes contain both specific modes such as 1000BASET Half/Full and generic ones such as TP that represent a class of modes. Since some modes such as Fibre, TP or Backplane match a wide range of specific modes, we can automatically set these bits if one of the specific modes it corresponds to is present in the list. The 'TP' bit is set whenever there's a BaseT linkmode in phydev->supported. The 'FIBRE' bit is set for BaseL, BaseS and BaseE linkmodes. Finally, the 'Backplane' is set whenever a BaseK mode is supported. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- drivers/net/phy/phy_device.c | 67 +++++++++++++++++++++++++++++++++++- include/linux/linkmode.h | 6 ++++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index a4cbc5a6f09d..942cfa7548c4 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1066,15 +1066,80 @@ static int phy_poll_reset(struct phy_device *phydev) * straightforward to maintain, since PHYs and MACs are subject to quirks and * erratas. This function re-builds the list of the supported pause parameters * by taking into account the parameters expressed in the driver's features - * list. + * list. It also sets the generic bits indicating Twisted Pair, Fibre and + * Backaplane link modes support based on the detailed list that can be built + * from the PHY's ability list. */ static void phy_update_linkmodes(struct phy_device *phydev) { + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_baset_features) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_fibre_features) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_backplane_features) = { 0, }; struct device_driver *drv = phydev->mdio.dev.driver; struct phy_driver *phydrv = to_phy_driver(drv); + const int phy_baset_features_array[] = { + ETHTOOL_LINK_MODE_10baseT_Half_BIT, + ETHTOOL_LINK_MODE_10baseT_Full_BIT, + ETHTOOL_LINK_MODE_100baseT_Half_BIT, + ETHTOOL_LINK_MODE_100baseT_Full_BIT, + ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + }; + + const int phy_fibre_features_array[] = { + ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, + ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, + ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, + ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, + ETHTOOL_LINK_MODE_10000baseER_Full_BIT, + }; + + const int phy_backplane_features_array[] = { + ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, + ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, + ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, + }; + + linkmode_set_bit_array(phy_baset_features_array, + ARRAY_SIZE(phy_baset_features_array), + phy_baset_features); + + linkmode_set_bit_array(phy_fibre_features_array, + ARRAY_SIZE(phy_fibre_features_array), + phy_fibre_features); + + linkmode_set_bit_array(phy_backplane_features_array, + ARRAY_SIZE(phy_backplane_features_array), + phy_backplane_features); + mutex_lock(&phydev->lock); + if (linkmode_intersects(phydev->supported, phy_baset_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); + + if (linkmode_intersects(phydev->supported, phy_fibre_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, + phydev->supported); + + if (linkmode_intersects(phydev->supported, phy_backplane_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, + phydev->supported); + /* The Pause Frame bits indicate that the PHY can support passing * pause frames. During autonegotiation, the PHYs will determine if * they should allow pause frames to pass. The MAC driver should then diff --git a/include/linux/linkmode.h b/include/linux/linkmode.h index a99c58866860..49ab6415e1e0 100644 --- a/include/linux/linkmode.h +++ b/include/linux/linkmode.h @@ -82,4 +82,10 @@ static inline int linkmode_equal(const unsigned long *src1, return bitmap_equal(src1, src2, __ETHTOOL_LINK_MODE_MASK_NBITS); } +static inline bool linkmode_intersects(const unsigned long *src1, + const unsigned long *src2) +{ + return bitmap_intersects(src1, src2, __ETHTOOL_LINK_MODE_MASK_NBITS); +} + #endif /* __LINKMODE_H */ -- 2.19.2
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Chevallier <maxime.chevallier@bootlin.com> To: davem@davemloft.net Cc: Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>, mw@semihalf.com, Antoine Tenart <antoine.tenart@bootlin.com>, netdev@vger.kernel.org, gregory.clement@bootlin.com, linux-kernel@vger.kernel.org, Maxime Chevallier <maxime.chevallier@bootlin.com>, nadavh@marvell.com, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com, Russell King <linux@armlinux.org.uk>, stefanc@marvell.com, linux-arm-kernel@lists.infradead.org, Heiner Kallweit <hkallweit1@gmail.com> Subject: [PATCH net-next v2 04/10] net: phy: Automatically fill the generic TP, FIBRE and Backplane modes Date: Thu, 7 Feb 2019 10:49:33 +0100 [thread overview] Message-ID: <20190207094939.27369-5-maxime.chevallier@bootlin.com> (raw) In-Reply-To: <20190207094939.27369-1-maxime.chevallier@bootlin.com> PHY advertised and supported linkmodes contain both specific modes such as 1000BASET Half/Full and generic ones such as TP that represent a class of modes. Since some modes such as Fibre, TP or Backplane match a wide range of specific modes, we can automatically set these bits if one of the specific modes it corresponds to is present in the list. The 'TP' bit is set whenever there's a BaseT linkmode in phydev->supported. The 'FIBRE' bit is set for BaseL, BaseS and BaseE linkmodes. Finally, the 'Backplane' is set whenever a BaseK mode is supported. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> --- drivers/net/phy/phy_device.c | 67 +++++++++++++++++++++++++++++++++++- include/linux/linkmode.h | 6 ++++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index a4cbc5a6f09d..942cfa7548c4 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1066,15 +1066,80 @@ static int phy_poll_reset(struct phy_device *phydev) * straightforward to maintain, since PHYs and MACs are subject to quirks and * erratas. This function re-builds the list of the supported pause parameters * by taking into account the parameters expressed in the driver's features - * list. + * list. It also sets the generic bits indicating Twisted Pair, Fibre and + * Backaplane link modes support based on the detailed list that can be built + * from the PHY's ability list. */ static void phy_update_linkmodes(struct phy_device *phydev) { + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_baset_features) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_fibre_features) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_backplane_features) = { 0, }; struct device_driver *drv = phydev->mdio.dev.driver; struct phy_driver *phydrv = to_phy_driver(drv); + const int phy_baset_features_array[] = { + ETHTOOL_LINK_MODE_10baseT_Half_BIT, + ETHTOOL_LINK_MODE_10baseT_Full_BIT, + ETHTOOL_LINK_MODE_100baseT_Half_BIT, + ETHTOOL_LINK_MODE_100baseT_Full_BIT, + ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + ETHTOOL_LINK_MODE_10000baseT_Full_BIT, + }; + + const int phy_fibre_features_array[] = { + ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, + ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, + ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, + ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, + ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, + ETHTOOL_LINK_MODE_10000baseER_Full_BIT, + }; + + const int phy_backplane_features_array[] = { + ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, + ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, + ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, + }; + + linkmode_set_bit_array(phy_baset_features_array, + ARRAY_SIZE(phy_baset_features_array), + phy_baset_features); + + linkmode_set_bit_array(phy_fibre_features_array, + ARRAY_SIZE(phy_fibre_features_array), + phy_fibre_features); + + linkmode_set_bit_array(phy_backplane_features_array, + ARRAY_SIZE(phy_backplane_features_array), + phy_backplane_features); + mutex_lock(&phydev->lock); + if (linkmode_intersects(phydev->supported, phy_baset_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported); + + if (linkmode_intersects(phydev->supported, phy_fibre_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, + phydev->supported); + + if (linkmode_intersects(phydev->supported, phy_backplane_features)) + linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, + phydev->supported); + /* The Pause Frame bits indicate that the PHY can support passing * pause frames. During autonegotiation, the PHYs will determine if * they should allow pause frames to pass. The MAC driver should then diff --git a/include/linux/linkmode.h b/include/linux/linkmode.h index a99c58866860..49ab6415e1e0 100644 --- a/include/linux/linkmode.h +++ b/include/linux/linkmode.h @@ -82,4 +82,10 @@ static inline int linkmode_equal(const unsigned long *src1, return bitmap_equal(src1, src2, __ETHTOOL_LINK_MODE_MASK_NBITS); } +static inline bool linkmode_intersects(const unsigned long *src1, + const unsigned long *src2) +{ + return bitmap_intersects(src1, src2, __ETHTOOL_LINK_MODE_MASK_NBITS); +} + #endif /* __LINKMODE_H */ -- 2.19.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-07 9:50 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-07 9:49 [PATCH net-next v2 00/10] net: phy: Add support for 2.5GBASET PHYs Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 01/10] net: phy: Update PHY linkmodes after config_init Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 10:31 ` Maxime Chevallier 2019-02-07 10:31 ` Maxime Chevallier 2019-02-07 13:48 ` Andrew Lunn 2019-02-07 13:48 ` Andrew Lunn 2019-02-07 13:55 ` Maxime Chevallier 2019-02-07 13:55 ` Maxime Chevallier 2019-02-07 18:21 ` Heiner Kallweit 2019-02-07 18:21 ` Heiner Kallweit 2019-02-07 9:49 ` [PATCH net-next v2 02/10] net: phy: Mask-out non-compatible modes when setting the max-speed Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 13:59 ` Andrew Lunn 2019-02-07 13:59 ` Andrew Lunn 2019-02-07 9:49 ` [PATCH net-next v2 03/10] net: phy: Move of_set_phy_eee_broken to phy-core.c Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 14:01 ` Andrew Lunn 2019-02-07 14:01 ` Andrew Lunn 2019-02-07 9:49 ` Maxime Chevallier [this message] 2019-02-07 9:49 ` [PATCH net-next v2 04/10] net: phy: Automatically fill the generic TP, FIBRE and Backplane modes Maxime Chevallier 2019-02-07 14:09 ` Andrew Lunn 2019-02-07 14:09 ` Andrew Lunn 2019-02-07 14:49 ` Maxime Chevallier 2019-02-07 14:49 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 05/10] net: phy: Extract genphy_c45_pma_read_abilities from marvell10g Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 06/10] net: phy: Add generic support for 2.5GBaseT and 5GBaseT Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 07/10] net: phy: marvell10g: Add support for 2.5GBASET Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 14:15 ` Andrew Lunn 2019-02-07 14:15 ` Andrew Lunn 2019-02-07 23:48 ` Russell King - ARM Linux admin 2019-02-07 23:48 ` Russell King - ARM Linux admin 2019-02-20 10:54 ` Maxime Chevallier 2019-02-20 10:54 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 08/10] net: phy: marvell10g: Force reading of 2.5/5G Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 9:49 ` [PATCH net-next v2 09/10] net: mvpp2: Add 2.5GBaseT support Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-07 14:17 ` Andrew Lunn 2019-02-07 14:17 ` Andrew Lunn 2019-02-07 9:49 ` [PATCH net-next v2 10/10] net: phy: marvell10g: add support for the 88x2110 PHY Maxime Chevallier 2019-02-07 9:49 ` Maxime Chevallier 2019-02-09 13:22 ` [PATCH net-next v2 00/10] net: phy: Add support for 2.5GBASET PHYs Heiner Kallweit 2019-02-09 13:22 ` Heiner Kallweit 2019-02-09 16:25 ` Andrew Lunn 2019-02-09 16:25 ` Andrew Lunn 2019-02-09 16:28 ` Heiner Kallweit 2019-02-09 16:28 ` Heiner Kallweit 2019-02-11 7:46 ` Maxime Chevallier 2019-02-11 7:46 ` Maxime Chevallier
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