[PATCH 0/5] staging: mt7621-pci: minor cleanups

[PATCH 0/5] staging: mt7621-pci: minor cleanups

[Sergio Paracuellos]

This patch series make some minor cleanups of this driver in order
to prepare it to be promoted from staging. Changes are:
* use general pcie reset line in device tree and use reset_control
to handle it,
* some minor space-tabs issue.
* Some minor removes of not needed stuff.

After this changes, only properly handling the clocks with a new
driver is remaining.

All changes are only compile-tested.

Hope this helps.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (5):
  staging: mt7621-pci: add reset control for general pcie reset
  staging: mt7621-dts: add general pcie reset line to pcie bindings
  staging: mt7621-pci: remove not used definitions
  staging: mt7621-pci: replace spaces with tabs in comment
  staging: mt7621-pci: remove two register writes

 drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
 drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
 2 files changed, 21 insertions(+), 22 deletions(-)

-- 
2.19.1

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[PATCH 1/5] staging: mt7621-pci: add reset control for general pcie reset

[Sergio Paracuellos]

There is still a reset line which is not being handled using reset_control
properly and just being accessing writing registers. Use reset_control
instead for pcie general reset line.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: NeilBrown <neil@brown.name>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index a5c31807bb8f..ad38a787b2da 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -39,9 +39,6 @@
 #define RALINK_RSTCTRL			0x34
 #define CHIP_REV_MT7621_E2		0x0101
 
-/* RALINK_RSTCTRL bits */
-#define RALINK_PCIE_RST			BIT(23)
-
 /* MediaTek specific configuration registers */
 #define PCIE_FTS_NUM			0x70c
 #define PCIE_FTS_NUM_MASK		GENMASK(15, 8)
@@ -125,6 +122,7 @@ struct mt7621_pcie_port {
  * @offset: IO / Memory offset
  * @dev: Pointer to PCIe device
  * @ports: pointer to PCIe port information
+ * @rst: pointer to pcie reset
  */
 struct mt7621_pcie {
 	void __iomem *base;
@@ -137,6 +135,7 @@ struct mt7621_pcie {
 		resource_size_t io;
 	} offset;
 	struct list_head ports;
+	struct reset_control *rst;
 };
 
 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
@@ -358,6 +357,12 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	if (IS_ERR(pcie->base))
 		return PTR_ERR(pcie->base);
 
+	pcie->rst = devm_reset_control_get_exclusive(dev, "pcie");
+	if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) {
+		dev_err(dev, "failed to get pcie reset control\n");
+		return PTR_ERR(pcie->rst);
+	}
+
 	for_each_available_child_of_node(node, child) {
 		int slot;
 
@@ -442,13 +447,13 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 		}
 	}
 
-	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
+	reset_control_assert(pcie->rst);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
 	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
 	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
 	msleep(50);
-	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
+	reset_control_deassert(pcie->rst);
 }
 
 static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
-- 
2.19.1

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[PATCH 2/5] staging: mt7621-dts: add general pcie reset line to pcie bindings

[Sergio Paracuellos]

Add general pci reset line to pcie bindings to use reset_control properly
in driver code.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: NeilBrown <neil@brown.name>
---
 drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index f0c51622eca1..3645360e7841 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -420,8 +420,8 @@
 
 		status = "disabled";
 
-		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
-		reset-names = "pcie0", "pcie1", "pcie2";
+		resets = <&rstctrl 23 &rstctrl 24 &rstctrl 25 &rstctrl 26>;
+		reset-names = "pcie", "pcie0", "pcie1", "pcie2";
 		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 		clock-names = "pcie0", "pcie1", "pcie2";
 		phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>;
-- 
2.19.1

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[PATCH 3/5] staging: mt7621-pci: remove not used definitions

[Sergio Paracuellos]

There are two definitions which are not being used at all.
Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: NeilBrown <neil@brown.name>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index ad38a787b2da..998d48fd3e7a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -35,8 +35,6 @@
 
 /* sysctl */
 #define MT7621_CHIP_REV_ID		0x0c
-#define RALINK_CLKCFG1			0x30
-#define RALINK_RSTCTRL			0x34
 #define CHIP_REV_MT7621_E2		0x0101
 
 /* MediaTek specific configuration registers */
-- 
2.19.1

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[PATCH 4/5] staging: mt7621-pci: replace spaces with tabs in comment

[Sergio Paracuellos]

To properly follow kernel style replace spaces with tabs in comment
where link status bits are explained.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: NeilBrown <neil@brown.name>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 998d48fd3e7a..fc2543d076c4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -546,15 +546,15 @@ static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
 		return -1;
 
 	/*
-	 * pcie(2/1/0) link status pcie2_num	pcie1_num	pcie0_num
-	 * 3'b000		   x	        x		x
-	 * 3'b001		   x	        x		0
-	 * 3'b010		   x	        0		x
-	 * 3'b011		   x	        1		0
-	 * 3'b100		   0	        x		x
-	 * 3'b101	           1 	        x		0
-	 * 3'b110	           1	        0		x
-	 * 3'b111		   2	        1		0
+	 * pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
+	 * 3'b000			x		x		x
+	 * 3'b001			x		x		0
+	 * 3'b010			x		0		x
+	 * 3'b011			x		1		0
+	 * 3'b100			0		x		x
+	 * 3'b101			1		x		0
+	 * 3'b110			1		0		x
+	 * 3'b111			2		1		0
 	 */
 	switch (pcie_link_status) {
 	case 2:
-- 
2.19.1

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[PATCH 5/5] staging: mt7621-pci: remove two register writes

[Sergio Paracuellos]

There is no need to write IO and memory space window Host PCI bridge
registers before doing anything else. Just use its default values which
should be ok.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Reviewed-by: NeilBrown <neil@brown.name>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index fc2543d076c4..8a682ce22508 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -88,7 +88,6 @@
 #define PCIE_CLK_GEN_DIS		0
 #define PCIE_CLK_GEN1_DIS		GENMASK(30, 24)
 #define PCIE_CLK_GEN1_EN		(BIT(27) | BIT(25))
-#define RALINK_PCI_IO_MAP_BASE		0x1e160000
 #define MEMORY_BASE			0x0
 
 /**
@@ -666,9 +665,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		return 0;
 	}
 
-	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
-	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-
 	mt7621_pcie_enable_ports(pcie);
 
 	err = mt7621_pci_parse_request_of_pci_ranges(pcie);
-- 
2.19.1

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Re: [PATCH 0/5] staging: mt7621-pci: minor cleanups

[NeilBrown]

[-- Attachment #1.1: Type: text/plain, Size: 3117 bytes --]

On Tue, Feb 12 2019, Sergio Paracuellos wrote:

> This patch series make some minor cleanups of this driver in order
> to prepare it to be promoted from staging. Changes are:
> * use general pcie reset line in device tree and use reset_control
> to handle it,
> * some minor space-tabs issue.
> * Some minor removes of not needed stuff.
>
> After this changes, only properly handling the clocks with a new
> driver is remaining.
>
> All changes are only compile-tested.
>
> Hope this helps.
>
> Best regards,
>     Sergio Paracuellos
>
> Sergio Paracuellos (5):
>   staging: mt7621-pci: add reset control for general pcie reset
>   staging: mt7621-dts: add general pcie reset line to pcie bindings
>   staging: mt7621-pci: remove not used definitions
>   staging: mt7621-pci: replace spaces with tabs in comment
>   staging: mt7621-pci: remove two register writes
>
>  drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
>  drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
>  2 files changed, 21 insertions(+), 22 deletions(-)

Thanks for these.  They may sense to me.

I tried testing and am not having much luck - but that isn't because of
these patches.
Building
Commit 209312369e6d ("staging: erofs: remove redundant unlikely annotation in unzip_vle.c")

(current staging-next branch) with

CONFIG_PCI_MT7621=y
CONFIG_PCI_MT7621_PHY=y

results in

[    0.480000] mt7621-pci 1e140000.pcie: Parsing DT failed
[    0.490000] mt7621-pci-phy 1a149000.pcie-phy: can't request region for resource [mem 0x1a149000-0x1a1496ff]
[    0.510000] mt7621-pci-phy 1a149000.pcie-phy: failed to remap phy regs
[    0.520000] mt7621-pci-phy: probe of 1a149000.pcie-phy failed with error -16
[    0.530000] mt7621-pci-phy 1a14a000.pcie-phy: can't request region for resource [mem 0x1a14a000-0x1a14a6ff]
[    0.550000] mt7621-pci-phy 1a14a000.pcie-phy: failed to remap phy regs
[    0.570000] mt7621-pci-phy: probe of 1a14a000.pcie-phy failed with error -16
...

[   10.260000] rt2880-pinmux pinctrl: pcie is already enabled
[   10.270000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
[   10.280000] mt7621-pci 1e140000.pcie: Parsing DT failed
[   10.290000] rt2880-pinmux pinctrl: pcie is already enabled
[   10.300000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
[   10.320000] mt7621-pci 1e140000.pcie: Parsing DT failed
.....
[   10.630000] rt2880-pinmux pinctrl: pcie is already enabled
[   10.640000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
...
[   10.650000] mt7621-pci 1e140000.pcie: Parsing DT failed
...
[   10.700000] rt2880-pinmux pinctrl: pcie is already enabled
[   10.710000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
[   10.720000] mt7621-pci 1e140000.pcie: Parsing DT failed
...
[   11.320000] rt2880-pinmux pinctrl: pcie is already enabled
[   11.330000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
[   11.350000] mt7621-pci 1e140000.pcie: Parsing DT failed


So something is messed up somewhere.
I might be able to have a deeper look on the weekend.

NeilBrown

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Re: [PATCH 0/5] staging: mt7621-pci: minor cleanups

[Sergio Paracuellos]

Hi Neil,

On Wed, Feb 13, 2019 at 1:24 AM NeilBrown <neil@brown.name> wrote:
>
> On Tue, Feb 12 2019, Sergio Paracuellos wrote:
>
> > This patch series make some minor cleanups of this driver in order
> > to prepare it to be promoted from staging. Changes are:
> > * use general pcie reset line in device tree and use reset_control
> > to handle it,
> > * some minor space-tabs issue.
> > * Some minor removes of not needed stuff.
> >
> > After this changes, only properly handling the clocks with a new
> > driver is remaining.
> >
> > All changes are only compile-tested.
> >
> > Hope this helps.
> >
> > Best regards,
> >     Sergio Paracuellos
> >
> > Sergio Paracuellos (5):
> >   staging: mt7621-pci: add reset control for general pcie reset
> >   staging: mt7621-dts: add general pcie reset line to pcie bindings
> >   staging: mt7621-pci: remove not used definitions
> >   staging: mt7621-pci: replace spaces with tabs in comment
> >   staging: mt7621-pci: remove two register writes
> >
> >  drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
> >  2 files changed, 21 insertions(+), 22 deletions(-)
>
> Thanks for these.  They may sense to me.
>
> I tried testing and am not having much luck - but that isn't because of
> these patches.
> Building
> Commit 209312369e6d ("staging: erofs: remove redundant unlikely annotation in unzip_vle.c")
>
> (current staging-next branch) with
>
> CONFIG_PCI_MT7621=y
> CONFIG_PCI_MT7621_PHY=y
>
> results in
>
> [    0.480000] mt7621-pci 1e140000.pcie: Parsing DT failed
> [    0.490000] mt7621-pci-phy 1a149000.pcie-phy: can't request region for resource [mem 0x1a149000-0x1a1496ff]
> [    0.510000] mt7621-pci-phy 1a149000.pcie-phy: failed to remap phy regs
> [    0.520000] mt7621-pci-phy: probe of 1a149000.pcie-phy failed with error -16
> [    0.530000] mt7621-pci-phy 1a14a000.pcie-phy: can't request region for resource [mem 0x1a14a000-0x1a14a6ff]
> [    0.550000] mt7621-pci-phy 1a14a000.pcie-phy: failed to remap phy regs
> [    0.570000] mt7621-pci-phy: probe of 1a14a000.pcie-phy failed with error -16

I don't really understand why phy driver cannot remap properly these
regions. This is being done apparently properly in
mt7621-pci-phy probe function and addresses for resources in this log
are both ok.

> ...
>
> [   10.260000] rt2880-pinmux pinctrl: pcie is already enabled
> [   10.270000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> [   10.280000] mt7621-pci 1e140000.pcie: Parsing DT failed
> [   10.290000] rt2880-pinmux pinctrl: pcie is already enabled
> [   10.300000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> [   10.320000] mt7621-pci 1e140000.pcie: Parsing DT failed
> .....
> [   10.630000] rt2880-pinmux pinctrl: pcie is already enabled
> [   10.640000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> ...
> [   10.650000] mt7621-pci 1e140000.pcie: Parsing DT failed
> ...
> [   10.700000] rt2880-pinmux pinctrl: pcie is already enabled
> [   10.710000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> [   10.720000] mt7621-pci 1e140000.pcie: Parsing DT failed
> ...
> [   11.320000] rt2880-pinmux pinctrl: pcie is already enabled
> [   11.330000] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> [   11.350000] mt7621-pci 1e140000.pcie: Parsing DT failed

pinctrl errors seems to be related with pcie device tree:

pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;

where

pcie_pins: pcie0 {
     pcie0 {
          groups = "pcie";
          function = "pcie rst";
     };
};

Maybe adding some extra traces to mt7621_pcie_parse_dt in some error
paths is helpful.

>
>
> So something is messed up somewhere.
> I might be able to have a deeper look on the weekend.

That would be really helpful, thank you.

>
> NeilBrown

Best regards,
    Sergio Paracuellos
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Re: [PATCH 0/5] staging: mt7621-pci: minor cleanups

[NeilBrown]

[-- Attachment #1: Type: text/plain, Size: 11290 bytes --]

On Tue, Feb 12 2019, Sergio Paracuellos wrote:

> This patch series make some minor cleanups of this driver in order
> to prepare it to be promoted from staging. Changes are:
> * use general pcie reset line in device tree and use reset_control
> to handle it,
> * some minor space-tabs issue.
> * Some minor removes of not needed stuff.
>
> After this changes, only properly handling the clocks with a new
> driver is remaining.
>
> All changes are only compile-tested.
>
> Hope this helps.
>
> Best regards,
>     Sergio Paracuellos
>
> Sergio Paracuellos (5):
>   staging: mt7621-pci: add reset control for general pcie reset
>   staging: mt7621-dts: add general pcie reset line to pcie bindings
>   staging: mt7621-pci: remove not used definitions
>   staging: mt7621-pci: replace spaces with tabs in comment
>   staging: mt7621-pci: remove two register writes
>
>  drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
>  drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
>  2 files changed, 21 insertions(+), 22 deletions(-)
>

I've now tested these after fixing the two issues with the previous
series and it all appears to work.

Reviewed-by: NeilBrown <neil@brown.name>

There seem to be more PCI related messages than before.
See below.

The "no space for ..." messages have always been there and don't seem to
cause problems.  It would be nice to know what is causing them.

Other messages seem more noisy than really necessary.

Any thoughts?

Thanks,
NeilBrown


[   10.320000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
[   10.330000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
[   10.460000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
[   10.470000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
[   10.600000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
[   10.610000] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
[   10.690000] mt7621-pci 1e140000.pcie: de-assert port 0 PERST_N
[   10.700000] mt7621-pci 1e140000.pcie: de-assert port 1 PERST_N
[   10.710000] mt7621-pci 1e140000.pcie: de-assert port 2 PERST_N
[   10.720000] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
[   10.740000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[   10.750000] pci_bus 0000:00: root bus resource [io  0xffffffff]
[   10.760000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
[   10.780000] pci_bus 0000:00: root bus resource [bus 00-ff]
[   10.790000] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
[   10.790000] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[   10.790000] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[   10.790000] pci 0000:00:00.0: supports D1
[   10.790000] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[   10.790000] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
[   10.790000] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[   10.790000] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[   10.790000] pci 0000:00:01.0: supports D1
[   10.790000] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
[   10.790000] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400
[   10.790000] pci 0000:00:02.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[   10.790000] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[   10.790000] pci 0000:00:02.0: supports D1
[   10.790000] pci 0000:00:02.0: PME# supported from D0 D1 D3hot
[   10.790000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[   10.810000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[   10.820000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[   10.840000] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185
[   10.840000] pci 0000:01:00.0: reg 0x10: [io  0x0000-0x0007]
[   10.840000] pci 0000:01:00.0: reg 0x14: [io  0x0000-0x0003]
[   10.840000] pci 0000:01:00.0: reg 0x18: [io  0x0000-0x0007]
[   10.840000] pci 0000:01:00.0: reg 0x1c: [io  0x0000-0x0003]
[   10.840000] pci 0000:01:00.0: reg 0x20: [io  0x0000-0x000f]
[   10.840000] pci 0000:01:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[   10.840000] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[   10.870000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[   10.880000] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
[   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
[   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
[   10.880000] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[   10.880000] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185
[   10.880000] pci 0000:02:00.0: reg 0x10: [io  0x0000-0x0007]
[   10.880000] pci 0000:02:00.0: reg 0x14: [io  0x0000-0x0003]
[   10.880000] pci 0000:02:00.0: reg 0x18: [io  0x0000-0x0007]
[   10.880000] pci 0000:02:00.0: reg 0x1c: [io  0x0000-0x0003]
[   10.880000] pci 0000:02:00.0: reg 0x20: [io  0x0000-0x000f]
[   10.880000] pci 0000:02:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[   10.880000] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[   10.910000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[   10.920000] pci 0000:00:01.0:   bridge window [io  0x0000-0x0fff]
[   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff]
[   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff pref]
[   10.920000] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[   10.920000] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185
[   10.920000] pci 0000:03:00.0: reg 0x10: [io  0x0000-0x0007]
[   10.920000] pci 0000:03:00.0: reg 0x14: [io  0x0000-0x0003]
[   10.920000] pci 0000:03:00.0: reg 0x18: [io  0x0000-0x0007]
[   10.920000] pci 0000:03:00.0: reg 0x1c: [io  0x0000-0x0003]
[   10.920000] pci 0000:03:00.0: reg 0x20: [io  0x0000-0x000f]
[   10.920000] pci 0000:03:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[   10.920000] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[   10.950000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[   10.960000] pci 0000:00:02.0:   bridge window [io  0x0000-0x0fff]
[   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff]
[   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff pref]
[   10.960000] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
[   10.960000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[   10.970000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[   10.980000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[   11.000000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[   11.010000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[   11.020000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[   11.040000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[   11.050000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
[   11.070000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[   11.080000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
[   11.090000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
[   11.110000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
[   11.120000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
[   11.130000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
[   11.150000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
[   11.160000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
[   11.170000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
[   11.190000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
[   11.200000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
[   11.210000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
[   11.230000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
[   11.240000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[   11.250000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
[   11.260000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
[   11.280000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
[   11.290000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
[   11.300000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
[   11.320000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
[   11.330000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
[   11.340000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
[   11.350000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
[   11.370000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
[   11.380000] pci 0000:00:00.0: PCI bridge to [bus 01]
[   11.390000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
[   11.400000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
[   11.420000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[   11.430000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
[   11.440000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
[   11.460000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
[   11.470000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
[   11.480000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
[   11.500000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
[   11.510000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
[   11.520000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
[   11.530000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
[   11.550000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
[   11.560000] pci 0000:00:01.0: PCI bridge to [bus 02]
[   11.570000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
[   11.580000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
[   11.600000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
[   11.610000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
[   11.620000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
[   11.640000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
[   11.650000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
[   11.660000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
[   11.680000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
[   11.690000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
[   11.700000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
[   11.710000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
[   11.730000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
[   11.740000] pci 0000:00:02.0: PCI bridge to [bus 03]
[   11.750000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
[   11.760000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]

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Re: [PATCH 0/5] staging: mt7621-pci: minor cleanups

[Sergio Paracuellos]

Hi Neil,

On Fri, Feb 15, 2019 at 10:31 AM NeilBrown <neil@brown.name> wrote:
>
> On Tue, Feb 12 2019, Sergio Paracuellos wrote:
>
> > This patch series make some minor cleanups of this driver in order
> > to prepare it to be promoted from staging. Changes are:
> > * use general pcie reset line in device tree and use reset_control
> > to handle it,
> > * some minor space-tabs issue.
> > * Some minor removes of not needed stuff.
> >
> > After this changes, only properly handling the clocks with a new
> > driver is remaining.
> >
> > All changes are only compile-tested.
> >
> > Hope this helps.
> >
> > Best regards,
> >     Sergio Paracuellos
> >
> > Sergio Paracuellos (5):
> >   staging: mt7621-pci: add reset control for general pcie reset
> >   staging: mt7621-dts: add general pcie reset line to pcie bindings
> >   staging: mt7621-pci: remove not used definitions
> >   staging: mt7621-pci: replace spaces with tabs in comment
> >   staging: mt7621-pci: remove two register writes
> >
> >  drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
> >  2 files changed, 21 insertions(+), 22 deletions(-)
> >
>
> I've now tested these after fixing the two issues with the previous
> series and it all appears to work.

Good news! :-)

>
> Reviewed-by: NeilBrown <neil@brown.name>

Thanks for testing and reviewing all of this.

>
> There seem to be more PCI related messages than before.
> See below.
>
> The "no space for ..." messages have always been there and don't seem to
> cause problems.  It would be nice to know what is causing them.

All of them seems to be related with pci io. I'll try to check why this messages
are occurring.

>
> Other messages seem more noisy than really necessary.
>
> Any thoughts?
>
> Thanks,
> NeilBrown
>

Best regards,
    Sergio Paracuellos

>
> [   10.320000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> [   10.330000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> [   10.460000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> [   10.470000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> [   10.600000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> [   10.610000] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> [   10.690000] mt7621-pci 1e140000.pcie: de-assert port 0 PERST_N
> [   10.700000] mt7621-pci 1e140000.pcie: de-assert port 1 PERST_N
> [   10.710000] mt7621-pci 1e140000.pcie: de-assert port 2 PERST_N
> [   10.720000] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> [   10.740000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [   10.750000] pci_bus 0000:00: root bus resource [io  0xffffffff]
> [   10.760000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> [   10.780000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [   10.790000] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:00.0: supports D1
> [   10.790000] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:01.0: supports D1
> [   10.790000] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:02.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:02.0: supports D1
> [   10.790000] pci 0000:00:02.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.810000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.820000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.840000] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185
> [   10.840000] pci 0000:01:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.840000] pci 0000:01:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.840000] pci 0000:01:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.840000] pci 0000:01:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.840000] pci 0000:01:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.840000] pci 0000:01:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.840000] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.870000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [   10.880000] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
> [   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.880000] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> [   10.880000] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185
> [   10.880000] pci 0000:02:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.880000] pci 0000:02:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.880000] pci 0000:02:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.880000] pci 0000:02:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.880000] pci 0000:02:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.880000] pci 0000:02:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.880000] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.910000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [   10.920000] pci 0000:00:01.0:   bridge window [io  0x0000-0x0fff]
> [   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.920000] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> [   10.920000] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185
> [   10.920000] pci 0000:03:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.920000] pci 0000:03:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.920000] pci 0000:03:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.920000] pci 0000:03:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.920000] pci 0000:03:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.920000] pci 0000:03:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.920000] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.950000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [   10.960000] pci 0000:00:02.0:   bridge window [io  0x0000-0x0fff]
> [   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.960000] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> [   10.960000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [   10.970000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [   10.980000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [   11.000000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [   11.010000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [   11.020000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [   11.040000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [   11.050000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
> [   11.070000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [   11.080000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
> [   11.090000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
> [   11.110000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
> [   11.120000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
> [   11.130000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
> [   11.150000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
> [   11.160000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [   11.170000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.190000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [   11.200000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.210000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [   11.230000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.240000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [   11.250000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.260000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.280000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.290000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.300000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.320000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.330000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.340000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.350000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.370000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.380000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [   11.390000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [   11.400000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
> [   11.420000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [   11.430000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.440000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.460000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.470000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.480000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.500000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.510000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.520000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.530000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.550000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.560000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [   11.570000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
> [   11.580000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
> [   11.600000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
> [   11.610000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.620000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.640000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.650000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.660000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.680000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.690000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.700000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.710000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.730000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.740000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [   11.750000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
> [   11.760000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
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Re: [PATCH 0/5] staging: mt7621-pci: minor cleanups

[Sergio Paracuellos]

Hi Neil,

Looking at this trace I have one concern. Please, see below.

On Fri, Feb 15, 2019 at 10:31 AM NeilBrown <neil@brown.name> wrote:
>
> On Tue, Feb 12 2019, Sergio Paracuellos wrote:
>
> > This patch series make some minor cleanups of this driver in order
> > to prepare it to be promoted from staging. Changes are:
> > * use general pcie reset line in device tree and use reset_control
> > to handle it,
> > * some minor space-tabs issue.
> > * Some minor removes of not needed stuff.
> >
> > After this changes, only properly handling the clocks with a new
> > driver is remaining.
> >
> > All changes are only compile-tested.
> >
> > Hope this helps.
> >
> > Best regards,
> >     Sergio Paracuellos
> >
> > Sergio Paracuellos (5):
> >   staging: mt7621-pci: add reset control for general pcie reset
> >   staging: mt7621-dts: add general pcie reset line to pcie bindings
> >   staging: mt7621-pci: remove not used definitions
> >   staging: mt7621-pci: replace spaces with tabs in comment
> >   staging: mt7621-pci: remove two register writes
> >
> >  drivers/staging/mt7621-dts/mt7621.dtsi  |  4 +--
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 39 ++++++++++++-------------
> >  2 files changed, 21 insertions(+), 22 deletions(-)
> >
>
> I've now tested these after fixing the two issues with the previous
> series and it all appears to work.
>
> Reviewed-by: NeilBrown <neil@brown.name>
>
> There seem to be more PCI related messages than before.
> See below.
>
> The "no space for ..." messages have always been there and don't seem to
> cause problems.  It would be nice to know what is causing them.
>
> Other messages seem more noisy than really necessary.
>
> Any thoughts?
>
> Thanks,
> NeilBrown
>
>
> [   10.320000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 0
> [   10.330000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> [   10.460000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 1
> [   10.470000] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> [   10.600000] mt7621-pci 1e140000.pcie: Port 454043648 N_FTS = 2
> [   10.610000] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz


> [   10.690000] mt7621-pci 1e140000.pcie: de-assert port 0 PERST_N
> [   10.700000] mt7621-pci 1e140000.pcie: de-assert port 1 PERST_N
> [   10.710000] mt7621-pci 1e140000.pcie: de-assert port 2 PERST_N

This three traces should not be here. This is in
'mt7621_pcie_enable_ports'. The following
code is wrong:

list_for_each_entry(port, &pcie->ports, list) {
     if (port->enabled) {
             if (!mt7621_pcie_enable_port(port)) {
                    dev_err(dev, "de-assert port %d PERST_N\n", port->slot);
                    continue;
             }
             dev_info(dev, "PCIE%d enabled\n", slot);
             num_slots_enabled++;
      }
}

The condition for success in mt7621_pcie_enable_port is returning zero
so the check is reversed. Should be:

if (mt7621_pcie_enable_port(port)) {
   ...
}

If this is being done as it is nothing in the next for is being
initialized... but it seems to be working... So nothing of the
stuff in the next for is necessary?

Anyway, I'll send a fix for this if statement.

Best regards,
    Sergio Paracuellos

> [   10.720000] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> [   10.740000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [   10.750000] pci_bus 0000:00: root bus resource [io  0xffffffff]
> [   10.760000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> [   10.780000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [   10.790000] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:00.0: supports D1
> [   10.790000] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:01.0: supports D1
> [   10.790000] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400
> [   10.790000] pci 0000:00:02.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [   10.790000] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x0000ffff]
> [   10.790000] pci 0000:00:02.0: supports D1
> [   10.790000] pci 0000:00:02.0: PME# supported from D0 D1 D3hot
> [   10.790000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.810000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.820000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [   10.840000] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185
> [   10.840000] pci 0000:01:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.840000] pci 0000:01:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.840000] pci 0000:01:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.840000] pci 0000:01:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.840000] pci 0000:01:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.840000] pci 0000:01:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.840000] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.870000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [   10.880000] pci 0000:00:00.0:   bridge window [io  0x0000-0x0fff]
> [   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.880000] pci 0000:00:00.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.880000] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> [   10.880000] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185
> [   10.880000] pci 0000:02:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.880000] pci 0000:02:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.880000] pci 0000:02:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.880000] pci 0000:02:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.880000] pci 0000:02:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.880000] pci 0000:02:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.880000] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.910000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [   10.920000] pci 0000:00:01.0:   bridge window [io  0x0000-0x0fff]
> [   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.920000] pci 0000:00:01.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.920000] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> [   10.920000] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185
> [   10.920000] pci 0000:03:00.0: reg 0x10: [io  0x0000-0x0007]
> [   10.920000] pci 0000:03:00.0: reg 0x14: [io  0x0000-0x0003]
> [   10.920000] pci 0000:03:00.0: reg 0x18: [io  0x0000-0x0007]
> [   10.920000] pci 0000:03:00.0: reg 0x1c: [io  0x0000-0x0003]
> [   10.920000] pci 0000:03:00.0: reg 0x20: [io  0x0000-0x000f]
> [   10.920000] pci 0000:03:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
> [   10.920000] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [   10.950000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [   10.960000] pci 0000:00:02.0:   bridge window [io  0x0000-0x0fff]
> [   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff]
> [   10.960000] pci 0000:00:02.0:   bridge window [mem 0x00000000-0x000fffff pref]
> [   10.960000] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> [   10.960000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [   10.970000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [   10.980000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [   11.000000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [   11.010000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [   11.020000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [   11.040000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [   11.050000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
> [   11.070000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [   11.080000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
> [   11.090000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
> [   11.110000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
> [   11.120000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
> [   11.130000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
> [   11.150000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
> [   11.160000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [   11.170000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.190000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [   11.200000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.210000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [   11.230000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [   11.240000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [   11.250000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.260000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.280000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.290000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.300000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.320000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.330000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.340000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.350000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.370000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.380000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [   11.390000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [   11.400000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
> [   11.420000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [   11.430000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.440000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.460000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.470000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.480000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.500000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.510000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.520000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.530000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.550000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.560000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [   11.570000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
> [   11.580000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
> [   11.600000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
> [   11.610000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [   11.620000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [   11.640000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [   11.650000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [   11.660000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [   11.680000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [   11.690000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [   11.700000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [   11.710000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [   11.730000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [   11.740000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [   11.750000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
> [   11.760000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
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[PATCH 3/5] staging: mt7621-pci: remove not used definitions

[Sergio Paracuellos]

GPIO mode is not needed to be set up anymore. Hence
remove useless related definitions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d58c880d3818..fb6e65f7624b 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -81,8 +81,6 @@
 #define PCIE_PORT_LINKUP		BIT(0)
 
 #define MEMORY_BASE			0x0
-#define PERST_MODE_MASK			GENMASK(11, 10)
-#define PERST_MODE_GPIO			BIT(10)
 #define PERST_DELAY_US			100
 
 /**
-- 
2.25.1

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