[PATCH 0/3] Make DRM DSC helpers more generally usable

[PATCH 0/3] Make DRM DSC helpers more generally usable

[David Francis]

drm_dsc could use some work so that drm drivers other than
i915 can make use of it their own DSC implementations

Move rc compute, a function that forms part of the DSC spec,
into drm. Update it to DSC 1.2. Also change the packing function
to operate only on the packing struct, to allow for drivers with
their own SDP struct headers

David Francis (3):
  drm/i915: Move dsc rate params compute into drm
  drm/dsc: Add native 420 and 422 support to compute_rc_params
  drm/dsc: Change infoframe_pack to payload_pack

 drivers/gpu/drm/drm_dsc.c         | 236 ++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_vdsc.c | 131 +----------------
 include/drm/drm_dsc.h             |   7 +-
 3 files changed, 200 insertions(+), 174 deletions(-)

-- 
2.17.1

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[PATCH 1/3] drm/i915: Move dsc rate params compute into drm

[David Francis]

The function intel_compute_rc_parameters is part of the dsc spec
and is not driver-specific. Other drm drivers might like to use
it.  The function is not changed; just moved and renamed.

Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dsc.c         | 133 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_vdsc.c | 125 +---------------------------
 include/drm/drm_dsc.h             |   1 +
 3 files changed, 135 insertions(+), 124 deletions(-)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index bc2b23adb072..4b0e3c9c3ff8 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/byteorder/generic.h>
+#include <drm/drm_print.h>
 #include <drm/drm_dp_helper.h>
 #include <drm/drm_dsc.h>
 
@@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 	/* PPS 94 - 127 are O */
 }
 EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
+
+/**
+ * drm_dsc_compute_rc_parameters() - Write rate control
+ * parameters to the dsc configuration. Some configuration
+ * fields must be present beforehand.
+ *
+ * @dsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
+{
+	unsigned long groups_per_line = 0;
+	unsigned long groups_total = 0;
+	unsigned long num_extra_mux_bits = 0;
+	unsigned long slice_bits = 0;
+	unsigned long hrd_delay = 0;
+	unsigned long final_scale = 0;
+	unsigned long rbs_min = 0;
+
+	/* Number of groups used to code each line of a slice */
+	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+				       DSC_RC_PIXELS_PER_GROUP);
+
+	/* chunksize in Bytes */
+	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+						  vdsc_cfg->bits_per_pixel,
+						  (8 * 16));
+
+	if (vdsc_cfg->convert_rgb)
+		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
+					  (4 * vdsc_cfg->bits_per_component + 4)
+					  - 2);
+	else
+		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+			(4 * vdsc_cfg->bits_per_component + 4) +
+			2 * (4 * vdsc_cfg->bits_per_component) - 2;
+	/* Number of bits in one Slice */
+	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
+
+	while ((num_extra_mux_bits > 0) &&
+	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+		num_extra_mux_bits--;
+
+	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+		vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+	/* scale_decrement_interval calculation according to DSC spec 1.11 */
+	if (vdsc_cfg->initial_scale_value > 8)
+		vdsc_cfg->scale_decrement_interval = groups_per_line /
+			(vdsc_cfg->initial_scale_value - 8);
+	else
+		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
+
+	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+		(vdsc_cfg->initial_xmit_delay *
+		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
+
+	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
+		return -ERANGE;
+	}
+
+	final_scale = (vdsc_cfg->rc_model_size * 8) /
+		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+	if (vdsc_cfg->slice_height > 1)
+		/*
+		 * NflBpgOffset is 16 bit value with 11 fractional bits
+		 * hence we multiply by 2^11 for preserving the
+		 * fractional part
+		 */
+		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
+							(vdsc_cfg->slice_height - 1));
+	else
+		vdsc_cfg->nfl_bpg_offset = 0;
+
+	/* 2^16 - 1 */
+	if (vdsc_cfg->nfl_bpg_offset > 65535) {
+		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
+		return -ERANGE;
+	}
+
+	/* Number of groups used to code the entire slice */
+	groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
+	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
+						    vdsc_cfg->initial_offset +
+						    num_extra_mux_bits) << 11),
+						  groups_total);
+
+	if (final_scale > 9) {
+		/*
+		 * ScaleIncrementInterval =
+		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
+		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
+		 * we need divide by 2^11 from pstDscCfg values
+		 */
+		vdsc_cfg->scale_increment_interval =
+				(vdsc_cfg->final_offset * (1 << 11)) /
+				((vdsc_cfg->nfl_bpg_offset +
+				vdsc_cfg->slice_bpg_offset) *
+				(final_scale - 9));
+	} else {
+		/*
+		 * If finalScaleValue is less than or equal to 9, a value of 0 should
+		 * be used to disable the scale increment at the end of the slice
+		 */
+		vdsc_cfg->scale_increment_interval = 0;
+	}
+
+	if (vdsc_cfg->scale_increment_interval > 65535) {
+		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
+		return -ERANGE;
+	}
+
+	/*
+	 * DSC spec mentions that bits_per_pixel specifies the target
+	 * bits/pixel (bpp) rate that is used by the encoder,
+	 * in steps of 1/16 of a bit per pixel
+	 */
+	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
+			     vdsc_cfg->bits_per_pixel, 16) +
+		groups_per_line * vdsc_cfg->first_line_bpg_offset;
+
+	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
+	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index c56ba0e04044..c76cec8bfb74 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
 	}
 }
 
-static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
-{
-	unsigned long groups_per_line = 0;
-	unsigned long groups_total = 0;
-	unsigned long num_extra_mux_bits = 0;
-	unsigned long slice_bits = 0;
-	unsigned long hrd_delay = 0;
-	unsigned long final_scale = 0;
-	unsigned long rbs_min = 0;
-
-	/* Number of groups used to code each line of a slice */
-	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
-				       DSC_RC_PIXELS_PER_GROUP);
-
-	/* chunksize in Bytes */
-	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
-						  vdsc_cfg->bits_per_pixel,
-						  (8 * 16));
-
-	if (vdsc_cfg->convert_rgb)
-		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
-					  (4 * vdsc_cfg->bits_per_component + 4)
-					  - 2);
-	else
-		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
-			(4 * vdsc_cfg->bits_per_component + 4) +
-			2 * (4 * vdsc_cfg->bits_per_component) - 2;
-	/* Number of bits in one Slice */
-	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
-
-	while ((num_extra_mux_bits > 0) &&
-	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
-		num_extra_mux_bits--;
-
-	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
-		vdsc_cfg->initial_scale_value = groups_per_line + 8;
-
-	/* scale_decrement_interval calculation according to DSC spec 1.11 */
-	if (vdsc_cfg->initial_scale_value > 8)
-		vdsc_cfg->scale_decrement_interval = groups_per_line /
-			(vdsc_cfg->initial_scale_value - 8);
-	else
-		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
-
-	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
-		(vdsc_cfg->initial_xmit_delay *
-		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
-
-	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
-		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
-		return -ERANGE;
-	}
-
-	final_scale = (vdsc_cfg->rc_model_size * 8) /
-		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
-	if (vdsc_cfg->slice_height > 1)
-		/*
-		 * NflBpgOffset is 16 bit value with 11 fractional bits
-		 * hence we multiply by 2^11 for preserving the
-		 * fractional part
-		 */
-		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
-							(vdsc_cfg->slice_height - 1));
-	else
-		vdsc_cfg->nfl_bpg_offset = 0;
-
-	/* 2^16 - 1 */
-	if (vdsc_cfg->nfl_bpg_offset > 65535) {
-		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
-		return -ERANGE;
-	}
-
-	/* Number of groups used to code the entire slice */
-	groups_total = groups_per_line * vdsc_cfg->slice_height;
-
-	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
-	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
-						    vdsc_cfg->initial_offset +
-						    num_extra_mux_bits) << 11),
-						  groups_total);
-
-	if (final_scale > 9) {
-		/*
-		 * ScaleIncrementInterval =
-		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
-		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
-		 * we need divide by 2^11 from pstDscCfg values
-		 */
-		vdsc_cfg->scale_increment_interval =
-				(vdsc_cfg->final_offset * (1 << 11)) /
-				((vdsc_cfg->nfl_bpg_offset +
-				vdsc_cfg->slice_bpg_offset) *
-				(final_scale - 9));
-	} else {
-		/*
-		 * If finalScaleValue is less than or equal to 9, a value of 0 should
-		 * be used to disable the scale increment at the end of the slice
-		 */
-		vdsc_cfg->scale_increment_interval = 0;
-	}
-
-	if (vdsc_cfg->scale_increment_interval > 65535) {
-		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
-		return -ERANGE;
-	}
-
-	/*
-	 * DSC spec mentions that bits_per_pixel specifies the target
-	 * bits/pixel (bpp) rate that is used by the encoder,
-	 * in steps of 1/16 of a bit per pixel
-	 */
-	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
-		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
-			     vdsc_cfg->bits_per_pixel, 16) +
-		groups_per_line * vdsc_cfg->first_line_bpg_offset;
-
-	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
-	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
-	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
-
-	return 0;
-}
-
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config)
 {
@@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 
-	return intel_compute_rc_parameters(vdsc_cfg);
+	return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
 enum intel_display_power_domain
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index d03f1b83421a..ad43494f1cc8 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe {
 void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
 void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 				const struct drm_dsc_config *dsc_cfg);
+int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
 
 #endif /* _DRM_DSC_H_ */
-- 
2.17.1

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[PATCH 2/3] drm/dsc: Add native 420 and 422 support to compute_rc_params

[David Francis]

Native 420 and 422 transfer modes are new in DSC1.2

In these modes, each two pixels of a slice are treated as one
pixel, so the slice width is half as large (round down) for
the purposes of calucating the groups per line and chunk size
in bytes

In native 422 mode, each pixel has four components, so the
mux component of a group is larger by one additional mux word
and one additional component

Now that there is native 422 support, the configuration option
previously called enable422 is renamed to simple_422 to avoid
confusion

Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dsc.c         | 31 +++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_vdsc.c |  4 ++--
 include/drm/drm_dsc.h             |  4 ++--
 3 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 4b0e3c9c3ff8..9e675dd39a44 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -77,7 +77,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
 		 DSC_PPS_MSB_SHIFT) |
 		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
-		dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
+		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
 		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
 		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
 
@@ -246,19 +246,34 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 	unsigned long final_scale = 0;
 	unsigned long rbs_min = 0;
 
-	/* Number of groups used to code each line of a slice */
-	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
-				       DSC_RC_PIXELS_PER_GROUP);
+	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
+		/* Number of groups used to code each line of a slice */
+		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
+					       DSC_RC_PIXELS_PER_GROUP);
 
-	/* chunksize in Bytes */
-	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
-						  vdsc_cfg->bits_per_pixel,
-						  (8 * 16));
+		/* chunksize in Bytes */
+		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
+							  vdsc_cfg->bits_per_pixel,
+							  (8 * 16));
+	} else {
+		/* Number of groups used to code each line of a slice */
+		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+					       DSC_RC_PIXELS_PER_GROUP);
+
+		/* chunksize in Bytes */
+		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+							  vdsc_cfg->bits_per_pixel,
+							  (8 * 16));
+	}
 
 	if (vdsc_cfg->convert_rgb)
 		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
 					  (4 * vdsc_cfg->bits_per_component + 4)
 					  - 2);
+	else if (vdsc_cfg->native_422)
+		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
+			(4 * vdsc_cfg->bits_per_component + 4) +
+			3 * (4 * vdsc_cfg->bits_per_component) - 2;
 	else
 		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
 			(4 * vdsc_cfg->bits_per_component + 4) +
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index c76cec8bfb74..7702c5c8b3f2 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -369,7 +369,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 
 	/* Gen 11 does not support YCbCr */
-	vdsc_cfg->enable422 = false;
+	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 	vdsc_cfg->block_pred_enable =
@@ -496,7 +496,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
 		pps_val |= DSC_COLOR_SPACE_CONVERSION;
-	if (vdsc_cfg->enable422)
+	if (vdsc_cfg->simple_422)
 		pps_val |= DSC_422_ENABLE;
 	if (vdsc_cfg->vbr_enable)
 		pps_val |= DSC_VBR_ENABLE;
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index ad43494f1cc8..4e55e37943d7 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -70,10 +70,10 @@ struct drm_dsc_config {
 	/* Slice Height */
 	u16 slice_height;
 	/*
-	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+	 * Simple 4:2:2 mode (from PPS, 4:2:2 conversion happens
 	 * outside of DSC encode/decode algorithm)
 	 */
-	bool enable422;
+	bool simple_422;
 	/* Picture Width */
 	u16 pic_width;
 	/* Picture Height */
-- 
2.17.1

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[PATCH 3/3] drm/dsc: Change infoframe_pack to payload_pack

[David Francis]

The function drm_dsc_pps_infoframe_pack only
packed the payload portion of the infoframe.
Change the input struct to the PPS payload
to clarify the function's purpose and allow
for drivers with their own handling of sdp.
(e.g. drivers with their own struct for
all SDP transactions)

Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/drm_dsc.c         | 86 +++++++++++++++----------------
 drivers/gpu/drm/i915/intel_vdsc.c |  2 +-
 include/drm/drm_dsc.h             |  2 +-
 3 files changed, 45 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
index 9e675dd39a44..4ada4d4f59ac 100644
--- a/drivers/gpu/drm/drm_dsc.c
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -38,42 +38,42 @@ void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
 
 /**
- * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * drm_dsc_pps_payload_pack() - Populates the DSC PPS payload
  * using the DSC configuration parameters in the order expected
  * by the DSC Display Sink device. For the DSC, the sink device
  * expects the PPS payload in the big endian format for the fields
  * that span more than 1 byte.
  *
- * @pps_sdp:
- * Secondary data packet for DSC Picture Parameter Set
+ * @pps_payload:
+ * DSC Picture Parameter Set
  * @dsc_cfg:
  * DSC Configuration data filled by driver
  */
-void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
 				const struct drm_dsc_config *dsc_cfg)
 {
 	int i;
 
 	/* Protect against someone accidently changing struct size */
-	BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
+	BUILD_BUG_ON(sizeof(*pps_payload) !=
 		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
 
-	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+	memset(pps_payload, 0, sizeof(*pps_payload));
 
 	/* PPS 0 */
-	pps_sdp->pps_payload.dsc_version =
+	pps_payload->dsc_version =
 		dsc_cfg->dsc_version_minor |
 		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
 
 	/* PPS 1, 2 is 0 */
 
 	/* PPS 3 */
-	pps_sdp->pps_payload.pps_3 =
+	pps_payload->pps_3 =
 		dsc_cfg->line_buf_depth |
 		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
 
 	/* PPS 4 */
-	pps_sdp->pps_payload.pps_4 =
+	pps_payload->pps_4 =
 		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
 		 DSC_PPS_MSB_SHIFT) |
 		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
@@ -82,7 +82,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
 
 	/* PPS 5 */
-	pps_sdp->pps_payload.bits_per_pixel_low =
+	pps_payload->bits_per_pixel_low =
 		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
 
 	/*
@@ -93,103 +93,103 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 	 */
 
 	/* PPS 6, 7 */
-	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
+	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
 
 	/* PPS 8, 9 */
-	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
+	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
 
 	/* PPS 10, 11 */
-	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
+	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
 
 	/* PPS 12, 13 */
-	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
+	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
 
 	/* PPS 14, 15 */
-	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
+	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
 
 	/* PPS 16 */
-	pps_sdp->pps_payload.initial_xmit_delay_high =
+	pps_payload->initial_xmit_delay_high =
 		((dsc_cfg->initial_xmit_delay &
 		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
 		 DSC_PPS_MSB_SHIFT);
 
 	/* PPS 17 */
-	pps_sdp->pps_payload.initial_xmit_delay_low =
+	pps_payload->initial_xmit_delay_low =
 		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
 
 	/* PPS 18, 19 */
-	pps_sdp->pps_payload.initial_dec_delay =
+	pps_payload->initial_dec_delay =
 		cpu_to_be16(dsc_cfg->initial_dec_delay);
 
 	/* PPS 20 is 0 */
 
 	/* PPS 21 */
-	pps_sdp->pps_payload.initial_scale_value =
+	pps_payload->initial_scale_value =
 		dsc_cfg->initial_scale_value;
 
 	/* PPS 22, 23 */
-	pps_sdp->pps_payload.scale_increment_interval =
+	pps_payload->scale_increment_interval =
 		cpu_to_be16(dsc_cfg->scale_increment_interval);
 
 	/* PPS 24 */
-	pps_sdp->pps_payload.scale_decrement_interval_high =
+	pps_payload->scale_decrement_interval_high =
 		((dsc_cfg->scale_decrement_interval &
 		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
 		 DSC_PPS_MSB_SHIFT);
 
 	/* PPS 25 */
-	pps_sdp->pps_payload.scale_decrement_interval_low =
+	pps_payload->scale_decrement_interval_low =
 		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
 
 	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
 
 	/* PPS 27 */
-	pps_sdp->pps_payload.first_line_bpg_offset =
+	pps_payload->first_line_bpg_offset =
 		dsc_cfg->first_line_bpg_offset;
 
 	/* PPS 28, 29 */
-	pps_sdp->pps_payload.nfl_bpg_offset =
+	pps_payload->nfl_bpg_offset =
 		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
 
 	/* PPS 30, 31 */
-	pps_sdp->pps_payload.slice_bpg_offset =
+	pps_payload->slice_bpg_offset =
 		cpu_to_be16(dsc_cfg->slice_bpg_offset);
 
 	/* PPS 32, 33 */
-	pps_sdp->pps_payload.initial_offset =
+	pps_payload->initial_offset =
 		cpu_to_be16(dsc_cfg->initial_offset);
 
 	/* PPS 34, 35 */
-	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
+	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
 
 	/* PPS 36 */
-	pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;
+	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
 
 	/* PPS 37 */
-	pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;
+	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
 
 	/* PPS 38, 39 */
-	pps_sdp->pps_payload.rc_model_size =
+	pps_payload->rc_model_size =
 		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
 
 	/* PPS 40 */
-	pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
 
 	/* PPS 41 */
-	pps_sdp->pps_payload.rc_quant_incr_limit0 =
+	pps_payload->rc_quant_incr_limit0 =
 		dsc_cfg->rc_quant_incr_limit0;
 
 	/* PPS 42 */
-	pps_sdp->pps_payload.rc_quant_incr_limit1 =
+	pps_payload->rc_quant_incr_limit1 =
 		dsc_cfg->rc_quant_incr_limit1;
 
 	/* PPS 43 */
-	pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
+	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
 		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
 
 	/* PPS 44 - 57 */
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
-		pps_sdp->pps_payload.rc_buf_thresh[i] =
+		pps_payload->rc_buf_thresh[i] =
 			dsc_cfg->rc_buf_thresh[i];
 
 	/* PPS 58 - 87 */
@@ -198,35 +198,35 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
 	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
 	 */
 	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
-		pps_sdp->pps_payload.rc_range_parameters[i] =
+		pps_payload->rc_range_parameters[i] =
 			((dsc_cfg->rc_range_params[i].range_min_qp <<
 			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
 			 (dsc_cfg->rc_range_params[i].range_max_qp <<
 			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
 			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
-		pps_sdp->pps_payload.rc_range_parameters[i] =
-			cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
+		pps_payload->rc_range_parameters[i] =
+			cpu_to_be16(pps_payload->rc_range_parameters[i]);
 	}
 
 	/* PPS 88 */
-	pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |
+	pps_payload->native_422_420 = dsc_cfg->native_422 |
 		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
 
 	/* PPS 89 */
-	pps_sdp->pps_payload.second_line_bpg_offset =
+	pps_payload->second_line_bpg_offset =
 		dsc_cfg->second_line_bpg_offset;
 
 	/* PPS 90, 91 */
-	pps_sdp->pps_payload.nsl_bpg_offset =
+	pps_payload->nsl_bpg_offset =
 		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
 
 	/* PPS 92, 93 */
-	pps_sdp->pps_payload.second_line_offset_adj =
+	pps_payload->second_line_offset_adj =
 		cpu_to_be16(dsc_cfg->second_line_offset_adj);
 
 	/* PPS 94 - 127 are O */
 }
-EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
+EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
 
 /**
  * drm_dsc_compute_rc_parameters() - Write rate control
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 7702c5c8b3f2..223c7b6c6e78 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 	drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
 
 	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
-	drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
+	drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
 
 	intel_dig_port->write_infoframe(encoder, crtc_state,
 					DP_SDP_PPS, &dp_dsc_pps_sdp,
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 4e55e37943d7..3bed1f119576 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -479,7 +479,7 @@ struct drm_dsc_pps_infoframe {
 } __packed;
 
 void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
-void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
 				const struct drm_dsc_config *dsc_cfg);
 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
 
-- 
2.17.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
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Re: [PATCH 1/3] drm/i915: Move dsc rate params compute into drm

[Wentland, Harry]

On 2019-02-13 9:45 a.m., David Francis wrote:
> The function intel_compute_rc_parameters is part of the dsc spec
> and is not driver-specific. Other drm drivers might like to use
> it.  The function is not changed; just moved and renamed.
> 
> Signed-off-by: David Francis <David.Francis@amd.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

This one also needs an RB or AB from i915 guys.

Harry

> ---
>  drivers/gpu/drm/drm_dsc.c         | 133 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_vdsc.c | 125 +---------------------------
>  include/drm/drm_dsc.h             |   1 +
>  3 files changed, 135 insertions(+), 124 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index bc2b23adb072..4b0e3c9c3ff8 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -11,6 +11,7 @@
>  #include <linux/init.h>
>  #include <linux/errno.h>
>  #include <linux/byteorder/generic.h>
> +#include <drm/drm_print.h>
>  #include <drm/drm_dp_helper.h>
>  #include <drm/drm_dsc.h>
>  
> @@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	/* PPS 94 - 127 are O */
>  }
>  EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Write rate control
> + * parameters to the dsc configuration. Some configuration
> + * fields must be present beforehand.
> + *
> + * @dsc_cfg:
> + * DSC Configuration data partially filled by driver
> + */
> +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> +{
> +	unsigned long groups_per_line = 0;
> +	unsigned long groups_total = 0;
> +	unsigned long num_extra_mux_bits = 0;
> +	unsigned long slice_bits = 0;
> +	unsigned long hrd_delay = 0;
> +	unsigned long final_scale = 0;
> +	unsigned long rbs_min = 0;
> +
> +	/* Number of groups used to code each line of a slice */
> +	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +				       DSC_RC_PIXELS_PER_GROUP);
> +
> +	/* chunksize in Bytes */
> +	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> +						  vdsc_cfg->bits_per_pixel,
> +						  (8 * 16));
> +
> +	if (vdsc_cfg->convert_rgb)
> +		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> +					  (4 * vdsc_cfg->bits_per_component + 4)
> +					  - 2);
> +	else
> +		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> +			(4 * vdsc_cfg->bits_per_component + 4) +
> +			2 * (4 * vdsc_cfg->bits_per_component) - 2;
> +	/* Number of bits in one Slice */
> +	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> +
> +	while ((num_extra_mux_bits > 0) &&
> +	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> +		num_extra_mux_bits--;
> +
> +	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> +		vdsc_cfg->initial_scale_value = groups_per_line + 8;
> +
> +	/* scale_decrement_interval calculation according to DSC spec 1.11 */
> +	if (vdsc_cfg->initial_scale_value > 8)
> +		vdsc_cfg->scale_decrement_interval = groups_per_line /
> +			(vdsc_cfg->initial_scale_value - 8);
> +	else
> +		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
> +
> +	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> +		(vdsc_cfg->initial_xmit_delay *
> +		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
> +
> +	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> +		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
> +		return -ERANGE;
> +	}
> +
> +	final_scale = (vdsc_cfg->rc_model_size * 8) /
> +		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> +	if (vdsc_cfg->slice_height > 1)
> +		/*
> +		 * NflBpgOffset is 16 bit value with 11 fractional bits
> +		 * hence we multiply by 2^11 for preserving the
> +		 * fractional part
> +		 */
> +		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
> +							(vdsc_cfg->slice_height - 1));
> +	else
> +		vdsc_cfg->nfl_bpg_offset = 0;
> +
> +	/* 2^16 - 1 */
> +	if (vdsc_cfg->nfl_bpg_offset > 65535) {
> +		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
> +		return -ERANGE;
> +	}
> +
> +	/* Number of groups used to code the entire slice */
> +	groups_total = groups_per_line * vdsc_cfg->slice_height;
> +
> +	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
> +	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
> +						    vdsc_cfg->initial_offset +
> +						    num_extra_mux_bits) << 11),
> +						  groups_total);
> +
> +	if (final_scale > 9) {
> +		/*
> +		 * ScaleIncrementInterval =
> +		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
> +		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
> +		 * we need divide by 2^11 from pstDscCfg values
> +		 */
> +		vdsc_cfg->scale_increment_interval =
> +				(vdsc_cfg->final_offset * (1 << 11)) /
> +				((vdsc_cfg->nfl_bpg_offset +
> +				vdsc_cfg->slice_bpg_offset) *
> +				(final_scale - 9));
> +	} else {
> +		/*
> +		 * If finalScaleValue is less than or equal to 9, a value of 0 should
> +		 * be used to disable the scale increment at the end of the slice
> +		 */
> +		vdsc_cfg->scale_increment_interval = 0;
> +	}
> +
> +	if (vdsc_cfg->scale_increment_interval > 65535) {
> +		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
> +		return -ERANGE;
> +	}
> +
> +	/*
> +	 * DSC spec mentions that bits_per_pixel specifies the target
> +	 * bits/pixel (bpp) rate that is used by the encoder,
> +	 * in steps of 1/16 of a bit per pixel
> +	 */
> +	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> +		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> +			     vdsc_cfg->bits_per_pixel, 16) +
> +		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> +
> +	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
> +	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> +	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index c56ba0e04044..c76cec8bfb74 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
>  	}
>  }
>  
> -static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> -{
> -	unsigned long groups_per_line = 0;
> -	unsigned long groups_total = 0;
> -	unsigned long num_extra_mux_bits = 0;
> -	unsigned long slice_bits = 0;
> -	unsigned long hrd_delay = 0;
> -	unsigned long final_scale = 0;
> -	unsigned long rbs_min = 0;
> -
> -	/* Number of groups used to code each line of a slice */
> -	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> -				       DSC_RC_PIXELS_PER_GROUP);
> -
> -	/* chunksize in Bytes */
> -	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> -						  vdsc_cfg->bits_per_pixel,
> -						  (8 * 16));
> -
> -	if (vdsc_cfg->convert_rgb)
> -		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> -					  (4 * vdsc_cfg->bits_per_component + 4)
> -					  - 2);
> -	else
> -		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> -			(4 * vdsc_cfg->bits_per_component + 4) +
> -			2 * (4 * vdsc_cfg->bits_per_component) - 2;
> -	/* Number of bits in one Slice */
> -	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> -
> -	while ((num_extra_mux_bits > 0) &&
> -	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> -		num_extra_mux_bits--;
> -
> -	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> -		vdsc_cfg->initial_scale_value = groups_per_line + 8;
> -
> -	/* scale_decrement_interval calculation according to DSC spec 1.11 */
> -	if (vdsc_cfg->initial_scale_value > 8)
> -		vdsc_cfg->scale_decrement_interval = groups_per_line /
> -			(vdsc_cfg->initial_scale_value - 8);
> -	else
> -		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
> -
> -	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> -		(vdsc_cfg->initial_xmit_delay *
> -		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
> -
> -	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> -		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
> -		return -ERANGE;
> -	}
> -
> -	final_scale = (vdsc_cfg->rc_model_size * 8) /
> -		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> -	if (vdsc_cfg->slice_height > 1)
> -		/*
> -		 * NflBpgOffset is 16 bit value with 11 fractional bits
> -		 * hence we multiply by 2^11 for preserving the
> -		 * fractional part
> -		 */
> -		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
> -							(vdsc_cfg->slice_height - 1));
> -	else
> -		vdsc_cfg->nfl_bpg_offset = 0;
> -
> -	/* 2^16 - 1 */
> -	if (vdsc_cfg->nfl_bpg_offset > 65535) {
> -		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
> -		return -ERANGE;
> -	}
> -
> -	/* Number of groups used to code the entire slice */
> -	groups_total = groups_per_line * vdsc_cfg->slice_height;
> -
> -	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
> -	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
> -						    vdsc_cfg->initial_offset +
> -						    num_extra_mux_bits) << 11),
> -						  groups_total);
> -
> -	if (final_scale > 9) {
> -		/*
> -		 * ScaleIncrementInterval =
> -		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
> -		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
> -		 * we need divide by 2^11 from pstDscCfg values
> -		 */
> -		vdsc_cfg->scale_increment_interval =
> -				(vdsc_cfg->final_offset * (1 << 11)) /
> -				((vdsc_cfg->nfl_bpg_offset +
> -				vdsc_cfg->slice_bpg_offset) *
> -				(final_scale - 9));
> -	} else {
> -		/*
> -		 * If finalScaleValue is less than or equal to 9, a value of 0 should
> -		 * be used to disable the scale increment at the end of the slice
> -		 */
> -		vdsc_cfg->scale_increment_interval = 0;
> -	}
> -
> -	if (vdsc_cfg->scale_increment_interval > 65535) {
> -		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
> -		return -ERANGE;
> -	}
> -
> -	/*
> -	 * DSC spec mentions that bits_per_pixel specifies the target
> -	 * bits/pixel (bpp) rate that is used by the encoder,
> -	 * in steps of 1/16 of a bit per pixel
> -	 */
> -	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> -		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> -			     vdsc_cfg->bits_per_pixel, 16) +
> -		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> -
> -	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
> -	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> -	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
> -
> -	return 0;
> -}
> -
>  int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config)
>  {
> @@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>  
> -	return intel_compute_rc_parameters(vdsc_cfg);
> +	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
>  
>  enum intel_display_power_domain
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index d03f1b83421a..ad43494f1cc8 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe {
>  void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
>  void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  				const struct drm_dsc_config *dsc_cfg);
> +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>  
>  #endif /* _DRM_DSC_H_ */
> 
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Re: [PATCH 2/3] drm/dsc: Add native 420 and 422 support to compute_rc_params

[Wentland, Harry]

On 2019-02-13 9:45 a.m., David Francis wrote:
> Native 420 and 422 transfer modes are new in DSC1.2
> 
> In these modes, each two pixels of a slice are treated as one
> pixel, so the slice width is half as large (round down) for
> the purposes of calucating the groups per line and chunk size
> in bytes
> 
> In native 422 mode, each pixel has four components, so the
> mux component of a group is larger by one additional mux word
> and one additional component
> 
> Now that there is native 422 support, the configuration option
> previously called enable422 is renamed to simple_422 to avoid
> confusion
> 
> Signed-off-by: David Francis <David.Francis@amd.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/drm_dsc.c         | 31 +++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_vdsc.c |  4 ++--
>  include/drm/drm_dsc.h             |  4 ++--
>  3 files changed, 27 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index 4b0e3c9c3ff8..9e675dd39a44 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -77,7 +77,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT) |
>  		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> -		dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> +		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
>  		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
>  		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>  
> @@ -246,19 +246,34 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  	unsigned long final_scale = 0;
>  	unsigned long rbs_min = 0;
>  
> -	/* Number of groups used to code each line of a slice */
> -	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> -				       DSC_RC_PIXELS_PER_GROUP);
> +	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
> +		/* Number of groups used to code each line of a slice */
> +		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
> +					       DSC_RC_PIXELS_PER_GROUP);
>  
> -	/* chunksize in Bytes */
> -	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> -						  vdsc_cfg->bits_per_pixel,
> -						  (8 * 16));
> +		/* chunksize in Bytes */
> +		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
> +							  vdsc_cfg->bits_per_pixel,
> +							  (8 * 16));
> +	} else {
> +		/* Number of groups used to code each line of a slice */
> +		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +					       DSC_RC_PIXELS_PER_GROUP);
> +
> +		/* chunksize in Bytes */
> +		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> +							  vdsc_cfg->bits_per_pixel,
> +							  (8 * 16));
> +	}
>  
>  	if (vdsc_cfg->convert_rgb)
>  		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
>  					  (4 * vdsc_cfg->bits_per_component + 4)
>  					  - 2);
> +	else if (vdsc_cfg->native_422)
> +		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
> +			(4 * vdsc_cfg->bits_per_component + 4) +
> +			3 * (4 * vdsc_cfg->bits_per_component) - 2;
>  	else
>  		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
>  			(4 * vdsc_cfg->bits_per_component + 4) +
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index c76cec8bfb74..7702c5c8b3f2 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -369,7 +369,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
>  
>  	/* Gen 11 does not support YCbCr */
> -	vdsc_cfg->enable422 = false;
> +	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
>  	vdsc_cfg->block_pred_enable =
> @@ -496,7 +496,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
>  		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> -	if (vdsc_cfg->enable422)
> +	if (vdsc_cfg->simple_422)
>  		pps_val |= DSC_422_ENABLE;
>  	if (vdsc_cfg->vbr_enable)
>  		pps_val |= DSC_VBR_ENABLE;
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index ad43494f1cc8..4e55e37943d7 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -70,10 +70,10 @@ struct drm_dsc_config {
>  	/* Slice Height */
>  	u16 slice_height;
>  	/*
> -	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> +	 * Simple 4:2:2 mode (from PPS, 4:2:2 conversion happens
>  	 * outside of DSC encode/decode algorithm)
>  	 */
> -	bool enable422;
> +	bool simple_422;
>  	/* Picture Width */
>  	u16 pic_width;
>  	/* Picture Height */
> 
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Re: [PATCH 3/3] drm/dsc: Change infoframe_pack to payload_pack

[Wentland, Harry]

On 2019-02-13 9:45 a.m., David Francis wrote:
> The function drm_dsc_pps_infoframe_pack only
> packed the payload portion of the infoframe.
> Change the input struct to the PPS payload
> to clarify the function's purpose and allow
> for drivers with their own handling of sdp.
> (e.g. drivers with their own struct for
> all SDP transactions)
> 
> Signed-off-by: David Francis <David.Francis@amd.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Again, ideally we'd want an AB from i915 guys as well.

Harry

> ---
>  drivers/gpu/drm/drm_dsc.c         | 86 +++++++++++++++----------------
>  drivers/gpu/drm/i915/intel_vdsc.c |  2 +-
>  include/drm/drm_dsc.h             |  2 +-
>  3 files changed, 45 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index 9e675dd39a44..4ada4d4f59ac 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -38,42 +38,42 @@ void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
>  EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
>  
>  /**
> - * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> + * drm_dsc_pps_payload_pack() - Populates the DSC PPS payload
>   * using the DSC configuration parameters in the order expected
>   * by the DSC Display Sink device. For the DSC, the sink device
>   * expects the PPS payload in the big endian format for the fields
>   * that span more than 1 byte.
>   *
> - * @pps_sdp:
> - * Secondary data packet for DSC Picture Parameter Set
> + * @pps_payload:
> + * DSC Picture Parameter Set
>   * @dsc_cfg:
>   * DSC Configuration data filled by driver
>   */
> -void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>  				const struct drm_dsc_config *dsc_cfg)
>  {
>  	int i;
>  
>  	/* Protect against someone accidently changing struct size */
> -	BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
> +	BUILD_BUG_ON(sizeof(*pps_payload) !=
>  		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
>  
> -	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> +	memset(pps_payload, 0, sizeof(*pps_payload));
>  
>  	/* PPS 0 */
> -	pps_sdp->pps_payload.dsc_version =
> +	pps_payload->dsc_version =
>  		dsc_cfg->dsc_version_minor |
>  		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
>  
>  	/* PPS 1, 2 is 0 */
>  
>  	/* PPS 3 */
> -	pps_sdp->pps_payload.pps_3 =
> +	pps_payload->pps_3 =
>  		dsc_cfg->line_buf_depth |
>  		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
>  
>  	/* PPS 4 */
> -	pps_sdp->pps_payload.pps_4 =
> +	pps_payload->pps_4 =
>  		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT) |
>  		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> @@ -82,7 +82,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>  
>  	/* PPS 5 */
> -	pps_sdp->pps_payload.bits_per_pixel_low =
> +	pps_payload->bits_per_pixel_low =
>  		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
>  
>  	/*
> @@ -93,103 +93,103 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	 */
>  
>  	/* PPS 6, 7 */
> -	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
> +	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
>  
>  	/* PPS 8, 9 */
> -	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
> +	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
>  
>  	/* PPS 10, 11 */
> -	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
> +	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
>  
>  	/* PPS 12, 13 */
> -	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
> +	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
>  
>  	/* PPS 14, 15 */
> -	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
> +	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
>  
>  	/* PPS 16 */
> -	pps_sdp->pps_payload.initial_xmit_delay_high =
> +	pps_payload->initial_xmit_delay_high =
>  		((dsc_cfg->initial_xmit_delay &
>  		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT);
>  
>  	/* PPS 17 */
> -	pps_sdp->pps_payload.initial_xmit_delay_low =
> +	pps_payload->initial_xmit_delay_low =
>  		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
>  
>  	/* PPS 18, 19 */
> -	pps_sdp->pps_payload.initial_dec_delay =
> +	pps_payload->initial_dec_delay =
>  		cpu_to_be16(dsc_cfg->initial_dec_delay);
>  
>  	/* PPS 20 is 0 */
>  
>  	/* PPS 21 */
> -	pps_sdp->pps_payload.initial_scale_value =
> +	pps_payload->initial_scale_value =
>  		dsc_cfg->initial_scale_value;
>  
>  	/* PPS 22, 23 */
> -	pps_sdp->pps_payload.scale_increment_interval =
> +	pps_payload->scale_increment_interval =
>  		cpu_to_be16(dsc_cfg->scale_increment_interval);
>  
>  	/* PPS 24 */
> -	pps_sdp->pps_payload.scale_decrement_interval_high =
> +	pps_payload->scale_decrement_interval_high =
>  		((dsc_cfg->scale_decrement_interval &
>  		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT);
>  
>  	/* PPS 25 */
> -	pps_sdp->pps_payload.scale_decrement_interval_low =
> +	pps_payload->scale_decrement_interval_low =
>  		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
>  
>  	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
>  
>  	/* PPS 27 */
> -	pps_sdp->pps_payload.first_line_bpg_offset =
> +	pps_payload->first_line_bpg_offset =
>  		dsc_cfg->first_line_bpg_offset;
>  
>  	/* PPS 28, 29 */
> -	pps_sdp->pps_payload.nfl_bpg_offset =
> +	pps_payload->nfl_bpg_offset =
>  		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
>  
>  	/* PPS 30, 31 */
> -	pps_sdp->pps_payload.slice_bpg_offset =
> +	pps_payload->slice_bpg_offset =
>  		cpu_to_be16(dsc_cfg->slice_bpg_offset);
>  
>  	/* PPS 32, 33 */
> -	pps_sdp->pps_payload.initial_offset =
> +	pps_payload->initial_offset =
>  		cpu_to_be16(dsc_cfg->initial_offset);
>  
>  	/* PPS 34, 35 */
> -	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
> +	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
>  
>  	/* PPS 36 */
> -	pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;
> +	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
>  
>  	/* PPS 37 */
> -	pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;
> +	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
>  
>  	/* PPS 38, 39 */
> -	pps_sdp->pps_payload.rc_model_size =
> +	pps_payload->rc_model_size =
>  		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
>  
>  	/* PPS 40 */
> -	pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
> +	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
>  
>  	/* PPS 41 */
> -	pps_sdp->pps_payload.rc_quant_incr_limit0 =
> +	pps_payload->rc_quant_incr_limit0 =
>  		dsc_cfg->rc_quant_incr_limit0;
>  
>  	/* PPS 42 */
> -	pps_sdp->pps_payload.rc_quant_incr_limit1 =
> +	pps_payload->rc_quant_incr_limit1 =
>  		dsc_cfg->rc_quant_incr_limit1;
>  
>  	/* PPS 43 */
> -	pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
> +	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
>  		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
>  
>  	/* PPS 44 - 57 */
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
> -		pps_sdp->pps_payload.rc_buf_thresh[i] =
> +		pps_payload->rc_buf_thresh[i] =
>  			dsc_cfg->rc_buf_thresh[i];
>  
>  	/* PPS 58 - 87 */
> @@ -198,35 +198,35 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
>  	 */
>  	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> -		pps_sdp->pps_payload.rc_range_parameters[i] =
> +		pps_payload->rc_range_parameters[i] =
>  			((dsc_cfg->rc_range_params[i].range_min_qp <<
>  			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
>  			 (dsc_cfg->rc_range_params[i].range_max_qp <<
>  			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
>  			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
> -		pps_sdp->pps_payload.rc_range_parameters[i] =
> -			cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
> +		pps_payload->rc_range_parameters[i] =
> +			cpu_to_be16(pps_payload->rc_range_parameters[i]);
>  	}
>  
>  	/* PPS 88 */
> -	pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |
> +	pps_payload->native_422_420 = dsc_cfg->native_422 |
>  		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
>  
>  	/* PPS 89 */
> -	pps_sdp->pps_payload.second_line_bpg_offset =
> +	pps_payload->second_line_bpg_offset =
>  		dsc_cfg->second_line_bpg_offset;
>  
>  	/* PPS 90, 91 */
> -	pps_sdp->pps_payload.nsl_bpg_offset =
> +	pps_payload->nsl_bpg_offset =
>  		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
>  
>  	/* PPS 92, 93 */
> -	pps_sdp->pps_payload.second_line_offset_adj =
> +	pps_payload->second_line_offset_adj =
>  		cpu_to_be16(dsc_cfg->second_line_offset_adj);
>  
>  	/* PPS 94 - 127 are O */
>  }
> -EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> +EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>  
>  /**
>   * drm_dsc_compute_rc_parameters() - Write rate control
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 7702c5c8b3f2..223c7b6c6e78 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
>  	drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
>  
>  	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
> -	drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
> +	drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
>  
>  	intel_dig_port->write_infoframe(encoder, crtc_state,
>  					DP_SDP_PPS, &dp_dsc_pps_sdp,
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index 4e55e37943d7..3bed1f119576 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -479,7 +479,7 @@ struct drm_dsc_pps_infoframe {
>  } __packed;
>  
>  void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
> -void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>  				const struct drm_dsc_config *dsc_cfg);
>  int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>  
> 
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✗ Fi.CI.BAT: failure for Make DRM DSC helpers more generally usable

[Patchwork]

== Series Details ==

Series: Make DRM DSC helpers more generally usable
URL   : https://patchwork.freedesktop.org/series/56608/
State : failure

== Summary ==

Applying: drm/i915: Move dsc rate params compute into drm
Applying: drm/dsc: Add native 420 and 422 support to compute_rc_params
error: sha1 information is lacking or useless (drivers/gpu/drm/drm_dsc.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/dsc: Add native 420 and 422 support to compute_rc_params
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH 1/3] drm/i915: Move dsc rate params compute into drm

[Manasi Navare]

On Wed, Feb 13, 2019 at 09:45:34AM -0500, David Francis wrote:
> The function intel_compute_rc_parameters is part of the dsc spec
> and is not driver-specific. Other drm drivers might like to use
> it.  The function is not changed; just moved and renamed.
>

Yes this sounds fair since its DSC spec related and can move to drm_dsc.c.
As a part of this series or later you should also consider moving the
rc_parameters struct for input bpc/output BPP combinations to DRM since that
is also purely spec related.

With this change and compute_rc_params function in DRM, please add appropriate
description of the function as part of kernel documentation.

With the documentation change, you have my r-b.

Regards
Manasi
 
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>  drivers/gpu/drm/drm_dsc.c         | 133 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_vdsc.c | 125 +---------------------------
>  include/drm/drm_dsc.h             |   1 +
>  3 files changed, 135 insertions(+), 124 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index bc2b23adb072..4b0e3c9c3ff8 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -11,6 +11,7 @@
>  #include <linux/init.h>
>  #include <linux/errno.h>
>  #include <linux/byteorder/generic.h>
> +#include <drm/drm_print.h>
>  #include <drm/drm_dp_helper.h>
>  #include <drm/drm_dsc.h>
>  
> @@ -226,3 +227,135 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	/* PPS 94 - 127 are O */
>  }
>  EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Write rate control
> + * parameters to the dsc configuration. Some configuration
> + * fields must be present beforehand.
> + *
> + * @dsc_cfg:
> + * DSC Configuration data partially filled by driver
> + */
> +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> +{
> +	unsigned long groups_per_line = 0;
> +	unsigned long groups_total = 0;
> +	unsigned long num_extra_mux_bits = 0;
> +	unsigned long slice_bits = 0;
> +	unsigned long hrd_delay = 0;
> +	unsigned long final_scale = 0;
> +	unsigned long rbs_min = 0;
> +
> +	/* Number of groups used to code each line of a slice */
> +	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +				       DSC_RC_PIXELS_PER_GROUP);
> +
> +	/* chunksize in Bytes */
> +	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> +						  vdsc_cfg->bits_per_pixel,
> +						  (8 * 16));
> +
> +	if (vdsc_cfg->convert_rgb)
> +		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> +					  (4 * vdsc_cfg->bits_per_component + 4)
> +					  - 2);
> +	else
> +		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> +			(4 * vdsc_cfg->bits_per_component + 4) +
> +			2 * (4 * vdsc_cfg->bits_per_component) - 2;
> +	/* Number of bits in one Slice */
> +	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> +
> +	while ((num_extra_mux_bits > 0) &&
> +	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> +		num_extra_mux_bits--;
> +
> +	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> +		vdsc_cfg->initial_scale_value = groups_per_line + 8;
> +
> +	/* scale_decrement_interval calculation according to DSC spec 1.11 */
> +	if (vdsc_cfg->initial_scale_value > 8)
> +		vdsc_cfg->scale_decrement_interval = groups_per_line /
> +			(vdsc_cfg->initial_scale_value - 8);
> +	else
> +		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
> +
> +	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> +		(vdsc_cfg->initial_xmit_delay *
> +		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
> +
> +	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> +		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
> +		return -ERANGE;
> +	}
> +
> +	final_scale = (vdsc_cfg->rc_model_size * 8) /
> +		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> +	if (vdsc_cfg->slice_height > 1)
> +		/*
> +		 * NflBpgOffset is 16 bit value with 11 fractional bits
> +		 * hence we multiply by 2^11 for preserving the
> +		 * fractional part
> +		 */
> +		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
> +							(vdsc_cfg->slice_height - 1));
> +	else
> +		vdsc_cfg->nfl_bpg_offset = 0;
> +
> +	/* 2^16 - 1 */
> +	if (vdsc_cfg->nfl_bpg_offset > 65535) {
> +		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
> +		return -ERANGE;
> +	}
> +
> +	/* Number of groups used to code the entire slice */
> +	groups_total = groups_per_line * vdsc_cfg->slice_height;
> +
> +	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
> +	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
> +						    vdsc_cfg->initial_offset +
> +						    num_extra_mux_bits) << 11),
> +						  groups_total);
> +
> +	if (final_scale > 9) {
> +		/*
> +		 * ScaleIncrementInterval =
> +		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
> +		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
> +		 * we need divide by 2^11 from pstDscCfg values
> +		 */
> +		vdsc_cfg->scale_increment_interval =
> +				(vdsc_cfg->final_offset * (1 << 11)) /
> +				((vdsc_cfg->nfl_bpg_offset +
> +				vdsc_cfg->slice_bpg_offset) *
> +				(final_scale - 9));
> +	} else {
> +		/*
> +		 * If finalScaleValue is less than or equal to 9, a value of 0 should
> +		 * be used to disable the scale increment at the end of the slice
> +		 */
> +		vdsc_cfg->scale_increment_interval = 0;
> +	}
> +
> +	if (vdsc_cfg->scale_increment_interval > 65535) {
> +		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
> +		return -ERANGE;
> +	}
> +
> +	/*
> +	 * DSC spec mentions that bits_per_pixel specifies the target
> +	 * bits/pixel (bpp) rate that is used by the encoder,
> +	 * in steps of 1/16 of a bit per pixel
> +	 */
> +	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> +		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> +			     vdsc_cfg->bits_per_pixel, 16) +
> +		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> +
> +	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
> +	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> +	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index c56ba0e04044..c76cec8bfb74 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -318,129 +318,6 @@ static int get_column_index_for_rc_params(u8 bits_per_component)
>  	}
>  }
>  
> -static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
> -{
> -	unsigned long groups_per_line = 0;
> -	unsigned long groups_total = 0;
> -	unsigned long num_extra_mux_bits = 0;
> -	unsigned long slice_bits = 0;
> -	unsigned long hrd_delay = 0;
> -	unsigned long final_scale = 0;
> -	unsigned long rbs_min = 0;
> -
> -	/* Number of groups used to code each line of a slice */
> -	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> -				       DSC_RC_PIXELS_PER_GROUP);
> -
> -	/* chunksize in Bytes */
> -	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> -						  vdsc_cfg->bits_per_pixel,
> -						  (8 * 16));
> -
> -	if (vdsc_cfg->convert_rgb)
> -		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
> -					  (4 * vdsc_cfg->bits_per_component + 4)
> -					  - 2);
> -	else
> -		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
> -			(4 * vdsc_cfg->bits_per_component + 4) +
> -			2 * (4 * vdsc_cfg->bits_per_component) - 2;
> -	/* Number of bits in one Slice */
> -	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
> -
> -	while ((num_extra_mux_bits > 0) &&
> -	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
> -		num_extra_mux_bits--;
> -
> -	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
> -		vdsc_cfg->initial_scale_value = groups_per_line + 8;
> -
> -	/* scale_decrement_interval calculation according to DSC spec 1.11 */
> -	if (vdsc_cfg->initial_scale_value > 8)
> -		vdsc_cfg->scale_decrement_interval = groups_per_line /
> -			(vdsc_cfg->initial_scale_value - 8);
> -	else
> -		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
> -
> -	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
> -		(vdsc_cfg->initial_xmit_delay *
> -		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
> -
> -	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
> -		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
> -		return -ERANGE;
> -	}
> -
> -	final_scale = (vdsc_cfg->rc_model_size * 8) /
> -		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
> -	if (vdsc_cfg->slice_height > 1)
> -		/*
> -		 * NflBpgOffset is 16 bit value with 11 fractional bits
> -		 * hence we multiply by 2^11 for preserving the
> -		 * fractional part
> -		 */
> -		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
> -							(vdsc_cfg->slice_height - 1));
> -	else
> -		vdsc_cfg->nfl_bpg_offset = 0;
> -
> -	/* 2^16 - 1 */
> -	if (vdsc_cfg->nfl_bpg_offset > 65535) {
> -		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
> -		return -ERANGE;
> -	}
> -
> -	/* Number of groups used to code the entire slice */
> -	groups_total = groups_per_line * vdsc_cfg->slice_height;
> -
> -	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
> -	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
> -						    vdsc_cfg->initial_offset +
> -						    num_extra_mux_bits) << 11),
> -						  groups_total);
> -
> -	if (final_scale > 9) {
> -		/*
> -		 * ScaleIncrementInterval =
> -		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
> -		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
> -		 * we need divide by 2^11 from pstDscCfg values
> -		 */
> -		vdsc_cfg->scale_increment_interval =
> -				(vdsc_cfg->final_offset * (1 << 11)) /
> -				((vdsc_cfg->nfl_bpg_offset +
> -				vdsc_cfg->slice_bpg_offset) *
> -				(final_scale - 9));
> -	} else {
> -		/*
> -		 * If finalScaleValue is less than or equal to 9, a value of 0 should
> -		 * be used to disable the scale increment at the end of the slice
> -		 */
> -		vdsc_cfg->scale_increment_interval = 0;
> -	}
> -
> -	if (vdsc_cfg->scale_increment_interval > 65535) {
> -		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
> -		return -ERANGE;
> -	}
> -
> -	/*
> -	 * DSC spec mentions that bits_per_pixel specifies the target
> -	 * bits/pixel (bpp) rate that is used by the encoder,
> -	 * in steps of 1/16 of a bit per pixel
> -	 */
> -	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
> -		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
> -			     vdsc_cfg->bits_per_pixel, 16) +
> -		groups_per_line * vdsc_cfg->first_line_bpg_offset;
> -
> -	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
> -	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
> -	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
> -
> -	return 0;
> -}
> -
>  int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config)
>  {
> @@ -575,7 +452,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>  
> -	return intel_compute_rc_parameters(vdsc_cfg);
> +	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
>  
>  enum intel_display_power_domain
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index d03f1b83421a..ad43494f1cc8 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -481,5 +481,6 @@ struct drm_dsc_pps_infoframe {
>  void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
>  void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  				const struct drm_dsc_config *dsc_cfg);
> +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>  
>  #endif /* _DRM_DSC_H_ */
> -- 
> 2.17.1
> 
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Re: [PATCH 2/3] drm/dsc: Add native 420 and 422 support to compute_rc_params

[Manasi Navare via amd-gfx]

On Wed, Feb 13, 2019 at 09:45:35AM -0500, David Francis wrote:
> Native 420 and 422 transfer modes are new in DSC1.2
> 
> In these modes, each two pixels of a slice are treated as one
> pixel, so the slice width is half as large (round down) for
> the purposes of calucating the groups per line and chunk size
> in bytes
> 
> In native 422 mode, each pixel has four components, so the
> mux component of a group is larger by one additional mux word
> and one additional component
> 
> Now that there is native 422 support, the configuration option
> previously called enable422 is renamed to simple_422 to avoid
> confusion
> 
> Signed-off-by: David Francis <David.Francis@amd.com>

This looks good and verified that the DSC 1.2 spec actually renames it
as simple_422.

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/drm_dsc.c         | 31 +++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_vdsc.c |  4 ++--
>  include/drm/drm_dsc.h             |  4 ++--
>  3 files changed, 27 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index 4b0e3c9c3ff8..9e675dd39a44 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -77,7 +77,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT) |
>  		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> -		dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> +		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
>  		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
>  		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>  
> @@ -246,19 +246,34 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>  	unsigned long final_scale = 0;
>  	unsigned long rbs_min = 0;
>  
> -	/* Number of groups used to code each line of a slice */
> -	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> -				       DSC_RC_PIXELS_PER_GROUP);
> +	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
> +		/* Number of groups used to code each line of a slice */
> +		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
> +					       DSC_RC_PIXELS_PER_GROUP);
>  
> -	/* chunksize in Bytes */
> -	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> -						  vdsc_cfg->bits_per_pixel,
> -						  (8 * 16));
> +		/* chunksize in Bytes */
> +		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
> +							  vdsc_cfg->bits_per_pixel,
> +							  (8 * 16));
> +	} else {
> +		/* Number of groups used to code each line of a slice */
> +		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
> +					       DSC_RC_PIXELS_PER_GROUP);
> +
> +		/* chunksize in Bytes */
> +		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
> +							  vdsc_cfg->bits_per_pixel,
> +							  (8 * 16));
> +	}
>  
>  	if (vdsc_cfg->convert_rgb)
>  		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
>  					  (4 * vdsc_cfg->bits_per_component + 4)
>  					  - 2);
> +	else if (vdsc_cfg->native_422)
> +		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
> +			(4 * vdsc_cfg->bits_per_component + 4) +
> +			3 * (4 * vdsc_cfg->bits_per_component) - 2;
>  	else
>  		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
>  			(4 * vdsc_cfg->bits_per_component + 4) +
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index c76cec8bfb74..7702c5c8b3f2 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -369,7 +369,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
>  
>  	/* Gen 11 does not support YCbCr */
> -	vdsc_cfg->enable422 = false;
> +	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
>  	vdsc_cfg->block_pred_enable =
> @@ -496,7 +496,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
>  		pps_val |= DSC_COLOR_SPACE_CONVERSION;
> -	if (vdsc_cfg->enable422)
> +	if (vdsc_cfg->simple_422)
>  		pps_val |= DSC_422_ENABLE;
>  	if (vdsc_cfg->vbr_enable)
>  		pps_val |= DSC_VBR_ENABLE;
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index ad43494f1cc8..4e55e37943d7 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -70,10 +70,10 @@ struct drm_dsc_config {
>  	/* Slice Height */
>  	u16 slice_height;
>  	/*
> -	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> +	 * Simple 4:2:2 mode (from PPS, 4:2:2 conversion happens
>  	 * outside of DSC encode/decode algorithm)
>  	 */
> -	bool enable422;
> +	bool simple_422;
>  	/* Picture Width */
>  	u16 pic_width;
>  	/* Picture Height */
> -- 
> 2.17.1
> 
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Re: [PATCH 3/3] drm/dsc: Change infoframe_pack to payload_pack

[Manasi Navare via amd-gfx]

On Wed, Feb 13, 2019 at 09:45:36AM -0500, David Francis wrote:
> The function drm_dsc_pps_infoframe_pack only
> packed the payload portion of the infoframe.
> Change the input struct to the PPS payload
> to clarify the function's purpose and allow
> for drivers with their own handling of sdp.
> (e.g. drivers with their own struct for
> all SDP transactions)
>

I think if we are just sending pps_payload as an argument to this function
to pack payload, it also makes sense to just send pps_header as an input
to drm_dsc_dp_pps_header_init() to follow the consistency there.
So with that the caller will have to call the header_init first , initialize the
sdp header and then call the _payload_pack to pack the payload bytes.
And then send the entire infoframe to the sink.

Could you please also make that change in this patch?

Regards
Manasi
 
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>  drivers/gpu/drm/drm_dsc.c         | 86 +++++++++++++++----------------
>  drivers/gpu/drm/i915/intel_vdsc.c |  2 +-
>  include/drm/drm_dsc.h             |  2 +-
>  3 files changed, 45 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> index 9e675dd39a44..4ada4d4f59ac 100644
> --- a/drivers/gpu/drm/drm_dsc.c
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -38,42 +38,42 @@ void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
>  EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
>  
>  /**
> - * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> + * drm_dsc_pps_payload_pack() - Populates the DSC PPS payload
>   * using the DSC configuration parameters in the order expected
>   * by the DSC Display Sink device. For the DSC, the sink device
>   * expects the PPS payload in the big endian format for the fields
>   * that span more than 1 byte.
>   *
> - * @pps_sdp:
> - * Secondary data packet for DSC Picture Parameter Set
> + * @pps_payload:
> + * DSC Picture Parameter Set
>   * @dsc_cfg:
>   * DSC Configuration data filled by driver
>   */
> -void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>  				const struct drm_dsc_config *dsc_cfg)
>  {
>  	int i;
>  
>  	/* Protect against someone accidently changing struct size */
> -	BUILD_BUG_ON(sizeof(pps_sdp->pps_payload) !=
> +	BUILD_BUG_ON(sizeof(*pps_payload) !=
>  		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
>  
> -	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> +	memset(pps_payload, 0, sizeof(*pps_payload));
>  
>  	/* PPS 0 */
> -	pps_sdp->pps_payload.dsc_version =
> +	pps_payload->dsc_version =
>  		dsc_cfg->dsc_version_minor |
>  		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
>  
>  	/* PPS 1, 2 is 0 */
>  
>  	/* PPS 3 */
> -	pps_sdp->pps_payload.pps_3 =
> +	pps_payload->pps_3 =
>  		dsc_cfg->line_buf_depth |
>  		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
>  
>  	/* PPS 4 */
> -	pps_sdp->pps_payload.pps_4 =
> +	pps_payload->pps_4 =
>  		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT) |
>  		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> @@ -82,7 +82,7 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>  
>  	/* PPS 5 */
> -	pps_sdp->pps_payload.bits_per_pixel_low =
> +	pps_payload->bits_per_pixel_low =
>  		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
>  
>  	/*
> @@ -93,103 +93,103 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	 */
>  
>  	/* PPS 6, 7 */
> -	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
> +	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
>  
>  	/* PPS 8, 9 */
> -	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
> +	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
>  
>  	/* PPS 10, 11 */
> -	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
> +	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
>  
>  	/* PPS 12, 13 */
> -	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
> +	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
>  
>  	/* PPS 14, 15 */
> -	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
> +	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
>  
>  	/* PPS 16 */
> -	pps_sdp->pps_payload.initial_xmit_delay_high =
> +	pps_payload->initial_xmit_delay_high =
>  		((dsc_cfg->initial_xmit_delay &
>  		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT);
>  
>  	/* PPS 17 */
> -	pps_sdp->pps_payload.initial_xmit_delay_low =
> +	pps_payload->initial_xmit_delay_low =
>  		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
>  
>  	/* PPS 18, 19 */
> -	pps_sdp->pps_payload.initial_dec_delay =
> +	pps_payload->initial_dec_delay =
>  		cpu_to_be16(dsc_cfg->initial_dec_delay);
>  
>  	/* PPS 20 is 0 */
>  
>  	/* PPS 21 */
> -	pps_sdp->pps_payload.initial_scale_value =
> +	pps_payload->initial_scale_value =
>  		dsc_cfg->initial_scale_value;
>  
>  	/* PPS 22, 23 */
> -	pps_sdp->pps_payload.scale_increment_interval =
> +	pps_payload->scale_increment_interval =
>  		cpu_to_be16(dsc_cfg->scale_increment_interval);
>  
>  	/* PPS 24 */
> -	pps_sdp->pps_payload.scale_decrement_interval_high =
> +	pps_payload->scale_decrement_interval_high =
>  		((dsc_cfg->scale_decrement_interval &
>  		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
>  		 DSC_PPS_MSB_SHIFT);
>  
>  	/* PPS 25 */
> -	pps_sdp->pps_payload.scale_decrement_interval_low =
> +	pps_payload->scale_decrement_interval_low =
>  		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
>  
>  	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
>  
>  	/* PPS 27 */
> -	pps_sdp->pps_payload.first_line_bpg_offset =
> +	pps_payload->first_line_bpg_offset =
>  		dsc_cfg->first_line_bpg_offset;
>  
>  	/* PPS 28, 29 */
> -	pps_sdp->pps_payload.nfl_bpg_offset =
> +	pps_payload->nfl_bpg_offset =
>  		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
>  
>  	/* PPS 30, 31 */
> -	pps_sdp->pps_payload.slice_bpg_offset =
> +	pps_payload->slice_bpg_offset =
>  		cpu_to_be16(dsc_cfg->slice_bpg_offset);
>  
>  	/* PPS 32, 33 */
> -	pps_sdp->pps_payload.initial_offset =
> +	pps_payload->initial_offset =
>  		cpu_to_be16(dsc_cfg->initial_offset);
>  
>  	/* PPS 34, 35 */
> -	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
> +	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
>  
>  	/* PPS 36 */
> -	pps_sdp->pps_payload.flatness_min_qp = dsc_cfg->flatness_min_qp;
> +	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
>  
>  	/* PPS 37 */
> -	pps_sdp->pps_payload.flatness_max_qp = dsc_cfg->flatness_max_qp;
> +	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
>  
>  	/* PPS 38, 39 */
> -	pps_sdp->pps_payload.rc_model_size =
> +	pps_payload->rc_model_size =
>  		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
>  
>  	/* PPS 40 */
> -	pps_sdp->pps_payload.rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
> +	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
>  
>  	/* PPS 41 */
> -	pps_sdp->pps_payload.rc_quant_incr_limit0 =
> +	pps_payload->rc_quant_incr_limit0 =
>  		dsc_cfg->rc_quant_incr_limit0;
>  
>  	/* PPS 42 */
> -	pps_sdp->pps_payload.rc_quant_incr_limit1 =
> +	pps_payload->rc_quant_incr_limit1 =
>  		dsc_cfg->rc_quant_incr_limit1;
>  
>  	/* PPS 43 */
> -	pps_sdp->pps_payload.rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
> +	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
>  		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
>  
>  	/* PPS 44 - 57 */
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
> -		pps_sdp->pps_payload.rc_buf_thresh[i] =
> +		pps_payload->rc_buf_thresh[i] =
>  			dsc_cfg->rc_buf_thresh[i];
>  
>  	/* PPS 58 - 87 */
> @@ -198,35 +198,35 @@ void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
>  	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
>  	 */
>  	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> -		pps_sdp->pps_payload.rc_range_parameters[i] =
> +		pps_payload->rc_range_parameters[i] =
>  			((dsc_cfg->rc_range_params[i].range_min_qp <<
>  			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
>  			 (dsc_cfg->rc_range_params[i].range_max_qp <<
>  			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
>  			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
> -		pps_sdp->pps_payload.rc_range_parameters[i] =
> -			cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
> +		pps_payload->rc_range_parameters[i] =
> +			cpu_to_be16(pps_payload->rc_range_parameters[i]);
>  	}
>  
>  	/* PPS 88 */
> -	pps_sdp->pps_payload.native_422_420 = dsc_cfg->native_422 |
> +	pps_payload->native_422_420 = dsc_cfg->native_422 |
>  		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
>  
>  	/* PPS 89 */
> -	pps_sdp->pps_payload.second_line_bpg_offset =
> +	pps_payload->second_line_bpg_offset =
>  		dsc_cfg->second_line_bpg_offset;
>  
>  	/* PPS 90, 91 */
> -	pps_sdp->pps_payload.nsl_bpg_offset =
> +	pps_payload->nsl_bpg_offset =
>  		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
>  
>  	/* PPS 92, 93 */
> -	pps_sdp->pps_payload.second_line_offset_adj =
> +	pps_payload->second_line_offset_adj =
>  		cpu_to_be16(dsc_cfg->second_line_offset_adj);
>  
>  	/* PPS 94 - 127 are O */
>  }
> -EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> +EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>  
>  /**
>   * drm_dsc_compute_rc_parameters() - Write rate control
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 7702c5c8b3f2..223c7b6c6e78 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -885,7 +885,7 @@ static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
>  	drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
>  
>  	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
> -	drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
> +	drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
>  
>  	intel_dig_port->write_infoframe(encoder, crtc_state,
>  					DP_SDP_PPS, &dp_dsc_pps_sdp,
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index 4e55e37943d7..3bed1f119576 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -479,7 +479,7 @@ struct drm_dsc_pps_infoframe {
>  } __packed;
>  
>  void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
> -void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>  				const struct drm_dsc_config *dsc_cfg);
>  int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>  
> -- 
> 2.17.1
> 
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Move dsc rate params compute into drm

[kbuild test robot via dri-devel]

[-- Attachment #1: Type: text/plain, Size: 23486 bytes --]

Hi David,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.0-rc4 next-20190213]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/David-Francis/Make-DRM-DSC-helpers-more-generally-usable/20190214-052541
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info'
   net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info'
   kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf'
   include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf'
   include/linux/dma-fence-array.h:54: warning: Function parameter or member 'work' not described in 'dma_fence_array'
   include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found
   include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip'
   include/linux/iio/hw-consumer.h:1: warning: no structured comments found
   include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry'
   drivers/mtd/nand/raw/nand_base.c:420: warning: Function parameter or member 'chip' not described in 'nand_fill_oob'
   drivers/mtd/nand/raw/nand_bbt.c:173: warning: Function parameter or member 'this' not described in 'read_bbt'
   drivers/mtd/nand/raw/nand_bbt.c:173: warning: Excess function parameter 'chip' description in 'read_bbt'
   include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints'
   include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops'
   arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb'
   arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb'
   arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb'
   arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb'
   arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb'
   drivers/slimbus/stream.c:1: warning: no structured comments found
   include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device'
   drivers/target/target_core_device.c:1: warning: no structured comments found
   drivers/usb/typec/bus.c:1: warning: no structured comments found
   drivers/usb/typec/class.c:1: warning: no structured comments found
   include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family'
   fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete'
   fs/file_table.c:1: warning: no structured comments found
   fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end'
   fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode'
   fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode'
   fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:183: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:382: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:383: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_leaf'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_leaf'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_leaf'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'end' not described in 'for_each_amdgpu_vm_pt_leaf'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:555: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_leaf'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:603: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:845: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1350: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_func'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1517: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_huge'
   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3093: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:128: warning: Incorrect use of kernel-doc format: Documentation Makefile include scripts source @atomic_obj
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj_lock' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager'
   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: no structured comments found
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_pin' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_unpin' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_res_obj' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_get_sg_table' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_import_sg_table' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_vmap' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_vunmap' not described in 'drm_driver'
   include/drm/drm_drv.h:618: warning: Function parameter or member 'gem_prime_mmap' not described in 'drm_driver'
   include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found
   drivers/gpu/drm/drm_dp_helper.c:1364: warning: Function parameter or member 'dsc_dpcd' not described in 'drm_dp_dsc_sink_max_slice_count'
   drivers/gpu/drm/drm_dp_helper.c:1364: warning: Function parameter or member 'is_edp' not described in 'drm_dp_dsc_sink_max_slice_count'
   drivers/gpu/drm/drm_dsc.c:240: warning: Excess function parameter 'dsc_cfg' description in 'drm_dsc_compute_rc_parameters'
>> drivers/gpu/drm/drm_dsc.c:241: warning: Function parameter or member 'vdsc_cfg' not described in 'drm_dsc_compute_rc_parameters'
   drivers/gpu/drm/drm_dsc.c:241: warning: Excess function parameter 'dsc_cfg' description in 'drm_dsc_compute_rc_parameters'
   drivers/gpu/drm/i915/i915_vma.h:49: warning: cannot understand function prototype: 'struct i915_vma '
   drivers/gpu/drm/i915/i915_vma.h:1: warning: no structured comments found
   drivers/gpu/drm/i915/intel_guc_fwif.h:536: warning: cannot understand function prototype: 'struct guc_log_buffer_state '
   drivers/gpu/drm/i915/i915_trace.h:1: warning: no structured comments found
   include/linux/skbuff.h:876: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'list' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'head_frag' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'encapsulation' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'csum_valid' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'vlan_present' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'csum_level' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff'
   include/linux/skbuff.h:876: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff'
   include/net/sock.h:238: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_portpair' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_cookie' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_listener' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common'
   include/net/sock.h:238: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common'
   include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.rmem_alloc' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.len' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.head' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.tail' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_wq_raw' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock'
   include/net/sock.h:513: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'adj_list.upper' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'adj_list.lower' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'gso_partial_features' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'switchdev_ops' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'name_assign_type' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'mpls_ptr' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'xdp_prog' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'qdisc_hash' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device'
   include/linux/netdevice.h:2048: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device'
   include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state'
   include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state'
   Documentation/admin-guide/cgroup-v2.rst:1509: WARNING: Block quote ends without a blank line; unexpected unindent.
   Documentation/admin-guide/cgroup-v2.rst:1511: WARNING: Block quote ends without a blank line; unexpected unindent.
   Documentation/admin-guide/cgroup-v2.rst:1512: WARNING: Block quote ends without a blank line; unexpected unindent.
   include/linux/interrupt.h:252: WARNING: Inline emphasis start-string without end-string.
   include/net/mac80211.h:1214: ERROR: Unexpected indentation.
   include/net/mac80211.h:1221: WARNING: Block quote ends without a blank line; unexpected unindent.
   include/linux/wait.h:110: WARNING: Block quote ends without a blank line; unexpected unindent.
   include/linux/wait.h:113: ERROR: Unexpected indentation.
   include/linux/wait.h:115: WARNING: Block quote ends without a blank line; unexpected unindent.
   kernel/time/hrtimer.c:1120: WARNING: Block quote ends without a blank line; unexpected unindent.
   kernel/signal.c:344: WARNING: Inline literal start-string without end-string.
   include/linux/kernel.h:137: WARNING: Inline interpreted text or phrase reference start-string without end-string.
   Documentation/driver-api/dmaengine/dmatest.rst:63: ERROR: Unexpected indentation.
   include/uapi/linux/firewire-cdev.h:312: WARNING: Inline literal start-string without end-string.
   Documentation/driver-api/gpio/board.rst:209: ERROR: Unexpected indentation.
   drivers/ata/libata-core.c:5959: ERROR: Unknown target name: "hw".
   drivers/message/fusion/mptbase.c:5057: WARNING: Definition list ends without a blank line; unexpected unindent.
   drivers/tty/serial/serial_core.c:1952: WARNING: Definition list ends without a blank line; unexpected unindent.
   include/linux/mtd/rawnand.h:1192: WARNING: Inline strong start-string without end-string.
   include/linux/mtd/rawnand.h:1194: WARNING: Inline strong start-string without end-string.
   include/linux/regulator/driver.h:287: ERROR: Unknown target name: "regulator_regmap_x_voltage".
   Documentation/driver-api/soundwire/locking.rst:50: ERROR: Inconsistent literal block quoting.
   Documentation/driver-api/soundwire/locking.rst:51: WARNING: Line block ends without a blank line.
   Documentation/driver-api/soundwire/locking.rst:55: WARNING: Inline substitution_reference start-string without end-string.
   Documentation/driver-api/soundwire/locking.rst:56: WARNING: Line block ends without a blank line.
   include/linux/spi/spi.h:368: ERROR: Unexpected indentation.
   fs/posix_acl.c:635: WARNING: Inline emphasis start-string without end-string.
   Documentation/filesystems/path-lookup.rst:347: WARNING: Title underline too short.

vim +241 drivers/gpu/drm/drm_dsc.c

   230	
   231	/**
   232	 * drm_dsc_compute_rc_parameters() - Write rate control
   233	 * parameters to the dsc configuration. Some configuration
   234	 * fields must be present beforehand.
   235	 *
   236	 * @dsc_cfg:
   237	 * DSC Configuration data partially filled by driver
   238	 */
   239	int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 > 240	{
 > 241		unsigned long groups_per_line = 0;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Move dsc rate params compute into drm

[Dan Carpenter via dri-devel]

Hi David,

url:    https://github.com/0day-ci/linux/commits/David-Francis/Make-DRM-DSC-helpers-more-generally-usable/20190214-052541

smatch warnings:
drivers/gpu/drm/drm_dsc.c:306 drm_dsc_compute_rc_parameters() warn: impossible condition '(vdsc_cfg->nfl_bpg_offset > 65535) => (0-u16max > u16max)'
drivers/gpu/drm/drm_dsc.c:340 drm_dsc_compute_rc_parameters() warn: impossible condition '(vdsc_cfg->scale_increment_interval > 65535) => (0-u16max > u16max)'

# https://github.com/0day-ci/linux/commit/932e204c9cbe2995451a800351bcd781fa7cb1c5
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 932e204c9cbe2995451a800351bcd781fa7cb1c5
vim +306 drivers/gpu/drm/drm_dsc.c

932e204c David Francis 2019-02-13  230  
932e204c David Francis 2019-02-13  231  /**
932e204c David Francis 2019-02-13  232   * drm_dsc_compute_rc_parameters() - Write rate control
932e204c David Francis 2019-02-13  233   * parameters to the dsc configuration. Some configuration
932e204c David Francis 2019-02-13  234   * fields must be present beforehand.
932e204c David Francis 2019-02-13  235   *
932e204c David Francis 2019-02-13  236   * @dsc_cfg:
932e204c David Francis 2019-02-13  237   * DSC Configuration data partially filled by driver
932e204c David Francis 2019-02-13  238   */
932e204c David Francis 2019-02-13  239  int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
932e204c David Francis 2019-02-13  240  {
932e204c David Francis 2019-02-13  241  	unsigned long groups_per_line = 0;
932e204c David Francis 2019-02-13  242  	unsigned long groups_total = 0;
932e204c David Francis 2019-02-13  243  	unsigned long num_extra_mux_bits = 0;
932e204c David Francis 2019-02-13  244  	unsigned long slice_bits = 0;
932e204c David Francis 2019-02-13  245  	unsigned long hrd_delay = 0;
932e204c David Francis 2019-02-13  246  	unsigned long final_scale = 0;
932e204c David Francis 2019-02-13  247  	unsigned long rbs_min = 0;
932e204c David Francis 2019-02-13  248  
932e204c David Francis 2019-02-13  249  	/* Number of groups used to code each line of a slice */
932e204c David Francis 2019-02-13  250  	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
932e204c David Francis 2019-02-13  251  				       DSC_RC_PIXELS_PER_GROUP);
932e204c David Francis 2019-02-13  252  
932e204c David Francis 2019-02-13  253  	/* chunksize in Bytes */
932e204c David Francis 2019-02-13  254  	vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
932e204c David Francis 2019-02-13  255  						  vdsc_cfg->bits_per_pixel,
932e204c David Francis 2019-02-13  256  						  (8 * 16));
932e204c David Francis 2019-02-13  257  
932e204c David Francis 2019-02-13  258  	if (vdsc_cfg->convert_rgb)
932e204c David Francis 2019-02-13  259  		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
932e204c David Francis 2019-02-13  260  					  (4 * vdsc_cfg->bits_per_component + 4)
932e204c David Francis 2019-02-13  261  					  - 2);
932e204c David Francis 2019-02-13  262  	else
932e204c David Francis 2019-02-13  263  		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
932e204c David Francis 2019-02-13  264  			(4 * vdsc_cfg->bits_per_component + 4) +
932e204c David Francis 2019-02-13  265  			2 * (4 * vdsc_cfg->bits_per_component) - 2;
932e204c David Francis 2019-02-13  266  	/* Number of bits in one Slice */
932e204c David Francis 2019-02-13  267  	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
932e204c David Francis 2019-02-13  268  
932e204c David Francis 2019-02-13  269  	while ((num_extra_mux_bits > 0) &&
932e204c David Francis 2019-02-13  270  	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
932e204c David Francis 2019-02-13  271  		num_extra_mux_bits--;
932e204c David Francis 2019-02-13  272  
932e204c David Francis 2019-02-13  273  	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
932e204c David Francis 2019-02-13  274  		vdsc_cfg->initial_scale_value = groups_per_line + 8;
932e204c David Francis 2019-02-13  275  
932e204c David Francis 2019-02-13  276  	/* scale_decrement_interval calculation according to DSC spec 1.11 */
932e204c David Francis 2019-02-13  277  	if (vdsc_cfg->initial_scale_value > 8)
932e204c David Francis 2019-02-13  278  		vdsc_cfg->scale_decrement_interval = groups_per_line /
932e204c David Francis 2019-02-13  279  			(vdsc_cfg->initial_scale_value - 8);
932e204c David Francis 2019-02-13  280  	else
932e204c David Francis 2019-02-13  281  		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
932e204c David Francis 2019-02-13  282  
932e204c David Francis 2019-02-13  283  	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
932e204c David Francis 2019-02-13  284  		(vdsc_cfg->initial_xmit_delay *
932e204c David Francis 2019-02-13  285  		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
932e204c David Francis 2019-02-13  286  
932e204c David Francis 2019-02-13  287  	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
932e204c David Francis 2019-02-13  288  		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
932e204c David Francis 2019-02-13  289  		return -ERANGE;
932e204c David Francis 2019-02-13  290  	}
932e204c David Francis 2019-02-13  291  
932e204c David Francis 2019-02-13  292  	final_scale = (vdsc_cfg->rc_model_size * 8) /
932e204c David Francis 2019-02-13  293  		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
932e204c David Francis 2019-02-13  294  	if (vdsc_cfg->slice_height > 1)
932e204c David Francis 2019-02-13  295  		/*
932e204c David Francis 2019-02-13  296  		 * NflBpgOffset is 16 bit value with 11 fractional bits
932e204c David Francis 2019-02-13  297  		 * hence we multiply by 2^11 for preserving the
932e204c David Francis 2019-02-13  298  		 * fractional part
932e204c David Francis 2019-02-13  299  		 */
932e204c David Francis 2019-02-13  300  		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
932e204c David Francis 2019-02-13  301  							(vdsc_cfg->slice_height - 1));
932e204c David Francis 2019-02-13  302  	else
932e204c David Francis 2019-02-13  303  		vdsc_cfg->nfl_bpg_offset = 0;
932e204c David Francis 2019-02-13  304  
932e204c David Francis 2019-02-13  305  	/* 2^16 - 1 */
932e204c David Francis 2019-02-13 @306  	if (vdsc_cfg->nfl_bpg_offset > 65535) {
932e204c David Francis 2019-02-13  307  		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
932e204c David Francis 2019-02-13  308  		return -ERANGE;
932e204c David Francis 2019-02-13  309  	}
932e204c David Francis 2019-02-13  310  
932e204c David Francis 2019-02-13  311  	/* Number of groups used to code the entire slice */
932e204c David Francis 2019-02-13  312  	groups_total = groups_per_line * vdsc_cfg->slice_height;
932e204c David Francis 2019-02-13  313  
932e204c David Francis 2019-02-13  314  	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
932e204c David Francis 2019-02-13  315  	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
932e204c David Francis 2019-02-13  316  						    vdsc_cfg->initial_offset +
932e204c David Francis 2019-02-13  317  						    num_extra_mux_bits) << 11),
932e204c David Francis 2019-02-13  318  						  groups_total);
932e204c David Francis 2019-02-13  319  
932e204c David Francis 2019-02-13  320  	if (final_scale > 9) {
932e204c David Francis 2019-02-13  321  		/*
932e204c David Francis 2019-02-13  322  		 * ScaleIncrementInterval =
932e204c David Francis 2019-02-13  323  		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
932e204c David Francis 2019-02-13  324  		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
932e204c David Francis 2019-02-13  325  		 * we need divide by 2^11 from pstDscCfg values
932e204c David Francis 2019-02-13  326  		 */
932e204c David Francis 2019-02-13  327  		vdsc_cfg->scale_increment_interval =
932e204c David Francis 2019-02-13  328  				(vdsc_cfg->final_offset * (1 << 11)) /
932e204c David Francis 2019-02-13  329  				((vdsc_cfg->nfl_bpg_offset +
932e204c David Francis 2019-02-13  330  				vdsc_cfg->slice_bpg_offset) *
932e204c David Francis 2019-02-13  331  				(final_scale - 9));
932e204c David Francis 2019-02-13  332  	} else {
932e204c David Francis 2019-02-13  333  		/*
932e204c David Francis 2019-02-13  334  		 * If finalScaleValue is less than or equal to 9, a value of 0 should
932e204c David Francis 2019-02-13  335  		 * be used to disable the scale increment at the end of the slice
932e204c David Francis 2019-02-13  336  		 */
932e204c David Francis 2019-02-13  337  		vdsc_cfg->scale_increment_interval = 0;
932e204c David Francis 2019-02-13  338  	}
932e204c David Francis 2019-02-13  339  
932e204c David Francis 2019-02-13 @340  	if (vdsc_cfg->scale_increment_interval > 65535) {

---
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Re: [Intel-gfx] [PATCH 0/3] Make DRM DSC helpers more generally usable

[Jani Nikula via amd-gfx]

On Wed, 13 Feb 2019, David Francis <David.Francis@amd.com> wrote:
> drm_dsc could use some work so that drm drivers other than
> i915 can make use of it their own DSC implementations
>
> Move rc compute, a function that forms part of the DSC spec,
> into drm. Update it to DSC 1.2. Also change the packing function
> to operate only on the packing struct, to allow for drivers with
> their own SDP struct headers

Acked-by: Jani Nikula <jani.nikula@intel.com>

as long as you've ironed out the details with Manasi's review. Also okay
to merge via drm-misc.

Ideally, please rebase on drm-tip and continue to Cc: intel-gfx so the
Intel CI machinery can crunch through this. Now the patches failed to
apply.

Thanks,
Jani.



>
> David Francis (3):
>   drm/i915: Move dsc rate params compute into drm
>   drm/dsc: Add native 420 and 422 support to compute_rc_params
>   drm/dsc: Change infoframe_pack to payload_pack
>
>  drivers/gpu/drm/drm_dsc.c         | 236 ++++++++++++++++++++++++------
>  drivers/gpu/drm/i915/intel_vdsc.c | 131 +----------------
>  include/drm/drm_dsc.h             |   7 +-
>  3 files changed, 200 insertions(+), 174 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center
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