* [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support
@ 2019-02-15 9:41 Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 1/4] arm: sync armada-xp dts files from Linux 5.0 Chris Packham
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Chris Packham @ 2019-02-15 9:41 UTC (permalink / raw)
To: u-boot
This series adds support for Marvell's Switches with integrated CPUs and
the DB-XC3-24G4XG board. The CPU side is similar to the Armada range.
For now the DDR training code needs to come from the Marvell bin_hdr.
It's one area where the integrated SoCs differ from the Armada range so
neither the Armada-XP nor Armada-38x training code will work as-is. I'm
asking Marvell about the possibility of re-licensing the code under a
Proprietary/BSD/GPL as they did with Armada-38x.
I also have access to a DB-DXBC2-MM board with a different chip. I'll
look at adding support for that as well at some point. It's harder to
work with because it has no USB, but other than that it's similar to the
DB-XC3.
Chris Packham (4):
arm: sync armada-xp dts files from Linux 5.0
arm: mvebu: Add Marvell's integrated CPUs
arm: mvebu: NAND clock support for MSYS devices
arm: mvebu: Add DB-XC3-24G4XG board
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/armada-370-xp.dtsi | 133 ++++----
arch/arm/dts/armada-xp-98dx3236.dtsi | 343 ++++++++++++++++++++
arch/arm/dts/armada-xp-98dx3336.dtsi | 39 +++
arch/arm/dts/armada-xp-98dx4251.dtsi | 54 +++
arch/arm/dts/armada-xp-db-xc3-24g4xg.dts | 122 +++++++
arch/arm/dts/armada-xp-gp.dts | 167 ++++------
arch/arm/dts/armada-xp-maxbcm.dts | 24 +-
arch/arm/dts/armada-xp-mv78230.dtsi | 55 +---
arch/arm/dts/armada-xp-mv78260.dtsi | 58 +---
arch/arm/dts/armada-xp-mv78460.dtsi | 58 +---
arch/arm/dts/armada-xp-synology-ds414.dts | 199 ++++++------
arch/arm/dts/armada-xp-theadorable.dts | 69 ++--
arch/arm/dts/armada-xp.dtsi | 214 ++++++------
arch/arm/mach-mvebu/Kconfig | 26 +-
arch/arm/mach-mvebu/Makefile | 1 +
arch/arm/mach-mvebu/cpu.c | 34 +-
arch/arm/mach-mvebu/include/mach/config.h | 2 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +
arch/arm/mach-mvebu/include/mach/soc.h | 31 ++
board/Marvell/db-xc3-24g4xg/MAINTAINERS | 7 +
board/Marvell/db-xc3-24g4xg/Makefile | 5 +
board/Marvell/db-xc3-24g4xg/README | 4 +
board/Marvell/db-xc3-24g4xg/binary.0 | 11 +
board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c | 71 ++++
board/Marvell/db-xc3-24g4xg/kwbimage.cfg | 12 +
configs/db-xc3-24g4xg_defconfig | 55 ++++
drivers/ddr/marvell/axp/xor_regs.h | 4 +
include/configs/db-xc3-24g4xg.h | 45 +++
tools/Makefile | 4 +
tools/kwbimage.c | 4 +
31 files changed, 1310 insertions(+), 547 deletions(-)
create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
create mode 100644 board/Marvell/db-xc3-24g4xg/README
create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
create mode 100644 configs/db-xc3-24g4xg_defconfig
create mode 100644 include/configs/db-xc3-24g4xg.h
--
2.20.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 1/4] arm: sync armada-xp dts files from Linux 5.0
2019-02-15 9:41 [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support Chris Packham
@ 2019-02-15 9:41 ` Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs Chris Packham
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2019-02-15 9:41 UTC (permalink / raw)
To: u-boot
Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't
got the new NAND driver the updating binding has not been included.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
arch/arm/dts/armada-370-xp.dtsi | 133 ++++++--------
arch/arm/dts/armada-xp-gp.dts | 167 +++++++----------
arch/arm/dts/armada-xp-maxbcm.dts | 24 +--
arch/arm/dts/armada-xp-mv78230.dtsi | 55 ++----
arch/arm/dts/armada-xp-mv78260.dtsi | 58 ++----
arch/arm/dts/armada-xp-mv78460.dtsi | 58 ++----
arch/arm/dts/armada-xp-synology-ds414.dts | 199 ++++++++++----------
arch/arm/dts/armada-xp-theadorable.dts | 69 +++----
arch/arm/dts/armada-xp.dtsi | 214 ++++++++++++----------
9 files changed, 435 insertions(+), 542 deletions(-)
diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi
index 0b2a78d39301..e4c35d4e98f4 100644
--- a/arch/arm/dts/armada-370-xp.dtsi
+++ b/arch/arm/dts/armada-370-xp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
@@ -8,50 +9,10 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
-/include/ "skeleton64.dtsi"
-
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
@@ -86,7 +47,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
- devbus-bootcs {
+ devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -96,7 +57,7 @@
status = "disabled";
};
- devbus-cs0 {
+ devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -106,7 +67,7 @@
status = "disabled";
};
- devbus-cs1 {
+ devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -116,7 +77,7 @@
status = "disabled";
};
- devbus-cs2 {
+ devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -126,7 +87,7 @@
status = "disabled";
};
- devbus-cs3 {
+ devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -141,34 +102,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
- u-boot,dm-pre-reloc;
- rtc at 10300 {
+ rtc: rtc at 10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
- spi0: spi at 10600 {
- reg = <0x10600 0x28>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <30>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- spi1: spi at 10680 {
- reg = <0x10680 0x28>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <92>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
i2c0: i2c at 11000 {
compatible = "marvell,mv64xxx-i2c";
#address-cells = <1>;
@@ -235,33 +175,38 @@
msi-controller;
};
- coherency-fabric at 20200 {
+ coherencyfab: coherency-fabric at 20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
- timer at 20300 {
+ timer: timer at 20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
- watchdog at 20300 {
+ watchdog: watchdog at 20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
- pmsu at 22000 {
+ cpurst: cpurst at 20800 {
+ compatible = "marvell,armada-370-cpu-reset";
+ reg = <0x20800 0x8>;
+ };
+
+ pmsu: pmsu at 22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
- usb at 50000 {
+ usb0: usb at 50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
- usb at 51000 {
+ usb1: usb at 51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@@ -275,7 +220,7 @@
status = "disabled";
};
- mdio: mdio {
+ mdio: mdio at 72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@@ -290,7 +235,7 @@
status = "disabled";
};
- sata at a0000 {
+ sata: sata at a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@@ -309,7 +254,7 @@
status = "disabled";
};
- mvsdio at d4000 {
+ sdio: mvsdio at d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
@@ -321,6 +266,42 @@
status = "disabled";
};
};
+
+ spi0: spi at 10600 {
+ reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
+ <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
+ <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
+ <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
+ <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
+ <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
+ <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
+ <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
+ <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <30>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ spi1: spi at 10680 {
+ reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
+ <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
+ <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
+ <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
+ <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
+ <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
+ <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
+ <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
+ <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <92>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
};
clocks {
diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts
index 27799d1254ea..1139e9469a83 100644
--- a/arch/arm/dts/armada-xp-gp.dts
+++ b/arch/arm/dts/armada-xp-gp.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP development board
* (DB-MV784MP-GP)
@@ -8,44 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
@@ -68,11 +31,7 @@
stdout-path = "serial0:115200n8";
};
- aliases {
- spi0 = &spi0;
- };
-
- memory {
+ memory at 0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
@@ -98,7 +57,10 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
- MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
devbus-bootcs {
status = "okay";
@@ -128,31 +90,9 @@
};
};
- pcie-controller {
- status = "okay";
-
- /*
- * The 3 slots are physically present as
- * standard PCIe slots on the board.
- */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie at 9,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- pcie at 10,0 {
- /* Port 3, Lane 0 */
- status = "okay";
- };
- };
-
internal-regs {
serial at 12000 {
status = "okay";
- u-boot,dm-pre-reloc;
};
serial at 12100 {
status = "okay";
@@ -177,43 +117,33 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy at 0 {
- reg = <16>;
- };
-
- phy1: ethernet-phy at 1 {
- reg = <17>;
- };
-
- phy2: ethernet-phy at 2 {
- reg = <18>;
- };
-
- phy3: ethernet-phy at 3 {
- reg = <19>;
- };
- };
-
ethernet at 70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "qsgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
};
ethernet at 74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "qsgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <1>;
};
ethernet at 30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "qsgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
};
ethernet at 34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "qsgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <3>;
};
/* Front-side USB slot */
@@ -226,27 +156,72 @@
status = "okay";
};
- spi0: spi at 10600 {
+ bm at c0000 {
status = "okay";
- u-boot,dm-pre-reloc;
-
- spi-flash at 0 {
- u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
};
nand at d0000 {
status = "okay";
+ label = "pxa3xx_nand-0";
num-cs = <1>;
marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
+
+ bm-bppi {
+ status = "okay";
+ };
+ };
+};
+
+&pciec {
+ status = "okay";
+
+ /*
+ * The 3 slots are physically present as
+ * standard PCIe slots on the board.
+ */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+ pcie at 9,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ pcie at a,0 {
+ /* Port 3, Lane 0 */
+ status = "okay";
+ };
+};
+
+&mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <16>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ reg = <17>;
+ };
+
+ phy2: ethernet-phy at 2 {
+ reg = <18>;
+ };
+
+ phy3: ethernet-phy at 3 {
+ reg = <19>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
};
};
diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts
index d7d7f65c85fe..921eb7086254 100644
--- a/arch/arm/dts/armada-xp-maxbcm.dts
+++ b/arch/arm/dts/armada-xp-maxbcm.dts
@@ -225,18 +225,6 @@
status = "okay";
};
- spi0: spi at 10600 {
- status = "okay";
-
- spi-flash at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
- };
- };
-
nand at d0000 {
status = "okay";
num-cs = <1>;
@@ -247,3 +235,15 @@
};
};
};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
+};
diff --git a/arch/arm/dts/armada-xp-mv78230.dtsi b/arch/arm/dts/armada-xp-mv78230.dtsi
index f6bab9fb20a9..8558bf6bb54c 100644
--- a/arch/arm/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/dts/armada-xp-mv78230.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78230 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -207,25 +170,33 @@
internal-regs {
gpio0: gpio at 18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio at 18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
+ clocks = <&coreclk 0>;
};
};
};
diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi b/arch/arm/dts/armada-xp-mv78260.dtsi
index d39231f69d9a..2d85fe8ac327 100644
--- a/arch/arm/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/dts/armada-xp-mv78260.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -294,29 +257,38 @@
internal-regs {
gpio0: gpio at 18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio at 18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio at 18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi b/arch/arm/dts/armada-xp-mv78460.dtsi
index c642565d1bc6..230a3fd36b30 100644
--- a/arch/arm/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/dts/armada-xp-mv78460.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -333,29 +296,38 @@
internal-regs {
gpio0: gpio at 18100 {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18100 0x40>, <0x181c0 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
+ clocks = <&coreclk 0>;
};
gpio1: gpio at 18140 {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
+ reg = <0x18140 0x40>, <0x181c8 0x08>;
+ reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
+ #pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
+ clocks = <&coreclk 0>;
};
gpio2: gpio at 18180 {
- compatible = "marvell,orion-gpio";
+ compatible = "marvell,armada-370-gpio",
+ "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts
index 0a60ddfa4149..861967cd7e87 100644
--- a/arch/arm/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/dts/armada-xp-synology-ds414.dts
@@ -1,13 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Synology DS414
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
@@ -42,36 +38,16 @@
spi0 = &spi0;
};
- memory {
+ memory at 0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
-
- pcie-controller {
- status = "okay";
-
- /*
- * Connected to Marvell 88SX7042 SATA-II controller
- * handling the four disks.
- */
- pcie at 1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /*
- * Connected to EtronTech EJ168A XHCI controller
- * providing the two rear USB 3.0 ports.
- */
- pcie at 5,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
internal-regs {
@@ -80,64 +56,6 @@
status = "disabled";
};
- spi0: spi at 10600 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- spi-flash at 0 {
- u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q064";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <20000000>;
-
- /*
- * Warning!
- *
- * Synology u-boot uses its compiled-in environment
- * and it seems Synology did not care to change u-boot
- * default configuration in order to allow saving a
- * modified environment at a sensible location. So,
- * if you do a 'saveenv' under u-boot, your modified
- * environment will be saved at 1MB after the start
- * of the flash, i.e. in the middle of the uImage.
- * For that reason, it is strongly advised not to
- * change the default environment, unless you know
- * what you are doing.
- */
- partition at 00000000 { /* u-boot */
- label = "RedBoot";
- reg = <0x00000000 0x000d0000>; /* 832KB */
- };
-
- partition at 000c0000 { /* uImage */
- label = "zImage";
- reg = <0x000d0000 0x002d0000>; /* 2880KB */
- };
-
- partition at 003a0000 { /* uInitramfs */
- label = "rd.gz";
- reg = <0x003a0000 0x00430000>; /* 4250KB */
- };
-
- partition at 007d0000 { /* MAC address and serial number */
- label = "vendor";
- reg = <0x007d0000 0x00010000>; /* 64KB */
- };
-
- partition at 007e0000 {
- label = "RedBoot config";
- reg = <0x007e0000 0x00010000>; /* 64KB */
- };
-
- partition at 007f0000 {
- label = "FIS directory";
- reg = <0x007f0000 0x00010000>; /* 64KB */
- };
- };
- };
-
i2c at 11000 {
clock-frequency = <400000>;
status = "okay";
@@ -179,16 +97,6 @@
status = "okay";
};
- mdio {
- phy0: ethernet-phy at 0 { /* Marvell 88E1512 */
- reg = <0>;
- };
-
- phy1: ethernet-phy at 1 { /* Marvell 88E1512 */
- reg = <1>;
- };
- };
-
ethernet at 70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -215,7 +123,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
- sata1_regulator: sata1-regulator {
+ sata1_regulator: sata1-regulator at 1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -228,7 +136,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
- sata2_regulator: sata2-regulator {
+ sata2_regulator: sata2-regulator at 2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@@ -241,7 +149,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
- sata3_regulator: sata3-regulator {
+ sata3_regulator: sata3-regulator at 3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@@ -254,7 +162,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
- sata4_regulator: sata4-regulator {
+ sata4_regulator: sata4-regulator at 4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
@@ -269,6 +177,39 @@
};
};
+&pciec {
+ status = "okay";
+
+ /*
+ * Connected to Marvell 88SX7042 SATA-II controller
+ * handling the four disks.
+ */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * Connected to EtronTech EJ168A XHCI controller
+ * providing the two rear USB 3.0 ports.
+ */
+ pcie at 5,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+};
+
+
+&mdio {
+ phy0: ethernet-phy at 0 { /* Marvell 88E1512 */
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 { /* Marvell 88E1512 */
+ reg = <1>;
+ };
+};
+
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";
@@ -335,3 +276,59 @@
marvell,function = "gpio";
};
};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q064", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+
+ /*
+ * Warning!
+ *
+ * Synology u-boot uses its compiled-in environment
+ * and it seems Synology did not care to change u-boot
+ * default configuration in order to allow saving a
+ * modified environment at a sensible location. So,
+ * if you do a 'saveenv' under u-boot, your modified
+ * environment will be saved at 1MB after the start
+ * of the flash, i.e. in the middle of the uImage.
+ * For that reason, it is strongly advised not to
+ * change the default environment, unless you know
+ * what you are doing.
+ */
+ partition at 0 { /* u-boot */
+ label = "RedBoot";
+ reg = <0x00000000 0x000d0000>; /* 832KB */
+ };
+
+ partition at c0000 { /* uImage */
+ label = "zImage";
+ reg = <0x000d0000 0x002d0000>; /* 2880KB */
+ };
+
+ partition at 3a0000 { /* uInitramfs */
+ label = "rd.gz";
+ reg = <0x003a0000 0x00430000>; /* 4250KB */
+ };
+
+ partition at 7d0000 { /* MAC address and serial number */
+ label = "vendor";
+ reg = <0x007d0000 0x00010000>; /* 64KB */
+ };
+
+ partition at 7e0000 {
+ label = "RedBoot config";
+ reg = <0x007e0000 0x00010000>; /* 64KB */
+ };
+
+ partition at 7f0000 {
+ label = "FIS directory";
+ reg = <0x007f0000 0x00010000>; /* 64KB */
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
index 5695e9b75856..bcb4bfdd5c19 100644
--- a/arch/arm/dts/armada-xp-theadorable.dts
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -126,40 +126,6 @@
status = "okay";
};
- spi0: spi at 10600 {
- status = "okay";
- u-boot,dm-pre-reloc;
-
- spi-flash at 0 {
- u-boot,dm-pre-reloc;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <27777777>;
- };
-
- fpga at 1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-generic-device";
- reg = <1>; /* Chip select 1 */
- spi-max-frequency = <27777777>;
- };
- };
-
- spi1: spi at 10680 {
- status = "okay";
-
- fpga at 0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-generic-device";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <27777777>;
- };
- };
-
/* The LCD controller is only used on this board */
lcd0: lcd-controller at e0000 {
compatible = "marvell,armada-xp-lcd";
@@ -188,6 +154,41 @@
};
};
+&spi0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash at 0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <27777777>;
+ };
+
+ fpga at 1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-generic-device";
+ reg = <1>; /* Chip select 1 */
+ spi-max-frequency = <27777777>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+
+ fpga at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-generic-device";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <27777777>;
+ };
+};
+
+
&pciec {
status = "okay";
diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi
index 3fac39e41d78..d856d9602272 100644
--- a/arch/arm/dts/armada-xp.dtsi
+++ b/arch/arm/dts/armada-xp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -8,44 +9,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
* Contains definitions specific to the Armada XP SoC that are not
* common to all Armada SoCs.
*/
@@ -53,6 +16,9 @@
#include "armada-370-xp.dtsi"
/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
@@ -71,12 +37,12 @@
};
internal-regs {
- sdramc at 1400 {
+ sdramc: sdramc at 1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
- L2: l2-cache {
+ L2: l2-cache at 8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@@ -85,29 +51,6 @@
wt-override;
};
- spi0: spi at 10600 {
- compatible = "marvell,armada-xp-spi",
- "marvell,orion-spi";
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- };
-
- spi1: spi at 10680 {
- compatible = "marvell,armada-xp-spi",
- "marvell,orion-spi";
- };
-
-
- i2c0: i2c at 11000 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11000 0x100>;
- };
-
- i2c1: i2c at 11100 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11100 0x100>;
- };
-
uart2: serial at 12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@@ -132,7 +75,7 @@
status = "disabled";
};
- system-controller at 18200 {
+ systemc: system-controller at 18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@@ -150,7 +93,7 @@
#clock-cells = <1>;
};
- thermal at 182b0 {
+ thermal: thermal at 182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@@ -164,25 +107,9 @@
clocks = <&coreclk 1>;
};
- interrupt-controller at 20a00 {
- reg = <0x20a00 0x2d0>, <0x21070 0x58>;
- };
-
- timer at 20300 {
- compatible = "marvell,armada-xp-timer";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- watchdog at 20300 {
- compatible = "marvell,armada-xp-wdt";
- clocks = <&coreclk 2>, <&refclk>;
- clock-names = "nbclk", "fixed";
- };
-
- cpurst at 20800 {
- compatible = "marvell,armada-370-cpu-reset";
- reg = <0x20800 0x20>;
+ cpu-config at 21000 {
+ compatible = "marvell,armada-xp-cpu-config";
+ reg = <0x21000 0x8>;
};
eth2: ethernet at 30000 {
@@ -193,15 +120,7 @@
status = "disabled";
};
- usb at 50000 {
- clocks = <&gateclk 18>;
- };
-
- usb at 51000 {
- clocks = <&gateclk 19>;
- };
-
- usb at 52000 {
+ usb2: usb at 52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@@ -209,7 +128,7 @@
status = "disabled";
};
- xor at 60900 {
+ xor1: xor at 60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -237,7 +156,27 @@
compatible = "marvell,armada-xp-neta";
};
- xor at f0900 {
+ cesa: crypto at 90000 {
+ compatible = "marvell,armada-xp-crypto";
+ reg = <0x90000 0x10000>;
+ reg-names = "regs";
+ interrupts = <48>, <49>;
+ clocks = <&gateclk 23>, <&gateclk 23>;
+ clock-names = "cesa0", "cesa1";
+ marvell,crypto-srams = <&crypto_sram0>,
+ <&crypto_sram1>;
+ marvell,crypto-sram-size = <0x800>;
+ };
+
+ bm: bm at c0000 {
+ compatible = "marvell,armada-380-neta-bm";
+ reg = <0xc0000 0xac>;
+ clocks = <&gateclk 13>;
+ internal-mem = <&bm_bppi>;
+ status = "disabled";
+ };
+
+ xor0: xor at f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
@@ -257,6 +196,35 @@
};
};
};
+
+ crypto_sram0: sa-sram0 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
+ clocks = <&gateclk 23>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
+ };
+
+ crypto_sram1: sa-sram1 {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
+ clocks = <&gateclk 23>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
+ };
+
+ bm_bppi: bm-bppi {
+ compatible = "mmio-sram";
+ reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
+ ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gateclk 13>;
+ no-memory-wc;
+ status = "disabled";
+ };
};
clocks {
@@ -269,6 +237,44 @@
};
};
+&i2c0 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x100>;
+};
+
+&mpic {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+ compatible = "marvell,armada-xp-timer";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+ compatible = "marvell,armada-xp-wdt";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+ reg = <0x20800 0x20>;
+};
+
+&usb0 {
+ clocks = <&gateclk 18>;
+};
+
+&usb1 {
+ clocks = <&gateclk 19>;
+};
+
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =
@@ -309,6 +315,12 @@
marvell,function = "spi0";
};
+ spi1_pins: spi1-pins {
+ marvell,pins = "mpp13", "mpp14",
+ "mpp16", "mpp17";
+ marvell,function = "spi1";
+ };
+
uart2_pins: uart2-pins {
marvell,pins = "mpp42", "mpp43";
marvell,function = "uart2";
@@ -319,3 +331,15 @@
marvell,function = "uart3";
};
};
+
+&spi0 {
+ compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+};
+
+&spi1 {
+ compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+ pinctrl-0 = <&spi1_pins>;
+ pinctrl-names = "default";
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs
2019-02-15 9:41 [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 1/4] arm: sync armada-xp dts files from Linux 5.0 Chris Packham
@ 2019-02-15 9:41 ` Chris Packham
2019-02-15 10:06 ` Stefan Roese
2019-02-15 9:41 ` [U-Boot] [PATCH 3/4] arm: mvebu: NAND clock support for MSYS devices Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board Chris Packham
3 siblings, 1 reply; 10+ messages in thread
From: Chris Packham @ 2019-02-15 9:41 UTC (permalink / raw)
To: u-boot
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex registers).
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++-
arch/arm/mach-mvebu/Makefile | 1 +
arch/arm/mach-mvebu/cpu.c | 32 +++++++++++++++++++++--
arch/arm/mach-mvebu/include/mach/config.h | 2 +-
arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++
arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++
drivers/ddr/marvell/axp/xor_regs.h | 4 +++
7 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7dda04e0e34e..05aa2ade0499 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -46,7 +46,7 @@ config ARMADA_8K
# Armada PLL frequency (used for NAND clock generation)
config SYS_MVEBU_PLL_CLOCK
int
- default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
+ default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || MSYS
default "1000000000" if ARMADA_38X || ARMADA_375
# Armada XP/38x SoC types...
@@ -63,6 +63,22 @@ config MV78460
bool
select ARMADA_XP
+config MSYS
+ bool
+ select ARMADA_32BIT
+
+config 98DX4251
+ bool
+ select MSYS
+
+config 98DX3336
+ bool
+ select MSYS
+
+config 98DX3236
+ bool
+ select MSYS
+
config 88F6820
bool
select ARMADA_38X
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index ee2eca913484..e7f1c59e6351 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -24,6 +24,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 919d05c88c77..e80f9a86c483 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -23,6 +23,12 @@ static struct mbus_win windows[] = {
/* NOR */
{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
+
+#ifdef CONFIG_MSYS
+ /* DFX */
+ { MBUS_DFX_BASE, MBUS_DFX_SIZE,
+ CPU_TARGET_DFX, 0 },
+#endif
};
void lowlevel_init(void)
@@ -121,6 +127,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x13, 0x0, 2000, 1000, 933 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
+#elif defined(CONFIG_MSYS)
+static const struct sar_freq_modes sar_freq_tab[] = {
+ { 0x0, 0x0, 400, 400, 400 },
+ { 0x2, 0x0, 667, 333, 667 },
+ { 0x3, 0x0, 800, 400, 800 },
+ { 0x5, 0x0, 800, 400, 800 },
+ { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
+};
#else
/* SAR frequency values for Armada XP */
static const struct sar_freq_modes sar_freq_tab[] = {
@@ -144,7 +158,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
u32 freq;
int i;
-#if defined(CONFIG_ARMADA_375)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_MSYS)
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
#else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
@@ -160,7 +174,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
#endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
if (sar_freq_tab[i].val == freq) {
-#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
+#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined (CONFIG_MSYS)
*sar_freq = sar_freq_tab[i];
return;
#else
@@ -270,6 +284,20 @@ int print_cpuinfo(void)
}
}
+ if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
+ switch (revid) {
+ case 3:
+ puts("A0");
+ break;
+ case 4:
+ puts("A1");
+ break;
+ default:
+ printf("?? (%x)", revid);
+ break;
+ }
+ }
+
get_sar_freq(&sar_freq);
printf(" at %d MHz\n", sar_freq.p_clk);
diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
index e3235fc67ecd..a78fbe5cc97b 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -17,7 +17,7 @@
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
- || defined(CONFIG_ARMADA_38X)
+ || defined(CONFIG_ARMADA_38X) || defined(CONFIG_MSYS)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 9e23043a4857..b9153d86c669 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -34,6 +34,7 @@ enum cpu_target {
CPU_TARGET_PCIE02 = 0x4,
CPU_TARGET_ETH01 = 0x7,
CPU_TARGET_PCIE13 = 0x8,
+ CPU_TARGET_DFX = 0x8,
CPU_TARGET_SASRAM = 0x9,
CPU_TARGET_SATA01 = 0xa, /* A38X */
CPU_TARGET_NAND = 0xd,
@@ -79,6 +80,8 @@ enum {
#define MBUS_PCI_IO_SIZE (64 << 10)
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
+#define MBUS_DFX_BASE 0xF6000000
+#define MBUS_DFX_SIZE (1 << 20)
#define MBUS_BOOTROM_BASE 0xF8000000
#define MBUS_BOOTROM_SIZE (8 << 20)
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 01577f469b0e..a7039516864e 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -76,7 +76,11 @@
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
+#ifdef CONFIG_MSYS
+#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
+#else
#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
+#endif
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
@@ -149,6 +153,22 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
+#elif defined(CONFIG_MSYS)
+/* SAR values for MSYS */
+#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
+#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
+
+#define SAR_CPU_FREQ_OFFS 18
+#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS 11
+#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS 11
+#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_NAND 0x1
+#define BOOT_FROM_UART 0x2
+#define BOOT_FROM_SPI 0x3
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
diff --git a/drivers/ddr/marvell/axp/xor_regs.h b/drivers/ddr/marvell/axp/xor_regs.h
index db5c41967393..bad41a3f3c1b 100644
--- a/drivers/ddr/marvell/axp/xor_regs.h
+++ b/drivers/ddr/marvell/axp/xor_regs.h
@@ -13,7 +13,11 @@
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
+#ifdef CONFIG_MSYS
+#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
+#else
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
+#endif
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/4] arm: mvebu: NAND clock support for MSYS devices
2019-02-15 9:41 [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 1/4] arm: sync armada-xp dts files from Linux 5.0 Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs Chris Packham
@ 2019-02-15 9:41 ` Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board Chris Packham
3 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2019-02-15 9:41 UTC (permalink / raw)
To: u-boot
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
arch/arm/mach-mvebu/cpu.c | 2 ++
arch/arm/mach-mvebu/include/mach/soc.h | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index e80f9a86c483..770b437d15c1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -500,6 +500,8 @@ u32 mvebu_get_nand_clock(void)
if (mvebu_soc_family() == MVEBU_SOC_A38X)
reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+ else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
+ reg = MVEBU_DFX_DIV_CLK_CTRL(8);
else
reg = MVEBU_CORE_DIV_CLK_CTRL(1);
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a7039516864e..efed55577b17 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -100,9 +100,20 @@
#define SPI_PUP_EN BIT(5)
#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#ifdef CONFIG_MSYS
+#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
+#define NAND_ECC_DIVCKL_RATIO_OFFS 6
+#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
+#endif
+#ifdef CONFIG_MSYS
+#define NAND_ECC_DIVCKL_RATIO_OFFS 6
+#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
+#else
#define NAND_ECC_DIVCKL_RATIO_OFFS 8
#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+#endif
#define SDRAM_MAX_CS 4
#define SDRAM_ADDR_MASK 0xFF000000
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board
2019-02-15 9:41 [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support Chris Packham
` (2 preceding siblings ...)
2019-02-15 9:41 ` [U-Boot] [PATCH 3/4] arm: mvebu: NAND clock support for MSYS devices Chris Packham
@ 2019-02-15 9:41 ` Chris Packham
2019-02-15 10:17 ` Stefan Roese
3 siblings, 1 reply; 10+ messages in thread
From: Chris Packham @ 2019-02-15 9:41 UTC (permalink / raw)
To: u-boot
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
The DB-XC3-24G4XG is a switch development board from Marvell. It can
either use and external CPU card such as the db-88f6820-amc or the
internal CPU that is integrated into the switch.
Add support for running U-Boot on the internal CPU and enable the USB,
SPI and NAND peripherals. For now this needs the bin_hdr from the
Marvell U-Boot for this board.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/armada-xp-98dx3236.dtsi | 343 ++++++++++++++++++++
arch/arm/dts/armada-xp-98dx3336.dtsi | 39 +++
arch/arm/dts/armada-xp-98dx4251.dtsi | 54 +++
arch/arm/dts/armada-xp-db-xc3-24g4xg.dts | 122 +++++++
arch/arm/mach-mvebu/Kconfig | 8 +
board/Marvell/db-xc3-24g4xg/MAINTAINERS | 7 +
board/Marvell/db-xc3-24g4xg/Makefile | 5 +
board/Marvell/db-xc3-24g4xg/README | 4 +
board/Marvell/db-xc3-24g4xg/binary.0 | 11 +
board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c | 71 ++++
board/Marvell/db-xc3-24g4xg/kwbimage.cfg | 12 +
configs/db-xc3-24g4xg_defconfig | 55 ++++
include/configs/db-xc3-24g4xg.h | 45 +++
tools/Makefile | 4 +
tools/kwbimage.c | 4 +
16 files changed, 786 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
create mode 100644 board/Marvell/db-xc3-24g4xg/README
create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
create mode 100644 configs/db-xc3-24g4xg_defconfig
create mode 100644 include/configs/db-xc3-24g4xg.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ca5062348087..133f09d8ba63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
- armada-385-atl-x530DP.dtb
+ armada-385-atl-x530DP.dtb \
+ armada-xp-db-xc3-24g4xg.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi
new file mode 100644
index 000000000000..5df1d1848dbc
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx3236 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-370-xp.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ model = "Marvell 98DX3236 SoC";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,98dx3236-smp";
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ compatible = "marvell,armadaxp-mbus", "simple-bus";
+
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
+ MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
+ MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
+
+ bootrom {
+ compatible = "marvell,bootrom";
+ reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+ };
+
+ /*
+ * 98DX3236 has 1 x1 PCIe unit Gen2.0
+ */
+ pciec: pcie at 82000000 {
+ compatible = "marvell,armada-xp-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
+ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
+
+ pcie1: pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ bus-range = <0x00 0xff>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &mpic 58>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+ };
+
+ internal-regs {
+ sdramc: sdramc at 1400 {
+ compatible = "marvell,armada-xp-sdram-controller";
+ reg = <0x1400 0x500>;
+ };
+
+ L2: l2-cache at 8000 {
+ compatible = "marvell,aurora-system-cache";
+ reg = <0x08000 0x1000>;
+ cache-id-part = <0x100>;
+ cache-level = <2>;
+ cache-unified;
+ wt-override;
+ };
+
+ gpio0: gpio at 18100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };
+
+ /* does not exist */
+ gpio1: gpio at 18140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ status = "disabled";
+ };
+
+ gpio2: gpio at 18180 { /* rework some properties */
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <1>; /* only gpio #32 */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <87>;
+ };
+
+ systemc: system-controller at 18200 {
+ compatible = "marvell,armada-370-xp-system-controller";
+ reg = <0x18200 0x500>;
+ };
+
+ gateclk: clock-gating-control at 18220 {
+ compatible = "marvell,mv98dx3236-gating-clock";
+ reg = <0x18220 0x4>;
+ clocks = <&coreclk 0>;
+ #clock-cells = <1>;
+ };
+
+ cpuclk: clock-complex at 18700 {
+ #clock-cells = <1>;
+ compatible = "marvell,mv98dx3236-cpu-clock";
+ reg = <0x18700 0x24>, <0x1c054 0x10>;
+ clocks = <&coreclk 1>;
+ };
+
+ corediv-clock at 18740 {
+ status = "disabled";
+ };
+
+ cpu-config at 21000 {
+ compatible = "marvell,armada-xp-cpu-config";
+ reg = <0x21000 0x8>;
+ };
+
+ ethernet at 70000 {
+ compatible = "marvell,armada-xp-neta";
+ };
+
+ ethernet at 74000 {
+ compatible = "marvell,armada-xp-neta";
+ };
+
+ xor1: xor at f0800 {
+ compatible = "marvell,orion-xor";
+ reg = <0xf0800 0x100
+ 0xf0a00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ nand_controller: nand at d0000 {
+ clocks = <&dfx_coredivclk 0>;
+ };
+
+ xor0: xor at f0900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xF0900 0x100
+ 0xF0B00 0x100>;
+ clocks = <&gateclk 28>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <94>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <95>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+ };
+
+ dfx: dfx-server at ac000000 {
+ compatible = "marvell,dfx-server", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+ reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ thermal: thermal at f8078 {
+ compatible = "marvell,armada380-thermal";
+ reg = <0xf8078 0x4>, <0xf8074 0x4>;
+ status = "okay";
+ };
+
+ coreclk: mvebu-sar at f8204 {
+ compatible = "marvell,mv98dx3236-core-clock";
+ reg = <0xf8204 0x4>;
+ #clock-cells = <1>;
+ };
+
+ dfx_coredivclk: corediv-clock at f8268 {
+ compatible = "marvell,mv98dx3236-corediv-clock";
+ reg = <0xf8268 0xc>;
+ #clock-cells = <1>;
+ clocks = <&mainpll>;
+ clock-output-names = "nand";
+ };
+ };
+
+ switch: switch at a8000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ pp0: packet-processor at 0 {
+ compatible = "marvell,prestera-98dx3236", "marvell,prestera";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+ };
+ };
+
+ clocks {
+ /* 25 MHz reference crystal */
+ refclk: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+ };
+};
+
+&i2c0 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+ compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x100>;
+};
+
+&mpic {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&timer {
+ compatible = "marvell,armada-xp-timer";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+ compatible = "marvell,armada-xp-wdt";
+ clocks = <&coreclk 2>, <&refclk>;
+ clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+ reg = <0x20800 0x20>;
+};
+
+&usb0 {
+ clocks = <&gateclk 18>;
+};
+
+&usb1 {
+ clocks = <&gateclk 19>;
+};
+
+&pinctrl {
+ compatible = "marvell,98dx3236-pinctrl";
+
+ nand_pins: nand-pins {
+ marvell,pins = "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25",
+ "mpp26", "mpp27", "mpp28",
+ "mpp29", "mpp30";
+ marvell,function = "dev";
+ };
+
+ nand_rb: nand-rb {
+ marvell,pins = "mpp19";
+ marvell,function = "nand";
+ };
+
+ spi0_pins: spi0-pins {
+ marvell,pins = "mpp0", "mpp1",
+ "mpp2", "mpp3";
+ marvell,function = "spi0";
+ };
+};
+
+&spi0 {
+ compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+ pinctrl-0 = <&spi0_pins>;
+ pinctrl-names = "default";
+};
+
+&sdio {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi b/arch/arm/dts/armada-xp-98dx3336.dtsi
new file mode 100644
index 000000000000..1d9d8a8ea60c
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx3336 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx3236 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX3336 SoC";
+ compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+ cpus {
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume at 20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx3336", "marvell,prestera";
+};
diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi b/arch/arm/dts/armada-xp-98dx4251.dtsi
new file mode 100644
index 000000000000..48ffdc72bfc7
--- /dev/null
+++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for Marvell 98dx4521 family SoC
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Contains definitions specific to the 98dx4521 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+#include "armada-xp-98dx3236.dtsi"
+
+/ {
+ model = "Marvell 98DX4251 SoC";
+ compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
+
+ cpus {
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ clock-latency = <1000000>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ resume at 20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+ };
+ };
+ };
+};
+
+&sdio {
+ status = "okay";
+};
+
+&pinctrl {
+ compatible = "marvell,98dx4251-pinctrl";
+
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp5", "mpp6", "mpp7",
+ "mpp8", "mpp9", "mpp10";
+ marvell,function = "sd0";
+ };
+};
+
+&pp0 {
+ compatible = "marvell,prestera-98dx4251", "marvell,prestera";
+ interrupts = <33>, <34>, <35>, <36>;
+};
diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
new file mode 100644
index 000000000000..2daf83e655ac
--- /dev/null
+++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for DB-XC3-24G4XG board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3336.dtsi"
+
+/ {
+ model = "DB-XC3-24G4XG";
+ compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
+ };
+};
+
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width = <16>;
+ devbus,turn-off-ps = <60000>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters */
+ devbus,sync-enable = <0>;
+ devbus,wr-high-ps = <60000>;
+ devbus,wr-low-ps = <60000>;
+ devbus,ale-wr-ps = <60000>;
+};
+
+&uart0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&nand_controller {
+ compatible="marvell,mvebu-pxa3xx-nand";
+ status = "okay";
+ label = "pxa3xx_nand-0";
+ nand-rb = <0>;
+ marvell,nand-keep-config;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ m25p,fast-read;
+
+ partition at u-boot {
+ reg = <0x00000000 0x00100000>;
+ label = "u-boot";
+ };
+ partition at u-boot-env {
+ reg = <0x00100000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition at unused {
+ reg = <0x00140000 0x00ec0000>;
+ label = "unused";
+ };
+
+ };
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 05aa2ade0499..938466615c66 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -152,6 +152,10 @@ config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
+config TARGET_DB_XC3_24G4XG
+ bool "Support DB-XC3-24G4XG"
+ select 98DX3336
+
endchoice
config SYS_BOARD
@@ -170,6 +174,7 @@ config SYS_BOARD
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
+ default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@@ -187,6 +192,7 @@ config SYS_CONFIG_NAME
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
+ default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
@@ -195,6 +201,8 @@ config SYS_VENDOR
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
default "Marvell" if TARGET_MVEBU_ARMADA_8K
+ default "Marvell" if TARGET_DB_XC3_24G4XG
+ default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
default "kobol" if TARGET_HELIOS4
default "Synology" if TARGET_DS414
diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
new file mode 100644
index 000000000000..94d4a901783b
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
@@ -0,0 +1,7 @@
+DB-XC3-24G4XG BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/Marvell/db-xc3-24g4xg/
+F: include/configs/db-xc3-24g4xg.h
+F: configs/db-xc3-24g4xg-amc_defconfig
+F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile
new file mode 100644
index 000000000000..199837a84fe6
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y := db-xc3-24g4xg.o
diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README
new file mode 100644
index 000000000000..5e479b433e4d
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/README
@@ -0,0 +1,4 @@
+To generate binary.0 from Marvell's bin_hdr.elf use the following command
+
+ arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
+ board/Marvell/db-xc3-24g4xg/binary.0
diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0
new file mode 100644
index 000000000000..8dd687286a00
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/binary.0
@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
new file mode 100644
index 000000000000..428e3f611798
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+ | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
+ | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
+#define DB_DX_AC3_GPP_POL_LOW 0x0
+#define DB_DX_AC3_GPP_POL_MID 0x0
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+ writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+ writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+ writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+ writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+ /* Set GPP Out value */
+ writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Disable MBUS Err Prop - in order to avoid data aborts */
+ clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board: " CONFIG_SYS_BOARD "\n");
+
+ return 0;
+}
+#endif
diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
new file mode 100644
index 000000000000..b8bb7a6eb75b
--- /dev/null
+++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
new file mode 100644
index 000000000000..0285ccaa365c
--- /dev/null
+++ b/configs/db-xc3-24g4xg_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DB_XC3_24G4XG=y
+CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_NAND=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
new file mode 100644
index 000000000000..2638ff9d7577
--- /dev/null
+++ b/include/configs/db-xc3-24g4xg.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_XC3_24G4G_H
+#define _CONFIG_DB_XC3_24G4G_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+
+/* NAND */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_XC3_24G4G_H */
diff --git a/tools/Makefile b/tools/Makefile
index 081383d7a790..463f165f9572 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -148,6 +148,10 @@ ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
endif
+ifneq ($(CONFIG_MSYS),)
+HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
+endif
+
# MXSImage needs LibSSL
ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
HOSTLOADLIBES_mkimage += \
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index a88a3830c0c8..8d60dc001112 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1252,8 +1252,12 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
+#ifdef CONFIG_MSYS
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+#else
main_hdr->destaddr = cpu_to_le32(params->addr)
- sizeof(image_header_t);
+#endif
main_hdr->execaddr = cpu_to_le32(params->ep);
main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
--
2.20.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs
2019-02-15 9:41 ` [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs Chris Packham
@ 2019-02-15 10:06 ` Stefan Roese
2019-02-15 11:57 ` Chris Packham
0 siblings, 1 reply; 10+ messages in thread
From: Stefan Roese @ 2019-02-15 10:06 UTC (permalink / raw)
To: u-boot
Hi Chris,
On 15.02.19 10:41, Chris Packham wrote:
> Marvell's switch chips with integrated CPUs (collectively referred to as
> MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
> (e.g. xor) are located at different addresses and DFX server exists as a
> separate target on the MBUS (on Armada-38x it's just part of the core
> complex registers).
>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
>
> arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++-
> arch/arm/mach-mvebu/Makefile | 1 +
> arch/arm/mach-mvebu/cpu.c | 32 +++++++++++++++++++++--
> arch/arm/mach-mvebu/include/mach/config.h | 2 +-
> arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++
> arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++
> drivers/ddr/marvell/axp/xor_regs.h | 4 +++
> 7 files changed, 76 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 7dda04e0e34e..05aa2ade0499 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -46,7 +46,7 @@ config ARMADA_8K
> # Armada PLL frequency (used for NAND clock generation)
> config SYS_MVEBU_PLL_CLOCK
> int
> - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
> + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || MSYS
I personally find this "MSYS" abbreviation quite short and not
descriptive. How is this handled (if at all yet) in Linux?
> default "1000000000" if ARMADA_38X || ARMADA_375
>
> # Armada XP/38x SoC types...
> @@ -63,6 +63,22 @@ config MV78460
> bool
> select ARMADA_XP
>
> +config MSYS
> + bool
> + select ARMADA_32BIT
> +
> +config 98DX4251
> + bool
> + select MSYS
> +
> +config 98DX3336
> + bool
> + select MSYS
> +
> +config 98DX3236
> + bool
> + select MSYS
> +
> config 88F6820
> bool
> select ARMADA_38X
> diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> index ee2eca913484..e7f1c59e6351 100644
> --- a/arch/arm/mach-mvebu/Makefile
> +++ b/arch/arm/mach-mvebu/Makefile
> @@ -24,6 +24,7 @@ ifndef CONFIG_SPL_BUILD
> obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
> obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
> +obj-$(CONFIG_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
> obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
>
> extra-y += kwbimage.cfg
> diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
> index 919d05c88c77..e80f9a86c483 100644
> --- a/arch/arm/mach-mvebu/cpu.c
> +++ b/arch/arm/mach-mvebu/cpu.c
> @@ -23,6 +23,12 @@ static struct mbus_win windows[] = {
> /* NOR */
> { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
> CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
> +
> +#ifdef CONFIG_MSYS
> + /* DFX */
> + { MBUS_DFX_BASE, MBUS_DFX_SIZE,
> + CPU_TARGET_DFX, 0 },
Nitpicking: Doesn't this fit into one single line?
> +#endif
> };
>
> void lowlevel_init(void)
> @@ -121,6 +127,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
> { 0x13, 0x0, 2000, 1000, 933 },
> { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> };
> +#elif defined(CONFIG_MSYS)
> +static const struct sar_freq_modes sar_freq_tab[] = {
> + { 0x0, 0x0, 400, 400, 400 },
> + { 0x2, 0x0, 667, 333, 667 },
> + { 0x3, 0x0, 800, 400, 800 },
> + { 0x5, 0x0, 800, 400, 800 },
> + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> +};
> #else
> /* SAR frequency values for Armada XP */
> static const struct sar_freq_modes sar_freq_tab[] = {
> @@ -144,7 +158,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> u32 freq;
> int i;
>
> -#if defined(CONFIG_ARMADA_375)
> +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_MSYS)
> val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
> #else
> val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
> @@ -160,7 +174,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> #endif
> for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
> if (sar_freq_tab[i].val == freq) {
> -#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
> +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined (CONFIG_MSYS)
> *sar_freq = sar_freq_tab[i];
> return;
> #else
> @@ -270,6 +284,20 @@ int print_cpuinfo(void)
> }
> }
>
> + if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
> + switch (revid) {
> + case 3:
> + puts("A0");
> + break;
> + case 4:
> + puts("A1");
> + break;
> + default:
> + printf("?? (%x)", revid);
> + break;
> + }
> + }
> +
> get_sar_freq(&sar_freq);
> printf(" at %d MHz\n", sar_freq.p_clk);
>
> diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h
> index e3235fc67ecd..a78fbe5cc97b 100644
> --- a/arch/arm/mach-mvebu/include/mach/config.h
> +++ b/arch/arm/mach-mvebu/include/mach/config.h
> @@ -17,7 +17,7 @@
> #include <asm/arch/soc.h>
>
> #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
> - || defined(CONFIG_ARMADA_38X)
> + || defined(CONFIG_ARMADA_38X) || defined(CONFIG_MSYS)
> /*
> * Set this for the common xor register definitions needed in dram.c
> * for A38x as well here.
> diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
> index 9e23043a4857..b9153d86c669 100644
> --- a/arch/arm/mach-mvebu/include/mach/cpu.h
> +++ b/arch/arm/mach-mvebu/include/mach/cpu.h
> @@ -34,6 +34,7 @@ enum cpu_target {
> CPU_TARGET_PCIE02 = 0x4,
> CPU_TARGET_ETH01 = 0x7,
> CPU_TARGET_PCIE13 = 0x8,
> + CPU_TARGET_DFX = 0x8,
> CPU_TARGET_SASRAM = 0x9,
> CPU_TARGET_SATA01 = 0xa, /* A38X */
> CPU_TARGET_NAND = 0xd,
> @@ -79,6 +80,8 @@ enum {
> #define MBUS_PCI_IO_SIZE (64 << 10)
> #define MBUS_SPI_BASE 0xF4000000
> #define MBUS_SPI_SIZE (8 << 20)
> +#define MBUS_DFX_BASE 0xF6000000
> +#define MBUS_DFX_SIZE (1 << 20)
> #define MBUS_BOOTROM_BASE 0xF8000000
> #define MBUS_BOOTROM_SIZE (8 << 20)
>
> diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
> index 01577f469b0e..a7039516864e 100644
> --- a/arch/arm/mach-mvebu/include/mach/soc.h
> +++ b/arch/arm/mach-mvebu/include/mach/soc.h
> @@ -76,7 +76,11 @@
> #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
> #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
> #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
> +#ifdef CONFIG_MSYS
> +#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
> +#else
> #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
> +#endif
>
> #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
> #define MBUS_ERR_PROP_EN (1 << 8)
> @@ -149,6 +153,22 @@
> #define BOOT_FROM_SPI 0x32
> #define BOOT_FROM_MMC 0x30
> #define BOOT_FROM_MMC_ALT 0x31
> +#elif defined(CONFIG_MSYS)
> +/* SAR values for MSYS */
> +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
> +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
> +
> +#define SAR_CPU_FREQ_OFFS 18
> +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
> +#define SAR_BOOT_DEVICE_OFFS 11
> +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
> +
> +#define BOOT_DEV_SEL_OFFS 11
> +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
> +
> +#define BOOT_FROM_NAND 0x1
> +#define BOOT_FROM_UART 0x2
> +#define BOOT_FROM_SPI 0x3
> #else
> /* SAR values for Armada XP */
> #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
> diff --git a/drivers/ddr/marvell/axp/xor_regs.h b/drivers/ddr/marvell/axp/xor_regs.h
> index db5c41967393..bad41a3f3c1b 100644
> --- a/drivers/ddr/marvell/axp/xor_regs.h
> +++ b/drivers/ddr/marvell/axp/xor_regs.h
> @@ -13,7 +13,11 @@
> #define XOR_UNIT(chan) ((chan) >> 1)
> #define XOR_CHAN(chan) ((chan) & 1)
>
> +#ifdef CONFIG_MSYS
> +#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
> +#else
> #define MV_XOR_REGS_OFFSET(unit) (0x60900)
> +#endif
> #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
>
> /* XOR Engine Control Register Map */
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board
2019-02-15 9:41 ` [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board Chris Packham
@ 2019-02-15 10:17 ` Stefan Roese
2019-02-15 12:18 ` Chris Packham
0 siblings, 1 reply; 10+ messages in thread
From: Stefan Roese @ 2019-02-15 10:17 UTC (permalink / raw)
To: u-boot
Hi Chris,
please find a few comments / questions below.
On 15.02.19 10:41, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> The DB-XC3-24G4XG is a switch development board from Marvell. It can
> either use and external CPU card such as the db-88f6820-amc or the
> internal CPU that is integrated into the switch.
>
> Add support for running U-Boot on the internal CPU and enable the USB,
> SPI and NAND peripherals. For now this needs the bin_hdr from the
> Marvell U-Boot for this board.
>
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
> ---
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/armada-xp-98dx3236.dtsi | 343 ++++++++++++++++++++
> arch/arm/dts/armada-xp-98dx3336.dtsi | 39 +++
> arch/arm/dts/armada-xp-98dx4251.dtsi | 54 +++
> arch/arm/dts/armada-xp-db-xc3-24g4xg.dts | 122 +++++++
> arch/arm/mach-mvebu/Kconfig | 8 +
> board/Marvell/db-xc3-24g4xg/MAINTAINERS | 7 +
> board/Marvell/db-xc3-24g4xg/Makefile | 5 +
> board/Marvell/db-xc3-24g4xg/README | 4 +
> board/Marvell/db-xc3-24g4xg/binary.0 | 11 +
> board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c | 71 ++++
> board/Marvell/db-xc3-24g4xg/kwbimage.cfg | 12 +
> configs/db-xc3-24g4xg_defconfig | 55 ++++
> include/configs/db-xc3-24g4xg.h | 45 +++
> tools/Makefile | 4 +
> tools/kwbimage.c | 4 +
Could you please split the kwbimage tool changes into a separate
patch?
> 16 files changed, 786 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
> create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
> create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
> create mode 100644 board/Marvell/db-xc3-24g4xg/README
> create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
> create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> create mode 100644 configs/db-xc3-24g4xg_defconfig
> create mode 100644 include/configs/db-xc3-24g4xg.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ca5062348087..133f09d8ba63 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
> armada-xp-theadorable.dtb \
> armada-38x-controlcenterdc.dtb \
> armada-385-atl-x530.dtb \
> - armada-385-atl-x530DP.dtb
> + armada-385-atl-x530DP.dtb \
> + armada-xp-db-xc3-24g4xg.dtb
>
> dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
> uniphier-ld11-global.dtb \
> diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi
> new file mode 100644
> index 000000000000..5df1d1848dbc
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
> @@ -0,0 +1,343 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx3236 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-370-xp.dtsi"
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + model = "Marvell 98DX3236 SoC";
> + compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "marvell,98dx3236-smp";
> +
> + cpu at 0 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <0>;
> + clocks = <&cpuclk 0>;
> + clock-latency = <1000000>;
> + };
> + };
> +
> + soc {
> + compatible = "marvell,armadaxp-mbus", "simple-bus";
> +
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> + MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> +
> + bootrom {
> + compatible = "marvell,bootrom";
> + reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> + };
> +
> + /*
> + * 98DX3236 has 1 x1 PCIe unit Gen2.0
> + */
> + pciec: pcie at 82000000 {
> + compatible = "marvell,armada-xp-pcie";
> + status = "disabled";
> + device_type = "pci";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + msi-parent = <&mpic>;
> + bus-range = <0x00 0xff>;
> +
> + ranges =
> + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
> + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
> + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
> +
> + pcie1: pcie at 1,0 {
> + device_type = "pci";
> + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> + 0x81000000 0 0 0x81000000 0x1 0 1 0>;
> + bus-range = <0x00 0xff>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &mpic 58>;
> + marvell,pcie-port = <0>;
> + marvell,pcie-lane = <0>;
> + clocks = <&gateclk 5>;
> + status = "disabled";
> + };
> + };
> +
> + internal-regs {
> + sdramc: sdramc at 1400 {
> + compatible = "marvell,armada-xp-sdram-controller";
> + reg = <0x1400 0x500>;
> + };
> +
> + L2: l2-cache at 8000 {
> + compatible = "marvell,aurora-system-cache";
> + reg = <0x08000 0x1000>;
> + cache-id-part = <0x100>;
> + cache-level = <2>;
> + cache-unified;
> + wt-override;
> + };
> +
> + gpio0: gpio at 18100 {
> + compatible = "marvell,orion-gpio";
> + reg = <0x18100 0x40>;
> + ngpios = <32>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <82>, <83>, <84>, <85>;
> + };
> +
> + /* does not exist */
> + gpio1: gpio at 18140 {
> + compatible = "marvell,orion-gpio";
> + reg = <0x18140 0x40>;
> + status = "disabled";
> + };
> +
> + gpio2: gpio at 18180 { /* rework some properties */
> + compatible = "marvell,orion-gpio";
> + reg = <0x18180 0x40>;
> + ngpios = <1>; /* only gpio #32 */
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <87>;
> + };
> +
> + systemc: system-controller at 18200 {
> + compatible = "marvell,armada-370-xp-system-controller";
> + reg = <0x18200 0x500>;
> + };
> +
> + gateclk: clock-gating-control at 18220 {
> + compatible = "marvell,mv98dx3236-gating-clock";
> + reg = <0x18220 0x4>;
> + clocks = <&coreclk 0>;
> + #clock-cells = <1>;
> + };
> +
> + cpuclk: clock-complex at 18700 {
> + #clock-cells = <1>;
> + compatible = "marvell,mv98dx3236-cpu-clock";
> + reg = <0x18700 0x24>, <0x1c054 0x10>;
> + clocks = <&coreclk 1>;
> + };
> +
> + corediv-clock at 18740 {
> + status = "disabled";
> + };
> +
> + cpu-config at 21000 {
> + compatible = "marvell,armada-xp-cpu-config";
> + reg = <0x21000 0x8>;
> + };
> +
> + ethernet at 70000 {
> + compatible = "marvell,armada-xp-neta";
> + };
> +
> + ethernet at 74000 {
> + compatible = "marvell,armada-xp-neta";
> + };
> +
> + xor1: xor at f0800 {
> + compatible = "marvell,orion-xor";
> + reg = <0xf0800 0x100
> + 0xf0a00 0x100>;
> + clocks = <&gateclk 22>;
> + status = "okay";
> +
> + xor10 {
> + interrupts = <51>;
> + dmacap,memcpy;
> + dmacap,xor;
> + };
> + xor11 {
> + interrupts = <52>;
> + dmacap,memcpy;
> + dmacap,xor;
> + dmacap,memset;
> + };
> + };
> +
> + nand_controller: nand at d0000 {
> + clocks = <&dfx_coredivclk 0>;
> + };
> +
> + xor0: xor at f0900 {
> + compatible = "marvell,orion-xor";
> + reg = <0xF0900 0x100
> + 0xF0B00 0x100>;
> + clocks = <&gateclk 28>;
> + status = "okay";
> +
> + xor00 {
> + interrupts = <94>;
> + dmacap,memcpy;
> + dmacap,xor;
> + };
> + xor01 {
> + interrupts = <95>;
> + dmacap,memcpy;
> + dmacap,xor;
> + dmacap,memset;
> + };
> + };
> + };
> +
> + dfx: dfx-server at ac000000 {
> + compatible = "marvell,dfx-server", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
> + reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
> +
> + thermal: thermal at f8078 {
> + compatible = "marvell,armada380-thermal";
> + reg = <0xf8078 0x4>, <0xf8074 0x4>;
> + status = "okay";
> + };
> +
> + coreclk: mvebu-sar at f8204 {
> + compatible = "marvell,mv98dx3236-core-clock";
> + reg = <0xf8204 0x4>;
> + #clock-cells = <1>;
> + };
> +
> + dfx_coredivclk: corediv-clock at f8268 {
> + compatible = "marvell,mv98dx3236-corediv-clock";
> + reg = <0xf8268 0xc>;
> + #clock-cells = <1>;
> + clocks = <&mainpll>;
> + clock-output-names = "nand";
> + };
> + };
> +
> + switch: switch at a8000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
> +
> + pp0: packet-processor at 0 {
> + compatible = "marvell,prestera-98dx3236", "marvell,prestera";
> + reg = <0 0x4000000>;
> + interrupts = <33>, <34>, <35>;
> + dfx = <&dfx>;
> + };
> + };
> + };
> +
> + clocks {
> + /* 25 MHz reference crystal */
> + refclk: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> + reg = <0x11000 0x100>;
> +};
> +
> +&i2c1 {
> + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> + reg = <0x11100 0x100>;
> +};
> +
> +&mpic {
> + reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> +};
> +
> +&rtc {
> + status = "disabled";
> +};
> +
> +&timer {
> + compatible = "marvell,armada-xp-timer";
> + clocks = <&coreclk 2>, <&refclk>;
> + clock-names = "nbclk", "fixed";
> +};
> +
> +&watchdog {
> + compatible = "marvell,armada-xp-wdt";
> + clocks = <&coreclk 2>, <&refclk>;
> + clock-names = "nbclk", "fixed";
> +};
> +
> +&cpurst {
> + reg = <0x20800 0x20>;
> +};
> +
> +&usb0 {
> + clocks = <&gateclk 18>;
> +};
> +
> +&usb1 {
> + clocks = <&gateclk 19>;
> +};
> +
> +&pinctrl {
> + compatible = "marvell,98dx3236-pinctrl";
> +
> + nand_pins: nand-pins {
> + marvell,pins = "mpp20", "mpp21", "mpp22",
> + "mpp23", "mpp24", "mpp25",
> + "mpp26", "mpp27", "mpp28",
> + "mpp29", "mpp30";
> + marvell,function = "dev";
> + };
> +
> + nand_rb: nand-rb {
> + marvell,pins = "mpp19";
> + marvell,function = "nand";
> + };
> +
> + spi0_pins: spi0-pins {
> + marvell,pins = "mpp0", "mpp1",
> + "mpp2", "mpp3";
> + marvell,function = "spi0";
> + };
> +};
> +
> +&spi0 {
> + compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
> + pinctrl-0 = <&spi0_pins>;
> + pinctrl-names = "default";
> +};
> +
> +&sdio {
> + status = "disabled";
> +};
> diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi b/arch/arm/dts/armada-xp-98dx3336.dtsi
> new file mode 100644
> index 000000000000..1d9d8a8ea60c
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx3336 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx3236 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX3336 SoC";
> + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <1000000>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume at 20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx3336", "marvell,prestera";
> +};
> diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi b/arch/arm/dts/armada-xp-98dx4251.dtsi
> new file mode 100644
> index 000000000000..48ffdc72bfc7
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Marvell 98dx4521 family SoC
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Contains definitions specific to the 98dx4521 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX4251 SoC";
> + compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu at 1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = <&cpuclk 1>;
> + clock-latency = <1000000>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume at 20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> +&sdio {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + compatible = "marvell,98dx4251-pinctrl";
> +
> + sdio_pins: sdio-pins {
> + marvell,pins = "mpp5", "mpp6", "mpp7",
> + "mpp8", "mpp9", "mpp10";
> + marvell,function = "sd0";
> + };
> +};
> +
> +&pp0 {
> + compatible = "marvell,prestera-98dx4251", "marvell,prestera";
> + interrupts = <33>, <34>, <35>, <36>;
> +};
> diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> new file mode 100644
> index 000000000000..2daf83e655ac
> --- /dev/null
> +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for DB-XC3-24G4XG board
> + *
> + * Copyright (C) 2016 Allied Telesis Labs
> + *
> + * Based on armada-xp-db.dts
> + *
> + * Note: this Device Tree assumes that the bootloader has remapped the
> + * internal registers to 0xf1000000 (instead of the default
> + * 0xd0000000). The 0xf1000000 is the default used by the recent,
> + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
> + * boards were delivered with an older version of the bootloader that
> + * left internal registers mapped at 0xd0000000. If you are in this
> + * situation, you should either update your bootloader (preferred
> + * solution) or the below Device Tree should be adjusted.
> + */
> +
> +/dts-v1/;
> +#include "armada-xp-98dx3336.dtsi"
> +
> +/ {
> + model = "DB-XC3-24G4XG";
> + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs = "console=ttyS0,115200 earlyprintk";
> + };
> +
> + aliases {
> + spi0 = &spi0;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> + };
> +};
> +
> +&L2 {
> + arm,parity-enable;
> + marvell,ecc-enable;
> +};
> +
> +&devbus_bootcs {
> + status = "okay";
> +
> + /* Device Bus parameters are required */
> +
> + /* Read parameters */
> + devbus,bus-width = <16>;
> + devbus,turn-off-ps = <60000>;
> + devbus,badr-skew-ps = <0>;
> + devbus,acc-first-ps = <124000>;
> + devbus,acc-next-ps = <248000>;
> + devbus,rd-setup-ps = <0>;
> + devbus,rd-hold-ps = <0>;
> +
> + /* Write parameters */
> + devbus,sync-enable = <0>;
> + devbus,wr-high-ps = <60000>;
> + devbus,wr-low-ps = <60000>;
> + devbus,ale-wr-ps = <60000>;
> +};
> +
> +&uart0 {
> + status = "okay";
> + u-boot,dm-pre-reloc;
All U-Boot specific DT properties into a *-u-boot.dtsi file please.
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&nand_controller {
> + compatible="marvell,mvebu-pxa3xx-nand";
> + status = "okay";
> + label = "pxa3xx_nand-0";
> + nand-rb = <0>;
> + marvell,nand-keep-config;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> + u-boot,dm-pre-reloc;
Here as well and all other occurrences too please.
> +
> + spi-flash at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-flash", "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <108000000>;
> + m25p,fast-read;
> +
> + partition at u-boot {
> + reg = <0x00000000 0x00100000>;
> + label = "u-boot";
> + };
> + partition at u-boot-env {
> + reg = <0x00100000 0x00040000>;
> + label = "u-boot-env";
> + };
> + partition at unused {
> + reg = <0x00140000 0x00ec0000>;
> + label = "unused";
> + };
> +
> + };
> +};
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index 05aa2ade0499..938466615c66 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -152,6 +152,10 @@ config TARGET_X530
> bool "Support Allied Telesis x530"
> select 88F6820
>
> +config TARGET_DB_XC3_24G4XG
> + bool "Support DB-XC3-24G4XG"
> + select 98DX3336
> +
> endchoice
>
> config SYS_BOARD
> @@ -170,6 +174,7 @@ config SYS_BOARD
> default "theadorable" if TARGET_THEADORABLE
> default "a38x" if TARGET_CONTROLCENTERDC
> default "x530" if TARGET_X530
> + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>
> config SYS_CONFIG_NAME
> default "clearfog" if TARGET_CLEARFOG
> @@ -187,6 +192,7 @@ config SYS_CONFIG_NAME
> default "turris_mox" if TARGET_TURRIS_MOX
> default "controlcenterdc" if TARGET_CONTROLCENTERDC
> default "x530" if TARGET_X530
> + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
>
> config SYS_VENDOR
> default "Marvell" if TARGET_DB_MV784MP_GP
> @@ -195,6 +201,8 @@ config SYS_VENDOR
> default "Marvell" if TARGET_DB_88F6820_GP
> default "Marvell" if TARGET_DB_88F6820_AMC
> default "Marvell" if TARGET_MVEBU_ARMADA_8K
> + default "Marvell" if TARGET_DB_XC3_24G4XG
> + default "Marvell" if TARGET_MVEBU_DB_88F7040
> default "solidrun" if TARGET_CLEARFOG
> default "kobol" if TARGET_HELIOS4
> default "Synology" if TARGET_DS414
> diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> new file mode 100644
> index 000000000000..94d4a901783b
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> @@ -0,0 +1,7 @@
> +DB-XC3-24G4XG BOARD
> +M: Chris Packham <chris.packham@alliedtelesis.co.nz>
> +S: Maintained
> +F: board/Marvell/db-xc3-24g4xg/
> +F: include/configs/db-xc3-24g4xg.h
> +F: configs/db-xc3-24g4xg-amc_defconfig
> +F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile
> new file mode 100644
> index 000000000000..199837a84fe6
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2015 Stefan Roese <sr@denx.de>
> +
> +obj-y := db-xc3-24g4xg.o
> diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README
> new file mode 100644
> index 000000000000..5e479b433e4d
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/README
> @@ -0,0 +1,4 @@
> +To generate binary.0 from Marvell's bin_hdr.elf use the following command
> +
> + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
> + board/Marvell/db-xc3-24g4xg/binary.0
> diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0
> new file mode 100644
> index 000000000000..8dd687286a00
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/binary.0
> @@ -0,0 +1,11 @@
> +--------
> +WARNING:
> +--------
> +This file should contain the bin_hdr generated by the original Marvell
> +U-Boot implementation. As this is currently not included in this
> +U-Boot version, we have added this placeholder, so that the U-Boot
> +image can be generated without errors.
> +
> +If you have a known to be working bin_hdr for your board, then you
> +just need to replace this text file here with the binary header
> +and recompile U-Boot.
> diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> new file mode 100644
> index 000000000000..428e3f611798
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> + */
> +
> +#include <common.h>
> +#include <i2c.h>
> +#include <asm/gpio.h>
> +#include <linux/mbus.h>
> +#include <linux/io.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/soc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * These values and defines are taken from the Marvell U-Boot version
> + * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
> + */
> +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
> + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
> +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
> +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
> + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
> +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
> +#define DB_DX_AC3_GPP_POL_LOW 0x0
> +#define DB_DX_AC3_GPP_POL_MID 0x0
> +
> +int board_early_init_f(void)
> +{
> + /* Configure MPP */
> + writel(0x00142222, MVEBU_MPP_BASE + 0x00);
> + writel(0x11122000, MVEBU_MPP_BASE + 0x04);
> + writel(0x44444004, MVEBU_MPP_BASE + 0x08);
> + writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
> + writel(0x00000001, MVEBU_MPP_BASE + 0x10);
> +
> + /* Set GPP Out value */
> + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
> + writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
> +
> + /* Set GPP Polarity */
> + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
> + writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
> +
> + /* Set GPP Out Enable */
> + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
> + writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> +
> + /* Disable MBUS Err Prop - in order to avoid data aborts */
> + clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
Is this some change that should be done for all "MSYS" boards?
If yes, then please move it to arch/arm/mach-mvebu instead.
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +int checkboard(void)
> +{
> + puts("Board: " CONFIG_SYS_BOARD "\n");
> +
> + return 0;
> +}
> +#endif
> diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> new file mode 100644
> index 000000000000..b8bb7a6eb75b
> --- /dev/null
> +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> @@ -0,0 +1,12 @@
> +#
> +# Copyright (C) 2014 Stefan Roese <sr@denx.de>
> +#
> +
> +# Armada XP uses version 1 image format
> +VERSION 1
> +
> +# Boot Media configurations
> +BOOT_FROM spi
> +
> +# Binary Header (bin_hdr) with DDR3 training code
> +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
> diff --git a/configs/db-xc3-24g4xg_defconfig b/configs/db-xc3-24g4xg_defconfig
> new file mode 100644
> index 000000000000..0285ccaa365c
> --- /dev/null
> +++ b/configs/db-xc3-24g4xg_defconfig
> @@ -0,0 +1,55 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_MVEBU=y
> +CONFIG_SYS_TEXT_BASE=0x00800000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_DB_XC3_24G4XG=y
> +CONFIG_BUILD_TARGET="u-boot.kwb"
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_CMD_MEMTEST=y
> +CONFIG_SYS_ALT_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_DHCP=y
> +CONFIG_CMD_TFTPPUT=y
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_CMD_UBI=y
> +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_BLK=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_MVTWSI=y
> +# CONFIG_MMC is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_DEVICE=y
> +CONFIG_NAND=y
> +CONFIG_NAND_PXA3XX=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_PCI=y
> +CONFIG_PCI_MVEBU=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_KIRKWOOD_SPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_HOST_ETHER=y
> +CONFIG_USB_ETHER_ASIX=y
> +CONFIG_USB_ETHER_RTL8152=y
> +CONFIG_USB_ETHER_SMSC95XX=y
> diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
> new file mode 100644
> index 000000000000..2638ff9d7577
> --- /dev/null
> +++ b/include/configs/db-xc3-24g4xg.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> + */
> +
> +#ifndef _CONFIG_DB_XC3_24G4G_H
> +#define _CONFIG_DB_XC3_24G4G_H
> +
> +/*
> + * High Level Configuration Options (easy to change)
> + */
> +
> +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
> +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
> +
> +/* SPI NOR flash default params, used by sf commands */
> +#define CONFIG_SF_DEFAULT_SPEED 1000000
> +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Do we still need these with the recent SPI flash changes? I
did not test, I'm just curious, if those can be omitted and
everything necessary gets extraced from the DT instead?
> +
> +/* USB/EHCI configuration */
> +#define CONFIG_EHCI_IS_TDI
> +
> +/* Environment in SPI NOR flash */
> +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
> +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
> +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
> +
> +/* NAND */
> +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> +#define CONFIG_SYS_NAND_ONFI_DETECTION
> +
> +/* Keep device tree and initrd in lower memory so the kernel can access them */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x10000000\0" \
> + "initrd_high=0x10000000\0"
> +
> +/*
> + * mv-common.h should be defined after CMD configs since it used them
> + * to enable certain macros
> + */
> +#include "mv-common.h"
> +#undef CONFIG_SYS_MAXARGS
> +#define CONFIG_SYS_MAXARGS 96
> +
> +#endif /* _CONFIG_DB_XC3_24G4G_H */
> diff --git a/tools/Makefile b/tools/Makefile
> index 081383d7a790..463f165f9572 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -148,6 +148,10 @@ ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
> HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
> endif
>
> +ifneq ($(CONFIG_MSYS),)
> +HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
> +endif
> +
Again, please move into a seperate patch.
> # MXSImage needs LibSSL
> ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
> HOSTLOADLIBES_mkimage += \
> diff --git a/tools/kwbimage.c b/tools/kwbimage.c
> index a88a3830c0c8..8d60dc001112 100644
> --- a/tools/kwbimage.c
> +++ b/tools/kwbimage.c
> @@ -1252,8 +1252,12 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
> cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
> main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
> main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
> +#ifdef CONFIG_MSYS
> + main_hdr->destaddr = cpu_to_le32(params->addr);
> +#else
> main_hdr->destaddr = cpu_to_le32(params->addr)
Why is this change necessary? Could you please explain?
Thanks,
Stefan
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs
2019-02-15 10:06 ` Stefan Roese
@ 2019-02-15 11:57 ` Chris Packham
2019-02-15 12:38 ` Stefan Roese
0 siblings, 1 reply; 10+ messages in thread
From: Chris Packham @ 2019-02-15 11:57 UTC (permalink / raw)
To: u-boot
On Fri, 15 Feb 2019, 11:06 PM Stefan Roese <sr@denx.de wrote:
> Hi Chris,
>
> On 15.02.19 10:41, Chris Packham wrote:
> > Marvell's switch chips with integrated CPUs (collectively referred to as
> > MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
> > (e.g. xor) are located at different addresses and DFX server exists as a
> > separate target on the MBUS (on Armada-38x it's just part of the core
> > complex registers).
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++-
> > arch/arm/mach-mvebu/Makefile | 1 +
> > arch/arm/mach-mvebu/cpu.c | 32 +++++++++++++++++++++--
> > arch/arm/mach-mvebu/include/mach/config.h | 2 +-
> > arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++
> > arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++
> > drivers/ddr/marvell/axp/xor_regs.h | 4 +++
> > 7 files changed, 76 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 7dda04e0e34e..05aa2ade0499 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -46,7 +46,7 @@ config ARMADA_8K
> > # Armada PLL frequency (used for NAND clock generation)
> > config SYS_MVEBU_PLL_CLOCK
> > int
> > - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
> > + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K ||
> MSYS
>
> I personally find this "MSYS" abbreviation quite short and not
> descriptive. How is this handled (if at all yet) in Linux?
>
I did briefly consider ARMADA_MSYS. But settled on MSYS because that's how
Marvell tend to refer to it. Marvells code uses MSYS, XCAT3, AC3 and BC2
depending on how specific they need to be (e.g. the ddr code needs to
distinguish AC3 and BC2).
In Linux I originally proposed MSYS but eventually we went with MV98DX3326
as the base and used the other chip names where needed. But that mostly
works out because the arch code is generic so the things that use these
names are mostly compat strings.
> > default "1000000000" if ARMADA_38X || ARMADA_375
> >
> > # Armada XP/38x SoC types...
> > @@ -63,6 +63,22 @@ config MV78460
> > bool
> > select ARMADA_XP
> >
> > +config MSYS
> > + bool
> > + select ARMADA_32BIT
> > +
> > +config 98DX4251
> > + bool
> > + select MSYS
> > +
> > +config 98DX3336
> > + bool
> > + select MSYS
> > +
> > +config 98DX3236
> > + bool
> > + select MSYS
> > +
> > config 88F6820
> > bool
> > select ARMADA_38X
> > diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
> > index ee2eca913484..e7f1c59e6351 100644
> > --- a/arch/arm/mach-mvebu/Makefile
> > +++ b/arch/arm/mach-mvebu/Makefile
> > @@ -24,6 +24,7 @@ ifndef CONFIG_SPL_BUILD
> > obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
> > obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
> > obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
> > +obj-$(CONFIG_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
> > obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
> >
> > extra-y += kwbimage.cfg
> > diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
> > index 919d05c88c77..e80f9a86c483 100644
> > --- a/arch/arm/mach-mvebu/cpu.c
> > +++ b/arch/arm/mach-mvebu/cpu.c
> > @@ -23,6 +23,12 @@ static struct mbus_win windows[] = {
> > /* NOR */
> > { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
> > CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
> > +
> > +#ifdef CONFIG_MSYS
> > + /* DFX */
> > + { MBUS_DFX_BASE, MBUS_DFX_SIZE,
> > + CPU_TARGET_DFX, 0 },
>
> Nitpicking: Doesn't this fit into one single line?
>
Will fix.
> > +#endif
> > };
> >
> > void lowlevel_init(void)
> > @@ -121,6 +127,14 @@ static const struct sar_freq_modes sar_freq_tab[] =
> {
> > { 0x13, 0x0, 2000, 1000, 933 },
> > { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> > };
> > +#elif defined(CONFIG_MSYS)
> > +static const struct sar_freq_modes sar_freq_tab[] = {
> > + { 0x0, 0x0, 400, 400, 400 },
> > + { 0x2, 0x0, 667, 333, 667 },
> > + { 0x3, 0x0, 800, 400, 800 },
> > + { 0x5, 0x0, 800, 400, 800 },
> > + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
> > +};
> > #else
> > /* SAR frequency values for Armada XP */
> > static const struct sar_freq_modes sar_freq_tab[] = {
> > @@ -144,7 +158,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> > u32 freq;
> > int i;
> >
> > -#if defined(CONFIG_ARMADA_375)
> > +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_MSYS)
> > val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
> > #else
> > val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
> > @@ -160,7 +174,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
> > #endif
> > for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
> > if (sar_freq_tab[i].val == freq) {
> > -#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
> > +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined
> (CONFIG_MSYS)
> > *sar_freq = sar_freq_tab[i];
> > return;
> > #else
> > @@ -270,6 +284,20 @@ int print_cpuinfo(void)
> > }
> > }
> >
> > + if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
> > + switch (revid) {
> > + case 3:
> > + puts("A0");
> > + break;
> > + case 4:
> > + puts("A1");
> > + break;
> > + default:
> > + printf("?? (%x)", revid);
> > + break;
> > + }
> > + }
> > +
> > get_sar_freq(&sar_freq);
> > printf(" at %d MHz\n", sar_freq.p_clk);
> >
> > diff --git a/arch/arm/mach-mvebu/include/mach/config.h
> b/arch/arm/mach-mvebu/include/mach/config.h
> > index e3235fc67ecd..a78fbe5cc97b 100644
> > --- a/arch/arm/mach-mvebu/include/mach/config.h
> > +++ b/arch/arm/mach-mvebu/include/mach/config.h
> > @@ -17,7 +17,7 @@
> > #include <asm/arch/soc.h>
> >
> > #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
> > - || defined(CONFIG_ARMADA_38X)
> > + || defined(CONFIG_ARMADA_38X) || defined(CONFIG_MSYS)
> > /*
> > * Set this for the common xor register definitions needed in dram.c
> > * for A38x as well here.
> > diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h
> b/arch/arm/mach-mvebu/include/mach/cpu.h
> > index 9e23043a4857..b9153d86c669 100644
> > --- a/arch/arm/mach-mvebu/include/mach/cpu.h
> > +++ b/arch/arm/mach-mvebu/include/mach/cpu.h
> > @@ -34,6 +34,7 @@ enum cpu_target {
> > CPU_TARGET_PCIE02 = 0x4,
> > CPU_TARGET_ETH01 = 0x7,
> > CPU_TARGET_PCIE13 = 0x8,
> > + CPU_TARGET_DFX = 0x8,
> > CPU_TARGET_SASRAM = 0x9,
> > CPU_TARGET_SATA01 = 0xa, /* A38X */
> > CPU_TARGET_NAND = 0xd,
> > @@ -79,6 +80,8 @@ enum {
> > #define MBUS_PCI_IO_SIZE (64 << 10)
> > #define MBUS_SPI_BASE 0xF4000000
> > #define MBUS_SPI_SIZE (8 << 20)
> > +#define MBUS_DFX_BASE 0xF6000000
> > +#define MBUS_DFX_SIZE (1 << 20)
> > #define MBUS_BOOTROM_BASE 0xF8000000
> > #define MBUS_BOOTROM_SIZE (8 << 20)
> >
> > diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
> b/arch/arm/mach-mvebu/include/mach/soc.h
> > index 01577f469b0e..a7039516864e 100644
> > --- a/arch/arm/mach-mvebu/include/mach/soc.h
> > +++ b/arch/arm/mach-mvebu/include/mach/soc.h
> > @@ -76,7 +76,11 @@
> > #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
> > #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
> > #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
> > +#ifdef CONFIG_MSYS
> > +#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
> > +#else
> > #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
> > +#endif
> >
> > #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
> > #define MBUS_ERR_PROP_EN (1 << 8)
> > @@ -149,6 +153,22 @@
> > #define BOOT_FROM_SPI 0x32
> > #define BOOT_FROM_MMC 0x30
> > #define BOOT_FROM_MMC_ALT 0x31
> > +#elif defined(CONFIG_MSYS)
> > +/* SAR values for MSYS */
> > +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
> > +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
> > +
> > +#define SAR_CPU_FREQ_OFFS 18
> > +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
> > +#define SAR_BOOT_DEVICE_OFFS 11
> > +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
> > +
> > +#define BOOT_DEV_SEL_OFFS 11
> > +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
> > +
> > +#define BOOT_FROM_NAND 0x1
> > +#define BOOT_FROM_UART 0x2
> > +#define BOOT_FROM_SPI 0x3
> > #else
> > /* SAR values for Armada XP */
> > #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
> > diff --git a/drivers/ddr/marvell/axp/xor_regs.h
> b/drivers/ddr/marvell/axp/xor_regs.h
> > index db5c41967393..bad41a3f3c1b 100644
> > --- a/drivers/ddr/marvell/axp/xor_regs.h
> > +++ b/drivers/ddr/marvell/axp/xor_regs.h
> > @@ -13,7 +13,11 @@
> > #define XOR_UNIT(chan) ((chan) >> 1)
> > #define XOR_CHAN(chan) ((chan) & 1)
> >
> > +#ifdef CONFIG_MSYS
> > +#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
> > +#else
> > #define MV_XOR_REGS_OFFSET(unit) (0x60900)
> > +#endif
> > #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
> >
> > /* XOR Engine Control Register Map */
> >
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board
2019-02-15 10:17 ` Stefan Roese
@ 2019-02-15 12:18 ` Chris Packham
0 siblings, 0 replies; 10+ messages in thread
From: Chris Packham @ 2019-02-15 12:18 UTC (permalink / raw)
To: u-boot
On Fri, 15 Feb 2019, 11:17 PM Stefan Roese <sr@denx.de wrote:
> Hi Chris,
>
> please find a few comments / questions below.
>
> On 15.02.19 10:41, Chris Packham wrote:
> > From: Chris Packham <chris.packham@alliedtelesis.co.nz>
> >
> > The DB-XC3-24G4XG is a switch development board from Marvell. It can
> > either use and external CPU card such as the db-88f6820-amc or the
> > internal CPU that is integrated into the switch.
> >
> > Add support for running U-Boot on the internal CPU and enable the USB,
> > SPI and NAND peripherals. For now this needs the bin_hdr from the
> > Marvell U-Boot for this board.
> >
> > Signed-off-by: Chris Packham <judge.packham@gmail.com>
> > ---
> >
> > arch/arm/dts/Makefile | 3 +-
> > arch/arm/dts/armada-xp-98dx3236.dtsi | 343 ++++++++++++++++++++
> > arch/arm/dts/armada-xp-98dx3336.dtsi | 39 +++
> > arch/arm/dts/armada-xp-98dx4251.dtsi | 54 +++
> > arch/arm/dts/armada-xp-db-xc3-24g4xg.dts | 122 +++++++
> > arch/arm/mach-mvebu/Kconfig | 8 +
> > board/Marvell/db-xc3-24g4xg/MAINTAINERS | 7 +
> > board/Marvell/db-xc3-24g4xg/Makefile | 5 +
> > board/Marvell/db-xc3-24g4xg/README | 4 +
> > board/Marvell/db-xc3-24g4xg/binary.0 | 11 +
> > board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c | 71 ++++
> > board/Marvell/db-xc3-24g4xg/kwbimage.cfg | 12 +
> > configs/db-xc3-24g4xg_defconfig | 55 ++++
> > include/configs/db-xc3-24g4xg.h | 45 +++
> > tools/Makefile | 4 +
> > tools/kwbimage.c | 4 +
>
> Could you please split the kwbimage tool changes into a separate
> patch?
>
Yes will do.
> > 16 files changed, 786 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi
> > create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi
> > create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi
> > create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > create mode 100644 board/Marvell/db-xc3-24g4xg/MAINTAINERS
> > create mode 100644 board/Marvell/db-xc3-24g4xg/Makefile
> > create mode 100644 board/Marvell/db-xc3-24g4xg/README
> > create mode 100644 board/Marvell/db-xc3-24g4xg/binary.0
> > create mode 100644 board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> > create mode 100644 board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> > create mode 100644 configs/db-xc3-24g4xg_defconfig
> > create mode 100644 include/configs/db-xc3-24g4xg.h
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index ca5062348087..133f09d8ba63 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
> > armada-xp-theadorable.dtb \
> > armada-38x-controlcenterdc.dtb \
> > armada-385-atl-x530.dtb \
> > - armada-385-atl-x530DP.dtb
> > + armada-385-atl-x530DP.dtb \
> > + armada-xp-db-xc3-24g4xg.dtb
> >
> > dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
> > uniphier-ld11-global.dtb \
> > diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi
> b/arch/arm/dts/armada-xp-98dx3236.dtsi
> > new file mode 100644
> > index 000000000000..5df1d1848dbc
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
> > @@ -0,0 +1,343 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx3236 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx3236 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-370-xp.dtsi"
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + model = "Marvell 98DX3236 SoC";
> > + compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > + aliases {
> > + gpio0 = &gpio0;
> > + gpio1 = &gpio1;
> > + gpio2 = &gpio2;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + enable-method = "marvell,98dx3236-smp";
> > +
> > + cpu at 0 {
> > + device_type = "cpu";
> > + compatible = "marvell,sheeva-v7";
> > + reg = <0>;
> > + clocks = <&cpuclk 0>;
> > + clock-latency = <1000000>;
> > + };
> > + };
> > +
> > + soc {
> > + compatible = "marvell,armadaxp-mbus", "simple-bus";
> > +
> > + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
> > + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
> > + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
> > + MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
> > + MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
> > +
> > + bootrom {
> > + compatible = "marvell,bootrom";
> > + reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
> > + };
> > +
> > + /*
> > + * 98DX3236 has 1 x1 PCIe unit Gen2.0
> > + */
> > + pciec: pcie at 82000000 {
> > + compatible = "marvell,armada-xp-pcie";
> > + status = "disabled";
> > + device_type = "pci";
> > +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > +
> > + msi-parent = <&mpic>;
> > + bus-range = <0x00 0xff>;
> > +
> > + ranges =
> > + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01)
> 0x40000 0 0x00002000 /* Port 0.0 registers */
> > + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8)
> 0 1 0 /* Port 0.0 MEM */
> > + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0)
> 0 1 0 /* Port 0.0 IO */>;
> > +
> > + pcie1: pcie at 1,0 {
> > + device_type = "pci";
> > + assigned-addresses = <0x82000800 0 0x40000
> 0 0x2000>;
> > + reg = <0x0800 0 0 0 0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + ranges = <0x82000000 0 0 0x82000000 0x1 0
> 1 0
> > + 0x81000000 0 0 0x81000000 0x1 0
> 1 0>;
> > + bus-range = <0x00 0xff>;
> > + interrupt-map-mask = <0 0 0 0>;
> > + interrupt-map = <0 0 0 0 &mpic 58>;
> > + marvell,pcie-port = <0>;
> > + marvell,pcie-lane = <0>;
> > + clocks = <&gateclk 5>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + internal-regs {
> > + sdramc: sdramc at 1400 {
> > + compatible =
> "marvell,armada-xp-sdram-controller";
> > + reg = <0x1400 0x500>;
> > + };
> > +
> > + L2: l2-cache at 8000 {
> > + compatible = "marvell,aurora-system-cache";
> > + reg = <0x08000 0x1000>;
> > + cache-id-part = <0x100>;
> > + cache-level = <2>;
> > + cache-unified;
> > + wt-override;
> > + };
> > +
> > + gpio0: gpio at 18100 {
> > + compatible = "marvell,orion-gpio";
> > + reg = <0x18100 0x40>;
> > + ngpios = <32>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <82>, <83>, <84>, <85>;
> > + };
> > +
> > + /* does not exist */
> > + gpio1: gpio at 18140 {
> > + compatible = "marvell,orion-gpio";
> > + reg = <0x18140 0x40>;
> > + status = "disabled";
> > + };
> > +
> > + gpio2: gpio at 18180 { /* rework some properties */
> > + compatible = "marvell,orion-gpio";
> > + reg = <0x18180 0x40>;
> > + ngpios = <1>; /* only gpio #32 */
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <87>;
> > + };
> > +
> > + systemc: system-controller at 18200 {
> > + compatible =
> "marvell,armada-370-xp-system-controller";
> > + reg = <0x18200 0x500>;
> > + };
> > +
> > + gateclk: clock-gating-control at 18220 {
> > + compatible =
> "marvell,mv98dx3236-gating-clock";
> > + reg = <0x18220 0x4>;
> > + clocks = <&coreclk 0>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + cpuclk: clock-complex at 18700 {
> > + #clock-cells = <1>;
> > + compatible =
> "marvell,mv98dx3236-cpu-clock";
> > + reg = <0x18700 0x24>, <0x1c054 0x10>;
> > + clocks = <&coreclk 1>;
> > + };
> > +
> > + corediv-clock at 18740 {
> > + status = "disabled";
> > + };
> > +
> > + cpu-config at 21000 {
> > + compatible =
> "marvell,armada-xp-cpu-config";
> > + reg = <0x21000 0x8>;
> > + };
> > +
> > + ethernet at 70000 {
> > + compatible = "marvell,armada-xp-neta";
> > + };
> > +
> > + ethernet at 74000 {
> > + compatible = "marvell,armada-xp-neta";
> > + };
> > +
> > + xor1: xor at f0800 {
> > + compatible = "marvell,orion-xor";
> > + reg = <0xf0800 0x100
> > + 0xf0a00 0x100>;
> > + clocks = <&gateclk 22>;
> > + status = "okay";
> > +
> > + xor10 {
> > + interrupts = <51>;
> > + dmacap,memcpy;
> > + dmacap,xor;
> > + };
> > + xor11 {
> > + interrupts = <52>;
> > + dmacap,memcpy;
> > + dmacap,xor;
> > + dmacap,memset;
> > + };
> > + };
> > +
> > + nand_controller: nand at d0000 {
> > + clocks = <&dfx_coredivclk 0>;
> > + };
> > +
> > + xor0: xor at f0900 {
> > + compatible = "marvell,orion-xor";
> > + reg = <0xF0900 0x100
> > + 0xF0B00 0x100>;
> > + clocks = <&gateclk 28>;
> > + status = "okay";
> > +
> > + xor00 {
> > + interrupts = <94>;
> > + dmacap,memcpy;
> > + dmacap,xor;
> > + };
> > + xor01 {
> > + interrupts = <95>;
> > + dmacap,memcpy;
> > + dmacap,xor;
> > + dmacap,memset;
> > + };
> > + };
> > + };
> > +
> > + dfx: dfx-server at ac000000 {
> > + compatible = "marvell,dfx-server", "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
> > + reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
> > +
> > + thermal: thermal at f8078 {
> > + compatible =
> "marvell,armada380-thermal";
> > + reg = <0xf8078 0x4>, <0xf8074 0x4>;
> > + status = "okay";
> > + };
> > +
> > + coreclk: mvebu-sar at f8204 {
> > + compatible =
> "marvell,mv98dx3236-core-clock";
> > + reg = <0xf8204 0x4>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + dfx_coredivclk: corediv-clock at f8268 {
> > + compatible =
> "marvell,mv98dx3236-corediv-clock";
> > + reg = <0xf8268 0xc>;
> > + #clock-cells = <1>;
> > + clocks = <&mainpll>;
> > + clock-output-names = "nand";
> > + };
> > + };
> > +
> > + switch: switch at a8000000 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
> > +
> > + pp0: packet-processor at 0 {
> > + compatible = "marvell,prestera-98dx3236",
> "marvell,prestera";
> > + reg = <0 0x4000000>;
> > + interrupts = <33>, <34>, <35>;
> > + dfx = <&dfx>;
> > + };
> > + };
> > + };
> > +
> > + clocks {
> > + /* 25 MHz reference crystal */
> > + refclk: oscillator {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <25000000>;
> > + };
> > + };
> > +};
> > +
> > +&i2c0 {
> > + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> > + reg = <0x11000 0x100>;
> > +};
> > +
> > +&i2c1 {
> > + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
> > + reg = <0x11100 0x100>;
> > +};
> > +
> > +&mpic {
> > + reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> > +};
> > +
> > +&rtc {
> > + status = "disabled";
> > +};
> > +
> > +&timer {
> > + compatible = "marvell,armada-xp-timer";
> > + clocks = <&coreclk 2>, <&refclk>;
> > + clock-names = "nbclk", "fixed";
> > +};
> > +
> > +&watchdog {
> > + compatible = "marvell,armada-xp-wdt";
> > + clocks = <&coreclk 2>, <&refclk>;
> > + clock-names = "nbclk", "fixed";
> > +};
> > +
> > +&cpurst {
> > + reg = <0x20800 0x20>;
> > +};
> > +
> > +&usb0 {
> > + clocks = <&gateclk 18>;
> > +};
> > +
> > +&usb1 {
> > + clocks = <&gateclk 19>;
> > +};
> > +
> > +&pinctrl {
> > + compatible = "marvell,98dx3236-pinctrl";
> > +
> > + nand_pins: nand-pins {
> > + marvell,pins = "mpp20", "mpp21", "mpp22",
> > + "mpp23", "mpp24", "mpp25",
> > + "mpp26", "mpp27", "mpp28",
> > + "mpp29", "mpp30";
> > + marvell,function = "dev";
> > + };
> > +
> > + nand_rb: nand-rb {
> > + marvell,pins = "mpp19";
> > + marvell,function = "nand";
> > + };
> > +
> > + spi0_pins: spi0-pins {
> > + marvell,pins = "mpp0", "mpp1",
> > + "mpp2", "mpp3";
> > + marvell,function = "spi0";
> > + };
> > +};
> > +
> > +&spi0 {
> > + compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
> > + pinctrl-0 = <&spi0_pins>;
> > + pinctrl-names = "default";
> > +};
> > +
> > +&sdio {
> > + status = "disabled";
> > +};
> > diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi
> b/arch/arm/dts/armada-xp-98dx3336.dtsi
> > new file mode 100644
> > index 000000000000..1d9d8a8ea60c
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx3336.dtsi
> > @@ -0,0 +1,39 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx3336 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx3236 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-xp-98dx3236.dtsi"
> > +
> > +/ {
> > + model = "Marvell 98DX3336 SoC";
> > + compatible = "marvell,armadaxp-98dx3336",
> "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > + cpus {
> > + cpu at 1 {
> > + device_type = "cpu";
> > + compatible = "marvell,sheeva-v7";
> > + reg = <1>;
> > + clocks = <&cpuclk 1>;
> > + clock-latency = <1000000>;
> > + };
> > + };
> > +
> > + soc {
> > + internal-regs {
> > + resume at 20980 {
> > + compatible =
> "marvell,98dx3336-resume-ctrl";
> > + reg = <0x20980 0x10>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&pp0 {
> > + compatible = "marvell,prestera-98dx3336", "marvell,prestera";
> > +};
> > diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi
> b/arch/arm/dts/armada-xp-98dx4251.dtsi
> > new file mode 100644
> > index 000000000000..48ffdc72bfc7
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-98dx4251.dtsi
> > @@ -0,0 +1,54 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree Include file for Marvell 98dx4521 family SoC
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Contains definitions specific to the 98dx4521 SoC that are not
> > + * common to all Armada XP SoCs.
> > + */
> > +
> > +#include "armada-xp-98dx3236.dtsi"
> > +
> > +/ {
> > + model = "Marvell 98DX4251 SoC";
> > + compatible = "marvell,armadaxp-98dx4251",
> "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
> > +
> > + cpus {
> > + cpu at 1 {
> > + device_type = "cpu";
> > + compatible = "marvell,sheeva-v7";
> > + reg = <1>;
> > + clocks = <&cpuclk 1>;
> > + clock-latency = <1000000>;
> > + };
> > + };
> > +
> > + soc {
> > + internal-regs {
> > + resume at 20980 {
> > + compatible =
> "marvell,98dx3336-resume-ctrl";
> > + reg = <0x20980 0x10>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&sdio {
> > + status = "okay";
> > +};
> > +
> > +&pinctrl {
> > + compatible = "marvell,98dx4251-pinctrl";
> > +
> > + sdio_pins: sdio-pins {
> > + marvell,pins = "mpp5", "mpp6", "mpp7",
> > + "mpp8", "mpp9", "mpp10";
> > + marvell,function = "sd0";
> > + };
> > +};
> > +
> > +&pp0 {
> > + compatible = "marvell,prestera-98dx4251", "marvell,prestera";
> > + interrupts = <33>, <34>, <35>, <36>;
> > +};
> > diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > new file mode 100644
> > index 000000000000..2daf83e655ac
> > --- /dev/null
> > +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree file for DB-XC3-24G4XG board
> > + *
> > + * Copyright (C) 2016 Allied Telesis Labs
> > + *
> > + * Based on armada-xp-db.dts
> > + *
> > + * Note: this Device Tree assumes that the bootloader has remapped the
> > + * internal registers to 0xf1000000 (instead of the default
> > + * 0xd0000000). The 0xf1000000 is the default used by the recent,
> > + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
> > + * boards were delivered with an older version of the bootloader that
> > + * left internal registers mapped at 0xd0000000. If you are in this
> > + * situation, you should either update your bootloader (preferred
> > + * solution) or the below Device Tree should be adjusted.
> > + */
> > +
> > +/dts-v1/;
> > +#include "armada-xp-98dx3336.dtsi"
> > +
> > +/ {
> > + model = "DB-XC3-24G4XG";
> > + compatible = "marvell,armadaxp-98dx3336",
> "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + bootargs = "console=ttyS0,115200 earlyprintk";
> > + };
> > +
> > + aliases {
> > + spi0 = &spi0;
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
> > + };
> > +};
> > +
> > +&L2 {
> > + arm,parity-enable;
> > + marvell,ecc-enable;
> > +};
> > +
> > +&devbus_bootcs {
> > + status = "okay";
> > +
> > + /* Device Bus parameters are required */
> > +
> > + /* Read parameters */
> > + devbus,bus-width = <16>;
> > + devbus,turn-off-ps = <60000>;
> > + devbus,badr-skew-ps = <0>;
> > + devbus,acc-first-ps = <124000>;
> > + devbus,acc-next-ps = <248000>;
> > + devbus,rd-setup-ps = <0>;
> > + devbus,rd-hold-ps = <0>;
> > +
> > + /* Write parameters */
> > + devbus,sync-enable = <0>;
> > + devbus,wr-high-ps = <60000>;
> > + devbus,wr-low-ps = <60000>;
> > + devbus,ale-wr-ps = <60000>;
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > + u-boot,dm-pre-reloc;
>
> All U-Boot specific DT properties into a *-u-boot.dtsi file please.
>
> > +};
> > +
> > +&uart1 {
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
> > + clock-frequency = <100000>;
> > + status = "okay";
> > +};
> > +
> > +&nand_controller {
> > + compatible="marvell,mvebu-pxa3xx-nand";
> > + status = "okay";
> > + label = "pxa3xx_nand-0";
> > + nand-rb = <0>;
> > + marvell,nand-keep-config;
> > + nand-on-flash-bbt;
> > + nand-ecc-strength = <4>;
> > + nand-ecc-step-size = <512>;
> > +};
> > +
> > +&usb0 {
> > + status = "okay";
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > + u-boot,dm-pre-reloc;
>
> Here as well and all other occurrences too please.
> > +
> > + spi-flash at 0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "spi-flash", "jedec,spi-nor";
> > + reg = <0>; /* Chip select 0 */
> > + spi-max-frequency = <108000000>;
> > + m25p,fast-read;
> > +
> > + partition at u-boot {
> > + reg = <0x00000000 0x00100000>;
> > + label = "u-boot";
> > + };
> > + partition at u-boot-env {
> > + reg = <0x00100000 0x00040000>;
> > + label = "u-boot-env";
> > + };
> > + partition at unused {
> > + reg = <0x00140000 0x00ec0000>;
> > + label = "unused";
> > + };
> > +
> > + };
> > +};
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 05aa2ade0499..938466615c66 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -152,6 +152,10 @@ config TARGET_X530
> > bool "Support Allied Telesis x530"
> > select 88F6820
> >
> > +config TARGET_DB_XC3_24G4XG
> > + bool "Support DB-XC3-24G4XG"
> > + select 98DX3336
> > +
> > endchoice
> >
> > config SYS_BOARD
> > @@ -170,6 +174,7 @@ config SYS_BOARD
> > default "theadorable" if TARGET_THEADORABLE
> > default "a38x" if TARGET_CONTROLCENTERDC
> > default "x530" if TARGET_X530
> > + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >
> > config SYS_CONFIG_NAME
> > default "clearfog" if TARGET_CLEARFOG
> > @@ -187,6 +192,7 @@ config SYS_CONFIG_NAME
> > default "turris_mox" if TARGET_TURRIS_MOX
> > default "controlcenterdc" if TARGET_CONTROLCENTERDC
> > default "x530" if TARGET_X530
> > + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
> >
> > config SYS_VENDOR
> > default "Marvell" if TARGET_DB_MV784MP_GP
> > @@ -195,6 +201,8 @@ config SYS_VENDOR
> > default "Marvell" if TARGET_DB_88F6820_GP
> > default "Marvell" if TARGET_DB_88F6820_AMC
> > default "Marvell" if TARGET_MVEBU_ARMADA_8K
> > + default "Marvell" if TARGET_DB_XC3_24G4XG
> > + default "Marvell" if TARGET_MVEBU_DB_88F7040
> > default "solidrun" if TARGET_CLEARFOG
> > default "kobol" if TARGET_HELIOS4
> > default "Synology" if TARGET_DS414
> > diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> > new file mode 100644
> > index 000000000000..94d4a901783b
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS
> > @@ -0,0 +1,7 @@
> > +DB-XC3-24G4XG BOARD
> > +M: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > +S: Maintained
> > +F: board/Marvell/db-xc3-24g4xg/
> > +F: include/configs/db-xc3-24g4xg.h
> > +F: configs/db-xc3-24g4xg-amc_defconfig
> > +F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts
> > diff --git a/board/Marvell/db-xc3-24g4xg/Makefile
> b/board/Marvell/db-xc3-24g4xg/Makefile
> > new file mode 100644
> > index 000000000000..199837a84fe6
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2015 Stefan Roese <sr@denx.de>
> > +
> > +obj-y := db-xc3-24g4xg.o
> > diff --git a/board/Marvell/db-xc3-24g4xg/README
> b/board/Marvell/db-xc3-24g4xg/README
> > new file mode 100644
> > index 000000000000..5e479b433e4d
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/README
> > @@ -0,0 +1,4 @@
> > +To generate binary.0 from Marvell's bin_hdr.elf use the following
> command
> > +
> > + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
> > + board/Marvell/db-xc3-24g4xg/binary.0
> > diff --git a/board/Marvell/db-xc3-24g4xg/binary.0
> b/board/Marvell/db-xc3-24g4xg/binary.0
> > new file mode 100644
> > index 000000000000..8dd687286a00
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/binary.0
> > @@ -0,0 +1,11 @@
> > +--------
> > +WARNING:
> > +--------
> > +This file should contain the bin_hdr generated by the original Marvell
> > +U-Boot implementation. As this is currently not included in this
> > +U-Boot version, we have added this placeholder, so that the U-Boot
> > +image can be generated without errors.
> > +
> > +If you have a known to be working bin_hdr for your board, then you
> > +just need to replace this text file here with the binary header
> > +and recompile U-Boot.
> > diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> > new file mode 100644
> > index 000000000000..428e3f611798
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c
> > @@ -0,0 +1,71 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> > + */
> > +
> > +#include <common.h>
> > +#include <i2c.h>
> > +#include <asm/gpio.h>
> > +#include <linux/mbus.h>
> > +#include <linux/io.h>
> > +#include <asm/arch/cpu.h>
> > +#include <asm/arch/soc.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/*
> > + * These values and defines are taken from the Marvell U-Boot version
> > + * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
> > + */
> > +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) |
> BIT(4) | BIT(6) | BIT(12) \
> > + | BIT(13) | BIT(16) | BIT(17) |
> BIT(20) | BIT(29) | BIT(30)))
> > +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
> > +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4)
> | BIT(6) | BIT(12) \
> > + | BIT(13) | BIT(16) | BIT(17) |
> BIT(20) | BIT(29) | BIT(30))
> > +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
> > +#define DB_DX_AC3_GPP_POL_LOW 0x0
> > +#define DB_DX_AC3_GPP_POL_MID 0x0
> > +
> > +int board_early_init_f(void)
> > +{
> > + /* Configure MPP */
> > + writel(0x00142222, MVEBU_MPP_BASE + 0x00);
> > + writel(0x11122000, MVEBU_MPP_BASE + 0x04);
> > + writel(0x44444004, MVEBU_MPP_BASE + 0x08);
> > + writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
> > + writel(0x00000001, MVEBU_MPP_BASE + 0x10);
> > +
> > + /* Set GPP Out value */
> > + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
> > + writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
> > +
> > + /* Set GPP Polarity */
> > + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
> > + writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
> > +
> > + /* Set GPP Out Enable */
> > + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
> > + writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
> > +
> > + return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > + /* address of boot parameters */
> > + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> > +
> > + /* Disable MBUS Err Prop - in order to avoid data aborts */
> > + clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8));
>
> Is this some change that should be done for all "MSYS" boards?
> If yes, then please move it to arch/arm/mach-mvebu instead.
>
Yes. I'll find a better home for it.
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_DISPLAY_BOARDINFO
> > +int checkboard(void)
> > +{
> > + puts("Board: " CONFIG_SYS_BOARD "\n");
> > +
> > + return 0;
> > +}
> > +#endif
> > diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> > new file mode 100644
> > index 000000000000..b8bb7a6eb75b
> > --- /dev/null
> > +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg
> > @@ -0,0 +1,12 @@
> > +#
> > +# Copyright (C) 2014 Stefan Roese <sr@denx.de>
> > +#
> > +
> > +# Armada XP uses version 1 image format
> > +VERSION 1
> > +
> > +# Boot Media configurations
> > +BOOT_FROM spi
> > +
> > +# Binary Header (bin_hdr) with DDR3 training code
> > +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068
> > diff --git a/configs/db-xc3-24g4xg_defconfig
> b/configs/db-xc3-24g4xg_defconfig
> > new file mode 100644
> > index 000000000000..0285ccaa365c
> > --- /dev/null
> > +++ b/configs/db-xc3-24g4xg_defconfig
> > @@ -0,0 +1,55 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_MVEBU=y
> > +CONFIG_SYS_TEXT_BASE=0x00800000
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_TARGET_DB_XC3_24G4XG=y
> > +CONFIG_BUILD_TARGET="u-boot.kwb"
> > +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> > +CONFIG_CMD_MEMTEST=y
> > +CONFIG_SYS_ALT_MEMTEST=y
> > +# CONFIG_CMD_FLASH is not set
> > +CONFIG_CMD_I2C=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_SETEXPR is not set
> > +CONFIG_CMD_DHCP=y
> > +CONFIG_CMD_TFTPPUT=y
> > +CONFIG_CMD_MII=y
> > +CONFIG_CMD_PING=y
> > +CONFIG_CMD_CACHE=y
> > +CONFIG_CMD_TIME=y
> > +CONFIG_CMD_EXT2=y
> > +CONFIG_CMD_EXT4=y
> > +CONFIG_CMD_FAT=y
> > +CONFIG_CMD_FS_GENERIC=y
> > +CONFIG_CMD_UBI=y
> > +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_SPL_OF_TRANSLATE=y
> > +CONFIG_BLK=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_MVTWSI=y
> > +# CONFIG_MMC is not set
> > +CONFIG_MTD=y
> > +CONFIG_MTD_DEVICE=y
> > +CONFIG_NAND=y
> > +CONFIG_NAND_PXA3XX=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_SPI_FLASH_SST=y
> > +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> > +CONFIG_PCI=y
> > +CONFIG_PCI_MVEBU=y
> > +CONFIG_SYS_NS16550=y
> > +CONFIG_KIRKWOOD_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_STORAGE=y
> > +CONFIG_USB_HOST_ETHER=y
> > +CONFIG_USB_ETHER_ASIX=y
> > +CONFIG_USB_ETHER_RTL8152=y
> > +CONFIG_USB_ETHER_SMSC95XX=y
> > diff --git a/include/configs/db-xc3-24g4xg.h
> b/include/configs/db-xc3-24g4xg.h
> > new file mode 100644
> > index 000000000000..2638ff9d7577
> > --- /dev/null
> > +++ b/include/configs/db-xc3-24g4xg.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
> > + */
> > +
> > +#ifndef _CONFIG_DB_XC3_24G4G_H
> > +#define _CONFIG_DB_XC3_24G4G_H
> > +
> > +/*
> > + * High Level Configuration Options (easy to change)
> > + */
> > +
> > +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
> > +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
> > +
> > +/* SPI NOR flash default params, used by sf commands */
> > +#define CONFIG_SF_DEFAULT_SPEED 1000000
> > +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
>
> Do we still need these with the recent SPI flash changes? I
> did not test, I'm just curious, if those can be omitted and
> everything necessary gets extraced from the DT instead?
>
I wasn't sure so i left it in. You're probably right so I'll drop it if i
can.
> > +
> > +/* USB/EHCI configuration */
> > +#define CONFIG_EHCI_IS_TDI
> > +
> > +/* Environment in SPI NOR flash */
> > +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
> > +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
> > +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
> > +
> > +/* NAND */
> > +#define CONFIG_SYS_NAND_USE_FLASH_BBT
> > +#define CONFIG_SYS_NAND_ONFI_DETECTION
> > +
> > +/* Keep device tree and initrd in lower memory so the kernel can access
> them */
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "fdt_high=0x10000000\0" \
> > + "initrd_high=0x10000000\0"
> > +
> > +/*
> > + * mv-common.h should be defined after CMD configs since it used them
> > + * to enable certain macros
> > + */
> > +#include "mv-common.h"
> > +#undef CONFIG_SYS_MAXARGS
> > +#define CONFIG_SYS_MAXARGS 96
> > +
> > +#endif /* _CONFIG_DB_XC3_24G4G_H */
> > diff --git a/tools/Makefile b/tools/Makefile
> > index 081383d7a790..463f165f9572 100644
> > --- a/tools/Makefile
> > +++ b/tools/Makefile
> > @@ -148,6 +148,10 @@ ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
> > HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
> > endif
> >
> > +ifneq ($(CONFIG_MSYS),)
> > +HOSTCFLAGS_kwbimage.o += -DCONFIG_MSYS
> > +endif
> > +
>
> Again, please move into a seperate patch.
>
> > # MXSImage needs LibSSL
> > ifneq
> ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE),)
> > HOSTLOADLIBES_mkimage += \
> > diff --git a/tools/kwbimage.c b/tools/kwbimage.c
> > index a88a3830c0c8..8d60dc001112 100644
> > --- a/tools/kwbimage.c
> > +++ b/tools/kwbimage.c
> > @@ -1252,8 +1252,12 @@ static void *image_create_v1(size_t *imagesz,
> struct image_tool_params *params,
> > cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
> > main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
> > main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
> > +#ifdef CONFIG_MSYS
> > + main_hdr->destaddr = cpu_to_le32(params->addr);
> > +#else
> > main_hdr->destaddr = cpu_to_le32(params->addr)
>
> Why is this change necessary? Could you please explain?
>
Because of using binary.0 instead of an SPL. The code that introduced this
was dealing with an extra image header that is included before kwb is
generated so destaddr needs to account for that. Because I don't have a SPL
(yet) I'm just taking bin_hdr from the Marvell u-boot and objcopying it to
get binary.0 which doesn't have the header so destaddr == execaddr.
I'll try and include this information int the commit message for the
kwbimage patch.
> Thanks,
> Stefan
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs
2019-02-15 11:57 ` Chris Packham
@ 2019-02-15 12:38 ` Stefan Roese
0 siblings, 0 replies; 10+ messages in thread
From: Stefan Roese @ 2019-02-15 12:38 UTC (permalink / raw)
To: u-boot
Hi Chis,
On 15.02.19 12:57, Chris Packham wrote:
>
>
> On Fri, 15 Feb 2019, 11:06 PM Stefan Roese <sr at denx.de <mailto:sr@denx.de> wrote:
>
> Hi Chris,
>
> On 15.02.19 10:41, Chris Packham wrote:
> > Marvell's switch chips with integrated CPUs (collectively referred to as
> > MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
> > (e.g. xor) are located at different addresses and DFX server exists as a
> > separate target on the MBUS (on Armada-38x it's just part of the core
> > complex registers).
> >
> > Signed-off-by: Chris Packham <judge.packham at gmail.com <mailto:judge.packham@gmail.com>>
> > ---
> >
> > arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++-
> > arch/arm/mach-mvebu/Makefile | 1 +
> > arch/arm/mach-mvebu/cpu.c | 32 +++++++++++++++++++++--
> > arch/arm/mach-mvebu/include/mach/config.h | 2 +-
> > arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++
> > arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++
> > drivers/ddr/marvell/axp/xor_regs.h | 4 +++
> > 7 files changed, 76 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index 7dda04e0e34e..05aa2ade0499 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -46,7 +46,7 @@ config ARMADA_8K
> > # Armada PLL frequency (used for NAND clock generation)
> > config SYS_MVEBU_PLL_CLOCK
> > int
> > - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
> > + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || MSYS
>
> I personally find this "MSYS" abbreviation quite short and not
> descriptive. How is this handled (if at all yet) in Linux?
>
>
> I did briefly consider ARMADA_MSYS. But settled on MSYS because that's
> how Marvell tend to refer to it. Marvells code uses MSYS, XCAT3, AC3
> and BC2 depending on how specific they need to be (e.g. the ddr code
> needs to distinguish AC3 and BC2).
I see. But now CONFIG_MSYS is mostly used vs CONFIG_ARMADA_38X etc.
I personally find this now clear and would prefer CONFIG_ARMADA_MSYS
over CONFIG_MSYS. You can always define CONFIG_MSYS in some DDR code
header, once this should be integrated.
> In Linux I originally proposed MSYS but eventually we went with
> MV98DX3326 as the base and used the other chip names where needed.
> But that mostly works out because the arch code is generic so the
> things that use these names are mostly compat strings.
I see. Isn't there any CONFIG_MACH_foo set for this SoC type (like
CONFIG_MACH_ARMADA_38X) in Linux? Or is CONFIG_MACH_ARMADA_XP selected
for this SoC as well?
Still, if we need to make this distinction in U-Boot (compared to the
more generic arch code in Linux), I would prefer CONFIG_ARMADA_MSYS
compared to CONFIG_MSYS or CONFIG_MV98DX3326.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-02-15 12:38 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-15 9:41 [U-Boot] [PATCH 0/4] Marvell DB-XC3-24G4XG board support Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 1/4] arm: sync armada-xp dts files from Linux 5.0 Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 2/4] arm: mvebu: Add Marvell's integrated CPUs Chris Packham
2019-02-15 10:06 ` Stefan Roese
2019-02-15 11:57 ` Chris Packham
2019-02-15 12:38 ` Stefan Roese
2019-02-15 9:41 ` [U-Boot] [PATCH 3/4] arm: mvebu: NAND clock support for MSYS devices Chris Packham
2019-02-15 9:41 ` [U-Boot] [PATCH 4/4] arm: mvebu: Add DB-XC3-24G4XG board Chris Packham
2019-02-15 10:17 ` Stefan Roese
2019-02-15 12:18 ` Chris Packham
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