* [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations
@ 2019-02-15 10:00 Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 01/17] target/ppc: convert VMX logical instructions to use " Mark Cave-Ayland
` (17 more replies)
0 siblings, 18 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
Now that all the pre-requisite patches and bugfixes have been merged, here is
the remainder of Richard's "tcg, target/ppc vector improvements" patchset that
converts various PPC VMX/VSX instructions over to use TCG vector operations.
Compared to the original posted patchset I've made a few minor changes:
- A fix to the boffs calculation for little-endian hosts in patch 4
(already reported and fixed on-list)
- A formatting fix to patch 8 to keep checkpatch happy
- Added David's A-B tags from the original series
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland (2):
target/ppc: convert VMX logical instructions to use vector operations
target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use
vector operations
Richard Henderson (15):
target/ppc: convert vspltis[bhw] to use vector operations
target/ppc: convert vsplt[bhw] to use vector operations
target/ppc: convert VSX logical operations to vector operations
target/ppc: convert xxspltib to vector operations
target/ppc: convert xxspltw to vector operations
target/ppc: convert xxsel to vector operations
target/ppc: Pass integer to helper_mtvscr
target/ppc: Use helper_mtvscr for reset and gdb
target/ppc: Remove vscr_nj and vscr_sat
target/ppc: Add helper_mfvscr
target/ppc: Use mtvscr/mfvscr for vmstate
target/ppc: Add set_vscr_sat
target/ppc: Split out VSCR_SAT to a vector field
target/ppc: convert vadd*s and vsub*s to vector operations
target/ppc: convert vmin* and vmax* to vector operations
target/ppc/arch_dump.c | 3 +-
target/ppc/cpu.h | 6 +-
target/ppc/helper.h | 57 ++------
target/ppc/int_helper.c | 129 +++++-------------
target/ppc/machine.c | 44 ++++++-
target/ppc/translate.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 251 +++++++++++++++++++-----------------
target/ppc/translate/vsx-impl.inc.c | 147 +++++++++------------
target/ppc/translate_init.inc.c | 7 +-
9 files changed, 290 insertions(+), 355 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 01/17] target/ppc: convert VMX logical instructions to use vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 02/17] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over " Mark Cave-Ayland
` (16 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 47 +++++++++++++------------------------
2 files changed, 17 insertions(+), 31 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e169c43643..f66786254d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -24,6 +24,7 @@
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index f99d0284c2..c74932e5ee 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -266,45 +266,30 @@ GEN_VX_VMUL10(vmul10euq, 1, 0);
GEN_VX_VMUL10(vmul10cuq, 0, 1);
GEN_VX_VMUL10(vmul10ecuq, 1, 1);
-/* Logical operations */
-#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
+#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 avr; \
- \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- avr = tcg_temp_new_i64(); \
- \
- get_avr64(t0, rA(ctx->opcode), true); \
- get_avr64(t1, rB(ctx->opcode), true); \
- tcg_op(avr, t0, t1); \
- set_avr64(rD(ctx->opcode), avr, true); \
- \
- get_avr64(t0, rA(ctx->opcode), false); \
- get_avr64(t1, rB(ctx->opcode), false); \
- tcg_op(avr, t0, t1); \
- set_avr64(rD(ctx->opcode), avr, false); \
\
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(avr); \
+ tcg_op(vece, \
+ avr64_offset(rD(ctx->opcode), true), \
+ avr64_offset(rA(ctx->opcode), true), \
+ avr64_offset(rB(ctx->opcode), true), \
+ 16, 16); \
}
-GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
-GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
-GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
-GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
-GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
-GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
-GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
-GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
+/* Logical operations */
+GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
+GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
+GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
+GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
+GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
+GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
+GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
+GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 02/17] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over to use vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 01/17] target/ppc: convert VMX logical instructions to use " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 03/17] target/ppc: convert vspltis[bhw] " Mark Cave-Ayland
` (15 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 8 --------
target/ppc/int_helper.c | 7 -------
target/ppc/translate/vmx-impl.inc.c | 16 ++++++++--------
3 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c7de04e068..553ff500c8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -108,14 +108,6 @@ DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64)
#define dh_ctype_avr ppc_avr_t *
#define dh_is_signed_avr dh_is_signed_ptr
-DEF_HELPER_3(vaddubm, void, avr, avr, avr)
-DEF_HELPER_3(vadduhm, void, avr, avr, avr)
-DEF_HELPER_3(vadduwm, void, avr, avr, avr)
-DEF_HELPER_3(vaddudm, void, avr, avr, avr)
-DEF_HELPER_3(vsububm, void, avr, avr, avr)
-DEF_HELPER_3(vsubuhm, void, avr, avr, avr)
-DEF_HELPER_3(vsubuwm, void, avr, avr, avr)
-DEF_HELPER_3(vsubudm, void, avr, avr, avr)
DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
DEF_HELPER_3(vavguw, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 8efc283388..ffccda8b9b 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -515,13 +515,6 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
r->element[i] = a->element[i] op b->element[i]; \
} \
}
-#define VARITH(suffix, element) \
- VARITH_DO(add##suffix, +, element) \
- VARITH_DO(sub##suffix, -, element)
-VARITH(ubm, u8)
-VARITH(uhm, u16)
-VARITH(uwm, u32)
-VARITH(udm, u64)
VARITH_DO(muluwm, *, u32)
#undef VARITH_DO
#undef VARITH
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index c74932e5ee..b104c6e38e 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -395,18 +395,18 @@ static void glue(gen_, name)(DisasContext *ctx) \
tcg_temp_free_ptr(rb); \
}
-GEN_VXFORM(vaddubm, 0, 0);
+GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
-GEN_VXFORM(vadduhm, 0, 1);
+GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
vmul10ecuq, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM(vadduwm, 0, 2);
-GEN_VXFORM(vaddudm, 0, 3);
-GEN_VXFORM(vsububm, 0, 16);
-GEN_VXFORM(vsubuhm, 0, 17);
-GEN_VXFORM(vsubuwm, 0, 18);
-GEN_VXFORM(vsubudm, 0, 19);
+GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
+GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
+GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
+GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
+GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
+GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
GEN_VXFORM(vmaxub, 1, 0);
GEN_VXFORM(vmaxuh, 1, 1);
GEN_VXFORM(vmaxuw, 1, 2);
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 03/17] target/ppc: convert vspltis[bhw] to use vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 01/17] target/ppc: convert VMX logical instructions to use " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 02/17] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 04/17] target/ppc: convert vsplt[bhw] " Mark Cave-Ayland
` (14 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/helper.h | 3 ---
target/ppc/int_helper.c | 15 ---------------
target/ppc/translate/vmx-impl.inc.c | 36 ++++++++----------------------------
3 files changed, 8 insertions(+), 46 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 553ff500c8..2aa60e5d36 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -246,9 +246,6 @@ DEF_HELPER_3(vrld, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
-DEF_HELPER_2(vspltisb, void, avr, i32)
-DEF_HELPER_2(vspltish, void, avr, i32)
-DEF_HELPER_2(vspltisw, void, avr, i32)
DEF_HELPER_3(vspltb, void, avr, avr, i32)
DEF_HELPER_3(vsplth, void, avr, avr, i32)
DEF_HELPER_3(vspltw, void, avr, avr, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ffccda8b9b..2f793a3543 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1998,21 +1998,6 @@ VNEG(vnegw, s32)
VNEG(vnegd, s64)
#undef VNEG
-#define VSPLTI(suffix, element, splat_type) \
- void helper_vspltis##suffix(ppc_avr_t *r, uint32_t splat) \
- { \
- splat_type x = (int8_t)(splat << 3) >> 3; \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- r->element[i] = x; \
- } \
- }
-VSPLTI(b, s8, int8_t)
-VSPLTI(h, s16, int16_t)
-VSPLTI(w, s32, int32_t)
-#undef VSPLTI
-
#define VSR(suffix, element, mask) \
void helper_vsr##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index b104c6e38e..c26c342e16 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -704,25 +704,21 @@ GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
-#define GEN_VXFORM_SIMM(name, opc2, opc3) \
+#define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv_ptr rd; \
- TCGv_i32 simm; \
+ int simm; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
- simm = tcg_const_i32(SIMM5(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name (rd, simm); \
- tcg_temp_free_i32(simm); \
- tcg_temp_free_ptr(rd); \
+ simm = SIMM5(ctx->opcode); \
+ tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \
}
-GEN_VXFORM_SIMM(vspltisb, 6, 12);
-GEN_VXFORM_SIMM(vspltish, 6, 13);
-GEN_VXFORM_SIMM(vspltisw, 6, 14);
+GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
+GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13);
+GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14);
#define GEN_VXFORM_NOA(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
@@ -802,22 +798,6 @@ GEN_VXFORM_NOA(vprtybw, 1, 24);
GEN_VXFORM_NOA(vprtybd, 1, 24);
GEN_VXFORM_NOA(vprtybq, 1, 24);
-#define GEN_VXFORM_SIMM(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rd; \
- TCGv_i32 simm; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- simm = tcg_const_i32(SIMM5(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name (rd, simm); \
- tcg_temp_free_i32(simm); \
- tcg_temp_free_ptr(rd); \
- }
-
#define GEN_VXFORM_UIMM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
@@ -1240,7 +1220,7 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
#undef GEN_VXRFORM_DUAL
#undef GEN_VXRFORM1
#undef GEN_VXRFORM
-#undef GEN_VXFORM_SIMM
+#undef GEN_VXFORM_DUPI
#undef GEN_VXFORM_NOA
#undef GEN_VXFORM_UIMM
#undef GEN_VAFORM_PAIRED
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 04/17] target/ppc: convert vsplt[bhw] to use vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (2 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 03/17] target/ppc: convert vspltis[bhw] " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 05/17] target/ppc: convert VSX logical operations to " Mark Cave-Ayland
` (13 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 3 ---
target/ppc/int_helper.c | 19 ---------------
target/ppc/translate/vmx-impl.inc.c | 46 ++++++++++++++++++++++---------------
3 files changed, 27 insertions(+), 41 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2aa60e5d36..069daa9883 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -246,9 +246,6 @@ DEF_HELPER_3(vrld, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
-DEF_HELPER_3(vspltb, void, avr, avr, i32)
-DEF_HELPER_3(vsplth, void, avr, avr, i32)
-DEF_HELPER_3(vspltw, void, avr, avr, i32)
DEF_HELPER_3(vextractub, void, avr, avr, i32)
DEF_HELPER_3(vextractuh, void, avr, avr, i32)
DEF_HELPER_3(vextractuw, void, avr, avr, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 2f793a3543..5c9623e952 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1869,25 +1869,6 @@ void helper_vslo(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
#endif
}
-/* Experimental testing shows that hardware masks the immediate. */
-#define _SPLAT_MASKED(element) (splat & (ARRAY_SIZE(r->element) - 1))
-#define SPLAT_ELEMENT(element) _SPLAT_MASKED(element)
-#define VSPLT(suffix, element, access) \
- void helper_vsplt##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \
- { \
- uint32_t s = b->access(SPLAT_ELEMENT(element)); \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- r->access(i) = s; \
- } \
- }
-VSPLT(b, u8, VsrB)
-VSPLT(h, u16, VsrH)
-VSPLT(w, u32, VsrW)
-#undef VSPLT
-#undef SPLAT_ELEMENT
-#undef _SPLAT_MASKED
#if defined(HOST_WORDS_BIGENDIAN)
#define VINSERT(suffix, element) \
void helper_vinsert##suffix(ppc_avr_t *r, ppc_avr_t *b, uint32_t index) \
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index c26c342e16..41ddbd879f 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -798,24 +798,32 @@ GEN_VXFORM_NOA(vprtybw, 1, 24);
GEN_VXFORM_NOA(vprtybd, 1, 24);
GEN_VXFORM_NOA(vprtybq, 1, 24);
-#define GEN_VXFORM_UIMM(name, opc2, opc3) \
-static void glue(gen_, name)(DisasContext *ctx) \
- { \
- TCGv_ptr rb, rd; \
- TCGv_i32 uimm; \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
- rb = gen_avr_ptr(rB(ctx->opcode)); \
- rd = gen_avr_ptr(rD(ctx->opcode)); \
- gen_helper_##name (rd, rb, uimm); \
- tcg_temp_free_i32(uimm); \
- tcg_temp_free_ptr(rb); \
- tcg_temp_free_ptr(rd); \
+static void gen_vsplt(DisasContext *ctx, int vece)
+{
+ int uimm, dofs, bofs;
+
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
}
+ uimm = UIMM5(ctx->opcode);
+ bofs = avr64_offset(rB(ctx->opcode), true);
+ dofs = avr64_offset(rD(ctx->opcode), true);
+
+ /* Experimental testing shows that hardware masks the immediate. */
+ bofs += (uimm << vece) & 15;
+#ifndef HOST_WORDS_BIGENDIAN
+ bofs ^= 15;
+ bofs &= ~((1 << vece) - 1);
+#endif
+
+ tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
+}
+
+#define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
+
#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
@@ -858,9 +866,9 @@ static void glue(gen_, name)(DisasContext *ctx) \
tcg_temp_free_ptr(rd); \
}
-GEN_VXFORM_UIMM(vspltb, 6, 8);
-GEN_VXFORM_UIMM(vsplth, 6, 9);
-GEN_VXFORM_UIMM(vspltw, 6, 10);
+GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
+GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
+GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 05/17] target/ppc: convert VSX logical operations to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (3 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 04/17] target/ppc: convert vsplt[bhw] " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 06/17] target/ppc: convert xxspltib " Mark Cave-Ayland
` (12 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 43 +++++++++++++++----------------------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index ed4fdceacf..2576d81ac5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -10,6 +10,11 @@ static inline void set_vsr(int n, TCGv_i64 src)
tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));
}
+static inline int vsr_full_offset(int n)
+{
+ return offsetof(CPUPPCState, vsr[n].u64[0]);
+}
+
static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
{
if (n < 32) {
@@ -1255,40 +1260,26 @@ static void gen_xxbrw(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
-#define VSX_LOGICAL(name, tcg_op) \
+#define VSX_LOGICAL(name, vece, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- get_cpu_vsrh(t0, xA(ctx->opcode)); \
- get_cpu_vsrh(t1, xB(ctx->opcode)); \
- tcg_op(t2, t0, t1); \
- set_cpu_vsrh(xT(ctx->opcode), t2); \
- get_cpu_vsrl(t0, xA(ctx->opcode)); \
- get_cpu_vsrl(t1, xB(ctx->opcode)); \
- tcg_op(t2, t0, t1); \
- set_cpu_vsrl(xT(ctx->opcode), t2); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
+ tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \
+ vsr_full_offset(xA(ctx->opcode)), \
+ vsr_full_offset(xB(ctx->opcode)), 16, 16); \
}
-VSX_LOGICAL(xxland, tcg_gen_and_i64)
-VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
-VSX_LOGICAL(xxlor, tcg_gen_or_i64)
-VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
-VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
-VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
-VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
-VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
+VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
+VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
+VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
+VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
+VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
+VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
+VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
+VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
#define VSX_XXMRG(name, high) \
static void glue(gen_, name)(DisasContext * ctx) \
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 06/17] target/ppc: convert xxspltib to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (4 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 05/17] target/ppc: convert VSX logical operations to " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 07/17] target/ppc: convert xxspltw " Mark Cave-Ayland
` (11 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2576d81ac5..944fc0608a 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1397,9 +1397,10 @@ static void gen_xxspltw(DisasContext *ctx)
static void gen_xxspltib(DisasContext *ctx)
{
- unsigned char uim8 = IMM8(ctx->opcode);
- TCGv_i64 vsr;
- if (xS(ctx->opcode) < 32) {
+ uint8_t uim8 = IMM8(ctx->opcode);
+ int rt = xT(ctx->opcode);
+
+ if (rt < 32) {
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
@@ -1410,11 +1411,7 @@ static void gen_xxspltib(DisasContext *ctx)
return;
}
}
- vsr = tcg_temp_new_i64();
- tcg_gen_movi_i64(vsr, pattern(uim8));
- set_cpu_vsrh(xT(ctx->opcode), vsr);
- set_cpu_vsrl(xT(ctx->opcode), vsr);
- tcg_temp_free_i64(vsr);
+ tcg_gen_gvec_dup8i(vsr_full_offset(rt), 16, 16, uim8);
}
static void gen_xxsldwi(DisasContext *ctx)
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 07/17] target/ppc: convert xxspltw to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (5 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 06/17] target/ppc: convert xxspltib " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 08/17] target/ppc: convert xxsel " Mark Cave-Ayland
` (10 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 36 +++++++++++-------------------------
1 file changed, 11 insertions(+), 25 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 944fc0608a..0e8cecb00a 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1359,38 +1359,24 @@ static void gen_xxsel(DisasContext * ctx)
static void gen_xxspltw(DisasContext *ctx)
{
- TCGv_i64 b, b2;
- TCGv_i64 vsr;
+ int rt = xT(ctx->opcode);
+ int rb = xB(ctx->opcode);
+ int uim = UIM(ctx->opcode);
+ int tofs, bofs;
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- vsr = tcg_temp_new_i64();
- if (UIM(ctx->opcode) & 2) {
- get_cpu_vsrl(vsr, xB(ctx->opcode));
- } else {
- get_cpu_vsrh(vsr, xB(ctx->opcode));
- }
-
- b = tcg_temp_new_i64();
- b2 = tcg_temp_new_i64();
-
- if (UIM(ctx->opcode) & 1) {
- tcg_gen_ext32u_i64(b, vsr);
- } else {
- tcg_gen_shri_i64(b, vsr, 32);
- }
-
- tcg_gen_shli_i64(b2, b, 32);
- tcg_gen_or_i64(vsr, b, b2);
- set_cpu_vsrh(xT(ctx->opcode), vsr);
- set_cpu_vsrl(xT(ctx->opcode), vsr);
+ tofs = vsr_full_offset(rt);
+ bofs = vsr_full_offset(rb);
+ bofs += uim << MO_32;
+#ifndef HOST_WORDS_BIG_ENDIAN
+ bofs ^= 8 | 4;
+#endif
- tcg_temp_free_i64(vsr);
- tcg_temp_free_i64(b);
- tcg_temp_free_i64(b2);
+ tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
}
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 08/17] target/ppc: convert xxsel to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (6 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 07/17] target/ppc: convert xxspltw " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 09/17] target/ppc: Pass integer to helper_mtvscr Mark Cave-Ayland
` (9 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 55 ++++++++++++++++++-------------------
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 0e8cecb00a..e73197e717 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1321,40 +1321,39 @@ static void glue(gen_, name)(DisasContext * ctx) \
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
-static void gen_xxsel(DisasContext * ctx)
+static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
{
- TCGv_i64 a, b, c, tmp;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- a = tcg_temp_new_i64();
- b = tcg_temp_new_i64();
- c = tcg_temp_new_i64();
- tmp = tcg_temp_new_i64();
-
- get_cpu_vsrh(a, xA(ctx->opcode));
- get_cpu_vsrh(b, xB(ctx->opcode));
- get_cpu_vsrh(c, xC(ctx->opcode));
-
tcg_gen_and_i64(b, b, c);
tcg_gen_andc_i64(a, a, c);
- tcg_gen_or_i64(tmp, a, b);
- set_cpu_vsrh(xT(ctx->opcode), tmp);
+ tcg_gen_or_i64(t, a, b);
+}
- get_cpu_vsrl(a, xA(ctx->opcode));
- get_cpu_vsrl(b, xB(ctx->opcode));
- get_cpu_vsrl(c, xC(ctx->opcode));
+static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a,
+ TCGv_vec b, TCGv_vec c)
+{
+ tcg_gen_and_vec(vece, b, b, c);
+ tcg_gen_andc_vec(vece, a, a, c);
+ tcg_gen_or_vec(vece, t, a, b);
+}
- tcg_gen_and_i64(b, b, c);
- tcg_gen_andc_i64(a, a, c);
- tcg_gen_or_i64(tmp, a, b);
- set_cpu_vsrl(xT(ctx->opcode), tmp);
+static void gen_xxsel(DisasContext *ctx)
+{
+ static const GVecGen4 g = {
+ .fni8 = xxsel_i64,
+ .fniv = xxsel_vec,
+ .vece = MO_64,
+ };
+ int rt = xT(ctx->opcode);
+ int ra = xA(ctx->opcode);
+ int rb = xB(ctx->opcode);
+ int rc = xC(ctx->opcode);
- tcg_temp_free_i64(a);
- tcg_temp_free_i64(b);
- tcg_temp_free_i64(c);
- tcg_temp_free_i64(tmp);
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra),
+ vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g);
}
static void gen_xxspltw(DisasContext *ctx)
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 09/17] target/ppc: Pass integer to helper_mtvscr
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (7 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 08/17] target/ppc: convert xxsel " Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 10/17] target/ppc: Use helper_mtvscr for reset and gdb Mark Cave-Ayland
` (8 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
We can re-use this helper elsewhere if we're not passing
in an entire vector register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 2 +-
target/ppc/int_helper.c | 6 +++---
target/ppc/translate/vmx-impl.inc.c | 17 +++++++++++++----
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 069daa9883..b3ffe28103 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -294,7 +294,7 @@ DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
-DEF_HELPER_2(mtvscr, void, env, avr)
+DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_3(lvebx, void, env, avr, tl)
DEF_HELPER_3(lvehx, void, env, avr, tl)
DEF_HELPER_3(lvewx, void, env, avr, tl)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 5c9623e952..aa6ad2ce7e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -457,10 +457,10 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh)
}
}
-void helper_mtvscr(CPUPPCState *env, ppc_avr_t *r)
+void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
{
- env->vscr = r->VsrW(3);
- set_flush_to_zero(vscr_nj, &env->vec_status);
+ env->vscr = vscr;
+ set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
}
void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 41ddbd879f..182d3fc563 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -196,14 +196,23 @@ static void gen_mfvscr(DisasContext *ctx)
static void gen_mtvscr(DisasContext *ctx)
{
- TCGv_ptr p;
+ TCGv_i32 val;
+ int bofs;
+
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
- p = gen_avr_ptr(rB(ctx->opcode));
- gen_helper_mtvscr(cpu_env, p);
- tcg_temp_free_ptr(p);
+
+ val = tcg_temp_new_i32();
+ bofs = avr64_offset(rB(ctx->opcode), true);
+#ifdef HOST_WORDS_BIGENDIAN
+ bofs += 3 * 4;
+#endif
+
+ tcg_gen_ld_i32(val, cpu_env, bofs);
+ gen_helper_mtvscr(cpu_env, val);
+ tcg_temp_free_i32(val);
}
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 10/17] target/ppc: Use helper_mtvscr for reset and gdb
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (8 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 09/17] target/ppc: Pass integer to helper_mtvscr Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 11/17] target/ppc: Remove vscr_nj and vscr_sat Mark Cave-Ayland
` (7 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Not setting flush_to_zero from gdb_set_avr_reg was a bug.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.inc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 59e0b86762..c8b2b760e5 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -601,10 +601,9 @@ static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
static inline void vscr_init(CPUPPCState *env, uint32_t val)
{
- env->vscr = val;
/* Altivec always uses round-to-nearest */
set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
- set_flush_to_zero(vscr_nj, &env->vec_status);
+ helper_mtvscr(env, val);
}
#ifdef CONFIG_USER_ONLY
@@ -9550,7 +9549,7 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
}
if (n == 32) {
ppc_maybe_bswap_register(env, mem_buf, 4);
- env->vscr = ldl_p(mem_buf);
+ helper_mtvscr(env, ldl_p(mem_buf));
return 4;
}
if (n == 33) {
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 11/17] target/ppc: Remove vscr_nj and vscr_sat
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (9 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 10/17] target/ppc: Use helper_mtvscr for reset and gdb Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 12/17] target/ppc: Add helper_mfvscr Mark Cave-Ayland
` (6 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
These macros are no longer used.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2c22292e7f..a62f628d28 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -688,8 +688,6 @@ enum {
/* Vector status and control register */
#define VSCR_NJ 16 /* Vector non-java */
#define VSCR_SAT 0 /* Vector saturation */
-#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
-#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
/*****************************************************************************/
/* BookE e500 MMU registers */
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 12/17] target/ppc: Add helper_mfvscr
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (10 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 11/17] target/ppc: Remove vscr_nj and vscr_sat Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate Mark Cave-Ayland
` (5 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
This is required before changing the representation of the register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/arch_dump.c | 3 ++-
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 5 +++++
target/ppc/translate/vmx-impl.inc.c | 2 +-
target/ppc/translate_init.inc.c | 2 +-
5 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c
index 3a00606d01..9ab04b2c38 100644
--- a/target/ppc/arch_dump.c
+++ b/target/ppc/arch_dump.c
@@ -17,6 +17,7 @@
#include "elf.h"
#include "sysemu/dump.h"
#include "sysemu/kvm.h"
+#include "exec/helper-proto.h"
#ifdef TARGET_PPC64
#define ELFCLASS ELFCLASS64
@@ -175,7 +176,7 @@ static void ppc_write_elf_vmxregset(NoteFuncArg *arg, PowerPCCPU *cpu)
vmxregset->avr[i].u64[1] = avr->u64[1];
}
}
- vmxregset->vscr.u32[3] = cpu_to_dump32(s, cpu->env.vscr);
+ vmxregset->vscr.u32[3] = cpu_to_dump32(s, helper_mfvscr(&cpu->env));
}
static void ppc_write_elf_vsxregset(NoteFuncArg *arg, PowerPCCPU *cpu)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index b3ffe28103..7dbb08b9dd 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -295,6 +295,7 @@ DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
DEF_HELPER_3(lvebx, void, env, avr, tl)
DEF_HELPER_3(lvehx, void, env, avr, tl)
DEF_HELPER_3(lvewx, void, env, avr, tl)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index aa6ad2ce7e..ec3ef9ff3f 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -463,6 +463,11 @@ void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
}
+uint32_t helper_mfvscr(CPUPPCState *env)
+{
+ return env->vscr;
+}
+
void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 182d3fc563..5e13edbf53 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -187,7 +187,7 @@ static void gen_mfvscr(DisasContext *ctx)
tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32();
- tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
+ gen_helper_mfvscr(t, cpu_env);
tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false);
tcg_temp_free_i32(t);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index c8b2b760e5..520d3e582b 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9520,7 +9520,7 @@ static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
return 16;
}
if (n == 32) {
- stl_p(mem_buf, env->vscr);
+ stl_p(mem_buf, helper_mfvscr(env));
ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (11 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 12/17] target/ppc: Add helper_mfvscr Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 11:14 ` [Qemu-devel] [Qemu-ppc] " BALATON Zoltan
2019-02-15 10:00 ` [Qemu-devel] [PATCH 14/17] target/ppc: Add set_vscr_sat Mark Cave-Ayland
` (4 subsequent siblings)
17 siblings, 1 reply; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
This is required before changing the representation of the register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/machine.c | 44 +++++++++++++++++++++++++++++++++++++++++---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index eff30053b0..756b6d2971 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -10,6 +10,7 @@
#include "migration/cpu.h"
#include "qapi/error.h"
#include "kvm_ppc.h"
+#include "exec/helper-proto.h"
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
@@ -17,7 +18,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
CPUPPCState *env = &cpu->env;
unsigned int i, j;
target_ulong sdr1;
- uint32_t fpscr;
+ uint32_t fpscr, vscr;
#if defined(TARGET_PPC64)
int32_t slb_nr;
#endif
@@ -84,7 +85,8 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
if (!cpu->vhyp) {
ppc_store_sdr1(env, sdr1);
}
- qemu_get_be32s(f, &env->vscr);
+ qemu_get_be32s(f, &vscr);
+ helper_mtvscr(env, vscr);
qemu_get_be64s(f, &env->spe_acc);
qemu_get_be32s(f, &env->spe_fscr);
qemu_get_betls(f, &env->msr_mask);
@@ -429,6 +431,28 @@ static bool altivec_needed(void *opaque)
return (cpu->env.insns_flags & PPC_ALTIVEC);
}
+static int get_vscr(QEMUFile *f, void *opaque, size_t size,
+ const VMStateField *field)
+{
+ PowerPCCPU *cpu = opaque;
+ helper_mtvscr(&cpu->env, qemu_get_be32(f));
+ return 0;
+}
+
+static int put_vscr(QEMUFile *f, void *opaque, size_t size,
+ const VMStateField *field, QJSON *vmdesc)
+{
+ PowerPCCPU *cpu = opaque;
+ qemu_put_be32(f, helper_mfvscr(&cpu->env));
+ return 0;
+}
+
+static const VMStateInfo vmstate_vscr = {
+ .name = "cpu/altivec/vscr",
+ .get = get_vscr,
+ .put = put_vscr,
+};
+
static const VMStateDescription vmstate_altivec = {
.name = "cpu/altivec",
.version_id = 1,
@@ -436,7 +460,21 @@ static const VMStateDescription vmstate_altivec = {
.needed = altivec_needed,
.fields = (VMStateField[]) {
VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32),
- VMSTATE_UINT32(env.vscr, PowerPCCPU),
+ /*
+ * Save the architecture value of the vscr, not the internally
+ * expanded version. Since this architecture value does not
+ * exist in memory to be stored, this requires a but of hoop
+ * jumping. We want OFFSET=0 so that we effectively pass CPU
+ * to the helper functions.
+ */
+ {
+ .name = "vscr",
+ .version_id = 0,
+ .size = sizeof(uint32_t),
+ .info = &vmstate_vscr,
+ .flags = VMS_SINGLE,
+ .offset = 0
+ },
VMSTATE_END_OF_LIST()
},
};
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 14/17] target/ppc: Add set_vscr_sat
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (12 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 15/17] target/ppc: Split out VSCR_SAT to a vector field Mark Cave-Ayland
` (3 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
This is required before changing the representation of the register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/int_helper.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ec3ef9ff3f..1d8a4b530b 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -468,6 +468,11 @@ uint32_t helper_mfvscr(CPUPPCState *env)
return env->vscr;
}
+static inline void set_vscr_sat(CPUPPCState *env)
+{
+ env->vscr |= 1 << VSCR_SAT;
+}
+
void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
@@ -581,7 +586,7 @@ VARITHFPFMA(nmsubfp, float_muladd_negate_result | float_muladd_negate_c);
} \
} \
if (sat) { \
- env->vscr |= (1 << VSCR_SAT); \
+ set_vscr_sat(env); \
} \
}
#define VARITHSAT_SIGNED(suffix, element, optype, cvt) \
@@ -853,7 +858,7 @@ void helper_vcmpbfp_dot(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
} \
} \
if (sat) { \
- env->vscr |= (1 << VSCR_SAT); \
+ set_vscr_sat(env); \
} \
}
VCT(uxs, cvtsduw, u32)
@@ -900,7 +905,7 @@ void helper_vmhaddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -917,7 +922,7 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -1029,7 +1034,7 @@ void helper_vmsumshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -1082,7 +1087,7 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -1599,7 +1604,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
} \
*r = result; \
if (dosat && sat) { \
- env->vscr |= (1 << VSCR_SAT); \
+ set_vscr_sat(env); \
} \
}
#define I(x, y) (x)
@@ -2043,7 +2048,7 @@ void helper_vsumsws(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
*r = result;
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -2066,7 +2071,7 @@ void helper_vsum2sws(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
*r = result;
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -2085,7 +2090,7 @@ void helper_vsum4sbs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -2102,7 +2107,7 @@ void helper_vsum4shs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
@@ -2121,7 +2126,7 @@ void helper_vsum4ubs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
if (sat) {
- env->vscr |= (1 << VSCR_SAT);
+ set_vscr_sat(env);
}
}
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 15/17] target/ppc: Split out VSCR_SAT to a vector field
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (13 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 14/17] target/ppc: Add set_vscr_sat Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 16/17] target/ppc: convert vadd*s and vsub*s to vector operations Mark Cave-Ayland
` (2 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Change the representation of VSCR_SAT such that it is easy
to set from vector code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 4 +++-
target/ppc/int_helper.c | 11 ++++++++---
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a62f628d28..171ec9739d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1051,10 +1051,12 @@ struct CPUPPCState {
/* Special purpose registers */
target_ulong spr[1024];
ppc_spr_t spr_cb[1024];
- /* Vector status and control register */
+ /* Vector status and control register, minus VSCR_SAT. */
uint32_t vscr;
/* VSX registers (including FP and AVR) */
ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
+ /* Non-zero if and only if VSCR_SAT should be set. */
+ ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
/* SPE registers */
uint64_t spe_acc;
uint32_t spe_fscr;
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 1d8a4b530b..6ad596a08b 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -459,18 +459,23 @@ void helper_lvsr(ppc_avr_t *r, target_ulong sh)
void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
{
- env->vscr = vscr;
+ env->vscr = vscr & ~(1u << VSCR_SAT);
+ /* Which bit we set is completely arbitrary, but clear the rest. */
+ env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
+ env->vscr_sat.u64[1] = 0;
set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
}
uint32_t helper_mfvscr(CPUPPCState *env)
{
- return env->vscr;
+ uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
+ return env->vscr | (sat << VSCR_SAT);
}
static inline void set_vscr_sat(CPUPPCState *env)
{
- env->vscr |= 1 << VSCR_SAT;
+ /* The choice of non-zero value is arbitrary. */
+ env->vscr_sat.u32[0] = 1;
}
void helper_vaddcuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 16/17] target/ppc: convert vadd*s and vsub*s to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (14 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 15/17] target/ppc: Split out VSCR_SAT to a vector field Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 17/17] target/ppc: convert vmin* and vmax* " Mark Cave-Ayland
2019-02-18 0:16 ` [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG " David Gibson
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 24 ++++++++--------
target/ppc/int_helper.c | 18 +++---------
target/ppc/translate/vmx-impl.inc.c | 57 +++++++++++++++++++++++++++++--------
3 files changed, 61 insertions(+), 38 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7dbb08b9dd..3daf6bf863 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -219,18 +219,18 @@ DEF_HELPER_2(vprtybq, void, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl)
DEF_HELPER_2(lvsr, void, avr, tl)
-DEF_HELPER_4(vaddsbs, void, env, avr, avr, avr)
-DEF_HELPER_4(vaddshs, void, env, avr, avr, avr)
-DEF_HELPER_4(vaddsws, void, env, avr, avr, avr)
-DEF_HELPER_4(vsubsbs, void, env, avr, avr, avr)
-DEF_HELPER_4(vsubshs, void, env, avr, avr, avr)
-DEF_HELPER_4(vsubsws, void, env, avr, avr, avr)
-DEF_HELPER_4(vaddubs, void, env, avr, avr, avr)
-DEF_HELPER_4(vadduhs, void, env, avr, avr, avr)
-DEF_HELPER_4(vadduws, void, env, avr, avr, avr)
-DEF_HELPER_4(vsububs, void, env, avr, avr, avr)
-DEF_HELPER_4(vsubuhs, void, env, avr, avr, avr)
-DEF_HELPER_4(vsubuws, void, env, avr, avr, avr)
+DEF_HELPER_FLAGS_5(vaddsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vaddshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vaddsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsubsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsubshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsubsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vaddubs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vadduhs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vadduws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsububs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsubuhs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_5(vsubuws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_3(vadduqm, void, avr, avr, avr)
DEF_HELPER_4(vaddecuq, void, avr, avr, avr, avr)
DEF_HELPER_4(vaddeuqm, void, avr, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 6ad596a08b..4aeb375edd 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -571,27 +571,17 @@ VARITHFPFMA(nmsubfp, float_muladd_negate_result | float_muladd_negate_c);
}
#define VARITHSAT_DO(name, op, optype, cvt, element) \
- void helper_v##name(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
- ppc_avr_t *b) \
+ void helper_v##name(ppc_avr_t *r, ppc_avr_t *vscr_sat, \
+ ppc_avr_t *a, ppc_avr_t *b, uint32_t desc) \
{ \
int sat = 0; \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- switch (sizeof(r->element[0])) { \
- case 1: \
- VARITHSAT_CASE(optype, op, cvt, element); \
- break; \
- case 2: \
- VARITHSAT_CASE(optype, op, cvt, element); \
- break; \
- case 4: \
- VARITHSAT_CASE(optype, op, cvt, element); \
- break; \
- } \
+ VARITHSAT_CASE(optype, op, cvt, element); \
} \
if (sat) { \
- set_vscr_sat(env); \
+ vscr_sat->u32[0] = 1; \
} \
}
#define VARITHSAT_SIGNED(suffix, element, optype, cvt) \
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 5e13edbf53..62c5578070 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -552,22 +552,55 @@ GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
-GEN_VXFORM_ENV(vaddubs, 0, 8);
+
+#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
+static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
+ TCGv_vec sat, TCGv_vec a, \
+ TCGv_vec b) \
+{ \
+ TCGv_vec x = tcg_temp_new_vec_matching(t); \
+ glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
+ glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
+ tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
+ tcg_gen_or_vec(VECE, sat, sat, x); \
+ tcg_temp_free_vec(x); \
+} \
+static void glue(gen_, NAME)(DisasContext *ctx) \
+{ \
+ static const GVecGen4 g = { \
+ .fniv = glue(glue(gen_, NAME), _vec), \
+ .fno = glue(gen_helper_, NAME), \
+ .opc = glue(glue(INDEX_op_, SAT), _vec), \
+ .write_aofs = true, \
+ .vece = VECE, \
+ }; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \
+ offsetof(CPUPPCState, vscr_sat), \
+ avr64_offset(rA(ctx->opcode), true), \
+ avr64_offset(rB(ctx->opcode), true), \
+ 16, 16, &g); \
+}
+
+GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
-GEN_VXFORM_ENV(vadduhs, 0, 9);
+GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
vmul10euq, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_ENV(vadduws, 0, 10);
-GEN_VXFORM_ENV(vaddsbs, 0, 12);
-GEN_VXFORM_ENV(vaddshs, 0, 13);
-GEN_VXFORM_ENV(vaddsws, 0, 14);
-GEN_VXFORM_ENV(vsububs, 0, 24);
-GEN_VXFORM_ENV(vsubuhs, 0, 25);
-GEN_VXFORM_ENV(vsubuws, 0, 26);
-GEN_VXFORM_ENV(vsubsbs, 0, 28);
-GEN_VXFORM_ENV(vsubshs, 0, 29);
-GEN_VXFORM_ENV(vsubsws, 0, 30);
+GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
+GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
+GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
+GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
+GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
+GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
+GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
+GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
+GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
+GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
GEN_VXFORM(vadduqm, 0, 4);
GEN_VXFORM(vaddcuq, 0, 5);
GEN_VXFORM3(vaddeuqm, 30, 0);
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 17/17] target/ppc: convert vmin* and vmax* to vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (15 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 16/17] target/ppc: convert vadd*s and vsub*s to vector operations Mark Cave-Ayland
@ 2019-02-15 10:00 ` Mark Cave-Ayland
2019-02-18 0:16 ` [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG " David Gibson
17 siblings, 0 replies; 20+ messages in thread
From: Mark Cave-Ayland @ 2019-02-15 10:00 UTC (permalink / raw)
To: qemu-devel, qemu-ppc, david, richard.henderson
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 16 ----------------
target/ppc/int_helper.c | 27 ---------------------------
target/ppc/translate/vmx-impl.inc.c | 32 ++++++++++++++++----------------
3 files changed, 16 insertions(+), 59 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3daf6bf863..18910d18a4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -117,22 +117,6 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
-DEF_HELPER_3(vminsb, void, avr, avr, avr)
-DEF_HELPER_3(vminsh, void, avr, avr, avr)
-DEF_HELPER_3(vminsw, void, avr, avr, avr)
-DEF_HELPER_3(vminsd, void, avr, avr, avr)
-DEF_HELPER_3(vmaxsb, void, avr, avr, avr)
-DEF_HELPER_3(vmaxsh, void, avr, avr, avr)
-DEF_HELPER_3(vmaxsw, void, avr, avr, avr)
-DEF_HELPER_3(vmaxsd, void, avr, avr, avr)
-DEF_HELPER_3(vminub, void, avr, avr, avr)
-DEF_HELPER_3(vminuh, void, avr, avr, avr)
-DEF_HELPER_3(vminuw, void, avr, avr, avr)
-DEF_HELPER_3(vminud, void, avr, avr, avr)
-DEF_HELPER_3(vmaxub, void, avr, avr, avr)
-DEF_HELPER_3(vmaxuh, void, avr, avr, avr)
-DEF_HELPER_3(vmaxuw, void, avr, avr, avr)
-DEF_HELPER_3(vmaxud, void, avr, avr, avr)
DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 4aeb375edd..162add561e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -921,33 +921,6 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
}
-#define VMINMAX_DO(name, compare, element) \
- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
- { \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- if (a->element[i] compare b->element[i]) { \
- r->element[i] = b->element[i]; \
- } else { \
- r->element[i] = a->element[i]; \
- } \
- } \
- }
-#define VMINMAX(suffix, element) \
- VMINMAX_DO(min##suffix, >, element) \
- VMINMAX_DO(max##suffix, <, element)
-VMINMAX(sb, s8)
-VMINMAX(sh, s16)
-VMINMAX(sw, s32)
-VMINMAX(sd, s64)
-VMINMAX(ub, u8)
-VMINMAX(uh, u16)
-VMINMAX(uw, u32)
-VMINMAX(ud, u64)
-#undef VMINMAX_DO
-#undef VMINMAX
-
void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 62c5578070..f1b15ae2cb 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -416,22 +416,22 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
-GEN_VXFORM(vmaxub, 1, 0);
-GEN_VXFORM(vmaxuh, 1, 1);
-GEN_VXFORM(vmaxuw, 1, 2);
-GEN_VXFORM(vmaxud, 1, 3);
-GEN_VXFORM(vmaxsb, 1, 4);
-GEN_VXFORM(vmaxsh, 1, 5);
-GEN_VXFORM(vmaxsw, 1, 6);
-GEN_VXFORM(vmaxsd, 1, 7);
-GEN_VXFORM(vminub, 1, 8);
-GEN_VXFORM(vminuh, 1, 9);
-GEN_VXFORM(vminuw, 1, 10);
-GEN_VXFORM(vminud, 1, 11);
-GEN_VXFORM(vminsb, 1, 12);
-GEN_VXFORM(vminsh, 1, 13);
-GEN_VXFORM(vminsw, 1, 14);
-GEN_VXFORM(vminsd, 1, 15);
+GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
+GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
+GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
+GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
+GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
+GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
+GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
+GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
+GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
+GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
+GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
+GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
+GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
+GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
+GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
+GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
GEN_VXFORM(vavgub, 1, 16);
GEN_VXFORM(vabsdub, 1, 16);
GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
--
2.11.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate
2019-02-15 10:00 ` [Qemu-devel] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate Mark Cave-Ayland
@ 2019-02-15 11:14 ` BALATON Zoltan
0 siblings, 0 replies; 20+ messages in thread
From: BALATON Zoltan @ 2019-02-15 11:14 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: qemu-devel, qemu-ppc, david, richard.henderson
On Fri, 15 Feb 2019, Mark Cave-Ayland wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> This is required before changing the representation of the register.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Acked-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/machine.c | 44 +++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 41 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/machine.c b/target/ppc/machine.c
> index eff30053b0..756b6d2971 100644
> --- a/target/ppc/machine.c
> +++ b/target/ppc/machine.c
> @@ -10,6 +10,7 @@
> #include "migration/cpu.h"
> #include "qapi/error.h"
> #include "kvm_ppc.h"
> +#include "exec/helper-proto.h"
>
> static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
> {
> @@ -17,7 +18,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
> CPUPPCState *env = &cpu->env;
> unsigned int i, j;
> target_ulong sdr1;
> - uint32_t fpscr;
> + uint32_t fpscr, vscr;
> #if defined(TARGET_PPC64)
> int32_t slb_nr;
> #endif
> @@ -84,7 +85,8 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
> if (!cpu->vhyp) {
> ppc_store_sdr1(env, sdr1);
> }
> - qemu_get_be32s(f, &env->vscr);
> + qemu_get_be32s(f, &vscr);
> + helper_mtvscr(env, vscr);
> qemu_get_be64s(f, &env->spe_acc);
> qemu_get_be32s(f, &env->spe_fscr);
> qemu_get_betls(f, &env->msr_mask);
> @@ -429,6 +431,28 @@ static bool altivec_needed(void *opaque)
> return (cpu->env.insns_flags & PPC_ALTIVEC);
> }
>
> +static int get_vscr(QEMUFile *f, void *opaque, size_t size,
> + const VMStateField *field)
> +{
> + PowerPCCPU *cpu = opaque;
> + helper_mtvscr(&cpu->env, qemu_get_be32(f));
> + return 0;
> +}
> +
> +static int put_vscr(QEMUFile *f, void *opaque, size_t size,
> + const VMStateField *field, QJSON *vmdesc)
> +{
> + PowerPCCPU *cpu = opaque;
> + qemu_put_be32(f, helper_mfvscr(&cpu->env));
> + return 0;
> +}
> +
> +static const VMStateInfo vmstate_vscr = {
> + .name = "cpu/altivec/vscr",
> + .get = get_vscr,
> + .put = put_vscr,
> +};
> +
> static const VMStateDescription vmstate_altivec = {
> .name = "cpu/altivec",
> .version_id = 1,
> @@ -436,7 +460,21 @@ static const VMStateDescription vmstate_altivec = {
> .needed = altivec_needed,
> .fields = (VMStateField[]) {
> VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32),
> - VMSTATE_UINT32(env.vscr, PowerPCCPU),
> + /*
> + * Save the architecture value of the vscr, not the internally
> + * expanded version. Since this architecture value does not
> + * exist in memory to be stored, this requires a but of hoop
Typo: but -> bit
Regards,
BALATON Zoltan
> + * jumping. We want OFFSET=0 so that we effectively pass CPU
> + * to the helper functions.
> + */
> + {
> + .name = "vscr",
> + .version_id = 0,
> + .size = sizeof(uint32_t),
> + .info = &vmstate_vscr,
> + .flags = VMS_SINGLE,
> + .offset = 0
> + },
> VMSTATE_END_OF_LIST()
> },
> };
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
` (16 preceding siblings ...)
2019-02-15 10:00 ` [Qemu-devel] [PATCH 17/17] target/ppc: convert vmin* and vmax* " Mark Cave-Ayland
@ 2019-02-18 0:16 ` David Gibson
17 siblings, 0 replies; 20+ messages in thread
From: David Gibson @ 2019-02-18 0:16 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: qemu-devel, qemu-ppc, richard.henderson
[-- Attachment #1: Type: text/plain, Size: 2540 bytes --]
On Fri, Feb 15, 2019 at 10:00:41AM +0000, Mark Cave-Ayland wrote:
> Now that all the pre-requisite patches and bugfixes have been merged, here is
> the remainder of Richard's "tcg, target/ppc vector improvements" patchset that
> converts various PPC VMX/VSX instructions over to use TCG vector operations.
>
> Compared to the original posted patchset I've made a few minor changes:
> - A fix to the boffs calculation for little-endian hosts in patch 4
> (already reported and fixed on-list)
> - A formatting fix to patch 8 to keep checkpatch happy
> - Added David's A-B tags from the original series
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Applied to ppc-for-4.0, thanks.
>
>
> Mark Cave-Ayland (2):
> target/ppc: convert VMX logical instructions to use vector operations
> target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use
> vector operations
>
> Richard Henderson (15):
> target/ppc: convert vspltis[bhw] to use vector operations
> target/ppc: convert vsplt[bhw] to use vector operations
> target/ppc: convert VSX logical operations to vector operations
> target/ppc: convert xxspltib to vector operations
> target/ppc: convert xxspltw to vector operations
> target/ppc: convert xxsel to vector operations
> target/ppc: Pass integer to helper_mtvscr
> target/ppc: Use helper_mtvscr for reset and gdb
> target/ppc: Remove vscr_nj and vscr_sat
> target/ppc: Add helper_mfvscr
> target/ppc: Use mtvscr/mfvscr for vmstate
> target/ppc: Add set_vscr_sat
> target/ppc: Split out VSCR_SAT to a vector field
> target/ppc: convert vadd*s and vsub*s to vector operations
> target/ppc: convert vmin* and vmax* to vector operations
>
> target/ppc/arch_dump.c | 3 +-
> target/ppc/cpu.h | 6 +-
> target/ppc/helper.h | 57 ++------
> target/ppc/int_helper.c | 129 +++++-------------
> target/ppc/machine.c | 44 ++++++-
> target/ppc/translate.c | 1 +
> target/ppc/translate/vmx-impl.inc.c | 251 +++++++++++++++++++-----------------
> target/ppc/translate/vsx-impl.inc.c | 147 +++++++++------------
> target/ppc/translate_init.inc.c | 7 +-
> 9 files changed, 290 insertions(+), 355 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2019-02-18 0:23 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-15 10:00 [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG vector operations Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 01/17] target/ppc: convert VMX logical instructions to use " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 02/17] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 03/17] target/ppc: convert vspltis[bhw] " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 04/17] target/ppc: convert vsplt[bhw] " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 05/17] target/ppc: convert VSX logical operations to " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 06/17] target/ppc: convert xxspltib " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 07/17] target/ppc: convert xxspltw " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 08/17] target/ppc: convert xxsel " Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 09/17] target/ppc: Pass integer to helper_mtvscr Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 10/17] target/ppc: Use helper_mtvscr for reset and gdb Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 11/17] target/ppc: Remove vscr_nj and vscr_sat Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 12/17] target/ppc: Add helper_mfvscr Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 13/17] target/ppc: Use mtvscr/mfvscr for vmstate Mark Cave-Ayland
2019-02-15 11:14 ` [Qemu-devel] [Qemu-ppc] " BALATON Zoltan
2019-02-15 10:00 ` [Qemu-devel] [PATCH 14/17] target/ppc: Add set_vscr_sat Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 15/17] target/ppc: Split out VSCR_SAT to a vector field Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 16/17] target/ppc: convert vadd*s and vsub*s to vector operations Mark Cave-Ayland
2019-02-15 10:00 ` [Qemu-devel] [PATCH 17/17] target/ppc: convert vmin* and vmax* " Mark Cave-Ayland
2019-02-18 0:16 ` [Qemu-devel] [PATCH 00/17] target/ppc: convert instructions to use TCG " David Gibson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.