From: Andrey Smirnov <andrew.smirnov@gmail.com> To: Shawn Guo <shawnguo@kernel.org> Cc: Andrey Smirnov <andrew.smirnov@gmail.com>, Lucas Stach <l.stach@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, Chris Healy <cphealy@gmail.com>, Leonard Crestez <leonard.crestez@nxp.com>, "A.s. Dong" <aisheng.dong@nxp.com>, Richard Zhu <hongxing.zhu@nxp.com>, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/5] arm64: dts: imx8mq: Combine PCIE power domains Date: Tue, 19 Feb 2019 17:58:55 -0800 [thread overview] Message-ID: <20190220015857.7136-4-andrew.smirnov@gmail.com> (raw) In-Reply-To: <20190220015857.7136-1-andrew.smirnov@gmail.com> According to NXP's FAE feedback and a comment in ATF firmware, PCIE1 and PCIE2 power domains can't really be used independently. Due to shared reset line both power domains have to be turned on at the same time. Account for that quirk by combining PCIE power domains into a single 'pgc_pcie' power domain. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 50436bd393ed..fca9b71de94f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -273,9 +273,25 @@ reg = <IMX8M_POWER_DOMAIN_MIPI>; }; - pgc_pcie1: power-domain@1 { + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_PCIE1>; + power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 { -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrey Smirnov <andrew.smirnov@gmail.com> To: Shawn Guo <shawnguo@kernel.org> Cc: "A.s. Dong" <aisheng.dong@nxp.com>, Richard Zhu <hongxing.zhu@nxp.com>, linux-arm-kernel@lists.infradead.org, Andrey Smirnov <andrew.smirnov@gmail.com>, linux-kernel@vger.kernel.org, linux-imx@nxp.com, Fabio Estevam <fabio.estevam@nxp.com>, Leonard Crestez <leonard.crestez@nxp.com>, Chris Healy <cphealy@gmail.com>, Lucas Stach <l.stach@pengutronix.de> Subject: [PATCH v3 3/5] arm64: dts: imx8mq: Combine PCIE power domains Date: Tue, 19 Feb 2019 17:58:55 -0800 [thread overview] Message-ID: <20190220015857.7136-4-andrew.smirnov@gmail.com> (raw) In-Reply-To: <20190220015857.7136-1-andrew.smirnov@gmail.com> According to NXP's FAE feedback and a comment in ATF firmware, PCIE1 and PCIE2 power domains can't really be used independently. Due to shared reset line both power domains have to be turned on at the same time. Account for that quirk by combining PCIE power domains into a single 'pgc_pcie' power domain. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 50436bd393ed..fca9b71de94f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -273,9 +273,25 @@ reg = <IMX8M_POWER_DOMAIN_MIPI>; }; - pgc_pcie1: power-domain@1 { + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_PCIE1>; + power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 { -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-20 1:59 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-20 1:58 [PATCH v3 0/5] PCIE support for i.MX8MQ (DT changes) Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov 2019-02-20 1:58 ` [PATCH v3 1/5] arm64: dts: imx8mq: Mark iomuxc_gpr as i.MX6Q compatible Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov 2019-02-20 1:58 ` [PATCH v3 2/5] arm64: dts: imx8mq: Add a node for SRC IP block Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov [this message] 2019-02-20 1:58 ` [PATCH v3 3/5] arm64: dts: imx8mq: Combine PCIE power domains Andrey Smirnov 2019-02-20 1:58 ` [PATCH v3 4/5] arm64: dts: imx8mq: Add nodes for PCIe IP blocks Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov 2019-02-20 1:58 ` [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface Andrey Smirnov 2019-02-20 1:58 ` Andrey Smirnov 2019-02-20 8:18 ` Lucas Stach 2019-02-20 8:18 ` Lucas Stach
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