* [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
@ 2019-02-25 23:03 Zhao, Yong
[not found] ` <20190225230257.18676-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Zhao, Yong @ 2019-02-25 23:03 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhao, Yong
This is recommended by HW designers. Previously when it was set to 1,
the PDE walk error in VM fault will be treated as
PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
The above behavior is kind of abnormal. Furthermore, the
PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
and it never made it way to production. Therefore, we should set it to 0.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index f5edddf3b29d..c10ed568ca6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
/* XXX for emulation, Refer to closed source code.*/
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index d0d966d6080a..2a039946a549 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
/* XXX for emulation, Refer to closed source code.*/
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0);
- tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
+ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <20190225230257.18676-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-26 2:53 ` Alex Deucher
[not found] ` <CADnq5_N9cvoGrHKBe22XWU1KPxFkAFhLkeAwPfeUdpYHfV2cMQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-02-26 10:29 ` Christian König
1 sibling, 1 reply; 9+ messages in thread
From: Alex Deucher @ 2019-02-26 2:53 UTC (permalink / raw)
To: Zhao, Yong; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Mon, Feb 25, 2019 at 6:03 PM Zhao, Yong <Yong.Zhao@amd.com> wrote:
>
> This is recommended by HW designers. Previously when it was set to 1,
> the PDE walk error in VM fault will be treated as
> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
> As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
>
> The above behavior is kind of abnormal. Furthermore, the
> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> and it never made it way to production. Therefore, we should set it to 0.
>
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index f5edddf3b29d..c10ed568ca6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index d0d966d6080a..2a039946a549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <CADnq5_N9cvoGrHKBe22XWU1KPxFkAFhLkeAwPfeUdpYHfV2cMQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2019-02-26 3:46 ` Bridgman, John
[not found] ` <20190226034609.6168661.29088.397406-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Bridgman, John @ 2019-02-26 3:46 UTC (permalink / raw)
To: Alex Deucher, Zhao, Yong; +Cc: amd-gfx list
Don't we want PDE faults to be treated the same way as page faults? Or am I misinterpreting the commit message?
Thanks,
John
Original Message
From: Alex Deucher
Sent: Monday, February 25, 2019 21:53
To: Zhao, Yong
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
On Mon, Feb 25, 2019 at 6:03 PM Zhao, Yong <Yong.Zhao@amd.com> wrote:
>
> This is recommended by HW designers. Previously when it was set to 1,
> the PDE walk error in VM fault will be treated as
> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
> As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
>
> The above behavior is kind of abnormal. Furthermore, the
> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> and it never made it way to production. Therefore, we should set it to 0.
>
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index f5edddf3b29d..c10ed568ca6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index d0d966d6080a..2a039946a549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <20190226034609.6168661.29088.397406-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-26 3:50 ` Bridgman, John
[not found] ` <20190226035032.6168661.20601.397409-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Bridgman, John @ 2019-02-26 3:50 UTC (permalink / raw)
To: Alex Deucher, Zhao, Yong; +Cc: amd-gfx list
Or is the idea that we should never see a PDE fault unless something goes wrong, and that we would set up an entry corresponding to an unmapped subtree as an invalid PTE for a very large page rather than an invalid PDE?
Thanks,
John
Original Message
From: Bridgman, John
Sent: Monday, February 25, 2019 22:46
To: Alex Deucher; Zhao, Yong
Cc: amd-gfx list
Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
Don't we want PDE faults to be treated the same way as page faults? Or am I misinterpreting the commit message?
Thanks,
John
Original Message
From: Alex Deucher
Sent: Monday, February 25, 2019 21:53
To: Zhao, Yong
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
On Mon, Feb 25, 2019 at 6:03 PM Zhao, Yong <Yong.Zhao@amd.com> wrote:
>
> This is recommended by HW designers. Previously when it was set to 1,
> the PDE walk error in VM fault will be treated as
> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
> As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
>
> The above behavior is kind of abnormal. Furthermore, the
> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> and it never made it way to production. Therefore, we should set it to 0.
>
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index f5edddf3b29d..c10ed568ca6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index d0d966d6080a..2a039946a549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <20190225230257.18676-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-26 2:53 ` Alex Deucher
@ 2019-02-26 10:29 ` Christian König
[not found] ` <0f3d8a85-e01b-625d-b591-205f7f28af8e-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
1 sibling, 1 reply; 9+ messages in thread
From: Christian König @ 2019-02-26 10:29 UTC (permalink / raw)
To: Zhao, Yong, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 26.02.19 um 00:03 schrieb Zhao, Yong:
> This is recommended by HW designers. Previously when it was set to 1,
> the PDE walk error in VM fault will be treated as
> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
> As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
>
> The above behavior is kind of abnormal. Furthermore, the
> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> and it never made it way to production. Therefore, we should set it to 0.
>
> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index f5edddf3b29d..c10ed568ca6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index d0d966d6080a..2a039946a549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
> /* XXX for emulation, Refer to closed source code.*/
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 0);
> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <20190226035032.6168661.20601.397409-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-26 10:33 ` Christian König
0 siblings, 0 replies; 9+ messages in thread
From: Christian König @ 2019-02-26 10:33 UTC (permalink / raw)
To: Bridgman, John, Alex Deucher, Zhao, Yong; +Cc: amd-gfx list
> Don't we want PDE faults to be treated the same way as page faults?
Yeah, I think that this was actually the original intention. Problem is
that this is actually the wrong approach for this.
> Or is the idea that we should never see a PDE fault unless something goes wrong
Exactly, yes. What you really want to do is to set the P bit for PDEs
which can be allocated dynamically.
This way the walker stops at the current processed entry and sends your
a standard page fault for a leave page.
Regards,
Christian.
Am 26.02.19 um 04:50 schrieb Bridgman, John:
> Or is the idea that we should never see a PDE fault unless something goes wrong, and that we would set up an entry corresponding to an unmapped subtree as an invalid PTE for a very large page rather than an invalid PDE?
>
> Thanks,
> John
> Original Message
> From: Bridgman, John
> Sent: Monday, February 25, 2019 22:46
> To: Alex Deucher; Zhao, Yong
> Cc: amd-gfx list
> Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
>
>
> Don't we want PDE faults to be treated the same way as page faults? Or am I misinterpreting the commit message?
>
> Thanks,
> John
> Original Message
> From: Alex Deucher
> Sent: Monday, February 25, 2019 21:53
> To: Zhao, Yong
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
>
>
> On Mon, Feb 25, 2019 at 6:03 PM Zhao, Yong <Yong.Zhao@amd.com> wrote:
>> This is recommended by HW designers. Previously when it was set to 1,
>> the PDE walk error in VM fault will be treated as
>> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT.
>> As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly.
>>
>> The above behavior is kind of abnormal. Furthermore, the
>> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
>> and it never made it way to production. Therefore, we should set it to 0.
>>
>> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index f5edddf3b29d..c10ed568ca6c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>> /* XXX for emulation, Refer to closed source code.*/
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
>> 0);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
>> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index d0d966d6080a..2a039946a549 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>> /* XXX for emulation, Refer to closed source code.*/
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
>> 0);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
>> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
>> --
>> 2.17.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <0f3d8a85-e01b-625d-b591-205f7f28af8e-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-02-26 23:18 ` Zhao, Yong
[not found] ` <d107229a-062b-8535-87c8-17110d2223ea-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Zhao, Yong @ 2019-02-26 23:18 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
So can I submit it only with the ACKs?
Yong
On 2019-02-26 5:29 a.m., Christian König wrote:
> Am 26.02.19 um 00:03 schrieb Zhao, Yong:
>> This is recommended by HW designers. Previously when it was set to 1,
>> the PDE walk error in VM fault will be treated as
>> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected
>> OTHER_FAULT.
>> As a result, the retry control in VM_CONTEXT*_CNTL will change
>> accordingly.
>>
>> The above behavior is kind of abnormal. Furthermore, the
>> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
>> and it never made it way to production. Therefore, we should set it
>> to 0.
>>
>> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
>
> Acked-by: Christian König <christian.koenig@amd.com>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index f5edddf3b29d..c10ed568ca6c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct
>> amdgpu_device *adev)
>> /* XXX for emulation, Refer to closed source code.*/
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> L2_PDE0_CACHE_TAG_GENERATION_MODE,
>> 0);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> IDENTITY_MODE_FRAGMENT_SIZE, 0);
>> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index d0d966d6080a..2a039946a549 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct
>> amdgpu_device *adev)
>> /* XXX for emulation, Refer to closed source code.*/
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> L2_PDE0_CACHE_TAG_GENERATION_MODE,
>> 0);
>> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
>> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
>> IDENTITY_MODE_FRAGMENT_SIZE, 0);
>> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <d107229a-062b-8535-87c8-17110d2223ea-5C7GfCeVMHo@public.gmane.org>
@ 2019-02-27 3:53 ` Alex Deucher
[not found] ` <CADnq5_O55w2btKnNK7TWvgRmOuE3wC0rGXUXg+u06SdJeOSZ4Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 9+ messages in thread
From: Alex Deucher @ 2019-02-27 3:53 UTC (permalink / raw)
To: Zhao, Yong; +Cc: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
yes, go ahead.
Alex
On Tue, Feb 26, 2019 at 6:18 PM Zhao, Yong <Yong.Zhao@amd.com> wrote:
>
> So can I submit it only with the ACKs?
>
> Yong
>
> On 2019-02-26 5:29 a.m., Christian König wrote:
> > Am 26.02.19 um 00:03 schrieb Zhao, Yong:
> >> This is recommended by HW designers. Previously when it was set to 1,
> >> the PDE walk error in VM fault will be treated as
> >> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected
> >> OTHER_FAULT.
> >> As a result, the retry control in VM_CONTEXT*_CNTL will change
> >> accordingly.
> >>
> >> The above behavior is kind of abnormal. Furthermore, the
> >> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> >> and it never made it way to production. Therefore, we should set it
> >> to 0.
> >>
> >> Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
> >
> > Acked-by: Christian König <christian.koenig@amd.com>
> >
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> >> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> >> 2 files changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> index f5edddf3b29d..c10ed568ca6c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct
> >> amdgpu_device *adev)
> >> /* XXX for emulation, Refer to closed source code.*/
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> L2_PDE0_CACHE_TAG_GENERATION_MODE,
> >> 0);
> >> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> >> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> IDENTITY_MODE_FRAGMENT_SIZE, 0);
> >> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> index d0d966d6080a..2a039946a549 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct
> >> amdgpu_device *adev)
> >> /* XXX for emulation, Refer to closed source code.*/
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> L2_PDE0_CACHE_TAG_GENERATION_MODE,
> >> 0);
> >> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> >> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> IDENTITY_MODE_FRAGMENT_SIZE, 0);
> >> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
> >
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
[not found] ` <CADnq5_O55w2btKnNK7TWvgRmOuE3wC0rGXUXg+u06SdJeOSZ4Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2019-02-27 16:52 ` Zhao, Yong
0 siblings, 0 replies; 9+ messages in thread
From: Zhao, Yong @ 2019-02-27 16:52 UTC (permalink / raw)
To: Alex Deucher; +Cc: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 3576 bytes --]
Pushed. Thanks.
Yong
________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Tuesday, February 26, 2019 10:53 PM
To: Zhao, Yong
Cc: Koenig, Christian; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0
yes, go ahead.
Alex
On Tue, Feb 26, 2019 at 6:18 PM Zhao, Yong <Yong.Zhao-5C7GfCeVMHo@public.gmane.org> wrote:
>
> So can I submit it only with the ACKs?
>
> Yong
>
> On 2019-02-26 5:29 a.m., Christian König wrote:
> > Am 26.02.19 um 00:03 schrieb Zhao, Yong:
> >> This is recommended by HW designers. Previously when it was set to 1,
> >> the PDE walk error in VM fault will be treated as
> >> PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected
> >> OTHER_FAULT.
> >> As a result, the retry control in VM_CONTEXT*_CNTL will change
> >> accordingly.
> >>
> >> The above behavior is kind of abnormal. Furthermore, the
> >> PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs
> >> and it never made it way to production. Therefore, we should set it
> >> to 0.
> >>
> >> Signed-off-by: Yong Zhao <Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
> >
> > Acked-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> >
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +-
> >> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> >> 2 files changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> index f5edddf3b29d..c10ed568ca6c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> >> @@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct
> >> amdgpu_device *adev)
> >> /* XXX for emulation, Refer to closed source code.*/
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> L2_PDE0_CACHE_TAG_GENERATION_MODE,
> >> 0);
> >> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> >> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> IDENTITY_MODE_FRAGMENT_SIZE, 0);
> >> WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> index d0d966d6080a..2a039946a549 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> >> @@ -163,7 +163,7 @@ static void mmhub_v1_0_init_cache_regs(struct
> >> amdgpu_device *adev)
> >> /* XXX for emulation, Refer to closed source code.*/
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> L2_PDE0_CACHE_TAG_GENERATION_MODE,
> >> 0);
> >> - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
> >> + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> >> tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,
> >> IDENTITY_MODE_FRAGMENT_SIZE, 0);
> >> WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
> >
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[-- Attachment #1.2: Type: text/html, Size: 6073 bytes --]
[-- Attachment #2: Type: text/plain, Size: 153 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-02-27 16:52 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-25 23:03 [PATCH] drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0 Zhao, Yong
[not found] ` <20190225230257.18676-1-Yong.Zhao-5C7GfCeVMHo@public.gmane.org>
2019-02-26 2:53 ` Alex Deucher
[not found] ` <CADnq5_N9cvoGrHKBe22XWU1KPxFkAFhLkeAwPfeUdpYHfV2cMQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-02-26 3:46 ` Bridgman, John
[not found] ` <20190226034609.6168661.29088.397406-5C7GfCeVMHo@public.gmane.org>
2019-02-26 3:50 ` Bridgman, John
[not found] ` <20190226035032.6168661.20601.397409-5C7GfCeVMHo@public.gmane.org>
2019-02-26 10:33 ` Christian König
2019-02-26 10:29 ` Christian König
[not found] ` <0f3d8a85-e01b-625d-b591-205f7f28af8e-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-02-26 23:18 ` Zhao, Yong
[not found] ` <d107229a-062b-8535-87c8-17110d2223ea-5C7GfCeVMHo@public.gmane.org>
2019-02-27 3:53 ` Alex Deucher
[not found] ` <CADnq5_O55w2btKnNK7TWvgRmOuE3wC0rGXUXg+u06SdJeOSZ4Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-02-27 16:52 ` Zhao, Yong
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