[PATCH v2] tegra2/tegra3 automotive clock init

[PATCH v2] tegra2/tegra3 automotive clock init

[Kejia Hu]

This is a re-implementation of adding clock initialization for
tegra2 and tegra3 automotive devices accroding to Dmitry Osipenko's
feedback on version 1[0].

We have moved the initialization from the clock driver to device
tree, but instead of putting them into a dtsi file, we used
dt overlay to patch the device tree at runtime, we believe the
ability to dynamically detect the chipset and apply the right
settings should be useful according to the discussion[1].

Changes against v1:
  - use device tree overlay to introduce the automative clock configs
  - enable dt overlay for tegra20/30
  - move the condition "soc_is_tegra_auto" to be after applied
    clock init table.

[0] https://www.spinics.net/lists/linux-tegra/msg38347.html
[1] https://www.spinics.net/lists/arm-kernel/msg665373.html

[PATCH v2 1/6] soc/tegra: initial tegra-automotive detection

[Kejia Hu]

From: Ben Dooks <ben.dooks@codethink.co.uk>

Add an initial soc_is_tegra_auto() with detection
via a change in the device-tree.

Also print the path taken through soc_is_tegra_auto() to
allow debugging. Only print when debug is enabled as this
function may be be called from multiple places, resulting
in duplicated messages in production.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
---
 drivers/soc/tegra/common.c             | 23 +++++++++++++++++++++++
 drivers/soc/tegra/fuse/tegra-apbmisc.c |  2 ++
 include/soc/tegra/common.h             |  1 +
 include/soc/tegra/fuse.h               |  1 +
 4 files changed, 27 insertions(+)

diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
index 7bfb154d6fa5..a10bd26fb5df 100644
--- a/drivers/soc/tegra/common.c
+++ b/drivers/soc/tegra/common.c
@@ -9,6 +9,7 @@
 #include <linux/of.h>
 
 #include <soc/tegra/common.h>
+#include <soc/tegra/fuse.h>
 
 static const struct of_device_id tegra_machine_match[] = {
 	{ .compatible = "nvidia,tegra20", },
@@ -34,3 +35,25 @@ bool soc_is_tegra(void)
 
 	return match != NULL;
 }
+
+static const struct of_device_id tegra_machine_match_auto[] = {
+	{ .compatible = "nvidia,tegra20auto", },
+	{ .compatible = "nvidia,tegra30auto", },
+	{ },
+};
+
+bool soc_is_tegra_auto(void)
+{
+	struct device_node *root;
+	bool id_match  = false;
+
+	root = of_find_node_by_path("/");
+
+	if (root && of_match_node(tegra_machine_match_auto, root))
+		id_match = true;
+
+	pr_debug("%s of_device_id match %d, tegra_sku_info.is_automotive %d\n",
+			__func__, id_match, tegra_sku_info.is_automotive);
+
+	return id_match || tegra_sku_info.is_automotive;
+}
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index e5a4d8f98b10..b2727afad24b 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -110,6 +110,8 @@ void __init tegra_init_revision(void)
 
 	tegra_sku_info.revision = rev;
 
+	tegra_sku_info.is_automotive = false;
+
 	tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
 }
 
diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h
index fc13a9a134e9..8dd178ddc6a6 100644
--- a/include/soc/tegra/common.h
+++ b/include/soc/tegra/common.h
@@ -10,5 +10,6 @@
 #define __SOC_TEGRA_COMMON_H__
 
 bool soc_is_tegra(void);
+bool soc_is_tegra_auto(void);
 
 #endif /* __SOC_TEGRA_COMMON_H__ */
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index 8fb2f8a87339..ea4caf6f0cf7 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -56,6 +56,7 @@ struct tegra_sku_info {
 	int gpu_speedo_id;
 	int gpu_speedo_value;
 	enum tegra_revision revision;
+	bool is_automotive;
 };
 
 u32 tegra_read_straps(void);
-- 
2.11.0

[PATCH v2 2/6] soc/tegra: fuse: add is_automotive for tegra30

[Kejia Hu]

From: Ben Dooks <ben.dooks@codethink.co.uk>

Add an is_automotive flag to the tegra-sku info, and
add an implementation for the tegra30 from what we
know from all the autotmotive parts we've seen.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
---
 drivers/soc/tegra/fuse/fuse-tegra30.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 257e254c6137..d92025e486e0 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -106,6 +106,10 @@ static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
 	if (fuse->soc->speedo_init)
 		fuse->soc->speedo_init(&tegra_sku_info);
 
+	if (tegra_sku_info.revision == TEGRA_REVISION_A03 &&
+	    tegra_sku_info.sku_id == 176)
+		tegra_sku_info.is_automotive = true;
+
 	tegra30_fuse_add_randomness();
 }
 #endif
-- 
2.11.0

[PATCH v2 3/6] soc/tegra: fuse: Add is_automotive for tegra20

[Kejia Hu]

From: Thomas Preston <thomas.preston@codethink.co.uk>

Add an is_automotive implementation for tegra20.

Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
---
 drivers/soc/tegra/fuse/fuse-tegra20.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c
index 49ff017f3ded..0184c9f62f80 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra20.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra20.c
@@ -167,6 +167,11 @@ static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
 
 	tegra_init_revision();
 	fuse->soc->speedo_init(&tegra_sku_info);
+
+	if (tegra_sku_info.revision == TEGRA_REVISION_A04 &&
+			tegra_sku_info.sku_id == 44)
+		tegra_sku_info.is_automotive = true;
+
 	tegra20_fuse_add_randomness();
 }
 
-- 
2.11.0

[PATCH v2 4/6] kconfig: build device tree overlay into tegra20/30

[Kejia Hu]

Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
---
 drivers/clk/tegra/Makefile | 6 ++++--
 drivers/soc/tegra/Kconfig  | 2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 6507acc843c7..b9d8281c3629 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -16,8 +16,10 @@ obj-y					+= clk-tegra-pmc.o
 obj-y					+= clk-tegra-fixed.o
 obj-y					+= clk-tegra-super-gen4.o
 obj-$(CONFIG_TEGRA_CLK_EMC)		+= clk-emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o \
+					   tegra20_automative_dt_overlay.dtb.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o \
+					   tegra30_automative_dt_overlay.dtb.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)	+= clk-tegra114.o
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124.o
 obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index fe4481676da6..a61f34af738d 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -15,6 +15,7 @@ config ARCH_TEGRA_2x_SOC
 	select SOC_TEGRA_FLOWCTRL
 	select SOC_TEGRA_PMC
 	select TEGRA_TIMER
+	select OF_OVERLAY
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -28,6 +29,7 @@ config ARCH_TEGRA_3x_SOC
 	select SOC_TEGRA_FLOWCTRL
 	select SOC_TEGRA_PMC
 	select TEGRA_TIMER
+	select OF_OVERLAY
 	help
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
-- 
2.11.0

[PATCH v2 5/6] clk: tegra20: add automotive specific clocks as dt overlay

[Kejia Hu]

Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
---
 drivers/clk/tegra/clk-tegra20.c                    |  19 ++++
 .../clk/tegra/tegra20_automative_dt_overlay.dts    | 117 +++++++++++++++++++++
 2 files changed, 136 insertions(+)
 create mode 100644 drivers/clk/tegra/tegra20_automative_dt_overlay.dts

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index c71b61162a32..ec9fce298c39 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -22,6 +22,7 @@
 #include <linux/clk/tegra.h>
 #include <linux/delay.h>
 #include <dt-bindings/clock/tegra20-car.h>
+#include <soc/tegra/common.h>
 
 #include "clk.h"
 #include "clk-id.h"
@@ -127,6 +128,11 @@
 #define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
 #define CPU_RESET(cpu)	(0x1111ul << (cpu))
 
+extern char __dtb_tegra20_automative_dt_overlay_begin[];
+extern char __dtb_tegra20_automative_dt_overlay_end[];
+
+
+
 #ifdef CONFIG_PM_SLEEP
 static struct cpu_clk_suspend_context {
 	u32 pllx_misc;
@@ -1188,6 +1194,19 @@ static void __init tegra20_clock_init(struct device_node *np)
 
 	tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
 
+	if (soc_is_tegra_auto()) {
+		int ret = 0;
+		int ovcs_id;
+		void *begin = __dtb_tegra20_automative_dt_overlay_begin;
+		void *end = __dtb_tegra20_automative_dt_overlay_end;
+
+		pr_info("Initialise Tegra Automotive clocks\n");
+
+		ret = of_overlay_fdt_apply(begin, end - begin, &ovcs_id);
+		if (ret)
+			pr_err("Failed to apply device tree overlay, ret = %d\n", ret);
+	}
+
 	tegra_cpu_car_ops = &tegra20_cpu_car_ops;
 }
 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
diff --git a/drivers/clk/tegra/tegra20_automative_dt_overlay.dts b/drivers/clk/tegra/tegra20_automative_dt_overlay.dts
new file mode 100644
index 000000000000..454046b1a055
--- /dev/null
+++ b/drivers/clk/tegra/tegra20_automative_dt_overlay.dts
@@ -0,0 +1,117 @@
+/*
+ * Clock initialization specific to Tegra2 Automative Chipset
+ *
+ * Copyright (C) 2019 Codethink Ltd
+ *                    Kejia Hu <kejia.hu@codethink.co.uk>
+*/
+
+#include <dt-bindings/clock/tegra20-car.h>
+
+/dts-v1/;
+/plugin/;
+
+/ {
+        fragment@0 {
+                target-path = "/pmc@7000e400";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_PCLK>;
+                        assigned-clock-rates = <120000000>;
+                };
+        };
+
+        fragment@1 {
+                target-path = "/spi@7000d400";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+                        assigned-clock-rates = <12000000>;
+                };
+        };
+
+        fragment@2 {
+                target-path = "/spi@7000d600";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+                        assigned-clock-rates = <12000000>;
+                };
+        };
+
+        fragment@3 {
+                target-path = "/spi@7000d800";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+                        assigned-clock-rates = <12000000>;
+                };
+        };
+
+        fragment@4 {
+                target-path = "/spi@7000da00";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+                        assigned-clock-rates = <12000000>;
+                };
+        };
+
+        fragment@5 {
+                target-path = "/nand-controller@70008000";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_P>;
+                        assigned-clock-rates = <86500000>;
+                };
+        };
+
+        fragment@6 {
+                target-path = "/vde@6001a000";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_VDE>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+                };
+        };
+
+        fragment@7 {
+                target-path = "/host1x@50000000";
+                __overlay__ {
+                        assigned-clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+			assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_M>;
+                        assigned-clock-rates = <266400000>;
+
+	                mpe@54040000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_MPE>;
+				assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+				assigned-clock-rates = <300000000>;
+			};
+
+	                vi@54080000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_VI>;
+				assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_M>;
+				assigned-clock-rates = <111000000>;
+			};
+
+	                epp@540c0000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_EPP>;
+				assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_M>;
+				assigned-clock-rates = <266400000>;
+			};
+
+	                gr2d@54140000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+			};
+
+	                gr3d@54180000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+				assigned-clock-rates = <300000000>;
+			};
+
+	                dc@54200000 {
+				assigned-clocks = <&tegra_car TEGRA20_CLK_DISP1>;
+				assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+				assigned-clock-rates = <297000000>;
+			};
+                };
+        };
+};
+
-- 
2.11.0

[PATCH v2 6/6] clk: tegra30: add automotive specific clocks as dt overlay

[Kejia Hu]

Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
---
 drivers/clk/tegra/clk-tegra30.c                    |  17 ++
 .../clk/tegra/tegra30_automative_dt_overlay.dts    | 256 +++++++++++++++++++++
 2 files changed, 273 insertions(+)
 create mode 100644 drivers/clk/tegra/tegra30_automative_dt_overlay.dts

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index fa8d573ac626..757551af2b29 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -25,6 +25,7 @@
 #include <soc/tegra/pmc.h>
 
 #include <dt-bindings/clock/tegra30-car.h>
+#include <soc/tegra/common.h>
 
 #include "clk.h"
 #include "clk-id.h"
@@ -145,6 +146,9 @@
 /* PLLM override registers */
 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
 
+extern char __dtb_tegra30_automative_dt_overlay_begin[];
+extern char __dtb_tegra30_automative_dt_overlay_end[];
+
 #ifdef CONFIG_PM_SLEEP
 static struct cpu_clk_suspend_context {
 	u32 pllx_misc;
@@ -1361,6 +1365,19 @@ static void __init tegra30_clock_init(struct device_node *np)
 
 	tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
 
+	if (soc_is_tegra_auto()) {
+		int ret = 0;
+		int ovcs_id;
+		void *begin = __dtb_tegra30_automative_dt_overlay_begin;
+		void *end = __dtb_tegra30_automative_dt_overlay_end;
+
+		pr_info("Initialise Tegra Automotive clocks\n");
+
+		ret = of_overlay_fdt_apply(begin, end - begin, &ovcs_id);
+		if (ret)
+			pr_err("Failed to apply device tree overlay, ret = %d\n", ret);
+	}
+
 	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
 CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
diff --git a/drivers/clk/tegra/tegra30_automative_dt_overlay.dts b/drivers/clk/tegra/tegra30_automative_dt_overlay.dts
new file mode 100644
index 000000000000..008d05ef3544
--- /dev/null
+++ b/drivers/clk/tegra/tegra30_automative_dt_overlay.dts
@@ -0,0 +1,256 @@
+/*
+ * Clock initialization specific to Tegra3 Automative Chipset
+ *
+ * Copyright (C) 2019 Codethink Ltd
+ *                    Kejia Hu <kejia.hu@codethink.co.uk>
+*/
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/tegra30-car.h>
+
+/ {
+	fragment@0 {
+		target-path = "/sound";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+					  <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+					  <&tegra_car TEGRA30_CLK_EXTERN1>;
+			assigned-clock-rates = <552960000>,
+					       <24576000>,
+					       <24576000>;
+		};
+	};
+
+	fragment@1 {
+		target-path = "/ahub@70080000/tegra_i2s0";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <12288000>;
+		};
+	};
+
+	fragment@2 {
+		target-path = "/ahub@70080000/tegra_i2s1";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <12288000>;
+		};
+	};
+
+	fragment@3 {
+		target-path = "/ahub@70080000/tegra_i2s2";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <12288000>;
+		};
+	};
+
+	fragment@4 {
+		target-path = "/ahub@70080000/tegra_i2s3";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <12288000>;
+		};
+	};
+
+	fragment@5 {
+		target-path = "/ahub@70080000/tegra_i2s4";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <12288000>;
+		};
+	};
+
+	fragment@6 {
+		target-path = "/sdhci@78000200";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+			assigned-clock-rates = <104000000>;
+		};
+	};
+
+	fragment@7 {
+		target-path = "/sdhci@78000600";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+			assigned-clock-rates = <48000000>;
+		};
+	};
+
+	fragment@8 {
+		target-path = "/spi@7000d400";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <15822784>;
+		};
+	};
+
+	fragment@9 {
+		target-path = "/spi@7000d600";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <100000000>;
+		};
+	};
+
+	fragment@10 {
+		target-path = "/spi@7000d800";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <100000000>;
+		};
+	};
+
+	fragment@11 {
+		target-path = "/spi@7000da00";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <100000000>;
+		};
+	};
+
+	fragment@12 {
+		target-path = "/spi@7000dc00";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <100000000>;
+		};
+	};
+
+	fragment@13 {
+		target-path = "/spi@7000de00";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
+			assigned-clock-rates = <100000000>;
+		};
+	};
+
+	fragment@14 {
+		target-path = "/host1x@50000000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+			assigned-clock-rates = <242000000>;
+
+			gr2d@54140000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_GR2D>;
+				assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_MAX>;
+				assigned-clock-rates = <484000000>;
+			};
+
+			gr3d@54180000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_GR3D>,
+						  <&tegra_car TEGRA30_CLK_GR3D2>;
+				assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_MAX>,
+							 <&tegra_car TEGRA30_CLK_CLK_MAX>;
+				assigned-clock-rates = <484000000>, <484000000>;
+			};
+
+			dc@54200000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_DISP1>;
+				assigned-clock-rates = <275000000>;
+			};
+
+			dc@54240000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_DISP2>;
+				assigned-clock-rates = <275000000>;
+			};
+
+			epp@540c0000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_EPP>;
+				assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+				assigned-clock-rates = <484000000>;
+			};
+
+			mpe@54040000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_MPE>;
+				assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+				assigned-clock-rates = <484000000>;
+			};
+
+			vi@54080000 {
+				assigned-clocks = <&tegra_car TEGRA30_CLK_VI>;
+				assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+				assigned-clock-rates = <150000000>;
+			};
+		};
+	};
+
+	fragment@15 {
+		target-path = "/vde@6001a000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+			assigned-clock-rates = <484000000>;
+		};
+	};
+
+	fragment@16 {
+		target-path = "/fuse@7000f800";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_FUSE>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_MAX>;
+			assigned-clock-rates = <12000000>;
+		};
+	};
+
+	fragment@17 {
+		target-path = "/hda@70030000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_HDA>,
+					  <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
+						 <&tegra_car TEGRA30_CLK_PLL_P>;
+			assigned-clock-rates = <108000000>, <48000000>;
+		};
+	};
+
+	fragment@18 {
+		target-path = "/gmi@70009000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_NOR>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
+			assigned-clock-rates = <102000000>;
+		};
+	};
+
+	fragment@19 {
+		target-path = "/pmc@7000e400";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_PCLK>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_MAX>;
+			assigned-clock-rates = <166250000>;
+		};
+	};
+
+	fragment@20 {
+		target-path = "/ahub@70080000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>;
+			assigned-clock-rates = <24576000>;
+		};
+	};
+
+	fragment@21 {
+		target-path = "/pwm@7000a000";
+		__overlay__ {
+			assigned-clocks = <&tegra_car TEGRA30_CLK_PWM>;
+			assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_32K>;
+			assigned-clock-rates = <32768>;
+		};
+	};
+};
-- 
2.11.0

Re: [PATCH v2] tegra2/tegra3 automotive clock init

[Dmitry Osipenko]

01.03.2019 18:35, Kejia Hu пишет:
> This is a re-implementation of adding clock initialization for
> tegra2 and tegra3 automotive devices accroding to Dmitry Osipenko's
> feedback on version 1[0].
> 
> We have moved the initialization from the clock driver to device
> tree, but instead of putting them into a dtsi file, we used
> dt overlay to patch the device tree at runtime, we believe the
> ability to dynamically detect the chipset and apply the right
> settings should be useful according to the discussion[1].
> 
> Changes against v1:
>   - use device tree overlay to introduce the automative clock configs
>   - enable dt overlay for tegra20/30
>   - move the condition "soc_is_tegra_auto" to be after applied
>     clock init table.
> 
> [0] https://www.spinics.net/lists/linux-tegra/msg38347.html
> [1] https://www.spinics.net/lists/arm-kernel/msg665373.html
> 

Hello Kejia,

Thank you very much for your work! My point was that the clock-assignments should be moved into the board's DT file out from the kernel's driver, in this series you're not moving out the board-specific properties from the kernel sources and essential doing the same thing that was in the previous versions in a different way now. Please take a look at tegra124.dtsi / tegra124-nyan.dtsi / tegra124-nyan-big.dts for the example, in your case it could be something similar.. somewhat like tegra20.dtsi / tegra20-automotive.dtsi / tegra20-automotive-board.dts. Hence you won't need to touch kernel's code at all and could specify everything in the device-tree solely.

If you're trying to workaround the case where device-tree isn't easily changeable, then I'm afraid this is not going to work well in regards to upstreaming because upstream maintainers have no interest in supporting downstream. If it's not that case, then please try to explain what you're trying to achieve in more detail.

In overall you'll need to:

1) Upstream device-tree of the board.
2) Get all other required bits of kernel drivers upstream'ed.
3) Issue firmware update for the device that will contain new upstream-conformant device-tree and upstream kernel at once. Also note that kernel supports appending DTB (compiled device-tree binary) to the kernel's image, hence you may workaround locked-down bootloader that doesn't allow to replace (or doesn't support) device-tree.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 1/6] soc/tegra: initial tegra-automotive detection

[Thierry Reding]

[-- Attachment #1.1: Type: text/plain, Size: 2338 bytes --]

On Fri, Mar 01, 2019 at 03:35:35PM +0000, Kejia Hu wrote:
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> 
> Add an initial soc_is_tegra_auto() with detection
> via a change in the device-tree.
> 
> Also print the path taken through soc_is_tegra_auto() to
> allow debugging. Only print when debug is enabled as this
> function may be be called from multiple places, resulting
> in duplicated messages in production.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
> Signed-off-by: Kejia Hu <kejia.hu@codethink.co.uk>
> ---
>  drivers/soc/tegra/common.c             | 23 +++++++++++++++++++++++
>  drivers/soc/tegra/fuse/tegra-apbmisc.c |  2 ++
>  include/soc/tegra/common.h             |  1 +
>  include/soc/tegra/fuse.h               |  1 +
>  4 files changed, 27 insertions(+)
> 
> diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
> index 7bfb154d6fa5..a10bd26fb5df 100644
> --- a/drivers/soc/tegra/common.c
> +++ b/drivers/soc/tegra/common.c
> @@ -9,6 +9,7 @@
>  #include <linux/of.h>
>  
>  #include <soc/tegra/common.h>
> +#include <soc/tegra/fuse.h>
>  
>  static const struct of_device_id tegra_machine_match[] = {
>  	{ .compatible = "nvidia,tegra20", },
> @@ -34,3 +35,25 @@ bool soc_is_tegra(void)
>  
>  	return match != NULL;
>  }
> +
> +static const struct of_device_id tegra_machine_match_auto[] = {
> +	{ .compatible = "nvidia,tegra20auto", },
> +	{ .compatible = "nvidia,tegra30auto", },
> +	{ },
> +};
> +
> +bool soc_is_tegra_auto(void)
> +{
> +	struct device_node *root;
> +	bool id_match  = false;
> +
> +	root = of_find_node_by_path("/");
> +
> +	if (root && of_match_node(tegra_machine_match_auto, root))
> +		id_match = true;
> +
> +	pr_debug("%s of_device_id match %d, tegra_sku_info.is_automotive %d\n",
> +			__func__, id_match, tegra_sku_info.is_automotive);
> +
> +	return id_match || tegra_sku_info.is_automotive;
> +}

Why do we need two ways of specifying the same thing? If we can read
this information from fuses, I don't think we need the extra compatible
string matching.

Also, if you're going to use this exclusively for clock setup, then the
alternative is to do that as part of the board's device tree, as Dmitry
pointed out.

Thierry

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel