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* [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
@ 2019-03-05 23:47 José Roberto de Souza
  2019-03-05 23:47 ` [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function José Roberto de Souza
                   ` (6 more replies)
  0 siblings, 7 replies; 14+ messages in thread
From: José Roberto de Souza @ 2019-03-05 23:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula, Dhinakaran Pandiyan

A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.

v2: replacing enum to numerical usec time (Jani)

BSpec: 20131

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_bios.c     | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_psr.c      |  8 ++++----
 drivers/gpu/drm/i915/intel_vbt_defs.h |  3 +++
 4 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff039750069d..661dce6ccb90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,7 @@ struct intel_vbt_data {
 		enum psr_lines_to_wait lines_to_wait;
 		int tp1_wakeup_time_us;
 		int tp2_tp3_wakeup_time_us;
+		int psr2_tp2_tp3_wakeup_time_us;
 	} psr;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..ecc352ec7715 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -760,6 +760,31 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
 		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
 	}
+
+	if (bdb->version >= 226) {
+		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+
+		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+		switch (wakeup_time) {
+		case 0:
+			wakeup_time = 500;
+			break;
+		case 1:
+			wakeup_time = 100;
+			break;
+		case 3:
+			wakeup_time = 50;
+			break;
+		default:
+		case 2:
+			wakeup_time = 2500;
+			break;
+		}
+		dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+	} else {
+		/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
+		dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
+	}
 }
 
 static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 75c1a5deebf5..831f345b4ad8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -511,12 +511,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
 
-	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
-	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+	if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
+	    dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 		val |= EDP_PSR2_TP2_TIME_50us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR2_TP2_TIME_100us;
-	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 		val |= EDP_PSR2_TP2_TIME_500us;
 	else
 		val |= EDP_PSR2_TP2_TIME_2500us;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index bf3662ad5fed..fdbbb9a53804 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,6 +772,9 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
-- 
2.21.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
@ 2019-03-05 23:47 ` José Roberto de Souza
  2019-03-11 23:28   ` Rodrigo Vivi
  2019-03-05 23:47 ` [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR José Roberto de Souza
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: José Roberto de Souza @ 2019-03-05 23:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan

This will make hsw_activate_psr1() more easy to read and will make
future modification to TPS registers more easy to review and read.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 56 +++++++++++++++++++-------------
 1 file changed, 33 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 831f345b4ad8..2fa2f4c9c935 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 }
 
-static void hsw_activate_psr1(struct intel_dp *intel_dp)
+static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	u32 max_sleep_time = 0x1f;
-	u32 val = EDP_PSR_ENABLE;
-
-	/* Let's use 6 as the minimum to cover all known cases including the
-	 * off-by-one issue that HW has in some cases.
-	 */
-	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
-	/* sink_sync_latency of 8 means source has to wait for more than 8
-	 * frames, we'll go with 9 frames for now
-	 */
-	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
-	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
-
-	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
-	if (IS_HASWELL(dev_priv))
-		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
-
-	if (dev_priv->psr.link_standby)
-		val |= EDP_PSR_LINK_STANDBY;
+	u32 val = 0;
 
 	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
-		val |=  EDP_PSR_TP1_TIME_0us;
+		val |= EDP_PSR_TP1_TIME_0us;
 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP1_TIME_100us;
 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
@@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 		val |= EDP_PSR_TP1_TIME_2500us;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
-		val |=  EDP_PSR_TP2_TP3_TIME_0us;
+		val |= EDP_PSR_TP2_TP3_TIME_0us;
 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 		val |= EDP_PSR_TP2_TP3_TIME_100us;
 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
@@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR_TP1_TP2_SEL;
 
+	return val;
+}
+
+static void hsw_activate_psr1(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u32 max_sleep_time = 0x1f;
+	u32 val = EDP_PSR_ENABLE;
+
+	/* Let's use 6 as the minimum to cover all known cases including the
+	 * off-by-one issue that HW has in some cases.
+	 */
+	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+
+	/* sink_sync_latency of 8 means source has to wait for more than 8
+	 * frames, we'll go with 9 frames for now
+	 */
+	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+
+	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+	if (IS_HASWELL(dev_priv))
+		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
+
+	if (dev_priv->psr.link_standby)
+		val |= EDP_PSR_LINK_STANDBY;
+
+	val |= psr1_tps_regs_val_get(intel_dp);
+
 	if (INTEL_GEN(dev_priv) >= 8)
 		val |= EDP_PSR_CRC_ENABLE;
 
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
  2019-03-05 23:47 ` [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function José Roberto de Souza
@ 2019-03-05 23:47 ` José Roberto de Souza
  2019-03-11 23:34   ` Rodrigo Vivi
  2019-03-06  0:11 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time Patchwork
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: José Roberto de Souza @ 2019-03-05 23:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan

TPS4 support was added to PSR because HBR3/PSR spec was not closed
when ICL was freezed so if HBR3 was supported by PSR, ICL would
already be ready but it was not added to spec so lets always
disable TPS4.

v3: Missed ";" SPANK SPANK SPANK!!!

BSpec: 17524

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_psr.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 16ce9c609c65..a7697909e0c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4205,6 +4205,8 @@ enum {
 #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
+#define   EDP_PSR_TP4_TIME_SHIFT		(6) /* ICL+ */
+#define   EDP_PSR_TP4_TIME_0US			(3 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
 #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
 #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2fa2f4c9c935..c70d735f5b93 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 val = 0;
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		val |= EDP_PSR_TP4_TIME_0US;
+
 	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 		val |= EDP_PSR_TP1_TIME_0us;
 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
  2019-03-05 23:47 ` [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function José Roberto de Souza
  2019-03-05 23:47 ` [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR José Roberto de Souza
@ 2019-03-06  0:11 ` Patchwork
  2019-03-06  0:12 ` ✗ Fi.CI.SPARSE: " Patchwork
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-06  0:11 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
URL   : https://patchwork.freedesktop.org/series/57615/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
6bfff5b6e1e0 drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/i915/intel_bios.c:786:
+		dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;

total: 0 errors, 1 warnings, 0 checks, 63 lines checked
e5ba837d0010 drm/i915/psr: Move logic to get TPS registers values to another function
409676aab5a3 drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
                   ` (2 preceding siblings ...)
  2019-03-06  0:11 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time Patchwork
@ 2019-03-06  0:12 ` Patchwork
  2019-03-06  0:39 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-06  0:12 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
URL   : https://patchwork.freedesktop.org/series/57615/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void)

Commit: drm/i915/psr: Move logic to get TPS registers values to another function
-O:drivers/gpu/drm/i915/intel_psr.c:449:27: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:481:27: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:486:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:486:23: warning: expression using sizeof(void)

Commit: drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
Okay!

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
                   ` (3 preceding siblings ...)
  2019-03-06  0:12 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-03-06  0:39 ` Patchwork
  2019-03-06  8:33 ` ✓ Fi.CI.IGT: " Patchwork
  2019-03-11 21:59 ` [PATCH v3 1/3] " Rodrigo Vivi
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-06  0:39 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
URL   : https://patchwork.freedesktop.org/series/57615/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12384
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57615/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12384 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7560u:       PASS -> INCOMPLETE [fdo#109831]
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-byt-j1900:       PASS -> SKIP [fdo#109271]
    - fi-bsw-kefka:       PASS -> SKIP [fdo#109271]

  * igt@i915_pm_rpm@basic-rte:
    - fi-byt-j1900:       PASS -> FAIL [fdo#108800]
    - fi-bsw-kefka:       PASS -> FAIL [fdo#108800]

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#108529]
    - fi-skl-6770hq:      PASS -> FAIL [fdo#108511]

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_busy@basic-flip-b:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       PASS -> SKIP [fdo#109271] +33

  * igt@kms_psr@primary_mmap_gtt:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +27

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
#### Possible fixes ####

  * igt@gem_mmap@basic-small-bo:
    - {fi-icl-y}:         DMESG-WARN -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831


Participating hosts (47 -> 39)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-icl-u3 fi-byt-n2820 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5708 -> Patchwork_12384

  CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12384: 409676aab5a3ff1670d9fe33719825659217a536 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

409676aab5a3 drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
e5ba837d0010 drm/i915/psr: Move logic to get TPS registers values to another function
6bfff5b6e1e0 drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12384/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
                   ` (4 preceding siblings ...)
  2019-03-06  0:39 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-06  8:33 ` Patchwork
  2019-03-11 21:59 ` [PATCH v3 1/3] " Rodrigo Vivi
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-03-06  8:33 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx

== Series Details ==

Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
URL   : https://patchwork.freedesktop.org/series/57615/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12384_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12384_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@reset-stress:
    - shard-snb:          NOTRUN -> INCOMPLETE [fdo#105411]

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          PASS -> FAIL [fdo#109661]

  * igt@gem_exec_parse@oacontrol-tracking:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +37

  * igt@gem_exec_schedule@preempt-other-chain-blt:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +105

  * igt@gem_tiled_swapping@non-threaded:
    - shard-skl:          PASS -> DMESG-WARN [fdo#108686]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-snb:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
    - shard-skl:          NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +5

  * igt@kms_fbcon_fbt@psr:
    - shard-skl:          NOTRUN -> FAIL [fdo#103833]

  * igt@kms_flip_tiling@flip-yf-tiled:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
    - shard-glk:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +15

  * igt@kms_panel_fitting@legacy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105456]

  * igt@kms_plane@plane-position-covered-pipe-c-planes:
    - shard-apl:          PASS -> FAIL [fdo#103166] +1
    - shard-glk:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-skl:          PASS -> FAIL [fdo#103925] / [fdo#107815]

  * igt@kms_setmode@basic:
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  
#### Possible fixes ####

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-glk:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-kbl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
    - shard-skl:          FAIL [fdo#104671] -> PASS

  * igt@kms_cursor_crc@cursor-256x85-offscreen:
    - shard-skl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-64x64-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          FAIL [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
    - shard-skl:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-skl:          FAIL [fdo#105682] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-skl:          FAIL [fdo#103167] / [fdo#105682] -> PASS

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
    - shard-apl:          FAIL [fdo#103166] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          INCOMPLETE [fdo#103665] -> PASS

  
#### Warnings ####

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-skl:          DMESG-FAIL [fdo#103166] / [fdo#106885] -> FAIL [fdo#103166]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
  [fdo#103925]: https://bugs.freedesktop.org/show_bug.cgi?id=103925
  [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (6 -> 6)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5708 -> Patchwork_12384

  CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12384: 409676aab5a3ff1670d9fe33719825659217a536 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12384/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
  2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
                   ` (5 preceding siblings ...)
  2019-03-06  8:33 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-03-11 21:59 ` Rodrigo Vivi
  6 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-03-11 21:59 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: Jani Nikula, intel-gfx, Dhinakaran Pandiyan

On Tue, Mar 05, 2019 at 03:47:32PM -0800, José Roberto de Souza wrote:
> A new field with the training pattern(TP) wakeup time for PSR2 was
> added to VBT, so lets use it when available otherwise it will
> fallback to PSR1 wakeup time.
> 
> v2: replacing enum to numerical usec time (Jani)
> 
> BSpec: 20131
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_bios.c     | 25 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_psr.c      |  8 ++++----
>  drivers/gpu/drm/i915/intel_vbt_defs.h |  3 +++
>  4 files changed, 33 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ff039750069d..661dce6ccb90 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1006,6 +1006,7 @@ struct intel_vbt_data {
>  		enum psr_lines_to_wait lines_to_wait;
>  		int tp1_wakeup_time_us;
>  		int tp2_tp3_wakeup_time_us;
> +		int psr2_tp2_tp3_wakeup_time_us;
>  	} psr;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index b508d8a735e0..ecc352ec7715 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -760,6 +760,31 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  		dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
>  		dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
>  	}
> +
> +	if (bdb->version >= 226) {
> +		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +
> +		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> +		switch (wakeup_time) {
> +		case 0:
> +			wakeup_time = 500;
> +			break;
> +		case 1:
> +			wakeup_time = 100;
> +			break;
> +		case 3:
> +			wakeup_time = 50;
> +			break;
> +		default:
> +		case 2:
> +			wakeup_time = 2500;
> +			break;
> +		}
> +		dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
> +	} else {
> +		/* Reusing PSR1 wakeup time for PSR2 in older VBTs */
> +		dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
> +	}
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 75c1a5deebf5..831f345b4ad8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -511,12 +511,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  
>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>  
> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
> -	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
> +	if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
> +	    dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
>  		val |= EDP_PSR2_TP2_TIME_50us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> +	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR2_TP2_TIME_100us;
> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> +	else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
>  		val |= EDP_PSR2_TP2_TIME_500us;
>  	else
>  		val |= EDP_PSR2_TP2_TIME_2500us;
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index bf3662ad5fed..fdbbb9a53804 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -772,6 +772,9 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
  2019-03-05 23:47 ` [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function José Roberto de Souza
@ 2019-03-11 23:28   ` Rodrigo Vivi
  2019-03-12  0:15     ` Dhinakaran Pandiyan
  0 siblings, 1 reply; 14+ messages in thread
From: Rodrigo Vivi @ 2019-03-11 23:28 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx, Dhinakaran Pandiyan

On Tue, Mar 05, 2019 at 03:47:33PM -0800, José Roberto de Souza wrote:
> This will make hsw_activate_psr1() more easy to read and will make
> future modification to TPS registers more easy to review and read.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 56 +++++++++++++++++++-------------
>  1 file changed, 33 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 831f345b4ad8..2fa2f4c9c935 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
>  }
>  
> -static void hsw_activate_psr1(struct intel_dp *intel_dp)
> +static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	u32 max_sleep_time = 0x1f;
> -	u32 val = EDP_PSR_ENABLE;
> -
> -	/* Let's use 6 as the minimum to cover all known cases including the
> -	 * off-by-one issue that HW has in some cases.
> -	 */
> -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> -
> -	/* sink_sync_latency of 8 means source has to wait for more than 8
> -	 * frames, we'll go with 9 frames for now
> -	 */
> -	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
> -	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> -
> -	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> -	if (IS_HASWELL(dev_priv))
> -		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> -
> -	if (dev_priv->psr.link_standby)
> -		val |= EDP_PSR_LINK_STANDBY;
> +	u32 val = 0;
>  
>  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> -		val |=  EDP_PSR_TP1_TIME_0us;
> +		val |= EDP_PSR_TP1_TIME_0us;
>  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP1_TIME_100us;
>  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> @@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  		val |= EDP_PSR_TP1_TIME_2500us;
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> -		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> +		val |= EDP_PSR_TP2_TP3_TIME_0us;
>  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>  		val |= EDP_PSR_TP2_TP3_TIME_100us;
>  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> @@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR_TP1_TP2_SEL;
>  
> +	return val;
> +}
> +
> +static void hsw_activate_psr1(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u32 max_sleep_time = 0x1f;
> +	u32 val = EDP_PSR_ENABLE;
> +
> +	/* Let's use 6 as the minimum to cover all known cases including the
> +	 * off-by-one issue that HW has in some cases.
> +	 */
> +	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> +
> +	/* sink_sync_latency of 8 means source has to wait for more than 8
> +	 * frames, we'll go with 9 frames for now
> +	 */
> +	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
> +	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> +
> +	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> +	if (IS_HASWELL(dev_priv))
> +		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> +
> +	if (dev_priv->psr.link_standby)
> +		val |= EDP_PSR_LINK_STANDBY;
> +
> +	val |= psr1_tps_regs_val_get(intel_dp);

I'd prefer intel_psr1_tps...

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +
>  	if (INTEL_GEN(dev_priv) >= 8)
>  		val |= EDP_PSR_CRC_ENABLE;
>  
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
  2019-03-05 23:47 ` [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR José Roberto de Souza
@ 2019-03-11 23:34   ` Rodrigo Vivi
  2019-03-11 23:38     ` Souza, Jose
  0 siblings, 1 reply; 14+ messages in thread
From: Rodrigo Vivi @ 2019-03-11 23:34 UTC (permalink / raw)
  To: José Roberto de Souza; +Cc: intel-gfx, Dhinakaran Pandiyan

On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza wrote:
> TPS4 support was added to PSR because HBR3/PSR spec was not closed
> when ICL was freezed so if HBR3 was supported by PSR, ICL would
> already be ready but it was not added to spec so lets always
> disable TPS4.
> 
> v3: Missed ";" SPANK SPANK SPANK!!!
> 
> BSpec: 17524
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>  drivers/gpu/drm/i915/intel_psr.c | 3 +++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 16ce9c609c65..a7697909e0c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4205,6 +4205,8 @@ enum {
>  #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
>  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
>  #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
> +#define   EDP_PSR_TP4_TIME_SHIFT		(6) /* ICL+ */
> +#define   EDP_PSR_TP4_TIME_0US			(3 << EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */

could we please leave this as the rest of the reg and use (3 << 6)
imo easier to read because the rest of reg was already there

>  #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
>  #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
>  #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2fa2f4c9c935..c70d735f5b93 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u32 val = 0;
>  
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		val |= EDP_PSR_TP4_TIME_0US;
> +
>  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>  		val |= EDP_PSR_TP1_TIME_0us;
>  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
  2019-03-11 23:34   ` Rodrigo Vivi
@ 2019-03-11 23:38     ` Souza, Jose
  2019-03-11 23:44       ` Rodrigo Vivi
  0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2019-03-11 23:38 UTC (permalink / raw)
  To: Vivi, Rodrigo; +Cc: intel-gfx, Pandiyan, Dhinakaran


[-- Attachment #1.1: Type: text/plain, Size: 2437 bytes --]

On Mon, 2019-03-11 at 16:34 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza
> wrote:
> > TPS4 support was added to PSR because HBR3/PSR spec was not closed
> > when ICL was freezed so if HBR3 was supported by PSR, ICL would
> > already be ready but it was not added to spec so lets always
> > disable TPS4.
> > 
> > v3: Missed ";" SPANK SPANK SPANK!!!
> > 
> > BSpec: 17524
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> >  drivers/gpu/drm/i915/intel_psr.c | 3 +++
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 16ce9c609c65..a7697909e0c9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4205,6 +4205,8 @@ enum {
> >  #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
> >  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
> >  #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
> > +#define   EDP_PSR_TP4_TIME_SHIFT		(6) /* ICL+ */
> > +#define   EDP_PSR_TP4_TIME_0US			(3 <<
> > EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
> 
> could we please leave this as the rest of the reg and use (3 << 6)
> imo easier to read because the rest of reg was already there

Sure, I will change to (3 << 6)

> 
> >  #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
> >  #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
> >  #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2fa2f4c9c935..c70d735f5b93 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct
> > intel_dp *intel_dp)
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u32 val = 0;
> >  
> > +	if (INTEL_GEN(dev_priv) >= 11)
> > +		val |= EDP_PSR_TP4_TIME_0US;
> > +
> >  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> >  		val |= EDP_PSR_TP1_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> > -- 
> > 2.21.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
  2019-03-11 23:38     ` Souza, Jose
@ 2019-03-11 23:44       ` Rodrigo Vivi
  0 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-03-11 23:44 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx, Pandiyan, Dhinakaran

On Mon, Mar 11, 2019 at 04:38:00PM -0700, Souza, Jose wrote:
> On Mon, 2019-03-11 at 16:34 -0700, Rodrigo Vivi wrote:
> > On Tue, Mar 05, 2019 at 03:47:34PM -0800, José Roberto de Souza
> > wrote:
> > > TPS4 support was added to PSR because HBR3/PSR spec was not closed
> > > when ICL was freezed so if HBR3 was supported by PSR, ICL would
> > > already be ready but it was not added to spec so lets always
> > > disable TPS4.
> > > 
> > > v3: Missed ";" SPANK SPANK SPANK!!!
> > > 
> > > BSpec: 17524
> > > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> > >  drivers/gpu/drm/i915/intel_psr.c | 3 +++
> > >  2 files changed, 5 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 16ce9c609c65..a7697909e0c9 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4205,6 +4205,8 @@ enum {
> > >  #define   EDP_PSR_TP2_TP3_TIME_100us		(1 << 8)
> > >  #define   EDP_PSR_TP2_TP3_TIME_2500us		(2 << 8)
> > >  #define   EDP_PSR_TP2_TP3_TIME_0us		(3 << 8)
> > > +#define   EDP_PSR_TP4_TIME_SHIFT		(6) /* ICL+ */
> > > +#define   EDP_PSR_TP4_TIME_0US			(3 <<
> > > EDP_PSR_TP4_TIME_SHIFT) /* ICL+ */
> > 
> > could we please leave this as the rest of the reg and use (3 << 6)
> > imo easier to read because the rest of reg was already there
> 
> Sure, I will change to (3 << 6)


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> > 
> > >  #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
> > >  #define   EDP_PSR_TP1_TIME_100us		(1 << 4)
> > >  #define   EDP_PSR_TP1_TIME_2500us		(2 << 4)
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 2fa2f4c9c935..c70d735f5b93 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct
> > > intel_dp *intel_dp)
> > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >  	u32 val = 0;
> > >  
> > > +	if (INTEL_GEN(dev_priv) >= 11)
> > > +		val |= EDP_PSR_TP4_TIME_0US;
> > > +
> > >  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > >  		val |= EDP_PSR_TP1_TIME_0us;
> > >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> > > -- 
> > > 2.21.0
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
  2019-03-11 23:28   ` Rodrigo Vivi
@ 2019-03-12  0:15     ` Dhinakaran Pandiyan
  2019-03-12  3:22       ` Vivi, Rodrigo
  0 siblings, 1 reply; 14+ messages in thread
From: Dhinakaran Pandiyan @ 2019-03-12  0:15 UTC (permalink / raw)
  To: Rodrigo Vivi, José Roberto de Souza; +Cc: intel-gfx

On Mon, 2019-03-11 at 16:28 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 05, 2019 at 03:47:33PM -0800, José Roberto de Souza
> wrote:
> > This will make hsw_activate_psr1() more easy to read and will make
> > future modification to TPS registers more easy to review and read.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 56 +++++++++++++++++++---------
> > ----
> >  1 file changed, 33 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 831f345b4ad8..2fa2f4c9c935 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct
> > intel_dp *intel_dp)
> >  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> >  }
> >  
> > -static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > +static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -	u32 max_sleep_time = 0x1f;
> > -	u32 val = EDP_PSR_ENABLE;
> > -
> > -	/* Let's use 6 as the minimum to cover all known cases
> > including the
> > -	 * off-by-one issue that HW has in some cases.
> > -	 */
> > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -
> > -	/* sink_sync_latency of 8 means source has to wait for more
> > than 8
> > -	 * frames, we'll go with 9 frames for now
> > -	 */
> > -	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> > -	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> > -
> > -	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > -	if (IS_HASWELL(dev_priv))
> > -		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > -
> > -	if (dev_priv->psr.link_standby)
> > -		val |= EDP_PSR_LINK_STANDBY;
> > +	u32 val = 0;
> >  
> >  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > -		val |=  EDP_PSR_TP1_TIME_0us;
> > +		val |= EDP_PSR_TP1_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> >  		val |= EDP_PSR_TP1_TIME_100us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> > @@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> >  		val |= EDP_PSR_TP1_TIME_2500us;
> >  
> >  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> > -		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> > +		val |= EDP_PSR_TP2_TP3_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> >  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> >  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> > @@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> >  	else
> >  		val |= EDP_PSR_TP1_TP2_SEL;
> >  
> > +	return val;
> > +}
> > +
> > +static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > +{
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +	u32 max_sleep_time = 0x1f;
> > +	u32 val = EDP_PSR_ENABLE;
> > +
> > +	/* Let's use 6 as the minimum to cover all known cases
> > including the
> > +	 * off-by-one issue that HW has in some cases.
> > +	 */
> > +	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > +
> > +	/* sink_sync_latency of 8 means source has to wait for more
> > than 8
> > +	 * frames, we'll go with 9 frames for now
> > +	 */
> > +	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> > +	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> > +
> > +	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > +	if (IS_HASWELL(dev_priv))
> > +		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > +
> > +	if (dev_priv->psr.link_standby)
> > +		val |= EDP_PSR_LINK_STANDBY;
> > +
> > +	val |= psr1_tps_regs_val_get(intel_dp);
> 
> I'd prefer intel_psr1_tps...
> 

intel_psr1_get_tp_time(intel_dp)?

> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > +
> >  	if (INTEL_GEN(dev_priv) >= 8)
> >  		val |= EDP_PSR_CRC_ENABLE;
> >  
> > -- 
> > 2.21.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
  2019-03-12  0:15     ` Dhinakaran Pandiyan
@ 2019-03-12  3:22       ` Vivi, Rodrigo
  0 siblings, 0 replies; 14+ messages in thread
From: Vivi, Rodrigo @ 2019-03-12  3:22 UTC (permalink / raw)
  To: Pandiyan, Dhinakaran; +Cc: intel-gfx



> On Mar 11, 2019, at 5:15 PM, Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> wrote:
> 
>> On Mon, 2019-03-11 at 16:28 -0700, Rodrigo Vivi wrote:
>> On Tue, Mar 05, 2019 at 03:47:33PM -0800, José Roberto de Souza
>> wrote:
>>> This will make hsw_activate_psr1() more easy to read and will make
>>> future modification to TPS registers more easy to review and read.
>>> 
>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_psr.c | 56 +++++++++++++++++++---------
>>> ----
>>> 1 file changed, 33 insertions(+), 23 deletions(-)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>>> b/drivers/gpu/drm/i915/intel_psr.c
>>> index 831f345b4ad8..2fa2f4c9c935 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct
>>> intel_dp *intel_dp)
>>>    drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>>> DP_SET_POWER_D0);
>>> }
>>> 
>>> -static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>> +static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
>>> {
>>>    struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>> -    u32 max_sleep_time = 0x1f;
>>> -    u32 val = EDP_PSR_ENABLE;
>>> -
>>> -    /* Let's use 6 as the minimum to cover all known cases
>>> including the
>>> -     * off-by-one issue that HW has in some cases.
>>> -     */
>>> -    int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>>> -
>>> -    /* sink_sync_latency of 8 means source has to wait for more
>>> than 8
>>> -     * frames, we'll go with 9 frames for now
>>> -     */
>>> -    idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
>>> + 1);
>>> -    val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>>> -
>>> -    val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
>>> -    if (IS_HASWELL(dev_priv))
>>> -        val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>>> -
>>> -    if (dev_priv->psr.link_standby)
>>> -        val |= EDP_PSR_LINK_STANDBY;
>>> +    u32 val = 0;
>>> 
>>>    if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
>>> -        val |=  EDP_PSR_TP1_TIME_0us;
>>> +        val |= EDP_PSR_TP1_TIME_0us;
>>>    else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
>>>        val |= EDP_PSR_TP1_TIME_100us;
>>>    else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
>>> @@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp
>>> *intel_dp)
>>>        val |= EDP_PSR_TP1_TIME_2500us;
>>> 
>>>    if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
>>> -        val |=  EDP_PSR_TP2_TP3_TIME_0us;
>>> +        val |= EDP_PSR_TP2_TP3_TIME_0us;
>>>    else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
>>>        val |= EDP_PSR_TP2_TP3_TIME_100us;
>>>    else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
>>> @@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp
>>> *intel_dp)
>>>    else
>>>        val |= EDP_PSR_TP1_TP2_SEL;
>>> 
>>> +    return val;
>>> +}
>>> +
>>> +static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>> +{
>>> +    struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>>> +    u32 max_sleep_time = 0x1f;
>>> +    u32 val = EDP_PSR_ENABLE;
>>> +
>>> +    /* Let's use 6 as the minimum to cover all known cases
>>> including the
>>> +     * off-by-one issue that HW has in some cases.
>>> +     */
>>> +    int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>>> +
>>> +    /* sink_sync_latency of 8 means source has to wait for more
>>> than 8
>>> +     * frames, we'll go with 9 frames for now
>>> +     */
>>> +    idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
>>> + 1);
>>> +    val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>>> +
>>> +    val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
>>> +    if (IS_HASWELL(dev_priv))
>>> +        val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>>> +
>>> +    if (dev_priv->psr.link_standby)
>>> +        val |= EDP_PSR_LINK_STANDBY;
>>> +
>>> +    val |= psr1_tps_regs_val_get(intel_dp);
>> 
>> I'd prefer intel_psr1_tps...
>> 
> 
> intel_psr1_get_tp_time(intel_dp)?

+1

> 
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> 
>>> +
>>>    if (INTEL_GEN(dev_priv) >= 8)
>>>        val |= EDP_PSR_CRC_ENABLE;
>>> 
>>> -- 
>>> 2.21.0
>>> 
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-03-12  3:22 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-05 23:47 [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time José Roberto de Souza
2019-03-05 23:47 ` [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function José Roberto de Souza
2019-03-11 23:28   ` Rodrigo Vivi
2019-03-12  0:15     ` Dhinakaran Pandiyan
2019-03-12  3:22       ` Vivi, Rodrigo
2019-03-05 23:47 ` [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR José Roberto de Souza
2019-03-11 23:34   ` Rodrigo Vivi
2019-03-11 23:38     ` Souza, Jose
2019-03-11 23:44       ` Rodrigo Vivi
2019-03-06  0:11 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time Patchwork
2019-03-06  0:12 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-06  0:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-06  8:33 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-11 21:59 ` [PATCH v3 1/3] " Rodrigo Vivi

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