* [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register
@ 2019-03-05 13:52 Jani Nikula
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Jani Nikula @ 2019-03-05 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
PPS locking is a thing on pre-DDI, up to and including CPT and PPT.
The PPS divisor register exists up to gen 9 BC, replaced by a field in
the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on.
Commit b0a08bec9631 ("drm/i915/bxt: eDP Panel Power sequencing") stopped
using the divisor register, but inadvertently conflated the PPS unlock
in the change. No longer doing the unlocking was the right thing to do,
however we should've stopped already at LPT (or DDI platforms).
Deconflate the two.
Arguably this could be moved away from here altogether, but this is the
minimally intrusive change for now.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e1a051c0fbfe..e0f421e76305 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6425,15 +6425,16 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
intel_pps_get_registers(intel_dp, ®s);
- /* Workaround: Need to write PP_CONTROL with the unlock key as
- * the very first thing. */
pp_ctl = ironlake_get_pp_control(intel_dp);
+ /* Ensure PPS is unlocked */
+ if (!HAS_DDI(dev_priv))
+ I915_WRITE(regs.pp_ctrl, pp_ctl);
+
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
!HAS_PCH_ICP(dev_priv)) {
- I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
@ 2019-03-05 13:52 ` Jani Nikula
2019-03-05 20:17 ` Lucas De Marchi
2019-03-05 20:22 ` Rodrigo Vivi
2019-03-05 14:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from " Patchwork
` (5 subsequent siblings)
6 siblings, 2 replies; 11+ messages in thread
From: Jani Nikula @ 2019-03-05 13:52 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
register isn't there, and use i915_mmio_reg_valid() instead of repeating
the condition all over the place.
Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
value is unchanged from 0.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 73 ++++++++++++++++++---------------
1 file changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e0f421e76305..f40b3342d82a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
- !HAS_PCH_ICP(dev_priv))
+
+ /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
+ HAS_PCH_ICP(dev_priv))
+ regs->pp_div = INVALID_MMIO_REG;
+ else
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -6420,7 +6424,7 @@ static void
intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
+ u32 pp_on, pp_off, pp_ctl;
struct pps_registers regs;
intel_pps_get_registers(intel_dp, ®s);
@@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
- !HAS_PCH_ICP(dev_priv)) {
- pp_div = I915_READ(regs.pp_div);
- }
/* Pull timing values out of registers */
seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
@@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv)) {
+ if (i915_mmio_reg_valid(regs.pp_div)) {
+ u32 pp_div;
+
+ pp_div = I915_READ(regs.pp_div);
+
+ seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
+
+ } else {
seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
- } else {
- seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
}
}
@@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
bool force_disable_vdd)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, pp_div, port_sel = 0;
+ u32 pp_on, pp_off, port_sel = 0;
int div = dev_priv->rawclk_freq / 1000;
struct pps_registers regs;
enum port port = dp_to_dig_port(intel_dp)->base.port;
@@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
- /* Compute the divisor for the pp clock, simply match the Bspec
- * formula. */
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv)) {
- pp_div = I915_READ(regs.pp_ctrl);
- pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
- << BXT_POWER_CYCLE_DELAY_SHIFT);
- } else {
- pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
- << PANEL_POWER_CYCLE_DELAY_SHIFT);
- }
/* Haswell doesn't have any port selection bits for the panel
* power sequencer any more. */
@@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv))
- I915_WRITE(regs.pp_ctrl, pp_div);
- else
+
+ /*
+ * Compute the divisor for the pp clock, simply match the Bspec formula.
+ */
+ if (i915_mmio_reg_valid(regs.pp_div)) {
+ u32 pp_div;
+
+ pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
+ pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
+ PANEL_POWER_CYCLE_DELAY_SHIFT);
I915_WRITE(regs.pp_div, pp_div);
+ } else {
+ u32 pp_ctl;
+
+ pp_ctl = I915_READ(regs.pp_ctrl);
+ pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
+ pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
+ BXT_POWER_CYCLE_DELAY_SHIFT);
+ I915_WRITE(regs.pp_ctrl, pp_ctl);
+ }
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv)) ?
- (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
- I915_READ(regs.pp_div));
+ i915_mmio_reg_valid(regs.pp_div) ?
+ I915_READ(regs.pp_div) :
+ (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
}
static void intel_dp_pps_init(struct intel_dp *intel_dp)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
@ 2019-03-05 14:31 ` Patchwork
2019-03-05 16:28 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-05 14:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register
URL : https://patchwork.freedesktop.org/series/57579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5703 -> Patchwork_12369
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57579/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12369 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_psr@cursor_plane_move:
- fi-skl-6260u: NOTRUN -> SKIP [fdo#109271] +37
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: FAIL [fdo#108800] -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: SKIP [fdo#109271] / [fdo#109278] -> PASS +2
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: SKIP [fdo#109271] -> PASS +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Participating hosts (46 -> 42)
------------------------------
Additional (2): fi-icl-y fi-skl-6260u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5703 -> Patchwork_12369
CI_DRM_5703: 453da75010eb2a0806e75490b86d24beb6fa76a7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12369: 33141ce0b29f11928f8490784be562063771a5ae @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
33141ce0b29f drm/i915/dp: use single point of truth for PPS divisor register
e63397f4fcbe drm/i915/dp: deconflate PPS unlock from divisor register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12369/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
2019-03-05 14:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from " Patchwork
@ 2019-03-05 16:28 ` Patchwork
2019-03-05 20:19 ` [PATCH 1/2] " Rodrigo Vivi
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-05 16:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register
URL : https://patchwork.freedesktop.org/series/57579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5703_full -> Patchwork_12369_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12369_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12369_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12369_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@basic-busy-default:
- shard-iclb: NOTRUN -> WARN
* igt@gem_exec_schedule@independent-bsd:
- shard-iclb: NOTRUN -> DMESG-FAIL +1
* igt@gem_exec_schedule@out-order-vebox:
- shard-iclb: NOTRUN -> DMESG-WARN
* igt@gem_ringfill@basic-default-hang:
- shard-iclb: NOTRUN -> FAIL +4
* igt@runner@aborted:
- shard-iclb: NOTRUN -> ( 8 FAIL ) [fdo#106612]
Known issues
------------
Here are the changes found in Patchwork_12369_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@gem_ctx_isolation@rcs0-s3:
- shard-iclb: NOTRUN -> SKIP [fdo#109281] +17
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109281] +3
* igt@gem_ctx_param@invalid-param-get:
- shard-iclb: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
- shard-iclb: NOTRUN -> FAIL [fdo#109674]
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> SKIP [fdo#109314]
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-iclb: NOTRUN -> SKIP [fdo#109313]
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> SKIP [fdo#109283] +3
* igt@gem_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> SKIP [fdo#109289] +16
* igt@gem_exec_schedule@preempt-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +105
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +3
* igt@gem_mocs_settings@mocs-reset-ctx-render:
- shard-iclb: NOTRUN -> SKIP [fdo#109287] +11
* igt@gem_pwrite@huge-gtt-backwards:
- shard-iclb: NOTRUN -> SKIP [fdo#109290] +10
* igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> SKIP [fdo#109312] +1
* igt@gem_stolen@stolen-clear:
- shard-iclb: NOTRUN -> SKIP [fdo#109277] +10
* igt@i915_missed_irq:
- shard-iclb: NOTRUN -> SKIP [fdo#109503]
* igt@i915_pm_backlight@fade_with_suspend:
- shard-iclb: NOTRUN -> FAIL [fdo#107847]
* igt@i915_pm_lpsp@non-edp:
- shard-iclb: NOTRUN -> SKIP [fdo#109301] +3
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-iclb: NOTRUN -> SKIP [fdo#109308] +2
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> SKIP [fdo#109506]
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: NOTRUN -> INCOMPLETE [fdo#108840]
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-iclb: NOTRUN -> SKIP [fdo#109293]
* igt@i915_pm_rps@reset:
- shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] +1
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> SKIP [fdo#109288]
* igt@i915_query@query-topology-known-pci-ids:
- shard-iclb: NOTRUN -> SKIP [fdo#109303]
* igt@i915_query@query-topology-unsupported:
- shard-iclb: NOTRUN -> SKIP [fdo#109302]
* igt@i915_selftest@live_contexts:
- shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_atomic_transition@5x-modeset-transitions-fencing:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-iclb: NOTRUN -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-newfb-render-d:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +45
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +4
* igt@kms_ccs@pipe-a-crc-primary-rotation-180:
- shard-iclb: NOTRUN -> FAIL [fdo#107725] +6
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_chamelium@dp-frame-dump:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +36
* igt@kms_color@pipe-b-gamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782] +8
* igt@kms_color@pipe-c-ctm-max:
- shard-iclb: NOTRUN -> FAIL [fdo#108147] +1
* igt@kms_content_protection@atomic-dpms:
- shard-iclb: NOTRUN -> SKIP [fdo#109527]
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> SKIP [fdo#109300] / [fdo#109527] +1
* igt@kms_crtc_background_color:
- shard-iclb: NOTRUN -> SKIP [fdo#109305]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-iclb: NOTRUN -> FAIL [fdo#103232] +20
* igt@kms_cursor_crc@cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> SKIP [fdo#109279] +8
* igt@kms_cursor_crc@cursor-64x21-offscreen:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: NOTRUN -> FAIL [fdo#103355]
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: NOTRUN -> SKIP [fdo#109349] +1
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-iclb: NOTRUN -> FAIL [fdo#107791]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-iclb: NOTRUN -> FAIL [fdo#103833] +1
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +51
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip_tiling@flip-x-tiled:
- shard-skl: PASS -> FAIL [fdo#108145] / [fdo#108303]
* igt@kms_force_connector_basic@force-edid:
- shard-iclb: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +177
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +14
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +113
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +17
* igt@kms_invalid_dotclock:
- shard-iclb: NOTRUN -> SKIP [fdo#109310]
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-iclb: NOTRUN -> FAIL [fdo#103166] +5
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +1
- shard-apl: PASS -> FAIL [fdo#108948]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-iclb: NOTRUN -> INCOMPLETE [fdo#107713]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-iclb: NOTRUN -> FAIL [fdo#108948] +1
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] / [fdo#109278]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +4
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: NOTRUN -> SKIP [fdo#109642] +1
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> SKIP [fdo#109441] +15
* igt@kms_vblank@pipe-c-ts-continuation-modeset:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> SKIP [fdo#109502]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +131
* igt@prime_nv_api@nv_i915_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> SKIP [fdo#109291] +21
* igt@prime_vgem@basic-fence-flip:
- shard-iclb: NOTRUN -> SKIP [fdo#109294]
* igt@prime_vgem@coherency-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109292]
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> SKIP [fdo#109295] +2
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
* igt@v3d_get_param@get-bad-flags:
- shard-iclb: NOTRUN -> SKIP [fdo#109315] +4
#### Possible fixes ####
* igt@i915_suspend@debugfs-reader:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-apl: FAIL [fdo#109660] -> PASS
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_chv_cursor_fail@pipe-c-256x256-right-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: FAIL [fdo#103232] -> PASS +4
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-alpha-transparent:
- shard-skl: FAIL [fdo#109350] -> PASS
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_flip_tiling@flip-changes-tiling:
- shard-skl: FAIL [fdo#108303] -> PASS
* igt@kms_flip_tiling@flip-to-yf-tiled:
- shard-skl: FAIL [fdo#107931] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-glk: FAIL [fdo#103167] -> PASS +6
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: FAIL [fdo#103167] / [fdo#105682] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-glk: FAIL [fdo#103166] -> PASS +3
* igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm:
- shard-apl: FAIL [fdo#104894] -> PASS +1
* igt@perf_pmu@rc6:
- shard-kbl: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-apl: INCOMPLETE [fdo#103927] -> SKIP [fdo#109271]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102250]: https://bugs.freedesktop.org/show_bug.cgi?id=102250
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106510]: https://bugs.freedesktop.org/show_bug.cgi?id=106510
[fdo#106612]: https://bugs.freedesktop.org/show_bug.cgi?id=106612
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
[fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109281]: https://bugs.freedesktop.org/show_bug.cgi?id=109281
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
[fdo#109288]: https://bugs.freedesktop.org/show_bug.cgi?id=109288
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109305]: https://bugs.freedesktop.org/show_bug.cgi?id=109305
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109310]: https://bugs.freedesktop.org/show_bug.cgi?id=109310
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
[fdo#109503]: https://bugs.freedesktop.org/show_bug.cgi?id=109503
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
[fdo#109559]: https://bugs.freedesktop.org/show_bug.cgi?id=109559
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
Participating hosts (6 -> 7)
------------------------------
Additional (1): shard-iclb
Build changes
-------------
* Linux: CI_DRM_5703 -> Patchwork_12369
CI_DRM_5703: 453da75010eb2a0806e75490b86d24beb6fa76a7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12369: 33141ce0b29f11928f8490784be562063771a5ae @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12369/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
@ 2019-03-05 20:17 ` Lucas De Marchi
2019-03-05 20:22 ` Rodrigo Vivi
1 sibling, 0 replies; 11+ messages in thread
From: Lucas De Marchi @ 2019-03-05 20:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
>Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
>register isn't there, and use i915_mmio_reg_valid() instead of repeating
>the condition all over the place.
>
>Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
>value is unchanged from 0.
>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/intel_dp.c | 73 ++++++++++++++++++---------------
> 1 file changed, 39 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index e0f421e76305..f40b3342d82a 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
>- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>- !HAS_PCH_ICP(dev_priv))
>+
>+ /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
>+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>+ HAS_PCH_ICP(dev_priv))
>+ regs->pp_div = INVALID_MMIO_REG;
>+ else
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
>@@ -6420,7 +6424,7 @@ static void
> intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>- u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
>+ u32 pp_on, pp_off, pp_ctl;
> struct pps_registers regs;
>
> intel_pps_get_registers(intel_dp, ®s);
>@@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
>- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>- !HAS_PCH_ICP(dev_priv)) {
>- pp_div = I915_READ(regs.pp_div);
>- }
>
> /* Pull timing values out of registers */
> seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
>@@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
>- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>- HAS_PCH_ICP(dev_priv)) {
>+ if (i915_mmio_reg_valid(regs.pp_div)) {
>+ u32 pp_div;
>+
>+ pp_div = I915_READ(regs.pp_div);
>+
>+ seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
>+ PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
>+
>+ } else {
> seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
>- } else {
>- seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
>- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> }
> }
>
>@@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> bool force_disable_vdd)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>- u32 pp_on, pp_off, pp_div, port_sel = 0;
>+ u32 pp_on, pp_off, port_sel = 0;
> int div = dev_priv->rawclk_freq / 1000;
> struct pps_registers regs;
> enum port port = dp_to_dig_port(intel_dp)->base.port;
>@@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>- /* Compute the divisor for the pp clock, simply match the Bspec
>- * formula. */
>- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>- HAS_PCH_ICP(dev_priv)) {
>- pp_div = I915_READ(regs.pp_ctrl);
>- pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
>- << BXT_POWER_CYCLE_DELAY_SHIFT);
>- } else {
>- pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
>- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
>- << PANEL_POWER_CYCLE_DELAY_SHIFT);
>- }
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequencer any more. */
>@@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
>- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>- HAS_PCH_ICP(dev_priv))
>- I915_WRITE(regs.pp_ctrl, pp_div);
>- else
>+
>+ /*
>+ * Compute the divisor for the pp clock, simply match the Bspec formula.
>+ */
>+ if (i915_mmio_reg_valid(regs.pp_div)) {
>+ u32 pp_div;
>+
>+ pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
>+ pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
>+ PANEL_POWER_CYCLE_DELAY_SHIFT);
> I915_WRITE(regs.pp_div, pp_div);
>+ } else {
>+ u32 pp_ctl;
>+
>+ pp_ctl = I915_READ(regs.pp_ctrl);
>+ pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
>+ pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
>+ BXT_POWER_CYCLE_DELAY_SHIFT);
>+ I915_WRITE(regs.pp_ctrl, pp_ctl);
>+ }
>
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
>- (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>- HAS_PCH_ICP(dev_priv)) ?
>- (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>- I915_READ(regs.pp_div));
>+ i915_mmio_reg_valid(regs.pp_div) ?
>+ I915_READ(regs.pp_div) :
>+ (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
> }
>
> static void intel_dp_pps_init(struct intel_dp *intel_dp)
>--
>2.20.1
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
` (2 preceding siblings ...)
2019-03-05 16:28 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-03-05 20:19 ` Rodrigo Vivi
2019-03-06 8:17 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev2) Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2019-03-05 20:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Mar 05, 2019 at 03:52:14PM +0200, Jani Nikula wrote:
> PPS locking is a thing on pre-DDI, up to and including CPT and PPT.
>
> The PPS divisor register exists up to gen 9 BC, replaced by a field in
> the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on.
>
> Commit b0a08bec9631 ("drm/i915/bxt: eDP Panel Power sequencing") stopped
> using the divisor register, but inadvertently conflated the PPS unlock
> in the change. No longer doing the unlocking was the right thing to do,
> however we should've stopped already at LPT (or DDI platforms).
>
> Deconflate the two.
>
> Arguably this could be moved away from here altogether, but this is the
> minimally intrusive change for now.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e1a051c0fbfe..e0f421e76305 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6425,15 +6425,16 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>
> intel_pps_get_registers(intel_dp, ®s);
>
> - /* Workaround: Need to write PP_CONTROL with the unlock key as
> - * the very first thing. */
> pp_ctl = ironlake_get_pp_control(intel_dp);
>
> + /* Ensure PPS is unlocked */
> + if (!HAS_DDI(dev_priv))
> + I915_WRITE(regs.pp_ctrl, pp_ctl);
> +
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> !HAS_PCH_ICP(dev_priv)) {
> - I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
>
> --
> 2.20.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
2019-03-05 20:17 ` Lucas De Marchi
@ 2019-03-05 20:22 ` Rodrigo Vivi
2019-03-08 11:35 ` Jani Nikula
1 sibling, 1 reply; 11+ messages in thread
From: Rodrigo Vivi @ 2019-03-05 20:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
> Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
> register isn't there, and use i915_mmio_reg_valid() instead of repeating
> the condition all over the place.
>
> Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
> value is unchanged from 0.
great clean up. Thanks for that.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 73 ++++++++++++++++++---------------
> 1 file changed, 39 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e0f421e76305..f40b3342d82a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> - !HAS_PCH_ICP(dev_priv))
> +
> + /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + HAS_PCH_ICP(dev_priv))
> + regs->pp_div = INVALID_MMIO_REG;
> + else
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -6420,7 +6424,7 @@ static void
> intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> + u32 pp_on, pp_off, pp_ctl;
> struct pps_registers regs;
>
> intel_pps_get_registers(intel_dp, ®s);
> @@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> - !HAS_PCH_ICP(dev_priv)) {
> - pp_div = I915_READ(regs.pp_div);
> - }
>
> /* Pull timing values out of registers */
> seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> @@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv)) {
> + if (i915_mmio_reg_valid(regs.pp_div)) {
> + u32 pp_div;
> +
> + pp_div = I915_READ(regs.pp_div);
> +
> + seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> +
> + } else {
> seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
> - } else {
> - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> }
> }
>
> @@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> bool force_disable_vdd)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, pp_div, port_sel = 0;
> + u32 pp_on, pp_off, port_sel = 0;
> int div = dev_priv->rawclk_freq / 1000;
> struct pps_registers regs;
> enum port port = dp_to_dig_port(intel_dp)->base.port;
> @@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
> (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> - /* Compute the divisor for the pp clock, simply match the Bspec
> - * formula. */
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv)) {
> - pp_div = I915_READ(regs.pp_ctrl);
> - pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> - << BXT_POWER_CYCLE_DELAY_SHIFT);
> - } else {
> - pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> - << PANEL_POWER_CYCLE_DELAY_SHIFT);
> - }
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequencer any more. */
> @@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv))
> - I915_WRITE(regs.pp_ctrl, pp_div);
> - else
> +
> + /*
> + * Compute the divisor for the pp clock, simply match the Bspec formula.
> + */
> + if (i915_mmio_reg_valid(regs.pp_div)) {
> + u32 pp_div;
> +
> + pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> + pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
> + PANEL_POWER_CYCLE_DELAY_SHIFT);
> I915_WRITE(regs.pp_div, pp_div);
> + } else {
> + u32 pp_ctl;
> +
> + pp_ctl = I915_READ(regs.pp_ctrl);
> + pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
> + pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
> + BXT_POWER_CYCLE_DELAY_SHIFT);
> + I915_WRITE(regs.pp_ctrl, pp_ctl);
> + }
>
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv)) ?
> - (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> - I915_READ(regs.pp_div));
> + i915_mmio_reg_valid(regs.pp_div) ?
> + I915_READ(regs.pp_div) :
> + (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
> }
>
> static void intel_dp_pps_init(struct intel_dp *intel_dp)
> --
> 2.20.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev2)
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
` (3 preceding siblings ...)
2019-03-05 20:19 ` [PATCH 1/2] " Rodrigo Vivi
@ 2019-03-06 8:17 ` Patchwork
2019-03-06 10:33 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3) Patchwork
2019-03-06 15:06 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-06 8:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev2)
URL : https://patchwork.freedesktop.org/series/57579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12389
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12389 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12389, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57579/revisions/2/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12389:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: PASS -> INCOMPLETE
* igt@i915_selftest@live_requests:
- fi-byt-j1900: PASS -> DMESG-WARN
* igt@runner@aborted:
- fi-byt-j1900: NOTRUN -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12389 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7560u: PASS -> FAIL [fdo#103375]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5708 -> Patchwork_12389
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12389: fb3fb873190d5e6ad6a35f4f1490cf3127565cdd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fb3fb873190d drm/i915/dp: use single point of truth for PPS divisor register
44f86ec22c7d drm/i915/dp: deconflate PPS unlock from divisor register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12389/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3)
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
` (4 preceding siblings ...)
2019-03-06 8:17 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev2) Patchwork
@ 2019-03-06 10:33 ` Patchwork
2019-03-06 15:06 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-06 10:33 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3)
URL : https://patchwork.freedesktop.org/series/57579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12392
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/57579/revisions/3/mbox/
Known issues
------------
Here are the changes found in Patchwork_12392 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@readonly-bsd1:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#109831]
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: PASS -> SKIP [fdo#109271]
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_selftest@live_contexts:
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831
Participating hosts (47 -> 42)
------------------------------
Additional (1): fi-icl-u2
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5708 -> Patchwork_12392
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12392: 0bfebdd71a7cecdbddf6aa75a1a3c776935d952e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0bfebdd71a7c drm/i915/dp: use single point of truth for PPS divisor register
48afdab96953 drm/i915/dp: deconflate PPS unlock from divisor register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12392/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3)
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
` (5 preceding siblings ...)
2019-03-06 10:33 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3) Patchwork
@ 2019-03-06 15:06 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2019-03-06 15:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3)
URL : https://patchwork.freedesktop.org/series/57579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12392_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12392_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_big:
- shard-hsw: PASS -> TIMEOUT [fdo#107937]
* igt@gem_exec_schedule@preempt-other-chain-blt:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +115
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-newfb-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +17
* igt@kms_color@pipe-a-legacy-gamma:
- shard-glk: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip_tiling@flip-yf-tiled:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +15
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
#### Possible fixes ####
* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_cursor_crc@cursor-256x85-offscreen:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: FAIL [fdo#109350] -> PASS
- shard-glk: FAIL [fdo#109350] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-skl: FAIL [fdo#103167] / [fdo#105682] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-apl: FAIL [fdo#103166] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107937]: https://bugs.freedesktop.org/show_bug.cgi?id=107937
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (6 -> 6)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5708 -> Patchwork_12392
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12392: 0bfebdd71a7cecdbddf6aa75a1a3c776935d952e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12392/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
2019-03-05 20:22 ` Rodrigo Vivi
@ 2019-03-08 11:35 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2019-03-08 11:35 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, 05 Mar 2019, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
>> Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
>> register isn't there, and use i915_mmio_reg_valid() instead of repeating
>> the condition all over the place.
>>
>> Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
>> value is unchanged from 0.
>
> great clean up. Thanks for that.
>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks for the reviews, pushed to dinq.
BR,
Jani.
>
>
>
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 73 ++++++++++++++++++---------------
>> 1 file changed, 39 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index e0f421e76305..f40b3342d82a 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp,
>> regs->pp_stat = PP_STATUS(pps_idx);
>> regs->pp_on = PP_ON_DELAYS(pps_idx);
>> regs->pp_off = PP_OFF_DELAYS(pps_idx);
>> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>> - !HAS_PCH_ICP(dev_priv))
>> +
>> + /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
>> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>> + HAS_PCH_ICP(dev_priv))
>> + regs->pp_div = INVALID_MMIO_REG;
>> + else
>> regs->pp_div = PP_DIVISOR(pps_idx);
>> }
>>
>> @@ -6420,7 +6424,7 @@ static void
>> intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> - u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
>> + u32 pp_on, pp_off, pp_ctl;
>> struct pps_registers regs;
>>
>> intel_pps_get_registers(intel_dp, ®s);
>> @@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>>
>> pp_on = I915_READ(regs.pp_on);
>> pp_off = I915_READ(regs.pp_off);
>> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
>> - !HAS_PCH_ICP(dev_priv)) {
>> - pp_div = I915_READ(regs.pp_div);
>> - }
>>
>> /* Pull timing values out of registers */
>> seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
>> @@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
>> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
>> PANEL_POWER_DOWN_DELAY_SHIFT;
>>
>> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>> - HAS_PCH_ICP(dev_priv)) {
>> + if (i915_mmio_reg_valid(regs.pp_div)) {
>> + u32 pp_div;
>> +
>> + pp_div = I915_READ(regs.pp_div);
>> +
>> + seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
>> + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
>> +
>> + } else {
>> seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
>> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
>> - } else {
>> - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
>> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
>> }
>> }
>>
>> @@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>> bool force_disable_vdd)
>> {
>> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>> - u32 pp_on, pp_off, pp_div, port_sel = 0;
>> + u32 pp_on, pp_off, port_sel = 0;
>> int div = dev_priv->rawclk_freq / 1000;
>> struct pps_registers regs;
>> enum port port = dp_to_dig_port(intel_dp)->base.port;
>> @@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>> (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
>> pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
>> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>> - /* Compute the divisor for the pp clock, simply match the Bspec
>> - * formula. */
>> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>> - HAS_PCH_ICP(dev_priv)) {
>> - pp_div = I915_READ(regs.pp_ctrl);
>> - pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
>> - << BXT_POWER_CYCLE_DELAY_SHIFT);
>> - } else {
>> - pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
>> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
>> - << PANEL_POWER_CYCLE_DELAY_SHIFT);
>> - }
>>
>> /* Haswell doesn't have any port selection bits for the panel
>> * power sequencer any more. */
>> @@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
>>
>> I915_WRITE(regs.pp_on, pp_on);
>> I915_WRITE(regs.pp_off, pp_off);
>> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>> - HAS_PCH_ICP(dev_priv))
>> - I915_WRITE(regs.pp_ctrl, pp_div);
>> - else
>> +
>> + /*
>> + * Compute the divisor for the pp clock, simply match the Bspec formula.
>> + */
>> + if (i915_mmio_reg_valid(regs.pp_div)) {
>> + u32 pp_div;
>> +
>> + pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
>> + pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
>> + PANEL_POWER_CYCLE_DELAY_SHIFT);
>> I915_WRITE(regs.pp_div, pp_div);
>> + } else {
>> + u32 pp_ctl;
>> +
>> + pp_ctl = I915_READ(regs.pp_ctrl);
>> + pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
>> + pp_ctl |= (DIV_ROUND_UP(seq->t11_t12, 1000) <<
>> + BXT_POWER_CYCLE_DELAY_SHIFT);
>> + I915_WRITE(regs.pp_ctrl, pp_ctl);
>> + }
>>
>> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>> I915_READ(regs.pp_on),
>> I915_READ(regs.pp_off),
>> - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
>> - HAS_PCH_ICP(dev_priv)) ?
>> - (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>> - I915_READ(regs.pp_div));
>> + i915_mmio_reg_valid(regs.pp_div) ?
>> + I915_READ(regs.pp_div) :
>> + (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
>> }
>>
>> static void intel_dp_pps_init(struct intel_dp *intel_dp)
>> --
>> 2.20.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-03-08 11:35 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-05 13:52 [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register Jani Nikula
2019-03-05 13:52 ` [PATCH 2/2] drm/i915/dp: use single point of truth for PPS " Jani Nikula
2019-03-05 20:17 ` Lucas De Marchi
2019-03-05 20:22 ` Rodrigo Vivi
2019-03-08 11:35 ` Jani Nikula
2019-03-05 14:31 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from " Patchwork
2019-03-05 16:28 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-03-05 20:19 ` [PATCH 1/2] " Rodrigo Vivi
2019-03-06 8:17 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev2) Patchwork
2019-03-06 10:33 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dp: deconflate PPS unlock from divisor register (rev3) Patchwork
2019-03-06 15:06 ` ✓ Fi.CI.IGT: " Patchwork
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