* [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
@ 2019-03-07 12:15 David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 01/32] s390x/tcg: Define vector instruction formats David Hildenbrand
` (39 more replies)
0 siblings, 40 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
This is the first part of vector instruction support for s390x. Parts
will be sent and reviewed piece by piece.
Part 1: Vector Support Instructions
Part 2: Vector Integer Instructions
Part 3: Vector String Instructions
Part 4: Vector Floating-Point Instructions
The current state can be found at (kept updated):
https://github.com/davidhildenbrand/qemu/tree/vx
It is based on
https://github.com/cohuck/qemu/tree/s390-next
With the current state I can boot Linux kernel + user space compiled with
SIMD support. This allows to boot distributions compiled exclusively for
z13, requiring SIMD support. Also, I have a growing set of tests for
kvm-unit-tests and tests/tcg which I cross-test on a real s390x system.
In this part, the basic infrastructure and all Vector Support Instructions
introduced with the "Vector Facility" are added. The Vector Extension
Facilities are not considered for now.
We make use of the existing gvec expansion + ool (out-of-line) support.
This will be heavily used especially for part 2 (Integer Instructions)
where we can actually reuse quite some existing gvec expansions.
v2 -> v3:
- "s390x/tcg: Utilities for vector instruction helpers"
-- inline helpers in header file
- "s390x/tcg: Implement VECTOR LOAD MULTIPLE"
-- optimize loading of last element
- "s390x/tcg: Implement VECTOR PACK *"
-- make the static funtion arrays const
- "s390x/tcg: Implement VECTOR REPLICATE"
-- use "tcg_gen_gvec_dup_mem"
- "s390x/tcg: Provide probe_write helper"
-- Add check for CONFIG_USER_ONLY
-- Optimize calculation of length
- Added r-b's
v1 -> v2:
- Basically address all wonderful review comments from Richard (too many
to name them all)
- Probe write access to get rid of FIXMEs
- Heavily rework "s390x/tcg: Implement VECTOR PACK *"
-- Process cc and !cc separately.
-- Helper for VPK
- Don't use a temporary vector register (for now)
- Drop load_vec_element() and store_vec_element()
- Use ES_* instead of MO_*, will come in handy when we use ES_128 later
- .... many many other minor things
David Hildenbrand (32):
s390x/tcg: Define vector instruction formats
s390x/tcg: Check vector register instructions at central point
s390x/tcg: Utilities for vector instruction helpers
s390x/tcg: Implement VECTOR GATHER ELEMENT
s390x/tcg: Implement VECTOR GENERATE BYTE MASK
s390x/tcg: Implement VECTOR GENERATE MASK
s390x/tcg: Implement VECTOR LOAD
s390x/tcg: Implement VECTOR LOAD AND REPLICATE
s390x/tcg: Implement VECTOR LOAD ELEMENT
s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
s390x/tcg: Implement VECTOR LOAD MULTIPLE
s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
s390x/tcg: Implement VECTOR LOAD WITH LENGTH
s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
s390x/tcg: Implement VECTOR PACK *
s390x/tcg: Implement VECTOR PERMUTE
s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
s390x/tcg: Implement VECTOR REPLICATE
s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
s390x/tcg: Implement VECTOR SCATTER ELEMENT
s390x/tcg: Implement VECTOR SELECT
s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
s390x/tcg: Provide probe_write_access helper
s390x/tcg: Implement VECTOR STORE
s390x/tcg: Implement VECTOR STORE ELEMENT
s390x/tcg: Implement VECTOR STORE MULTIPLE
s390x/tcg: Implement VECTOR STORE WITH LENGTH
s390x/tcg: Implement VECTOR UNPACK *
target/s390x/Makefile.objs | 1 +
target/s390x/cpu.h | 7 +
target/s390x/helper.h | 21 +
target/s390x/insn-data.def | 82 +++
target/s390x/insn-format.def | 25 +
target/s390x/internal.h | 2 +
target/s390x/mem_helper.c | 25 +
target/s390x/translate.c | 61 ++-
target/s390x/translate_vx.inc.c | 935 ++++++++++++++++++++++++++++++++
target/s390x/vec.h | 101 ++++
target/s390x/vec_helper.c | 193 +++++++
11 files changed, 1452 insertions(+), 1 deletion(-)
create mode 100644 target/s390x/translate_vx.inc.c
create mode 100644 target/s390x/vec.h
create mode 100644 target/s390x/vec_helper.c
--
2.17.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 01/32] s390x/tcg: Define vector instruction formats
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 02/32] s390x/tcg: Check vector register instructions at central point David Hildenbrand
` (38 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
These are the new instruction formats related to vector instructions as
up to the z14 (a.k.a. latest PoP).
As v2 appeares (like x2 in VRX) with d2/b2 in VRV, we have to assign it a
higher field number to avoid collisions.
Properly take care of the MSB (to be able to address 32 registers) for
each vector register field stored in the RXB field (Bit 36 - 30 for all
vector instructions). As we have 32 bit vector registers and the
"v" fields are only 4 bit in size, the 5th bit is stored in the RXB.
We use a new type to indicate that the MSB has to be fetched from the
RXB.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-format.def | 25 +++++++++++++++++++++++
target/s390x/translate.c | 39 +++++++++++++++++++++++++++++++++++-
2 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/target/s390x/insn-format.def b/target/s390x/insn-format.def
index 4297ff4165..6253edbd19 100644
--- a/target/s390x/insn-format.def
+++ b/target/s390x/insn-format.def
@@ -54,3 +54,28 @@ F4(SS_e, R(1, 8), BD(2,16,20), R(3,12), BD(4,32,36))
F3(SS_f, BD(1,16,20), L(2,8,8), BD(2,32,36))
F2(SSE, BD(1,16,20), BD(2,32,36))
F3(SSF, BD(1,16,20), BD(2,32,36), R(3,8))
+F3(VRI_a, V(1,8), I(2,16,16), M(3,32))
+F4(VRI_b, V(1,8), I(2,16,8), I(3,24,8), M(4,32))
+F4(VRI_c, V(1,8), V(3,12), I(2,16,16), M(4,32))
+F5(VRI_d, V(1,8), V(2,12), V(3,16), I(4,24,8), M(5,32))
+F5(VRI_e, V(1,8), V(2,12), I(3,16,12), M(5,28), M(4,32))
+F5(VRI_f, V(1,8), V(2,12), V(3,16), M(5,24), I(4,28,8))
+F5(VRI_g, V(1,8), V(2,12), I(4,16,8), M(5,24), I(3,28,8))
+F3(VRI_h, V(1,8), I(2,16,16), I(3,32,4))
+F4(VRI_i, V(1,8), R(2,12), M(4,24), I(3,28,8))
+F5(VRR_a, V(1,8), V(2,12), M(5,24), M(4,28), M(3,32))
+F5(VRR_b, V(1,8), V(2,12), V(3,16), M(5,24), M(4,32))
+F6(VRR_c, V(1,8), V(2,12), V(3,16), M(6,24), M(5,28), M(4,32))
+F6(VRR_d, V(1,8), V(2,12), V(3,16), M(5,20), M(6,24), V(4,32))
+F6(VRR_e, V(1,8), V(2,12), V(3,16), M(6,20), M(5,28), V(4,32))
+F3(VRR_f, V(1,8), R(2,12), R(3,16))
+F1(VRR_g, V(1,12))
+F3(VRR_h, V(1,12), V(2,16), M(3,24))
+F3(VRR_i, R(1,8), V(2,12), M(3,24))
+F4(VRS_a, V(1,8), V(3,12), BD(2,16,20), M(4,32))
+F4(VRS_b, V(1,8), R(3,12), BD(2,16,20), M(4,32))
+F4(VRS_c, R(1,8), V(3,12), BD(2,16,20), M(4,32))
+F3(VRS_d, R(3,12), BD(2,16,20), V(1,32))
+F4(VRV, V(1,8), V(2,12), BD(2,16,20), M(3,32))
+F3(VRX, V(1,8), BXD(2), M(3,32))
+F3(VSI, I(3,8,8), BD(2,16,20), V(1,32))
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 41fb466bb4..1d8030f8cd 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -985,6 +985,7 @@ static void free_compare(DisasCompare *c)
#define F3(N, X1, X2, X3) F0(N)
#define F4(N, X1, X2, X3, X4) F0(N)
#define F5(N, X1, X2, X3, X4, X5) F0(N)
+#define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
typedef enum {
#include "insn-format.def"
@@ -996,6 +997,7 @@ typedef enum {
#undef F3
#undef F4
#undef F5
+#undef F6
/* Define a structure to hold the decoded fields. We'll store each inside
an array indexed by an enum. In order to conserve memory, we'll arrange
@@ -1010,6 +1012,8 @@ enum DisasFieldIndexO {
FLD_O_m1,
FLD_O_m3,
FLD_O_m4,
+ FLD_O_m5,
+ FLD_O_m6,
FLD_O_b1,
FLD_O_b2,
FLD_O_b4,
@@ -1023,7 +1027,11 @@ enum DisasFieldIndexO {
FLD_O_i2,
FLD_O_i3,
FLD_O_i4,
- FLD_O_i5
+ FLD_O_i5,
+ FLD_O_v1,
+ FLD_O_v2,
+ FLD_O_v3,
+ FLD_O_v4,
};
enum DisasFieldIndexC {
@@ -1031,6 +1039,7 @@ enum DisasFieldIndexC {
FLD_C_m1 = 0,
FLD_C_b1 = 0,
FLD_C_i1 = 0,
+ FLD_C_v1 = 0,
FLD_C_r2 = 1,
FLD_C_b2 = 1,
@@ -1039,20 +1048,25 @@ enum DisasFieldIndexC {
FLD_C_r3 = 2,
FLD_C_m3 = 2,
FLD_C_i3 = 2,
+ FLD_C_v3 = 2,
FLD_C_m4 = 3,
FLD_C_b4 = 3,
FLD_C_i4 = 3,
FLD_C_l1 = 3,
+ FLD_C_v4 = 3,
FLD_C_i5 = 4,
FLD_C_d1 = 4,
+ FLD_C_m5 = 4,
FLD_C_d2 = 5,
+ FLD_C_m6 = 5,
FLD_C_d4 = 6,
FLD_C_x2 = 6,
FLD_C_l2 = 6,
+ FLD_C_v2 = 6,
NUM_C_FIELD = 7
};
@@ -1097,6 +1111,7 @@ typedef struct DisasFormatInfo {
#define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
#define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
+#define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N }
#define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
{ BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
#define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
@@ -1116,6 +1131,7 @@ typedef struct DisasFormatInfo {
#define F3(N, X1, X2, X3) { { X1, X2, X3 } },
#define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
#define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
+#define F6(N, X1, X2, X3, X4, X5, X6) { { X1, X2, X3, X4, X5, X6 } },
static const DisasFormatInfo format_info[] = {
#include "insn-format.def"
@@ -1127,8 +1143,10 @@ static const DisasFormatInfo format_info[] = {
#undef F3
#undef F4
#undef F5
+#undef F6
#undef R
#undef M
+#undef V
#undef BD
#undef BXD
#undef BDL
@@ -6119,6 +6137,25 @@ static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
case 2: /* dl+dh split, signed 20 bit. */
r = ((int8_t)r << 12) | (r >> 8);
break;
+ case 3: /* MSB stored in RXB */
+ g_assert(f->size == 4);
+ switch (f->beg) {
+ case 8:
+ r |= extract64(insn, 63 - 36, 1) << 4;
+ break;
+ case 12:
+ r |= extract64(insn, 63 - 37, 1) << 4;
+ break;
+ case 16:
+ r |= extract64(insn, 63 - 38, 1) << 4;
+ break;
+ case 32:
+ r |= extract64(insn, 63 - 39, 1) << 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
default:
abort();
}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 02/32] s390x/tcg: Check vector register instructions at central point
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 01/32] s390x/tcg: Define vector instruction formats David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers David Hildenbrand
` (37 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Check them at a central point. We'll use a new instruction flag to
flag all vector instructions (IF_VEC) and handle it very similar to
AFP, whereby we use another unused position in the PSW mask to store
the state of vector register enablement per translation block.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cpu.h | 7 +++++++
target/s390x/translate.c | 12 ++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index b71ac5183d..cb6d77053a 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -257,6 +257,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
/* PSW defines */
#undef PSW_MASK_PER
#undef PSW_MASK_UNUSED_2
+#undef PSW_MASK_UNUSED_3
#undef PSW_MASK_DAT
#undef PSW_MASK_IO
#undef PSW_MASK_EXT
@@ -276,6 +277,7 @@ extern const struct VMStateDescription vmstate_s390_cpu;
#define PSW_MASK_PER 0x4000000000000000ULL
#define PSW_MASK_UNUSED_2 0x2000000000000000ULL
+#define PSW_MASK_UNUSED_3 0x1000000000000000ULL
#define PSW_MASK_DAT 0x0400000000000000ULL
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
@@ -323,12 +325,14 @@ extern const struct VMStateDescription vmstate_s390_cpu;
/* we'll use some unused PSW positions to store CR flags in tb flags */
#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
#define CR0_SECONDARY 0x0000000004000000ULL
#define CR0_EDAT 0x0000000000800000ULL
#define CR0_AFP 0x0000000000040000ULL
+#define CR0_VECTOR 0x0000000000020000ULL
#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
#define CR0_CKC_SC 0x0000000000000800ULL
@@ -373,6 +377,9 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
if (env->cregs[0] & CR0_AFP) {
*flags |= FLAG_MASK_AFP;
}
+ if (env->cregs[0] & CR0_VECTOR) {
+ *flags |= FLAG_MASK_VECTOR;
+ }
}
/* PER bits from control register 9 */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 1d8030f8cd..d52c02c572 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -1203,6 +1203,7 @@ typedef struct {
#define IF_BFP 0x0008 /* binary floating point instruction */
#define IF_DFP 0x0010 /* decimal floating point instruction */
#define IF_PRIV 0x0020 /* privileged instruction */
+#define IF_VEC 0x0040 /* vector instruction */
struct DisasInsn {
unsigned opc:16;
@@ -6337,11 +6338,22 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
if (insn->flags & IF_DFP) {
dxc = 3;
}
+ if (insn->flags & IF_VEC) {
+ dxc = 0xfe;
+ }
if (dxc) {
gen_data_exception(dxc);
return DISAS_NORETURN;
}
}
+
+ /* if vector instructions not enabled, executing them is forbidden */
+ if (insn->flags & IF_VEC) {
+ if (!((s->base.tb->flags & FLAG_MASK_VECTOR))) {
+ gen_data_exception(0xfe);
+ return DISAS_NORETURN;
+ }
+ }
}
/* Check for insn specification exceptions. */
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 01/32] s390x/tcg: Define vector instruction formats David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 02/32] s390x/tcg: Check vector register instructions at central point David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 13:11 ` Thomas Huth
2019-03-07 14:00 ` Richard Henderson
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 04/32] s390x/tcg: Implement VECTOR GATHER ELEMENT David Hildenbrand
` (36 subsequent siblings)
39 siblings, 2 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
We'll have to read/write vector elements quite frequently from helpers.
The tricky bit is properly taking care of endianess. Handle it similar
to aarch64.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/vec.h | 101 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
create mode 100644 target/s390x/vec.h
diff --git a/target/s390x/vec.h b/target/s390x/vec.h
new file mode 100644
index 0000000000..3313fb43ee
--- /dev/null
+++ b/target/s390x/vec.h
@@ -0,0 +1,101 @@
+/*
+ * QEMU TCG support -- s390x vector utilitites
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef S390X_VEC_H
+#define S390X_VEC_H
+
+typedef union S390Vector {
+ uint64_t doubleword[2];
+ uint32_t word[4];
+ uint16_t halfword[8];
+ uint8_t byte[16];
+} S390Vector;
+
+/*
+ * Each vector is stored as two 64bit host values. So when talking about
+ * byte/halfword/word numbers, we have to take care of proper translation
+ * between element numbers.
+ *
+ * Big Endian (target/possible host)
+ * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
+ * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
+ * W: [ 0][ 1] - [ 2][ 3]
+ * DW: [ 0] - [ 1]
+ *
+ * Little Endian (possible host)
+ * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
+ * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
+ * W: [ 1][ 0] - [ 3][ 2]
+ * DW: [ 0] - [ 1]
+ */
+#ifndef HOST_WORDS_BIGENDIAN
+#define H1(x) ((x) ^ 7)
+#define H2(x) ((x) ^ 3)
+#define H4(x) ((x) ^ 1)
+#else
+#define H1(x) (x)
+#define H2(x) (x)
+#define H4(x) (x)
+#endif
+
+static inline uint8_t s390_vec_read_element8(const S390Vector *v, uint8_t enr)
+{
+ g_assert(enr < 16);
+ return v->byte[H1(enr)];
+}
+
+static inline uint16_t s390_vec_read_element16(const S390Vector *v, uint8_t enr)
+{
+ g_assert(enr < 8);
+ return v->halfword[H2(enr)];
+}
+
+static inline uint32_t s390_vec_read_element32(const S390Vector *v, uint8_t enr)
+{
+ g_assert(enr < 4);
+ return v->word[H4(enr)];
+}
+
+static inline uint64_t s390_vec_read_element64(const S390Vector *v, uint8_t enr)
+{
+ g_assert(enr < 2);
+ return v->doubleword[enr];
+}
+
+static inline void s390_vec_write_element8(S390Vector *v, uint8_t enr,
+ uint8_t data)
+{
+ g_assert(enr < 16);
+ v->byte[H1(enr)] = data;
+}
+
+static inline void s390_vec_write_element16(S390Vector *v, uint8_t enr,
+ uint16_t data)
+{
+ g_assert(enr < 8);
+ v->halfword[H2(enr)] = data;
+}
+
+static inline void s390_vec_write_element32(S390Vector *v, uint8_t enr,
+ uint32_t data)
+{
+ g_assert(enr < 4);
+ v->word[H4(enr)] = data;
+}
+
+static inline void s390_vec_write_element64(S390Vector *v, uint8_t enr,
+ uint64_t data)
+{
+ g_assert(enr < 2);
+ v->doubleword[enr] = data;
+}
+
+#endif /* S390X_VEC_H */
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 04/32] s390x/tcg: Implement VECTOR GATHER ELEMENT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (2 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 05/32] s390x/tcg: Implement VECTOR GENERATE BYTE MASK David Hildenbrand
` (35 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Let's start with a more involved one, but it is the first in the list
of vector support instructions (introduced with the vector facility).
Good thing is, we need a lot of basic infrastructure for this. Reading
and writing vector elements as well as checking element validity.
All vector instruction related translation functions will reside in
translate_vx.inc.c, to be included in translate.c - similar to how
other architectures handle it.
While at it, directly add some documentation (which contains parts about
things added in follow-up patches, but splitting this up does not make
too much sense). Also add ES_* defines heavily used later.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 6 ++
target/s390x/translate.c | 2 +
target/s390x/translate_vx.inc.c | 135 ++++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 target/s390x/translate_vx.inc.c
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 61b750a855..7d128ac9d6 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -972,6 +972,12 @@
D(0xb93e, KIMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KIMD)
D(0xb93f, KLMD, RRE, MSA, 0, 0, 0, 0, msa, 0, S390_FEAT_TYPE_KLMD)
+/* === Vector Support Instructions === */
+
+/* VECTOR GATHER ELEMENT */
+ E(0xe713, VGEF, VRV, V, la2, 0, 0, 0, vge, 0, ES_32, IF_VEC)
+ E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)
+
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index d52c02c572..a1c6698dea 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5120,6 +5120,8 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
}
#endif
+#include "translate_vx.inc.c"
+
/* ====================================================================== */
/* The "Cc OUTput" generators. Given the generated output (and in some cases
the original inputs), update the various cc data structures in order to
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
new file mode 100644
index 0000000000..9864ec5134
--- /dev/null
+++ b/target/s390x/translate_vx.inc.c
@@ -0,0 +1,135 @@
+/*
+ * QEMU TCG support -- s390x vector instruction translation functions
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * For most instructions that use the same element size for reads and
+ * writes, we can use real gvec vector expansion, which potantially uses
+ * real host vector instructions. As they only work up to 64 bit elements,
+ * 128 bit elements (vector is a single element) have to be handled
+ * differently. Operations that are too complicated to encode via TCG ops
+ * are handled via gvec ool (out-of-line) handlers.
+ *
+ * As soon as instructions use different element sizes for reads and writes
+ * or access elements "out of their element scope" we expand them manually
+ * in fancy loops, as gvec expansion does not deal with actual element
+ * numbers and does also not support access to other elements.
+ *
+ * 128 bit elements:
+ * As we only have i32/i64, such elements have to be loaded into two
+ * i64 values and can then be processed e.g. by tcg_gen_add2_i64.
+ *
+ * Sizes:
+ * On s390x, the operand size (oprsz) and the maximum size (maxsz) are
+ * always 16 (128 bit). What gvec code calls "vece", s390x calls "es",
+ * a.k.a. "element size". These values nicely map to MO_8 ... MO_64. Only
+ * 128 bit element size has to be treated in a special way (MO_64 + 1).
+ * We will use ES_* instead of MO_* for this reason in this file.
+ *
+ * CC handling:
+ * As gvec ool-helpers can currently not return values (besides via
+ * pointers like vectors or cpu_env), whenever we have to set the CC and
+ * can't conclude the value from the result vector, we will directly
+ * set it in "env->cc_op" and mark it as static via set_cc_static()".
+ * Whenever this is done, the helper writes globals (cc_op).
+ */
+
+#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es))
+#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))
+
+#define ES_8 MO_8
+#define ES_16 MO_16
+#define ES_32 MO_32
+#define ES_64 MO_64
+#define ES_128 4
+
+static inline bool valid_vec_element(uint8_t enr, TCGMemOp es)
+{
+ return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1));
+}
+
+static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_ld8u_i64(dst, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i64(dst, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_ld32u_i64(dst, cpu_env, offs);
+ break;
+ case ES_8 | MO_SIGN:
+ tcg_gen_ld8s_i64(dst, cpu_env, offs);
+ break;
+ case ES_16 | MO_SIGN:
+ tcg_gen_ld16s_i64(dst, cpu_env, offs);
+ break;
+ case ES_32 | MO_SIGN:
+ tcg_gen_ld32s_i64(dst, cpu_env, offs);
+ break;
+ case ES_64:
+ case ES_64 | MO_SIGN:
+ tcg_gen_ld_i64(dst, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_st8_i64(src, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_st16_i64(src, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_st32_i64(src, cpu_env, offs);
+ break;
+ case ES_64:
+ tcg_gen_st_i64(src, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s->fields, v2), enr, es);
+ tcg_gen_add_i64(o->addr1, o->addr1, tmp);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
+
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 05/32] s390x/tcg: Implement VECTOR GENERATE BYTE MASK
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (3 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 04/32] s390x/tcg: Implement VECTOR GATHER ELEMENT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 06/32] s390x/tcg: Implement VECTOR GENERATE MASK David Hildenbrand
` (34 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Let's optimize it for the common cases (setting a vector to zero or all
ones) - courtesy of Richard.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c | 1 +
target/s390x/translate_vx.inc.c | 39 +++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 7d128ac9d6..d3f66c858f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -977,6 +977,8 @@
/* VECTOR GATHER ELEMENT */
E(0xe713, VGEF, VRV, V, la2, 0, 0, 0, vge, 0, ES_32, IF_VEC)
E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)
+/* VECTOR GENERATE BYTE MASK */
+ F(0xe744, VGBM, VRI_a, V, 0, 0, 0, 0, vgbm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a1c6698dea..588fc21dd2 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -34,6 +34,7 @@
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9864ec5134..395c0ebcc2 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -112,6 +112,9 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+#define gen_gvec_dup64i(v1, c) \
+ tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
@@ -133,3 +136,39 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static uint64_t generate_byte_mask(uint8_t mask)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if ((mask >> i) & 1) {
+ r |= 0xffull << (i * 8);
+ }
+ }
+ return r;
+}
+
+static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
+{
+ const uint16_t i2 = get_field(s->fields, i2);
+
+ if (i2 == (i2 & 0xff) * 0x0101) {
+ /*
+ * Masks for both 64 bit elements of the vector are the same.
+ * Trust tcg to produce a good constant loading.
+ */
+ gen_gvec_dup64i(get_field(s->fields, v1),
+ generate_byte_mask(i2 & 0xff));
+ } else {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
+ write_vec_element_i64(t, get_field(s->fields, v1), 0, ES_64);
+ tcg_gen_movi_i64(t, generate_byte_mask(i2));
+ write_vec_element_i64(t, get_field(s->fields, v1), 1, ES_64);
+ tcg_temp_free_i64(t);
+ }
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 06/32] s390x/tcg: Implement VECTOR GENERATE MASK
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (4 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 05/32] s390x/tcg: Implement VECTOR GENERATE BYTE MASK David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 07/32] s390x/tcg: Implement VECTOR LOAD David Hildenbrand
` (33 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Add gen_gvec_dupi() for handling duplication of immediates, so it can
be reused later.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 47 +++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d3f66c858f..c8cd5dfa24 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -979,6 +979,8 @@
E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)
/* VECTOR GENERATE BYTE MASK */
F(0xe744, VGBM, VRI_a, V, 0, 0, 0, 0, vgbm, 0, IF_VEC)
+/* VECTOR GENERATE MASK */
+ F(0xe746, VGM, VRI_b, V, 0, 0, 0, 0, vgm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 395c0ebcc2..28edd9b0c4 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -44,6 +44,7 @@
#define NUM_VEC_ELEMENT_BYTES(es) (1 << (es))
#define NUM_VEC_ELEMENTS(es) (16 / NUM_VEC_ELEMENT_BYTES(es))
+#define NUM_VEC_ELEMENT_BITS(es) (NUM_VEC_ELEMENT_BYTES(es) * BITS_PER_BYTE)
#define ES_8 MO_8
#define ES_16 MO_16
@@ -115,6 +116,26 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
+{
+ switch (es) {
+ case ES_8:
+ tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
+ break;
+ case ES_16:
+ tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
+ break;
+ case ES_32:
+ tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
+ break;
+ case ES_64:
+ gen_gvec_dup64i(reg, c);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
@@ -172,3 +193,29 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ const uint8_t bits = NUM_VEC_ELEMENT_BITS(es);
+ const uint8_t i2 = get_field(s->fields, i2) & (bits - 1);
+ const uint8_t i3 = get_field(s->fields, i3) & (bits - 1);
+ uint64_t mask = 0;
+ int i;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* generate the mask - take care of wrapping */
+ for (i = i2; ; i = (i + 1) % bits) {
+ mask |= 1ull << (bits - i - 1);
+ if (i == i3) {
+ break;
+ }
+ }
+
+ gen_gvec_dupi(es, get_field(s->fields, v1), mask);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 07/32] s390x/tcg: Implement VECTOR LOAD
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (5 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 06/32] s390x/tcg: Implement VECTOR GENERATE MASK David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 08/32] s390x/tcg: Implement VECTOR LOAD AND REPLICATE David Hildenbrand
` (32 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
When loading from memory, load both elements into temps first before
modifying the target vector
Loading with strange alingment from the end of the address space will
not properly wrap, we can ignore that for now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 3 +++
target/s390x/translate_vx.inc.c | 24 ++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index c8cd5dfa24..f129e51d41 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -981,6 +981,9 @@
F(0xe744, VGBM, VRI_a, V, 0, 0, 0, 0, vgbm, 0, IF_VEC)
/* VECTOR GENERATE MASK */
F(0xe746, VGM, VRI_b, V, 0, 0, 0, 0, vgm, 0, IF_VEC)
+/* VECTOR LOAD */
+ F(0xe706, VL, VRX, V, la2, 0, 0, 0, vl, 0, IF_VEC)
+ F(0xe756, VLR, VRR_a, V, 0, 0, 0, 0, vlr, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 28edd9b0c4..9063784a76 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -113,6 +113,9 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+#define gen_gvec_mov(v1, v2) \
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
+ 16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
@@ -219,3 +222,24 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
gen_gvec_dupi(es, get_field(s->fields, v1), mask);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_mov(get_field(s->fields, v1), get_field(s->fields, v2));
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 08/32] s390x/tcg: Implement VECTOR LOAD AND REPLICATE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (6 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 07/32] s390x/tcg: Implement VECTOR LOAD David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 09/32] s390x/tcg: Implement VECTOR LOAD ELEMENT David Hildenbrand
` (31 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
We can use tcg_gen_gvec_dup_i64() to carry out the duplication.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f129e51d41..7be8977989 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -984,6 +984,8 @@
/* VECTOR LOAD */
F(0xe706, VL, VRX, V, la2, 0, 0, 0, vl, 0, IF_VEC)
F(0xe756, VLR, VRR_a, V, 0, 0, 0, 0, vlr, 0, IF_VEC)
+/* VECTOR LOAD AND REPLICATE */
+ F(0xe705, VLREP, VRX, V, la2, 0, 0, 0, vlrep, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9063784a76..ede4cc4f6d 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -113,6 +113,8 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+#define gen_gvec_dup_i64(es, v1, c) \
+ tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
#define gen_gvec_mov(v1, v2) \
tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
16)
@@ -243,3 +245,20 @@ static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
gen_gvec_mov(get_field(s->fields, v1), get_field(s->fields, v2));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ gen_gvec_dup_i64(es, get_field(s->fields, v1), tmp);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 09/32] s390x/tcg: Implement VECTOR LOAD ELEMENT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (7 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 08/32] s390x/tcg: Implement VECTOR LOAD AND REPLICATE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 10/32] s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE David Hildenbrand
` (30 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Fairly easy, load with desired size and store it into the right element.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 5 +++++
target/s390x/translate_vx.inc.c | 18 ++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 7be8977989..aec0a3ba97 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -986,6 +986,11 @@
F(0xe756, VLR, VRR_a, V, 0, 0, 0, 0, vlr, 0, IF_VEC)
/* VECTOR LOAD AND REPLICATE */
F(0xe705, VLREP, VRX, V, la2, 0, 0, 0, vlrep, 0, IF_VEC)
+/* VECTOR LOAD ELEMENT */
+ E(0xe700, VLEB, VRX, V, la2, 0, 0, 0, vle, 0, ES_8, IF_VEC)
+ E(0xe701, VLEH, VRX, V, la2, 0, 0, 0, vle, 0, ES_16, IF_VEC)
+ E(0xe703, VLEF, VRX, V, la2, 0, 0, 0, vle, 0, ES_32, IF_VEC)
+ E(0xe702, VLEG, VRX, V, la2, 0, 0, 0, vle, 0, ES_64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index ede4cc4f6d..9134324aa8 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -262,3 +262,21 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 10/32] s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (8 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 09/32] s390x/tcg: Implement VECTOR LOAD ELEMENT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 11/32] s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT David Hildenbrand
` (29 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Take care of properly sign-extending the immediate.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 5 +++++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index aec0a3ba97..782d49e1db 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -991,6 +991,11 @@
E(0xe701, VLEH, VRX, V, la2, 0, 0, 0, vle, 0, ES_16, IF_VEC)
E(0xe703, VLEF, VRX, V, la2, 0, 0, 0, vle, 0, ES_32, IF_VEC)
E(0xe702, VLEG, VRX, V, la2, 0, 0, 0, vle, 0, ES_64, IF_VEC)
+/* VECTOR LOAD ELEMENT IMMEDIATE */
+ E(0xe740, VLEIB, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_8, IF_VEC)
+ E(0xe741, VLEIH, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_16, IF_VEC)
+ E(0xe743, VLEIF, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_32, IF_VEC)
+ E(0xe742, VLEIG, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9134324aa8..d450ce2d2b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -280,3 +280,20 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_const_i64((int16_t)get_field(s->fields, i2));
+ write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 11/32] s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (9 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 10/32] s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 12/32] s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO David Hildenbrand
` (28 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
To avoid an helper, we have to do the actual calculation of the element
address (offset in cpu_env + cpu_env) manually. Factor that out into
get_vec_element_ptr_i64(). The same logic will be reused for "VECTOR
LOAD VR ELEMENT FROM GR".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 63 +++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 782d49e1db..de811ddc47 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -996,6 +996,8 @@
E(0xe741, VLEIH, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_16, IF_VEC)
E(0xe743, VLEIF, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_32, IF_VEC)
E(0xe742, VLEIG, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)
+/* VECTOR LOAD GR FROM VR ELEMENT */
+ F(0xe721, VLGV, VRS_c, V, la2, 0, r1, 0, vlgv, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index d450ce2d2b..b163100b0d 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -113,6 +113,28 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
+ uint8_t es)
+{
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ /* mask off invalid parts from the element nr */
+ tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1);
+
+ /* convert it to an element offset relative to cpu_env (vec_reg_offset() */
+ tcg_gen_shli_i64(tmp, tmp, es);
+#ifndef HOST_WORDS_BIGENDIAN
+ tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es));
+#endif
+ tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg));
+
+ /* generate the final ptr by adding cpu_env */
+ tcg_gen_trunc_i64_ptr(ptr, tmp);
+ tcg_gen_add_ptr(ptr, ptr, cpu_env);
+
+ tcg_temp_free_i64(tmp);
+}
+
#define gen_gvec_dup_i64(es, v1, c) \
tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
#define gen_gvec_mov(v1, v2) \
@@ -297,3 +319,44 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_ptr ptr;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* fast path if we don't need the register content */
+ if (!get_field(s->fields, b2)) {
+ uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+
+ read_vec_element_i64(o->out, get_field(s->fields, v3), enr, es);
+ return DISAS_NEXT;
+ }
+
+ ptr = tcg_temp_new_ptr();
+ get_vec_element_ptr_i64(ptr, get_field(s->fields, v3), o->addr1, es);
+ switch (es) {
+ case ES_8:
+ tcg_gen_ld8u_i64(o->out, ptr, 0);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i64(o->out, ptr, 0);
+ break;
+ case ES_32:
+ tcg_gen_ld32u_i64(o->out, ptr, 0);
+ break;
+ case ES_64:
+ tcg_gen_ld_i64(o->out, ptr, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_ptr(ptr);
+
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 12/32] s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (10 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 11/32] s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 13/32] s390x/tcg: Implement VECTOR LOAD MULTIPLE David Hildenbrand
` (27 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Fairly easy, zero out the vector before we load the desired element.
Load the element before touching the vector.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 46 +++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index de811ddc47..2b36205c84 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -998,6 +998,8 @@
E(0xe742, VLEIG, VRI_a, V, 0, 0, 0, 0, vlei, 0, ES_64, IF_VEC)
/* VECTOR LOAD GR FROM VR ELEMENT */
F(0xe721, VLGV, VRS_c, V, la2, 0, r1, 0, vlgv, 0, IF_VEC)
+/* VECTOR LOAD LOGICAL ELEMENT AND ZERO */
+ F(0xe704, VLLEZ, VRX, V, la2, 0, 0, 0, vllez, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b163100b0d..cdad2a52f0 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -163,6 +163,11 @@ static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
}
}
+static void zero_vec(uint8_t reg)
+{
+ tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
+}
+
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
@@ -360,3 +365,44 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
+
+static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
+{
+ uint8_t es = get_field(s->fields, m3);
+ uint8_t enr;
+ TCGv_i64 t;
+
+ switch (es) {
+ /* rightmost sub-element of leftmost doubleword */
+ case ES_8:
+ enr = 7;
+ break;
+ case ES_16:
+ enr = 3;
+ break;
+ case ES_32:
+ enr = 1;
+ break;
+ case ES_64:
+ enr = 0;
+ break;
+ /* leftmost sub-element of leftmost doubleword */
+ case 6:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ es = ES_32;
+ enr = 0;
+ break;
+ }
+ default:
+ /* fallthrough */
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ t = tcg_temp_new_i64();
+ tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
+ zero_vec(get_field(s->fields, v1));
+ write_vec_element_i64(t, get_field(s->fields, v1), enr, es);
+ tcg_temp_free_i64(t);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 13/32] s390x/tcg: Implement VECTOR LOAD MULTIPLE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (11 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 12/32] s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 14/32] s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY David Hildenbrand
` (26 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Try to load the last element first. Access to the first element will
be checked afterwards. This way, we can guarantee that the vector is
not modified before we checked for all possible exceptions. (16 vectors
cannot cross more than two pages)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 40 +++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2b36205c84..fa0f3a9003 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1000,6 +1000,8 @@
F(0xe721, VLGV, VRS_c, V, la2, 0, r1, 0, vlgv, 0, IF_VEC)
/* VECTOR LOAD LOGICAL ELEMENT AND ZERO */
F(0xe704, VLLEZ, VRX, V, la2, 0, 0, 0, vllez, 0, IF_VEC)
+/* VECTOR LOAD MULTIPLE */
+ F(0xe736, VLM, VRS_a, V, la2, 0, 0, 0, vlm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index cdad2a52f0..083f5c6213 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -406,3 +406,43 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v3 = get_field(s->fields, v3);
+ uint8_t v1 = get_field(s->fields, v1);
+ TCGv_i64 t0, t1;
+
+ if (v3 < v1 || (v3 - v1 + 1) > 16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /*
+ * Check for possible access exceptions by trying to load the last
+ * element. The first element will be checked first next.
+ */
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ gen_addi_and_wrap_i64(s, t0, o->addr1, (v3 - v1) * 16 + 8);
+ tcg_gen_qemu_ld_i64(t0, t0, get_mem_index(s), MO_TEQ);
+
+ for (;; v1++) {
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t1, v1, 0, ES_64);
+ if (v1 == v3) {
+ break;
+ }
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
+ write_vec_element_i64(t1, v1, 1, ES_64);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ }
+
+ /* Store the last element, loaded first */
+ write_vec_element_i64(t0, v1, 1, ES_64);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 14/32] s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (12 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 13/32] s390x/tcg: Implement VECTOR LOAD MULTIPLE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 15/32] s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR David Hildenbrand
` (25 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Very similar to LOAD COUNT TO BLOCK BOUNDARY, but instead of only
calculating, the actual vector is loaded. Use a temporary vector to
not modify the real vector on exceptions. Initialize that one to zero,
to not leak any data. Provide a fast path if we're loading a full
vector.
As we don't have gvec ool handlers for single vectors, just calculate
the vector address manually.
We can reuse the helper later on for VECTOR LOAD WITH LENGTH. In fact,
we are going to name it "vll" right from the beginning, because that's
a better match.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/Makefile.objs | 1 +
target/s390x/helper.h | 3 +++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 25 +++++++++++++++++++
target/s390x/vec_helper.c | 44 +++++++++++++++++++++++++++++++++
5 files changed, 75 insertions(+)
create mode 100644 target/s390x/vec_helper.c
diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs
index 22a9a9927a..68eeee3d2f 100644
--- a/target/s390x/Makefile.objs
+++ b/target/s390x/Makefile.objs
@@ -1,6 +1,7 @@
obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
+obj-$(CONFIG_TCG) += vec_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
obj-$(CONFIG_SOFTMMU) += sigp.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index bb659257f6..6c745ba0f6 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -124,6 +124,9 @@ DEF_HELPER_5(msa, i32, env, i32, i32, i32, i32)
DEF_HELPER_FLAGS_1(stpt, TCG_CALL_NO_RWG, i64, env)
DEF_HELPER_FLAGS_1(stck, TCG_CALL_NO_RWG_SE, i64, env)
+/* === Vector Support Instructions === */
+DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
+
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
DEF_HELPER_4(diag, void, env, i32, i32, i32)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fa0f3a9003..ad8df5283c 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1002,6 +1002,8 @@
F(0xe704, VLLEZ, VRX, V, la2, 0, 0, 0, vllez, 0, IF_VEC)
/* VECTOR LOAD MULTIPLE */
F(0xe736, VLM, VRS_a, V, la2, 0, 0, 0, vlm, 0, IF_VEC)
+/* VECTOR LOAD TO BLOCK BOUNDARY */
+ F(0xe707, VLBB, VRX, V, la2, 0, 0, 0, vlbb, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 083f5c6213..f1eb458902 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -446,3 +446,28 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
+{
+ const int64_t block_size = (1ull << (get_field(s->fields, m3) + 6));
+ const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ TCGv_ptr a0;
+ TCGv_i64 bytes;
+
+ if (get_field(s->fields, m3) > 6) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ bytes = tcg_temp_new_i64();
+ a0 = tcg_temp_new_ptr();
+ /* calculate the number of bytes until the next block boundary */
+ tcg_gen_ori_i64(bytes, o->addr1, -block_size);
+ tcg_gen_neg_i64(bytes, bytes);
+
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vll(cpu_env, a0, o->addr1, bytes);
+ tcg_temp_free_i64(bytes);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_helper.c b/target/s390x/vec_helper.c
new file mode 100644
index 0000000000..5b2333a8d6
--- /dev/null
+++ b/target/s390x/vec_helper.c
@@ -0,0 +1,44 @@
+/*
+ * QEMU TCG support -- s390x vector support instructions
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "internal.h"
+#include "vec.h"
+#include "tcg/tcg.h"
+#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+#include "exec/exec-all.h"
+
+void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes)
+{
+ if (likely(bytes >= 16)) {
+ uint64_t t0, t1;
+
+ t0 = cpu_ldq_data_ra(env, addr, GETPC());
+ addr = wrap_address(env, addr + 8);
+ t1 = cpu_ldq_data_ra(env, addr, GETPC());
+ s390_vec_write_element64(v1, 0, t0);
+ s390_vec_write_element64(v1, 1, t1);
+ } else {
+ S390Vector tmp = {};
+ int i;
+
+ for (i = 0; i < bytes; i++) {
+ uint8_t byte = cpu_ldub_data_ra(env, addr, GETPC());
+
+ s390_vec_write_element8(&tmp, i, byte);
+ addr = wrap_address(env, addr + 1);
+ }
+ *(S390Vector *)v1 = tmp;
+ }
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 15/32] s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (13 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 14/32] s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 16/32] s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT David Hildenbrand
` (24 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Very similar to VECTOR LOAD GR FROM VR ELEMENT, just the opposite
direction. Also provide a fast path in case we don't care about the
register content.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 41 +++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ad8df5283c..6814061204 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1004,6 +1004,8 @@
F(0xe736, VLM, VRS_a, V, la2, 0, 0, 0, vlm, 0, IF_VEC)
/* VECTOR LOAD TO BLOCK BOUNDARY */
F(0xe707, VLBB, VRX, V, la2, 0, 0, 0, vlbb, 0, IF_VEC)
+/* VECTOR LOAD VR ELEMENT FROM GR */
+ F(0xe722, VLVG, VRS_b, V, la2, r3, 0, 0, vlvg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index f1eb458902..287bd9627d 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -471,3 +471,44 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_ptr ptr;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* fast path if we don't need the register content */
+ if (!get_field(s->fields, b2)) {
+ uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+
+ write_vec_element_i64(o->in2, get_field(s->fields, v1), enr, es);
+ return DISAS_NEXT;
+ }
+
+ ptr = tcg_temp_new_ptr();
+ get_vec_element_ptr_i64(ptr, get_field(s->fields, v1), o->addr1, es);
+ switch (es) {
+ case ES_8:
+ tcg_gen_st8_i64(o->in2, ptr, 0);
+ break;
+ case ES_16:
+ tcg_gen_st16_i64(o->in2, ptr, 0);
+ break;
+ case ES_32:
+ tcg_gen_st32_i64(o->in2, ptr, 0);
+ break;
+ case ES_64:
+ tcg_gen_st_i64(o->in2, ptr, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_ptr(ptr);
+
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 16/32] s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (14 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 15/32] s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 17/32] s390x/tcg: Implement VECTOR LOAD WITH LENGTH David Hildenbrand
` (23 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Fairly easy, just load from to gprs into a single vector.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 6814061204..bdd66758fa 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1006,6 +1006,8 @@
F(0xe707, VLBB, VRX, V, la2, 0, 0, 0, vlbb, 0, IF_VEC)
/* VECTOR LOAD VR ELEMENT FROM GR */
F(0xe722, VLVG, VRS_b, V, la2, r3, 0, 0, vlvg, 0, IF_VEC)
+/* VECTOR LOAD VR FROM GRS DISJOINT */
+ F(0xe762, VLVGP, VRR_f, V, r2, r3, 0, 0, vlvgp, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 287bd9627d..abd33a9e3d 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -512,3 +512,10 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
+{
+ write_vec_element_i64(o->in1, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(o->in2, get_field(s->fields, v1), 1, ES_64);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 17/32] s390x/tcg: Implement VECTOR LOAD WITH LENGTH
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (15 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 16/32] s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 18/32] s390x/tcg: Implement VECTOR MERGE (HIGH|LOW) David Hildenbrand
` (22 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
We can reuse the helper introduced along with VECTOR LOAD TO BLOCK
BOUNDARY. We just have to take care of converting the highest index into
a length.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c | 7 +++++++
target/s390x/translate_vx.inc.c | 13 +++++++++++++
3 files changed, 22 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index bdd66758fa..3c0b14bafd 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1008,6 +1008,8 @@
F(0xe722, VLVG, VRS_b, V, la2, r3, 0, 0, vlvg, 0, IF_VEC)
/* VECTOR LOAD VR FROM GRS DISJOINT */
F(0xe762, VLVGP, VRR_f, V, r2, r3, 0, 0, vlvgp, 0, IF_VEC)
+/* VECTOR LOAD WITH LENGTH */
+ F(0xe737, VLL, VRS_b, V, la2, r3_32u, 0, 0, vll, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 588fc21dd2..0afa8f7ca5 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5794,6 +5794,13 @@ static void in2_r3_sr32(DisasContext *s, DisasFields *f, DisasOps *o)
}
#define SPEC_in2_r3_sr32 0
+static void in2_r3_32u(DisasContext *s, DisasFields *f, DisasOps *o)
+{
+ o->in2 = tcg_temp_new_i64();
+ tcg_gen_ext32u_i64(o->in2, regs[get_field(f, r3)]);
+}
+#define SPEC_in2_r3_32u 0
+
static void in2_r2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index abd33a9e3d..b8e69856cd 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -519,3 +519,16 @@ static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
write_vec_element_i64(o->in2, get_field(s->fields, v1), 1, ES_64);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
+{
+ const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+
+ /* convert highest index into an actual length */
+ tcg_gen_addi_i64(o->in2, o->in2, 1);
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vll(cpu_env, a0, o->addr1, o->in2);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 18/32] s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (16 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 17/32] s390x/tcg: Implement VECTOR LOAD WITH LENGTH David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 19/32] s390x/tcg: Implement VECTOR PACK * David Hildenbrand
` (21 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
We cannot use gvec expansion as source and destination elements are
have different element numbers. So we'll expand using a fancy loop.
Also, we have to take care of overlapping source and destination
registers, therefore use a safe evaluation irder depending on the
operation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 42 +++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 3c0b14bafd..f7232f8615 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1010,6 +1010,10 @@
F(0xe762, VLVGP, VRR_f, V, r2, r3, 0, 0, vlvgp, 0, IF_VEC)
/* VECTOR LOAD WITH LENGTH */
F(0xe737, VLL, VRS_b, V, la2, r3_32u, 0, 0, vll, 0, IF_VEC)
+/* VECTOR MERGE HIGH */
+ F(0xe761, VMRH, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
+/* VECTOR MERGE LOW */
+ F(0xe760, VMRL, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b8e69856cd..9c2cf8a77b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -532,3 +532,45 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t es = get_field(s->fields, m4);
+ int dst_idx, src_idx;
+ TCGv_i64 tmp;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ if (s->fields->op2 == 0x61) {
+ /* iterate backwards to avoid overwriting data we might need later */
+ for (dst_idx = NUM_VEC_ELEMENTS(es) - 1; dst_idx >= 0; dst_idx--) {
+ src_idx = dst_idx / 2;
+ if (dst_idx % 2 == 0) {
+ read_vec_element_i64(tmp, v2, src_idx, es);
+ } else {
+ read_vec_element_i64(tmp, v3, src_idx, es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, es);
+ }
+ } else {
+ /* iterate forward to avoid overwriting data we might need later */
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(es); dst_idx++) {
+ src_idx = (dst_idx + NUM_VEC_ELEMENTS(es)) / 2;
+ if (dst_idx % 2 == 0) {
+ read_vec_element_i64(tmp, v2, src_idx, es);
+ } else {
+ read_vec_element_i64(tmp, v3, src_idx, es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, es);
+ }
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 19/32] s390x/tcg: Implement VECTOR PACK *
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (17 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 18/32] s390x/tcg: Implement VECTOR MERGE (HIGH|LOW) David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 20/32] s390x/tcg: Implement VECTOR PERMUTE David Hildenbrand
` (20 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
This is a big one. Luckily we only have a limited set of such nasty
instructions.
We'll implement all variants with helpers, except when sources and
the destination don't overlap for VECTOR PACK. Provide different helpers
when the cc is to be modified. We'll return the cc then via env->cc_op.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 15 +++++
target/s390x/insn-data.def | 6 ++
target/s390x/translate_vx.inc.c | 89 +++++++++++++++++++++++++++
target/s390x/vec_helper.c | 105 ++++++++++++++++++++++++++++++++
4 files changed, 215 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 6c745ba0f6..315495f49f 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -126,6 +126,21 @@ DEF_HELPER_FLAGS_1(stck, TCG_CALL_NO_RWG_SE, i64, env)
/* === Vector Support Instructions === */
DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
+DEF_HELPER_FLAGS_4(gvec_vpk16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpk32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpk64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpks16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpks32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpks64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_5(gvec_vpks_cc16, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vpks_cc32, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vpks_cc64, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vpkls16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpkls32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vpkls64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_5(gvec_vpkls_cc16, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vpkls_cc32, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f7232f8615..39cd6f27c1 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1014,6 +1014,12 @@
F(0xe761, VMRH, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
/* VECTOR MERGE LOW */
F(0xe760, VMRL, VRR_c, V, 0, 0, 0, 0, vmr, 0, IF_VEC)
+/* VECTOR PACK */
+ F(0xe794, VPK, VRR_c, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
+/* VECTOR PACK SATURATE */
+ F(0xe797, VPKS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
+/* VECTOR PACK LOGICAL SATURATE */
+ F(0xe795, VPKLS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9c2cf8a77b..7ae38f71f7 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -135,6 +135,12 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
tcg_temp_free_i64(tmp);
}
+#define gen_gvec_3_ool(v1, v2, v3, data, fn) \
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, data, fn)
+#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
#define gen_gvec_dup_i64(es, v1, c) \
tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
#define gen_gvec_mov(v1, v2) \
@@ -574,3 +580,86 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t es = get_field(s->fields, m4);
+ static gen_helper_gvec_3 * const vpk[3] = {
+ gen_helper_gvec_vpk16,
+ gen_helper_gvec_vpk32,
+ gen_helper_gvec_vpk64,
+ };
+ static gen_helper_gvec_3 * const vpks[3] = {
+ gen_helper_gvec_vpks16,
+ gen_helper_gvec_vpks32,
+ gen_helper_gvec_vpks64,
+ };
+ static gen_helper_gvec_3_ptr * const vpks_cc[3] = {
+ gen_helper_gvec_vpks_cc16,
+ gen_helper_gvec_vpks_cc32,
+ gen_helper_gvec_vpks_cc64,
+ };
+ static gen_helper_gvec_3 * const vpkls[3] = {
+ gen_helper_gvec_vpkls16,
+ gen_helper_gvec_vpkls32,
+ gen_helper_gvec_vpkls64,
+ };
+ static gen_helper_gvec_3_ptr * const vpkls_cc[3] = {
+ gen_helper_gvec_vpkls_cc16,
+ gen_helper_gvec_vpkls_cc32,
+ gen_helper_gvec_vpkls_cc64,
+ };
+
+ if (es == ES_8 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0x97:
+ if (get_field(s->fields, m5) & 0x1) {
+ gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]);
+ }
+ break;
+ case 0x95:
+ if (get_field(s->fields, m5) & 0x1) {
+ gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]);
+ set_cc_static(s);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]);
+ }
+ break;
+ case 0x94:
+ /* If sources and destination dont't overlap -> fast path */
+ if (v1 != v2 && v1 != v3) {
+ const uint8_t src_es = get_field(s->fields, m4);
+ const uint8_t dst_es = src_es - 1;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ int dst_idx, src_idx;
+
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
+ src_idx = dst_idx;
+ if (src_idx < NUM_VEC_ELEMENTS(src_es)) {
+ read_vec_element_i64(tmp, v2, src_idx, src_es);
+ } else {
+ src_idx -= NUM_VEC_ELEMENTS(src_es);
+ read_vec_element_i64(tmp, v3, src_idx, src_es);
+ }
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+ tcg_temp_free_i64(tmp);
+ } else {
+ gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_helper.c b/target/s390x/vec_helper.c
index 5b2333a8d6..7f680201b5 100644
--- a/target/s390x/vec_helper.c
+++ b/target/s390x/vec_helper.c
@@ -15,6 +15,7 @@
#include "internal.h"
#include "vec.h"
#include "tcg/tcg.h"
+#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
@@ -42,3 +43,107 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes)
*(S390Vector *)v1 = tmp;
}
}
+
+#define DEF_VPK_HFN(BITS, TBITS) \
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
+static int vpk##BITS##_hfn(S390Vector *v1, const S390Vector *v2, \
+ const S390Vector *v3, vpk##BITS##_fn fn) \
+{ \
+ int i, saturated = 0; \
+ S390Vector tmp; \
+ \
+ for (i = 0; i < (128 / TBITS); i++) { \
+ uint##BITS##_t src; \
+ \
+ if (i < (128 / BITS)) { \
+ src = s390_vec_read_element##BITS(v2, i); \
+ } else { \
+ src = s390_vec_read_element##BITS(v3, i - (128 / BITS)); \
+ } \
+ s390_vec_write_element##TBITS(&tmp, i, fn(src, &saturated)); \
+ } \
+ *v1 = tmp; \
+ return saturated; \
+}
+DEF_VPK_HFN(64, 32)
+DEF_VPK_HFN(32, 16)
+DEF_VPK_HFN(16, 8)
+
+#define DEF_VPK(BITS, TBITS) \
+static uint##TBITS##_t vpk##BITS##e(uint##BITS##_t src, int *saturated) \
+{ \
+ return src; \
+} \
+void HELPER(gvec_vpk##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ vpk##BITS##_hfn(v1, v2, v3, vpk##BITS##e); \
+}
+DEF_VPK(64, 32)
+DEF_VPK(32, 16)
+DEF_VPK(16, 8)
+
+#define DEF_VPKS(BITS, TBITS) \
+static uint##TBITS##_t vpks##BITS##e(uint##BITS##_t src, int *saturated) \
+{ \
+ if ((int##BITS##_t)src > INT##TBITS##_MAX) { \
+ (*saturated)++; \
+ return INT##TBITS##_MAX; \
+ } else if ((int##BITS##_t)src < INT##TBITS##_MIN) { \
+ (*saturated)++; \
+ return INT##TBITS##_MIN; \
+ } \
+ return src; \
+} \
+void HELPER(gvec_vpks##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ vpk##BITS##_hfn(v1, v2, v3, vpks##BITS##e); \
+} \
+void HELPER(gvec_vpks_cc##BITS)(void *v1, const void *v2, const void *v3, \
+ CPUS390XState *env, uint32_t desc) \
+{ \
+ int saturated = vpk##BITS##_hfn(v1, v2, v3, vpks##BITS##e); \
+ \
+ if (saturated == (128 / TBITS)) { \
+ env->cc_op = 3; \
+ } else if (saturated) { \
+ env->cc_op = 1; \
+ } else { \
+ env->cc_op = 0; \
+ } \
+}
+DEF_VPKS(64, 32)
+DEF_VPKS(32, 16)
+DEF_VPKS(16, 8)
+
+#define DEF_VPKLS(BITS, TBITS) \
+static uint##TBITS##_t vpkls##BITS##e(uint##BITS##_t src, int *saturated) \
+{ \
+ if (src > UINT##TBITS##_MAX) { \
+ (*saturated)++; \
+ return UINT##TBITS##_MAX; \
+ } \
+ return src; \
+} \
+void HELPER(gvec_vpkls##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ vpk##BITS##_hfn(v1, v2, v3, vpkls##BITS##e); \
+} \
+void HELPER(gvec_vpkls_cc##BITS)(void *v1, const void *v2, const void *v3, \
+ CPUS390XState *env, uint32_t desc) \
+{ \
+ int saturated = vpk##BITS##_hfn(v1, v2, v3, vpkls##BITS##e); \
+ \
+ if (saturated == (128 / TBITS)) { \
+ env->cc_op = 3; \
+ } else if (saturated) { \
+ env->cc_op = 1; \
+ } else { \
+ env->cc_op = 0; \
+ } \
+}
+DEF_VPKLS(64, 32)
+DEF_VPKLS(32, 16)
+DEF_VPKLS(16, 8)
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 20/32] s390x/tcg: Implement VECTOR PERMUTE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (18 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 19/32] s390x/tcg: Implement VECTOR PACK * David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 21/32] s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE David Hildenbrand
` (19 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Take care of overlying inputs and outputs by using a temporary vector.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 1 +
target/s390x/translate_vx.inc.c | 12 ++++++++++++
target/s390x/vec_helper.c | 20 ++++++++++++++++++++
4 files changed, 34 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 315495f49f..577edb384f 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -141,6 +141,7 @@ DEF_HELPER_FLAGS_4(gvec_vpkls64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_5(gvec_vpkls_cc16, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vpkls_cc32, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 39cd6f27c1..5f77462bb1 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1020,6 +1020,7 @@
F(0xe797, VPKS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
/* VECTOR PACK LOGICAL SATURATE */
F(0xe795, VPKLS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
+ F(0xe78c, VPERM, VRR_e, V, 0, 0, 0, 0, vperm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7ae38f71f7..d8cf4360cf 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -141,6 +141,10 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
+#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
+ 16, 16, data, fn)
#define gen_gvec_dup_i64(es, v1, c) \
tcg_gen_gvec_dup_i64(es, vec_full_reg_offset(v1), 16, 16, c)
#define gen_gvec_mov(v1, v2) \
@@ -663,3 +667,11 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static DisasJumpType op_vperm(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4),
+ 0, gen_helper_gvec_vperm);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_helper.c b/target/s390x/vec_helper.c
index 7f680201b5..021695b38c 100644
--- a/target/s390x/vec_helper.c
+++ b/target/s390x/vec_helper.c
@@ -147,3 +147,23 @@ void HELPER(gvec_vpkls_cc##BITS)(void *v1, const void *v2, const void *v3, \
DEF_VPKLS(64, 32)
DEF_VPKLS(32, 16)
DEF_VPKLS(16, 8)
+
+void HELPER(gvec_vperm)(void *v1, const void *v2, const void *v3,
+ const void *v4, uint32_t desc)
+{
+ S390Vector tmp;
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ const uint8_t selector = s390_vec_read_element8(v4, i) & 0x1f;
+ uint8_t byte;
+
+ if (selector < 16) {
+ byte = s390_vec_read_element8(v2, selector);
+ } else {
+ byte = s390_vec_read_element8(v3, selector - 16);
+ }
+ s390_vec_write_element8(&tmp, i, byte);
+ }
+ *(S390Vector *)v1 = tmp;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 21/32] s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (19 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 20/32] s390x/tcg: Implement VECTOR PERMUTE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 22/32] s390x/tcg: Implement VECTOR REPLICATE David Hildenbrand
` (18 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Read the whole input before modifying the destination vector.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 5f77462bb1..7314ae4704 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1021,6 +1021,8 @@
/* VECTOR PACK LOGICAL SATURATE */
F(0xe795, VPKLS, VRR_b, V, 0, 0, 0, 0, vpk, 0, IF_VEC)
F(0xe78c, VPERM, VRR_e, V, 0, 0, 0, 0, vperm, 0, IF_VEC)
+/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */
+ F(0xe784, VPDI, VRR_c, V, 0, 0, 0, 0, vpdi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index d8cf4360cf..b23955b848 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -675,3 +675,19 @@ static DisasJumpType op_vperm(DisasContext *s, DisasOps *o)
0, gen_helper_gvec_vperm);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
+{
+ const uint8_t i2 = extract32(get_field(s->fields, m4), 2, 1);
+ const uint8_t i3 = extract32(get_field(s->fields, m4), 0, 1);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ read_vec_element_i64(t0, get_field(s->fields, v2), i2, ES_64);
+ read_vec_element_i64(t1, get_field(s->fields, v3), i3, ES_64);
+ write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 22/32] s390x/tcg: Implement VECTOR REPLICATE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (20 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 21/32] s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 23/32] s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE David Hildenbrand
` (17 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Replicate via the special gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 7314ae4704..14e010765d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1023,6 +1023,8 @@
F(0xe78c, VPERM, VRR_e, V, 0, 0, 0, 0, vperm, 0, IF_VEC)
/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */
F(0xe784, VPDI, VRR_c, V, 0, 0, 0, 0, vpdi, 0, IF_VEC)
+/* VECTOR REPLICATE */
+ F(0xe74d, VREP, VRI_c, V, 0, 0, 0, 0, vrep, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b23955b848..21bf2dc58f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -691,3 +691,19 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(t1);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vrep(DisasContext *s, DisasOps *o)
+{
+ const uint8_t enr = get_field(s->fields, i2);
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_64 || !valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s->fields, v1)),
+ vec_reg_offset(get_field(s->fields, v3), enr, es),
+ 16, 16);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 23/32] s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (21 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 22/32] s390x/tcg: Implement VECTOR REPLICATE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 24/32] s390x/tcg: Implement VECTOR SCATTER ELEMENT David Hildenbrand
` (16 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Like VECTOR REPLICATE, but the element to be replicated comes from an
immediate.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 14e010765d..99fb697d91 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1025,6 +1025,8 @@
F(0xe784, VPDI, VRR_c, V, 0, 0, 0, 0, vpdi, 0, IF_VEC)
/* VECTOR REPLICATE */
F(0xe74d, VREP, VRI_c, V, 0, 0, 0, 0, vrep, 0, IF_VEC)
+/* VECTOR REPLICATE IMMEDIATE */
+ F(0xe745, VREPI, VRI_a, V, 0, 0, 0, 0, vrepi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 21bf2dc58f..b6061d7acf 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -707,3 +707,17 @@ static DisasJumpType op_vrep(DisasContext *s, DisasOps *o)
16, 16);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
+{
+ const int64_t data = (int16_t)get_field(s->fields, i2);
+ const uint8_t es = get_field(s->fields, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_dupi(es, get_field(s->fields, v1), data);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 24/32] s390x/tcg: Implement VECTOR SCATTER ELEMENT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (22 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 23/32] s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 25/32] s390x/tcg: Implement VECTOR SELECT David Hildenbrand
` (15 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Similar to VECTOR GATHER ELEMENT, but the other direction.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 3 +++
target/s390x/translate_vx.inc.c | 22 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 99fb697d91..8d7c834e7d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1027,6 +1027,9 @@
F(0xe74d, VREP, VRI_c, V, 0, 0, 0, 0, vrep, 0, IF_VEC)
/* VECTOR REPLICATE IMMEDIATE */
F(0xe745, VREPI, VRI_a, V, 0, 0, 0, 0, vrepi, 0, IF_VEC)
+/* VECTOR SCATTER ELEMENT */
+ E(0xe71b, VSCEF, VRV, V, la2, 0, 0, 0, vsce, 0, ES_32, IF_VEC)
+ E(0xe71a, VSCEG, VRV, V, la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b6061d7acf..cd8c173b36 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -721,3 +721,25 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
gen_gvec_dupi(es, get_field(s->fields, v1), data);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s->fields, v2), enr, es);
+ tcg_gen_add_i64(o->addr1, o->addr1, tmp);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
+
+ read_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 25/32] s390x/tcg: Implement VECTOR SELECT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (23 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 24/32] s390x/tcg: Implement VECTOR SCATTER ELEMENT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 26/32] s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD David Hildenbrand
` (14 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Provide an implementation based on i64 and on real host vectors.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 41 +++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 8d7c834e7d..ae58ff440b 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1030,6 +1030,8 @@
/* VECTOR SCATTER ELEMENT */
E(0xe71b, VSCEF, VRV, V, la2, 0, 0, 0, vsce, 0, ES_32, IF_VEC)
E(0xe71a, VSCEG, VRV, V, la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC)
+/* VECTOR SELECT */
+ F(0xe78d, VSEL, VRR_e, V, 0, 0, 0, 0, vsel, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index cd8c173b36..e685506b8c 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -141,6 +141,10 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
+#define gen_gvec_4(v1, v2, v3, v4, gen) \
+ tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
+ 16, 16, gen)
#define gen_gvec_4_ool(v1, v2, v3, v4, data, fn) \
tcg_gen_gvec_4_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
@@ -743,3 +747,40 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static void gen_sel_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ /* bit in c not set -> copy bit from b */
+ tcg_gen_andc_i64(t, b, c);
+ /* bit in c set -> copy bit from a */
+ tcg_gen_and_i64(d, a, c);
+ /* merge the results */
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_sel_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b,
+ TCGv_vec c)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_andc_vec(vece, t, b, c);
+ tcg_gen_and_vec(vece, d, a, c);
+ tcg_gen_or_vec(vece, d, d, t);
+ tcg_temp_free_vec(t);
+}
+
+static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
+{
+ static const GVecGen4 gvec_op = {
+ .fni8 = gen_sel_i64,
+ .fniv = gen_sel_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+
+ gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), &gvec_op);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 26/32] s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (24 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 25/32] s390x/tcg: Implement VECTOR SELECT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper David Hildenbrand
` (13 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Load both elements signed and store them into the two 64 bit elements.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ae58ff440b..555250fd5a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1032,6 +1032,8 @@
E(0xe71a, VSCEG, VRV, V, la2, 0, 0, 0, vsce, 0, ES_64, IF_VEC)
/* VECTOR SELECT */
F(0xe78d, VSEL, VRR_e, V, 0, 0, 0, 0, vsel, 0, IF_VEC)
+/* VECTOR SIGN EXTEND TO DOUBLEWORD */
+ F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index e685506b8c..cf1d319e4e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -784,3 +784,36 @@ static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), get_field(s->fields, v4), &gvec_op);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ int idx1, idx2;
+ TCGv_i64 tmp;
+
+ switch (es) {
+ case ES_8:
+ idx1 = 7;
+ idx2 = 15;
+ break;
+ case ES_16:
+ idx1 = 3;
+ idx2 = 7;
+ break;
+ case ES_32:
+ idx1 = 1;
+ idx2 = 3;
+ break;
+ default:
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s->fields, v2), idx1, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s->fields, v1), 0, ES_64);
+ read_vec_element_i64(tmp, get_field(s->fields, v2), idx2, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s->fields, v1), 1, ES_64);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (25 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 26/32] s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 14:10 ` Richard Henderson
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 28/32] s390x/tcg: Implement VECTOR STORE David Hildenbrand
` (12 subsequent siblings)
39 siblings, 1 reply; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Instead of checking e.g. the first access on every touched page, we should
check the actual access, otherwise we might get false positives when Low
Address Protection (LAP) is active. As probe_write() can only deal with
accesses to one page, we have to loop.
Use i64 for the length, although not needed - easier to reuse
TCG temps we already have in the translation functions where this will
be used. Also allow it to be used from other helpers.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/internal.h | 2 ++
target/s390x/mem_helper.c | 25 +++++++++++++++++++++++++
3 files changed, 28 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 577edb384f..e2710f4fb3 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -123,6 +123,7 @@ DEF_HELPER_4(cu42, i32, env, i32, i32, i32)
DEF_HELPER_5(msa, i32, env, i32, i32, i32, i32)
DEF_HELPER_FLAGS_1(stpt, TCG_CALL_NO_RWG, i64, env)
DEF_HELPER_FLAGS_1(stck, TCG_CALL_NO_RWG_SE, i64, env)
+DEF_HELPER_FLAGS_3(probe_write_access, TCG_CALL_NO_WG, void, env, i64, i64)
/* === Vector Support Instructions === */
DEF_HELPER_FLAGS_4(vll, TCG_CALL_NO_WG, void, env, ptr, i64, i64)
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 07b69b8ea0..3b4855c175 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -349,6 +349,8 @@ void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
/* mem_helper.c */
target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
+void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
+ uintptr_t ra);
/* mmu_helper.c */
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index a506d9ef99..b0fd5a2668 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -2623,3 +2623,28 @@ uint32_t HELPER(cu42)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t m3)
return convert_unicode(env, r1, r2, m3, GETPC(),
decode_utf32, encode_utf16);
}
+
+void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
+ uintptr_t ra)
+{
+#ifdef CONFIG_USER_ONLY
+ if (!h2g_valid(addr) || !h2g_valid(addr + len - 1)) {
+ s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
+ }
+#else
+ /* test the actual access, not just any access to the page due to LAP */
+ while (len) {
+ const uint64_t pagelen = -(addr | -TARGET_PAGE_MASK);
+ const uint64_t curlen = MIN(pagelen, len);
+
+ probe_write(env, addr, curlen, cpu_mmu_index(env, false), ra);
+ addr = wrap_address(env, addr + curlen);
+ len -= curlen;
+ }
+#endif
+}
+
+void HELPER(probe_write_access)(CPUS390XState *env, uint64_t addr, uint64_t len)
+{
+ probe_write_access(env, addr, len, GETPC());
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 28/32] s390x/tcg: Implement VECTOR STORE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (26 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 29/32] s390x/tcg: Implement VECTOR STORE ELEMENT David Hildenbrand
` (11 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Properly probe the whole access first.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 555250fd5a..4525d5b145 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1034,6 +1034,8 @@
F(0xe78d, VSEL, VRR_e, V, 0, 0, 0, 0, vsel, 0, IF_VEC)
/* VECTOR SIGN EXTEND TO DOUBLEWORD */
F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC)
+/* VECTOR STORE */
+ F(0xe70e, VST, VRX, V, la2, 0, 0, 0, vst, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index cf1d319e4e..fcddd0cde7 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -113,6 +113,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+
static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
uint8_t es)
{
@@ -817,3 +818,19 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 tmp = tcg_const_i64(16);
+
+ /* Probe write access before actually modifying memory */
+ gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+
+ read_vec_element_i64(tmp, get_field(s->fields, v1), 0, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ read_vec_element_i64(tmp, get_field(s->fields, v1), 1, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 29/32] s390x/tcg: Implement VECTOR STORE ELEMENT
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (27 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 28/32] s390x/tcg: Implement VECTOR STORE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 30/32] s390x/tcg: Implement VECTOR STORE MULTIPLE David Hildenbrand
` (10 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
As we only store one element, there is nothing to consider regarding
exceptions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 5 +++++
target/s390x/translate_vx.inc.c | 18 ++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 4525d5b145..ff5b9e7302 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1036,6 +1036,11 @@
F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC)
/* VECTOR STORE */
F(0xe70e, VST, VRX, V, la2, 0, 0, 0, vst, 0, IF_VEC)
+/* VECTOR STORE ELEMENT */
+ E(0xe708, VSTEB, VRX, V, la2, 0, 0, 0, vste, 0, ES_8, IF_VEC)
+ E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)
+ E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)
+ E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index fcddd0cde7..ecc295da5b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -834,3 +834,21 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = s->insn->data;
+ const uint8_t enr = get_field(s->fields, m3);
+ TCGv_i64 tmp;
+
+ if (!valid_vec_element(enr, es)) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ read_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 30/32] s390x/tcg: Implement VECTOR STORE MULTIPLE
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (28 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 29/32] s390x/tcg: Implement VECTOR STORE ELEMENT David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 31/32] s390x/tcg: Implement VECTOR STORE WITH LENGTH David Hildenbrand
` (9 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe
write access first.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index ff5b9e7302..17fd9a898b 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1041,6 +1041,8 @@
E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC)
E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC)
E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)
+/* VECTOR STORE MULTIPLE */
+ F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index ecc295da5b..0c75374203 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -852,3 +852,33 @@ static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v3 = get_field(s->fields, v3);
+ uint8_t v1 = get_field(s->fields, v1);
+ TCGv_i64 tmp;
+
+ while (v3 < v1 || (v3 - v1 + 1) > 16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ /* Probe write access before actually modifying memory */
+ tmp = tcg_const_i64((v3 - v1 + 1) * 16);
+ gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
+
+ for (;; v1++) {
+ read_vec_element_i64(tmp, v1, 0, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ read_vec_element_i64(tmp, v1, 1, ES_64);
+ tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
+ if (v1 == v3) {
+ break;
+ }
+ gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 31/32] s390x/tcg: Implement VECTOR STORE WITH LENGTH
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (29 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 30/32] s390x/tcg: Implement VECTOR STORE MULTIPLE David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 32/32] s390x/tcg: Implement VECTOR UNPACK * David Hildenbrand
` (8 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction.
Properly probe write access before modifying memory.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 13 +++++++++++++
target/s390x/vec_helper.c | 24 ++++++++++++++++++++++++
4 files changed, 40 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index e2710f4fb3..0b494a2fd2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -143,6 +143,7 @@ DEF_HELPER_5(gvec_vpkls_cc16, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vpkls_cc32, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 17fd9a898b..00ba9444a3 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1043,6 +1043,8 @@
E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC)
/* VECTOR STORE MULTIPLE */
F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC)
+/* VECTOR STORE WITH LENGTH */
+ F(0xe73f, VSTL, VRS_b, V, la2, r3_32u, 0, 0, vstl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0c75374203..fcdda0c591 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -882,3 +882,16 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
+{
+ const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+
+ /* convert highest index into an actual length */
+ tcg_gen_addi_i64(o->in2, o->in2, 1);
+ tcg_gen_addi_ptr(a0, cpu_env, v1_offs);
+ gen_helper_vstl(cpu_env, a0, o->addr1, o->in2);
+ tcg_temp_free_ptr(a0);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_helper.c b/target/s390x/vec_helper.c
index 021695b38c..bb4c9304f0 100644
--- a/target/s390x/vec_helper.c
+++ b/target/s390x/vec_helper.c
@@ -167,3 +167,27 @@ void HELPER(gvec_vperm)(void *v1, const void *v2, const void *v3,
}
*(S390Vector *)v1 = tmp;
}
+
+void HELPER(vstl)(CPUS390XState *env, const void *v1, uint64_t addr,
+ uint64_t bytes)
+{
+ /* Probe write access before actually modifying memory */
+ probe_write_access(env, addr, bytes, GETPC());
+
+ if (likely(bytes >= 16)) {
+ cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC());
+ addr = wrap_address(env, addr + 8);
+ cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC());
+ } else {
+ S390Vector tmp = {};
+ int i;
+
+ for (i = 0; i < bytes; i++) {
+ uint8_t byte = s390_vec_read_element8(v1, i);
+
+ cpu_stb_data_ra(env, addr, byte, GETPC());
+ addr = wrap_address(env, addr + 1);
+ }
+ *(S390Vector *)v1 = tmp;
+ }
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Qemu-devel] [PATCH v3 32/32] s390x/tcg: Implement VECTOR UNPACK *
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (30 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 31/32] s390x/tcg: Implement VECTOR STORE WITH LENGTH David Hildenbrand
@ 2019-03-07 12:15 ` David Hildenbrand
2019-03-07 12:49 ` [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 no-reply
` (7 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 12:15 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Combine all variant in a single handler. As source and destination
have different element sizes, we can't use gvec expansion. Expand
manually. Also watch out for overlapping source and destination
registers. Use a safe evaluation order depending on the operation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 8 +++++++
target/s390x/translate_vx.inc.c | 38 +++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 00ba9444a3..71fa9b8d6c 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1045,6 +1045,14 @@
F(0xe73e, VSTM, VRS_a, V, la2, 0, 0, 0, vstm, 0, IF_VEC)
/* VECTOR STORE WITH LENGTH */
F(0xe73f, VSTL, VRS_b, V, la2, r3_32u, 0, 0, vstl, 0, IF_VEC)
+/* VECTOR UNPACK HIGH */
+ F(0xe7d7, VUPH, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
+/* VECTOR UNPACK LOGICAL HIGH */
+ F(0xe7d5, VUPLH, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
+/* VECTOR UNPACK LOW */
+ F(0xe7d6, VUPL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
+/* VECTOR UNPACK LOGICAL LOW */
+ F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index fcdda0c591..76f9a5d939 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -895,3 +895,41 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
tcg_temp_free_ptr(a0);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
+{
+ const bool logical = s->fields->op2 == 0xd4 || s->fields->op2 == 0xd5;
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t src_es = get_field(s->fields, m3);
+ const uint8_t dst_es = src_es + 1;
+ int dst_idx, src_idx;
+ TCGv_i64 tmp;
+
+ if (src_es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tmp = tcg_temp_new_i64();
+ if (s->fields->op2 == 0xd7 || s->fields->op2 == 0xd5) {
+ /* iterate backwards to avoid overwriting data we might need later */
+ for (dst_idx = NUM_VEC_ELEMENTS(dst_es) - 1; dst_idx >= 0; dst_idx--) {
+ src_idx = dst_idx;
+ read_vec_element_i64(tmp, v2, src_idx,
+ src_es | (logical ? 0 : MO_SIGN));
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+
+ } else {
+ /* iterate forward to avoid overwriting data we might need later */
+ for (dst_idx = 0; dst_idx < NUM_VEC_ELEMENTS(dst_es); dst_idx++) {
+ src_idx = dst_idx + NUM_VEC_ELEMENTS(src_es) / 2;
+ read_vec_element_i64(tmp, v2, src_idx,
+ src_es | (logical ? 0 : MO_SIGN));
+ write_vec_element_i64(tmp, v1, dst_idx, dst_es);
+ }
+ }
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.17.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (31 preceding siblings ...)
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 32/32] s390x/tcg: Implement VECTOR UNPACK * David Hildenbrand
@ 2019-03-07 12:49 ` no-reply
2019-03-07 12:55 ` no-reply
` (6 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 12:49 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
dd15f0c0e0 s390x/tcg: Implement VECTOR UNPACK *
5469da27ba s390x/tcg: Implement VECTOR STORE WITH LENGTH
31f8d4ec4c s390x/tcg: Implement VECTOR STORE MULTIPLE
6de9465914 s390x/tcg: Implement VECTOR STORE ELEMENT
19cc52c3d2 s390x/tcg: Implement VECTOR STORE
2c4714a42d s390x/tcg: Provide probe_write_access helper
90fb919c9e s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
2992d1f3f1 s390x/tcg: Implement VECTOR SELECT
f82d8a987a s390x/tcg: Implement VECTOR SCATTER ELEMENT
db0d7a56b0 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
4c15d35ddd s390x/tcg: Implement VECTOR REPLICATE
9712ce8638 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
8d66a75a6b s390x/tcg: Implement VECTOR PERMUTE
8a0c283202 s390x/tcg: Implement VECTOR PACK *
a3d128e6fe s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
8a01124342 s390x/tcg: Implement VECTOR LOAD WITH LENGTH
29b6dfd4be s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
67a0b63e9c s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
0bf3c03799 s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
7926496f72 s390x/tcg: Implement VECTOR LOAD MULTIPLE
af823e986e s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
f054650162 s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
e68dbb9e5f s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
808ab4e4df s390x/tcg: Implement VECTOR LOAD ELEMENT
8e9b8ed6f0 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
ab0ad884ad s390x/tcg: Implement VECTOR LOAD
45def93691 s390x/tcg: Implement VECTOR GENERATE MASK
d0a1e4a8b5 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
2e8c1ed0c3 s390x/tcg: Implement VECTOR GATHER ELEMENT
be06a3dc42 s390x/tcg: Utilities for vector instruction helpers
40f44c517d s390x/tcg: Check vector register instructions at central point
065fe07ea4 s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit 065fe07ea481 (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 40f44c517dc2 (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit be06a3dc4268 (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 2e8c1ed0c337 (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit d0a1e4a8b579 (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 45def93691ce (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit ab0ad884ad95 (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit 8e9b8ed6f03c (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit 808ab4e4dfda (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit e68dbb9e5fc7 (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit f05465016299 (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit af823e986e19 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit 7926496f721a (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 0bf3c0379974 (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit 67a0b63e9c60 (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit 29b6dfd4be93 (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit 8a0112434299 (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit a3d128e6fea5 (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit 8a0c28320214 (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 8d66a75a6b4b (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit 9712ce8638ec (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 4c15d35dddce (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit db0d7a56b0ac (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit f82d8a987aa8 (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit 2992d1f3f1db (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 90fb919c9e5a (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit 2c4714a42d04 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 19cc52c3d24d (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit 6de946591469 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit 31f8d4ec4cee (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit 5469da27ba7f (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit dd15f0c0e0f1 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (32 preceding siblings ...)
2019-03-07 12:49 ` [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 no-reply
@ 2019-03-07 12:55 ` no-reply
2019-03-07 12:59 ` no-reply
` (5 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 12:55 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
580513b499 s390x/tcg: Implement VECTOR UNPACK *
60d054d17e s390x/tcg: Implement VECTOR STORE WITH LENGTH
8768efe234 s390x/tcg: Implement VECTOR STORE MULTIPLE
2c1a3aa9ba s390x/tcg: Implement VECTOR STORE ELEMENT
2a1c3a459d s390x/tcg: Implement VECTOR STORE
6125818044 s390x/tcg: Provide probe_write_access helper
12242884af s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
04466fb6cc s390x/tcg: Implement VECTOR SELECT
5b9fee2855 s390x/tcg: Implement VECTOR SCATTER ELEMENT
d67d89a961 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
367aa4a804 s390x/tcg: Implement VECTOR REPLICATE
79ad209659 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
8bf1ae3faa s390x/tcg: Implement VECTOR PERMUTE
211a230122 s390x/tcg: Implement VECTOR PACK *
20cee317af s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
224771a1cd s390x/tcg: Implement VECTOR LOAD WITH LENGTH
4749ebb288 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
0fff847013 s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
37a909d151 s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
79c915533c s390x/tcg: Implement VECTOR LOAD MULTIPLE
24c1d17dab s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
85b51d12c6 s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
9f02cf09a3 s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
75536edab1 s390x/tcg: Implement VECTOR LOAD ELEMENT
48429cf743 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
2369662b74 s390x/tcg: Implement VECTOR LOAD
790356aa6e s390x/tcg: Implement VECTOR GENERATE MASK
d267631a44 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
99152d0942 s390x/tcg: Implement VECTOR GATHER ELEMENT
cf78908216 s390x/tcg: Utilities for vector instruction helpers
ca8433ca52 s390x/tcg: Check vector register instructions at central point
1f23f9b130 s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit 1f23f9b1306f (s390x/tcg: Define vector instruction formats)
2/32 Checking commit ca8433ca52cc (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit cf78908216c1 (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 99152d0942c9 (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit d267631a44ab (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 790356aa6e3e (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit 2369662b7437 (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit 48429cf743f7 (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit 75536edab11e (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit 9f02cf09a392 (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit 85b51d12c6c9 (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit 24c1d17dabf5 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit 79c915533c2e (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 37a909d15183 (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit 0fff8470136e (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit 4749ebb28844 (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit 224771a1cd71 (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit 20cee317afb1 (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit 211a23012232 (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 8bf1ae3faa3b (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit 79ad20965945 (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 367aa4a8045b (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit d67d89a961c8 (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit 5b9fee28556d (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit 04466fb6cc86 (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 12242884af29 (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit 612581804455 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 2a1c3a459da3 (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit 2c1a3aa9ba36 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit 8768efe23460 (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit 60d054d17ebe (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit 580513b499b7 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (33 preceding siblings ...)
2019-03-07 12:55 ` no-reply
@ 2019-03-07 12:59 ` no-reply
2019-03-07 13:04 ` no-reply
` (4 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 12:59 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
8d0aa17606 s390x/tcg: Implement VECTOR UNPACK *
37636b591f s390x/tcg: Implement VECTOR STORE WITH LENGTH
6e1dfde0bd s390x/tcg: Implement VECTOR STORE MULTIPLE
859d21b77d s390x/tcg: Implement VECTOR STORE ELEMENT
4de96c3f56 s390x/tcg: Implement VECTOR STORE
87bf3f8544 s390x/tcg: Provide probe_write_access helper
4bc6b49371 s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
c32754d25c s390x/tcg: Implement VECTOR SELECT
2056f3d754 s390x/tcg: Implement VECTOR SCATTER ELEMENT
cb5e0ccad6 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
76ce69b4fb s390x/tcg: Implement VECTOR REPLICATE
76cfadc9a1 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
507dbe068d s390x/tcg: Implement VECTOR PERMUTE
17c46f0fa0 s390x/tcg: Implement VECTOR PACK *
b36fc71793 s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
f4bdf81489 s390x/tcg: Implement VECTOR LOAD WITH LENGTH
42fd374329 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
47cfb40ff7 s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
85b178934a s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
963cbd7c53 s390x/tcg: Implement VECTOR LOAD MULTIPLE
ca71a83f40 s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
edb2f7e2a0 s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
1372baf785 s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
f6e6ee9d3e s390x/tcg: Implement VECTOR LOAD ELEMENT
5b2c3f2ebd s390x/tcg: Implement VECTOR LOAD AND REPLICATE
c4cdedec4f s390x/tcg: Implement VECTOR LOAD
96a031b008 s390x/tcg: Implement VECTOR GENERATE MASK
38d6de5718 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
d2ef6fbd45 s390x/tcg: Implement VECTOR GATHER ELEMENT
0e60ea6953 s390x/tcg: Utilities for vector instruction helpers
16bf5f9541 s390x/tcg: Check vector register instructions at central point
7d0bdaedb7 s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit 7d0bdaedb7e4 (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 16bf5f9541e6 (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit 0e60ea695385 (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit d2ef6fbd45dd (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit 38d6de5718bc (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 96a031b0085f (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit c4cdedec4f7e (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit 5b2c3f2ebd02 (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit f6e6ee9d3e55 (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit 1372baf7858e (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit edb2f7e2a09f (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit ca71a83f4056 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit 963cbd7c5326 (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 85b178934a8d (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit 47cfb40ff7a8 (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit 42fd37432941 (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit f4bdf81489dd (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit b36fc717934b (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit 17c46f0fa09c (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 507dbe068dfb (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit 76cfadc9a15a (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 76ce69b4fb36 (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit cb5e0ccad69d (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit 2056f3d7543c (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit c32754d25ccc (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 4bc6b49371dd (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit 87bf3f85446e (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 4de96c3f5688 (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit 859d21b77de2 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit 6e1dfde0bd6a (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit 37636b591f70 (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit 8d0aa1760631 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (34 preceding siblings ...)
2019-03-07 12:59 ` no-reply
@ 2019-03-07 13:04 ` no-reply
2019-03-07 13:17 ` no-reply
` (3 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 13:04 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
5a2b60cdfb s390x/tcg: Implement VECTOR UNPACK *
e44f61a293 s390x/tcg: Implement VECTOR STORE WITH LENGTH
aaff19a223 s390x/tcg: Implement VECTOR STORE MULTIPLE
5bc9a4d3fc s390x/tcg: Implement VECTOR STORE ELEMENT
4a1d19133b s390x/tcg: Implement VECTOR STORE
a2b52e36cf s390x/tcg: Provide probe_write_access helper
2e2b0b7fa9 s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
597f117f0a s390x/tcg: Implement VECTOR SELECT
d9447b1e56 s390x/tcg: Implement VECTOR SCATTER ELEMENT
7b7cba6fe9 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
205ece0c65 s390x/tcg: Implement VECTOR REPLICATE
a315de6305 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
73b80eeca1 s390x/tcg: Implement VECTOR PERMUTE
1f2e90d518 s390x/tcg: Implement VECTOR PACK *
2d35935e85 s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
49cc55b02b s390x/tcg: Implement VECTOR LOAD WITH LENGTH
c9e430c6e1 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
2ff9e61202 s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
e6852c11e3 s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
c56f6d6229 s390x/tcg: Implement VECTOR LOAD MULTIPLE
3f392b0093 s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
9a2014681a s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
1fd9f4467f s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
770dcdb9a3 s390x/tcg: Implement VECTOR LOAD ELEMENT
b15a110f20 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
c63a56fc9a s390x/tcg: Implement VECTOR LOAD
a0c84dfb55 s390x/tcg: Implement VECTOR GENERATE MASK
e49400c153 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
fc5057a465 s390x/tcg: Implement VECTOR GATHER ELEMENT
7f20b31570 s390x/tcg: Utilities for vector instruction helpers
62756eecc5 s390x/tcg: Check vector register instructions at central point
ebe24ba51f s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit ebe24ba51fcc (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 62756eecc56f (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit 7f20b31570ba (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit fc5057a465cc (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit e49400c15376 (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit a0c84dfb55f2 (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit c63a56fc9a23 (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit b15a110f2029 (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit 770dcdb9a393 (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit 1fd9f4467f0d (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit 9a2014681a81 (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit 3f392b009361 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit c56f6d6229fa (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit e6852c11e3f9 (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit 2ff9e6120212 (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit c9e430c6e10b (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit 49cc55b02b81 (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit 2d35935e851b (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit 1f2e90d5182d (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 73b80eeca182 (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit a315de6305c7 (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 205ece0c65dd (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit 7b7cba6fe94c (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit d9447b1e5632 (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit 597f117f0a85 (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 2e2b0b7fa918 (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit a2b52e36cf82 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 4a1d19133ba4 (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit 5bc9a4d3fc79 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit aaff19a2236d (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit e44f61a2935d (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit 5a2b60cdfba8 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers David Hildenbrand
@ 2019-03-07 13:11 ` Thomas Huth
2019-03-07 14:00 ` Richard Henderson
1 sibling, 0 replies; 47+ messages in thread
From: Thomas Huth @ 2019-03-07 13:11 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Richard Henderson
On 07/03/2019 13.15, David Hildenbrand wrote:
> We'll have to read/write vector elements quite frequently from helpers.
> The tricky bit is properly taking care of endianess. Handle it similar
> to aarch64.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/vec.h | 101 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 target/s390x/vec.h
>
> diff --git a/target/s390x/vec.h b/target/s390x/vec.h
> new file mode 100644
> index 0000000000..3313fb43ee
> --- /dev/null
> +++ b/target/s390x/vec.h
> @@ -0,0 +1,101 @@
> +/*
> + * QEMU TCG support -- s390x vector utilitites
> + *
> + * Copyright (C) 2019 Red Hat Inc
> + *
> + * Authors:
> + * David Hildenbrand <david@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +#ifndef S390X_VEC_H
> +#define S390X_VEC_H
> +
> +typedef union S390Vector {
> + uint64_t doubleword[2];
> + uint32_t word[4];
> + uint16_t halfword[8];
> + uint8_t byte[16];
> +} S390Vector;
> +
> +/*
> + * Each vector is stored as two 64bit host values. So when talking about
> + * byte/halfword/word numbers, we have to take care of proper translation
> + * between element numbers.
> + *
> + * Big Endian (target/possible host)
> + * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
> + * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
> + * W: [ 0][ 1] - [ 2][ 3]
> + * DW: [ 0] - [ 1]
> + *
> + * Little Endian (possible host)
> + * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
> + * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
> + * W: [ 1][ 0] - [ 3][ 2]
> + * DW: [ 0] - [ 1]
> + */
> +#ifndef HOST_WORDS_BIGENDIAN
> +#define H1(x) ((x) ^ 7)
> +#define H2(x) ((x) ^ 3)
> +#define H4(x) ((x) ^ 1)
> +#else
> +#define H1(x) (x)
> +#define H2(x) (x)
> +#define H4(x) (x)
> +#endif
> +
> +static inline uint8_t s390_vec_read_element8(const S390Vector *v, uint8_t enr)
> +{
> + g_assert(enr < 16);
> + return v->byte[H1(enr)];
> +}
> +
> +static inline uint16_t s390_vec_read_element16(const S390Vector *v, uint8_t enr)
> +{
> + g_assert(enr < 8);
> + return v->halfword[H2(enr)];
> +}
> +
> +static inline uint32_t s390_vec_read_element32(const S390Vector *v, uint8_t enr)
> +{
> + g_assert(enr < 4);
> + return v->word[H4(enr)];
> +}
> +
> +static inline uint64_t s390_vec_read_element64(const S390Vector *v, uint8_t enr)
> +{
> + g_assert(enr < 2);
> + return v->doubleword[enr];
> +}
> +
> +static inline void s390_vec_write_element8(S390Vector *v, uint8_t enr,
> + uint8_t data)
> +{
> + g_assert(enr < 16);
> + v->byte[H1(enr)] = data;
> +}
> +
> +static inline void s390_vec_write_element16(S390Vector *v, uint8_t enr,
> + uint16_t data)
> +{
> + g_assert(enr < 8);
> + v->halfword[H2(enr)] = data;
> +}
> +
> +static inline void s390_vec_write_element32(S390Vector *v, uint8_t enr,
> + uint32_t data)
> +{
> + g_assert(enr < 4);
> + v->word[H4(enr)] = data;
> +}
> +
> +static inline void s390_vec_write_element64(S390Vector *v, uint8_t enr,
> + uint64_t data)
> +{
> + g_assert(enr < 2);
> + v->doubleword[enr] = data;
> +}
> +
> +#endif /* S390X_VEC_H */
>
Pretty brain-twisting, but it looks right to me.
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (35 preceding siblings ...)
2019-03-07 13:04 ` no-reply
@ 2019-03-07 13:17 ` no-reply
2019-03-07 14:05 ` no-reply
` (2 subsequent siblings)
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 13:17 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
f6954a7939 s390x/tcg: Implement VECTOR UNPACK *
79bdca318a s390x/tcg: Implement VECTOR STORE WITH LENGTH
b9021c771e s390x/tcg: Implement VECTOR STORE MULTIPLE
83e2794e3d s390x/tcg: Implement VECTOR STORE ELEMENT
829e3fb3e7 s390x/tcg: Implement VECTOR STORE
bd7415ba28 s390x/tcg: Provide probe_write_access helper
1e6e15312b s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
9364f826a7 s390x/tcg: Implement VECTOR SELECT
11059139e9 s390x/tcg: Implement VECTOR SCATTER ELEMENT
9f252fbd49 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
1c6291228f s390x/tcg: Implement VECTOR REPLICATE
9da07a7588 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
7d3e23524d s390x/tcg: Implement VECTOR PERMUTE
e164481b3a s390x/tcg: Implement VECTOR PACK *
5bcdba5d59 s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
8131f03bcb s390x/tcg: Implement VECTOR LOAD WITH LENGTH
6b3e1a5833 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
9b9456df6c s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
3e3137fc5a s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
e13b78fa3a s390x/tcg: Implement VECTOR LOAD MULTIPLE
5dd092c443 s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
73a7d5936f s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
4c3cac7dea s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
2ee78ce167 s390x/tcg: Implement VECTOR LOAD ELEMENT
654c614c56 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
d606d0b7f2 s390x/tcg: Implement VECTOR LOAD
15ae8fa740 s390x/tcg: Implement VECTOR GENERATE MASK
80cb753278 s390x/tcg: Implement VECTOR GENERATE BYTE MASK
3822dd2633 s390x/tcg: Implement VECTOR GATHER ELEMENT
3c360b8b2a s390x/tcg: Utilities for vector instruction helpers
21c62197c5 s390x/tcg: Check vector register instructions at central point
1eea0f8b7a s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit 1eea0f8b7a4c (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 21c62197c5d5 (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit 3c360b8b2ae6 (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 3822dd263336 (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit 80cb7532789c (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 15ae8fa740db (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit d606d0b7f275 (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit 654c614c569e (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit 2ee78ce167c7 (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit 4c3cac7dea14 (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit 73a7d5936fcb (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit 5dd092c44399 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit e13b78fa3a2f (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 3e3137fc5ada (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit 9b9456df6c4f (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit 6b3e1a5833f8 (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit 8131f03bcb21 (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit 5bcdba5d593d (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit e164481b3a2a (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 7d3e23524d30 (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit 9da07a75887b (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 1c6291228f55 (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit 9f252fbd49d5 (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit 11059139e9c2 (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit 9364f826a70a (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 1e6e15312b1f (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit bd7415ba2871 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 829e3fb3e7bf (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit 83e2794e3d7f (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit b9021c771e51 (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit 79bdca318a28 (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit f6954a793960 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers David Hildenbrand
2019-03-07 13:11 ` Thomas Huth
@ 2019-03-07 14:00 ` Richard Henderson
1 sibling, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2019-03-07 14:00 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 3/7/19 4:15 AM, David Hildenbrand wrote:
> We'll have to read/write vector elements quite frequently from helpers.
> The tricky bit is properly taking care of endianess. Handle it similar
> to aarch64.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/vec.h | 101 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
> create mode 100644 target/s390x/vec.h
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (36 preceding siblings ...)
2019-03-07 13:17 ` no-reply
@ 2019-03-07 14:05 ` no-reply
2019-03-07 15:49 ` no-reply
2019-03-07 16:35 ` Cornelia Huck
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 14:05 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
26fb2d7a48 s390x/tcg: Implement VECTOR UNPACK *
df2340ec06 s390x/tcg: Implement VECTOR STORE WITH LENGTH
809ea72f2a s390x/tcg: Implement VECTOR STORE MULTIPLE
bc20fcf1e4 s390x/tcg: Implement VECTOR STORE ELEMENT
79dc189d2c s390x/tcg: Implement VECTOR STORE
82ae500ad9 s390x/tcg: Provide probe_write_access helper
70ad09ba01 s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
387ce0c789 s390x/tcg: Implement VECTOR SELECT
428c54de2d s390x/tcg: Implement VECTOR SCATTER ELEMENT
14165826a8 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
62b8dd3043 s390x/tcg: Implement VECTOR REPLICATE
a0bbd82903 s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
fc9d89b81a s390x/tcg: Implement VECTOR PERMUTE
e118ce0140 s390x/tcg: Implement VECTOR PACK *
9eae02d1e8 s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
f43ab11966 s390x/tcg: Implement VECTOR LOAD WITH LENGTH
90b085e683 s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
c0d9c4a22b s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
cf328654bc s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
e87662b255 s390x/tcg: Implement VECTOR LOAD MULTIPLE
a871ece7dd s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
dd9cc4ad61 s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
b7af5ff813 s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
dd197feff8 s390x/tcg: Implement VECTOR LOAD ELEMENT
e6244fc7f9 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
484d13e05f s390x/tcg: Implement VECTOR LOAD
712ac0b13a s390x/tcg: Implement VECTOR GENERATE MASK
6c8dbd8eae s390x/tcg: Implement VECTOR GENERATE BYTE MASK
013df3f91c s390x/tcg: Implement VECTOR GATHER ELEMENT
d3cdda2073 s390x/tcg: Utilities for vector instruction helpers
57c9e3d42b s390x/tcg: Check vector register instructions at central point
379a1fb237 s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit 379a1fb237fa (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 57c9e3d42b26 (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit d3cdda20732a (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 013df3f91c15 (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit 6c8dbd8eaeeb (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 712ac0b13a69 (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit 484d13e05f3d (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit e6244fc7f980 (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit dd197feff85a (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit b7af5ff813f6 (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit dd9cc4ad61e4 (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit a871ece7ddd2 (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit e87662b2559f (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit cf328654bc45 (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit c0d9c4a22ba1 (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit 90b085e683ed (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit f43ab119664b (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit 9eae02d1e8d0 (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit e118ce014086 (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit fc9d89b81a36 (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit a0bbd8290392 (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 62b8dd304335 (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit 14165826a8bc (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit 428c54de2dc0 (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit 387ce0c789f8 (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 70ad09ba01c3 (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit 82ae500ad9b1 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 79dc189d2c1d (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit bc20fcf1e442 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit 809ea72f2ab2 (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit df2340ec061e (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit 26fb2d7a4829 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper David Hildenbrand
@ 2019-03-07 14:10 ` Richard Henderson
2019-03-07 14:34 ` David Hildenbrand
0 siblings, 1 reply; 47+ messages in thread
From: Richard Henderson @ 2019-03-07 14:10 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 3/7/19 4:15 AM, David Hildenbrand wrote:
> +void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
> + uintptr_t ra)
> +{
> +#ifdef CONFIG_USER_ONLY
> + if (!h2g_valid(addr) || !h2g_valid(addr + len - 1)) {
> + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
> + }
You need
|| page_check_range(addr, len, PAGE_WRITE) < 0
as well.
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper
2019-03-07 14:10 ` Richard Henderson
@ 2019-03-07 14:34 ` David Hildenbrand
2019-03-07 14:40 ` Cornelia Huck
2019-03-07 15:15 ` Richard Henderson
0 siblings, 2 replies; 47+ messages in thread
From: David Hildenbrand @ 2019-03-07 14:34 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 07.03.19 15:10, Richard Henderson wrote:
> On 3/7/19 4:15 AM, David Hildenbrand wrote:
>> +void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
>> + uintptr_t ra)
>> +{
>> +#ifdef CONFIG_USER_ONLY
>> + if (!h2g_valid(addr) || !h2g_valid(addr + len - 1)) {
>> + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
>> + }
>
> You need
>
> || page_check_range(addr, len, PAGE_WRITE) < 0
>
> as well.
Indeed, thanks.
So it should be
+void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
+ uintptr_t ra)
+{
+#ifdef CONFIG_USER_ONLY
+ if (!h2g_valid(addr) || !h2g_valid(addr + len - 1) ||
+ page_check_range(addr, len, PAGE_WRITE) < 0) {
+ s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
+ }
+#else
+ /* test the actual access, not just any access to the page due to LAP */
+ while (len) {
+ const uint64_t pagelen = -(addr | -TARGET_PAGE_MASK);
+ const uint64_t curlen = MIN(pagelen, len);
+
+ probe_write(env, addr, curlen, cpu_mmu_index(env, false), ra);
+ addr = wrap_address(env, addr + curlen);
+ len -= curlen;
+ }
+#endif
+}
Conny, I can resend if you don't feel like fixing up (or there is more to do).
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper
2019-03-07 14:34 ` David Hildenbrand
@ 2019-03-07 14:40 ` Cornelia Huck
2019-03-07 15:15 ` Richard Henderson
1 sibling, 0 replies; 47+ messages in thread
From: Cornelia Huck @ 2019-03-07 14:40 UTC (permalink / raw)
To: David Hildenbrand
Cc: Richard Henderson, qemu-devel, qemu-s390x, Thomas Huth,
Richard Henderson
On Thu, 7 Mar 2019 15:34:27 +0100
David Hildenbrand <david@redhat.com> wrote:
> On 07.03.19 15:10, Richard Henderson wrote:
> > On 3/7/19 4:15 AM, David Hildenbrand wrote:
> >> +void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
> >> + uintptr_t ra)
> >> +{
> >> +#ifdef CONFIG_USER_ONLY
> >> + if (!h2g_valid(addr) || !h2g_valid(addr + len - 1)) {
> >> + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
> >> + }
> >
> > You need
> >
> > || page_check_range(addr, len, PAGE_WRITE) < 0
> >
> > as well.
>
> Indeed, thanks.
>
> So it should be
>
>
> +void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
> + uintptr_t ra)
> +{
> +#ifdef CONFIG_USER_ONLY
> + if (!h2g_valid(addr) || !h2g_valid(addr + len - 1) ||
> + page_check_range(addr, len, PAGE_WRITE) < 0) {
> + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
> + }
> +#else
> + /* test the actual access, not just any access to the page due to LAP */
> + while (len) {
> + const uint64_t pagelen = -(addr | -TARGET_PAGE_MASK);
> + const uint64_t curlen = MIN(pagelen, len);
> +
> + probe_write(env, addr, curlen, cpu_mmu_index(env, false), ra);
> + addr = wrap_address(env, addr + curlen);
> + len -= curlen;
> + }
> +#endif
> +}
>
> Conny, I can resend if you don't feel like fixing up (or there is more to do).
>
If that's the only thing, I can easily fold it in.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper
2019-03-07 14:34 ` David Hildenbrand
2019-03-07 14:40 ` Cornelia Huck
@ 2019-03-07 15:15 ` Richard Henderson
1 sibling, 0 replies; 47+ messages in thread
From: Richard Henderson @ 2019-03-07 15:15 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 3/7/19 6:34 AM, David Hildenbrand wrote:
> So it should be
>
>
> +void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
> + uintptr_t ra)
> +{
> +#ifdef CONFIG_USER_ONLY
> + if (!h2g_valid(addr) || !h2g_valid(addr + len - 1) ||
> + page_check_range(addr, len, PAGE_WRITE) < 0) {
> + s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
> + }
Correct. With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (37 preceding siblings ...)
2019-03-07 14:05 ` no-reply
@ 2019-03-07 15:49 ` no-reply
2019-03-07 16:35 ` Cornelia Huck
39 siblings, 0 replies; 47+ messages in thread
From: no-reply @ 2019-03-07 15:49 UTC (permalink / raw)
To: david; +Cc: fam, qemu-devel, qemu-s390x, cohuck, thuth, rth
Patchew URL: https://patchew.org/QEMU/20190307121539.12842-1-david@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20190307121539.12842-1-david@redhat.com
Subject: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20190307121539.12842-1-david@redhat.com -> patchew/20190307121539.12842-1-david@redhat.com
Switched to a new branch 'test'
5848dfc88a s390x/tcg: Implement VECTOR UNPACK *
7e368477c5 s390x/tcg: Implement VECTOR STORE WITH LENGTH
609977f736 s390x/tcg: Implement VECTOR STORE MULTIPLE
db01dbf76f s390x/tcg: Implement VECTOR STORE ELEMENT
84c37b8f82 s390x/tcg: Implement VECTOR STORE
6ffbe981b0 s390x/tcg: Provide probe_write_access helper
5d1e9782e4 s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
d477bf8a42 s390x/tcg: Implement VECTOR SELECT
4ada4aa4e8 s390x/tcg: Implement VECTOR SCATTER ELEMENT
54495356f0 s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
53fd66335c s390x/tcg: Implement VECTOR REPLICATE
2f7d5675bf s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
1b0ea7576b s390x/tcg: Implement VECTOR PERMUTE
00d9df92c1 s390x/tcg: Implement VECTOR PACK *
3701ea61fb s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
29f6183c82 s390x/tcg: Implement VECTOR LOAD WITH LENGTH
c7914c98ce s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
a02ffced91 s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
0749abdbd4 s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
9bec1d6b0b s390x/tcg: Implement VECTOR LOAD MULTIPLE
4b839be686 s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
6198c749ec s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
23f6ed0387 s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
2168f3ed0e s390x/tcg: Implement VECTOR LOAD ELEMENT
961ce46497 s390x/tcg: Implement VECTOR LOAD AND REPLICATE
24e44fb771 s390x/tcg: Implement VECTOR LOAD
128d7ccfec s390x/tcg: Implement VECTOR GENERATE MASK
4b7349dc7e s390x/tcg: Implement VECTOR GENERATE BYTE MASK
54557b2dda s390x/tcg: Implement VECTOR GATHER ELEMENT
82ba050cbd s390x/tcg: Utilities for vector instruction helpers
1066457e34 s390x/tcg: Check vector register instructions at central point
bb70511084 s390x/tcg: Define vector instruction formats
=== OUTPUT BEGIN ===
1/32 Checking commit bb7051108455 (s390x/tcg: Define vector instruction formats)
2/32 Checking commit 1066457e346b (s390x/tcg: Check vector register instructions at central point)
3/32 Checking commit 82ba050cbd09 (s390x/tcg: Utilities for vector instruction helpers)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#17:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 3/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/32 Checking commit 54557b2dda03 (s390x/tcg: Implement VECTOR GATHER ELEMENT)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#56:
new file mode 100644
total: 0 errors, 1 warnings, 155 lines checked
Patch 4/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/32 Checking commit 4b7349dc7eee (s390x/tcg: Implement VECTOR GENERATE BYTE MASK)
6/32 Checking commit 128d7ccfec4e (s390x/tcg: Implement VECTOR GENERATE MASK)
7/32 Checking commit 24e44fb7712f (s390x/tcg: Implement VECTOR LOAD)
8/32 Checking commit 961ce46497cf (s390x/tcg: Implement VECTOR LOAD AND REPLICATE)
9/32 Checking commit 2168f3ed0e0c (s390x/tcg: Implement VECTOR LOAD ELEMENT)
10/32 Checking commit 23f6ed038729 (s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE)
11/32 Checking commit 6198c749ec94 (s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT)
12/32 Checking commit 4b839be6865f (s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO)
13/32 Checking commit 9bec1d6b0b63 (s390x/tcg: Implement VECTOR LOAD MULTIPLE)
14/32 Checking commit 0749abdbd438 (s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 96 lines checked
Patch 14/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/32 Checking commit a02ffced918f (s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR)
16/32 Checking commit c7914c98ce0e (s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT)
17/32 Checking commit 29f6183c820a (s390x/tcg: Implement VECTOR LOAD WITH LENGTH)
18/32 Checking commit 3701ea61fbbc (s390x/tcg: Implement VECTOR MERGE (HIGH|LOW))
19/32 Checking commit 00d9df92c1a8 (s390x/tcg: Implement VECTOR PACK *)
ERROR: space prohibited between function name and open parenthesis '('
#183: FILE: target/s390x/vec_helper.c:48:
+typedef uint##TBITS##_t (*vpk##BITS##_fn)(uint##BITS##_t, int *); \
total: 1 errors, 0 warnings, 245 lines checked
Patch 19/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/32 Checking commit 1b0ea7576bec (s390x/tcg: Implement VECTOR PERMUTE)
WARNING: line over 80 characters
#21: FILE: target/s390x/helper.h:144:
+DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
total: 0 errors, 1 warnings, 58 lines checked
Patch 20/32 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/32 Checking commit 2f7d5675bf89 (s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE)
22/32 Checking commit 53fd66335c53 (s390x/tcg: Implement VECTOR REPLICATE)
23/32 Checking commit 54495356f06c (s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE)
24/32 Checking commit 4ada4aa4e80b (s390x/tcg: Implement VECTOR SCATTER ELEMENT)
25/32 Checking commit d477bf8a42d9 (s390x/tcg: Implement VECTOR SELECT)
26/32 Checking commit 5d1e9782e43a (s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD)
27/32 Checking commit 6ffbe981b0c1 (s390x/tcg: Provide probe_write_access helper)
28/32 Checking commit 84c37b8f821a (s390x/tcg: Implement VECTOR STORE)
29/32 Checking commit db01dbf76f04 (s390x/tcg: Implement VECTOR STORE ELEMENT)
30/32 Checking commit 609977f73603 (s390x/tcg: Implement VECTOR STORE MULTIPLE)
31/32 Checking commit 7e368477c537 (s390x/tcg: Implement VECTOR STORE WITH LENGTH)
32/32 Checking commit 5848dfc88ab1 (s390x/tcg: Implement VECTOR UNPACK *)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190307121539.12842-1-david@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
` (38 preceding siblings ...)
2019-03-07 15:49 ` no-reply
@ 2019-03-07 16:35 ` Cornelia Huck
39 siblings, 0 replies; 47+ messages in thread
From: Cornelia Huck @ 2019-03-07 16:35 UTC (permalink / raw)
To: David Hildenbrand; +Cc: qemu-devel, qemu-s390x, Thomas Huth, Richard Henderson
On Thu, 7 Mar 2019 13:15:07 +0100
David Hildenbrand <david@redhat.com> wrote:
> This is the first part of vector instruction support for s390x. Parts
> will be sent and reviewed piece by piece.
>
> Part 1: Vector Support Instructions
> Part 2: Vector Integer Instructions
> Part 3: Vector String Instructions
> Part 4: Vector Floating-Point Instructions
>
> The current state can be found at (kept updated):
> https://github.com/davidhildenbrand/qemu/tree/vx
> It is based on
> https://github.com/cohuck/qemu/tree/s390-next
>
> With the current state I can boot Linux kernel + user space compiled with
> SIMD support. This allows to boot distributions compiled exclusively for
> z13, requiring SIMD support. Also, I have a growing set of tests for
> kvm-unit-tests and tests/tcg which I cross-test on a real s390x system.
>
> In this part, the basic infrastructure and all Vector Support Instructions
> introduced with the "Vector Facility" are added. The Vector Extension
> Facilities are not considered for now.
>
> We make use of the existing gvec expansion + ool (out-of-line) support.
> This will be heavily used especially for part 2 (Integer Instructions)
> where we can actually reuse quite some existing gvec expansions.
>
> v2 -> v3:
> - "s390x/tcg: Utilities for vector instruction helpers"
> -- inline helpers in header file
> - "s390x/tcg: Implement VECTOR LOAD MULTIPLE"
> -- optimize loading of last element
> - "s390x/tcg: Implement VECTOR PACK *"
> -- make the static funtion arrays const
> - "s390x/tcg: Implement VECTOR REPLICATE"
> -- use "tcg_gen_gvec_dup_mem"
> - "s390x/tcg: Provide probe_write helper"
> -- Add check for CONFIG_USER_ONLY
> -- Optimize calculation of length
> - Added r-b's
>
> v1 -> v2:
> - Basically address all wonderful review comments from Richard (too many
> to name them all)
> - Probe write access to get rid of FIXMEs
> - Heavily rework "s390x/tcg: Implement VECTOR PACK *"
> -- Process cc and !cc separately.
> -- Helper for VPK
> - Don't use a temporary vector register (for now)
> - Drop load_vec_element() and store_vec_element()
> - Use ES_* instead of MO_*, will come in handy when we use ES_128 later
> - .... many many other minor things
>
> David Hildenbrand (32):
> s390x/tcg: Define vector instruction formats
> s390x/tcg: Check vector register instructions at central point
> s390x/tcg: Utilities for vector instruction helpers
> s390x/tcg: Implement VECTOR GATHER ELEMENT
> s390x/tcg: Implement VECTOR GENERATE BYTE MASK
> s390x/tcg: Implement VECTOR GENERATE MASK
> s390x/tcg: Implement VECTOR LOAD
> s390x/tcg: Implement VECTOR LOAD AND REPLICATE
> s390x/tcg: Implement VECTOR LOAD ELEMENT
> s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE
> s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT
> s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO
> s390x/tcg: Implement VECTOR LOAD MULTIPLE
> s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY
> s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR
> s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT
> s390x/tcg: Implement VECTOR LOAD WITH LENGTH
> s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)
> s390x/tcg: Implement VECTOR PACK *
> s390x/tcg: Implement VECTOR PERMUTE
> s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE
> s390x/tcg: Implement VECTOR REPLICATE
> s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE
> s390x/tcg: Implement VECTOR SCATTER ELEMENT
> s390x/tcg: Implement VECTOR SELECT
> s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD
> s390x/tcg: Provide probe_write_access helper
> s390x/tcg: Implement VECTOR STORE
> s390x/tcg: Implement VECTOR STORE ELEMENT
> s390x/tcg: Implement VECTOR STORE MULTIPLE
> s390x/tcg: Implement VECTOR STORE WITH LENGTH
> s390x/tcg: Implement VECTOR UNPACK *
>
> target/s390x/Makefile.objs | 1 +
> target/s390x/cpu.h | 7 +
> target/s390x/helper.h | 21 +
> target/s390x/insn-data.def | 82 +++
> target/s390x/insn-format.def | 25 +
> target/s390x/internal.h | 2 +
> target/s390x/mem_helper.c | 25 +
> target/s390x/translate.c | 61 ++-
> target/s390x/translate_vx.inc.c | 935 ++++++++++++++++++++++++++++++++
> target/s390x/vec.h | 101 ++++
> target/s390x/vec_helper.c | 193 +++++++
> 11 files changed, 1452 insertions(+), 1 deletion(-)
> create mode 100644 target/s390x/translate_vx.inc.c
> create mode 100644 target/s390x/vec.h
> create mode 100644 target/s390x/vec_helper.c
>
Thanks, applied.
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2019-03-07 16:35 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-07 12:15 [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 01/32] s390x/tcg: Define vector instruction formats David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 02/32] s390x/tcg: Check vector register instructions at central point David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 03/32] s390x/tcg: Utilities for vector instruction helpers David Hildenbrand
2019-03-07 13:11 ` Thomas Huth
2019-03-07 14:00 ` Richard Henderson
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 04/32] s390x/tcg: Implement VECTOR GATHER ELEMENT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 05/32] s390x/tcg: Implement VECTOR GENERATE BYTE MASK David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 06/32] s390x/tcg: Implement VECTOR GENERATE MASK David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 07/32] s390x/tcg: Implement VECTOR LOAD David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 08/32] s390x/tcg: Implement VECTOR LOAD AND REPLICATE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 09/32] s390x/tcg: Implement VECTOR LOAD ELEMENT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 10/32] s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 11/32] s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 12/32] s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERO David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 13/32] s390x/tcg: Implement VECTOR LOAD MULTIPLE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 14/32] s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 15/32] s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 16/32] s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 17/32] s390x/tcg: Implement VECTOR LOAD WITH LENGTH David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 18/32] s390x/tcg: Implement VECTOR MERGE (HIGH|LOW) David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 19/32] s390x/tcg: Implement VECTOR PACK * David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 20/32] s390x/tcg: Implement VECTOR PERMUTE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 21/32] s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 22/32] s390x/tcg: Implement VECTOR REPLICATE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 23/32] s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 24/32] s390x/tcg: Implement VECTOR SCATTER ELEMENT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 25/32] s390x/tcg: Implement VECTOR SELECT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 26/32] s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 27/32] s390x/tcg: Provide probe_write_access helper David Hildenbrand
2019-03-07 14:10 ` Richard Henderson
2019-03-07 14:34 ` David Hildenbrand
2019-03-07 14:40 ` Cornelia Huck
2019-03-07 15:15 ` Richard Henderson
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 28/32] s390x/tcg: Implement VECTOR STORE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 29/32] s390x/tcg: Implement VECTOR STORE ELEMENT David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 30/32] s390x/tcg: Implement VECTOR STORE MULTIPLE David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 31/32] s390x/tcg: Implement VECTOR STORE WITH LENGTH David Hildenbrand
2019-03-07 12:15 ` [Qemu-devel] [PATCH v3 32/32] s390x/tcg: Implement VECTOR UNPACK * David Hildenbrand
2019-03-07 12:49 ` [Qemu-devel] [PATCH v3 00/32] s390x/tcg: Vector Instruction Support Part 1 no-reply
2019-03-07 12:55 ` no-reply
2019-03-07 12:59 ` no-reply
2019-03-07 13:04 ` no-reply
2019-03-07 13:17 ` no-reply
2019-03-07 14:05 ` no-reply
2019-03-07 15:49 ` no-reply
2019-03-07 16:35 ` Cornelia Huck
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.