[PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[José Roberto de Souza]

For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept set
while PSR2 is enabled, it causes some selective updates to fail after
got back from DC6 for the first time.
So lets clear this register before enabled PSR2, as it could be set
by a previous i915 module, firmware/BIOS or by a previous mode that
is not compatible with PSR2.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7bab6a009e0d..ae62f8124558 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u32 val;
+	int idle_frames;
+
+	/*
+	 * Keeping this PSR1 register set while PSR2 is enabled causes some
+	 * PSR2 selective updates to fail, corrupting screen.
+	 */
+	val = I915_READ(EDP_PSR_CTL);
+	if (val & EDP_PSR_TP1_TP3_SEL)
+		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);
 
 	/* Let's use 6 as the minimum to cover all known cases including the
 	 * off-by-one issue that HW has in some cases.
 	 */
-	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
+	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
 	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
 
-- 
2.21.0

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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Rodrigo Vivi]

On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza wrote:
> For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept set
> while PSR2 is enabled, it causes some selective updates to fail after
> got back from DC6 for the first time.
> So lets clear this register before enabled PSR2, as it could be set
> by a previous i915 module, firmware/BIOS or by a previous mode that
> is not compatible with PSR2.

Does it happen when you don't have DMC loaded?

Because It looks like a DMC bug for me...

If by removing DMC we don't see the issue, could we please file
this bug to DMC while adding a FIXME with DMC bugged version on it?

Aa: Pavana

If it doesn't happen with DMC loaded than maybe a HSD would for hw
team would be good anyway.

Cc: Art.

Thanks,
Rodrigo.

> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 7bab6a009e0d..ae62f8124558 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u32 val;
> +	int idle_frames;
> +
> +	/*
> +	 * Keeping this PSR1 register set while PSR2 is enabled causes some
> +	 * PSR2 selective updates to fail, corrupting screen.
> +	 */
> +	val = I915_READ(EDP_PSR_CTL);
> +	if (val & EDP_PSR_TP1_TP3_SEL)
> +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);
>  
>  	/* Let's use 6 as the minimum to cover all known cases including the
>  	 * off-by-one issue that HW has in some cases.
>  	 */
> -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> -
> +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
>  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
>  
> -- 
> 2.21.0
> 
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Dhinakaran Pandiyan]

On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> wrote:
> > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > set
> > while PSR2 is enabled, it causes some selective updates to fail
> > after
> > got back from DC6 for the first time.

That's suspicious, why does a PSR1 control register have any effect on
PSR2. Was PSR1 enabled before PSR2? 



> > So lets clear this register before enabled PSR2, as it could be set
> > by a previous i915 module, firmware/BIOS or by a previous mode that
> > is not compatible with PSR2.
> 
> Does it happen when you don't have DMC loaded?
> 
> Because It looks like a DMC bug for me...
> 
> If by removing DMC we don't see the issue, could we please file
> this bug to DMC while adding a FIXME with DMC bugged version on it?
> 
> Aa: Pavana
> 
> If it doesn't happen with DMC loaded than maybe a HSD would for hw
> team would be good anyway.
> 
> Cc: Art.
> 
> Thanks,
> Rodrigo.
> 
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> >  1 file changed, 10 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 7bab6a009e0d..ae62f8124558 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u32 val;
> > +	int idle_frames;
> > +
> > +	/*
> > +	 * Keeping this PSR1 register set while PSR2 is enabled causes
> > some
> > +	 * PSR2 selective updates to fail, corrupting screen.
> > +	 */
> > +	val = I915_READ(EDP_PSR_CTL);
> > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);

Since PSR1 should be disabled at this point, a rmw is not necessary.
Does this work? 
I915_WRITE(EDP_PSR_CTL, 0);

We could do the same thing in psr_exit() as well.

> >  
> >  	/* Let's use 6 as the minimum to cover all known cases
> > including the
> >  	 * off-by-one issue that HW has in some cases.
> >  	 */
> > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -
> > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> >  	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> >  
> > -- 
> > 2.21.0
> > 

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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 3329 bytes --]

On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > wrote:
> > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > > set
> > > while PSR2 is enabled, it causes some selective updates to fail
> > > after
> > > got back from DC6 for the first time.
> 
> That's suspicious, why does a PSR1 control register have any effect
> on
> PSR2. Was PSR1 enabled before PSR2? 

Yes it only happens when switching from PSR1 -> PSR2, I caught this
issue now because I had a external connector attached so display was
never going to DC6.

> 
> 
> 
> > > So lets clear this register before enabled PSR2, as it could be
> > > set
> > > by a previous i915 module, firmware/BIOS or by a previous mode
> > > that
> > > is not compatible with PSR2.
> > 
> > Does it happen when you don't have DMC loaded?
> > 
> > Because It looks like a DMC bug for me...
> > 
> > If by removing DMC we don't see the issue, could we please file
> > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > 
> > Aa: Pavana
> > 
> > If it doesn't happen with DMC loaded than maybe a HSD would for hw
> > team would be good anyway.
> > 
> > Cc: Art.
> > 
> > Thanks,
> > Rodrigo.
> > 
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 7bab6a009e0d..ae62f8124558 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > intel_dp
> > > *intel_dp)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >  	u32 val;
> > > +	int idle_frames;
> > > +
> > > +	/*
> > > +	 * Keeping this PSR1 register set while PSR2 is enabled causes
> > > some
> > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > +	 */
> > > +	val = I915_READ(EDP_PSR_CTL);
> > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);
> 
> Since PSR1 should be disabled at this point, a rmw is not necessary.
> Does this work? 
> I915_WRITE(EDP_PSR_CTL, 0);
> 
> We could do the same thing in psr_exit() as well.

Write 0 also works and I'm doing RMW because I always try to save any
writes.

No need to do it in psr_exit(), the important is do it here because
other i915 module or BIOS could leave it set.

> 
> > >  
> > >  	/* Let's use 6 as the minimum to cover all known cases
> > > including the
> > >  	 * off-by-one issue that HW has in some cases.
> > >  	 */
> > > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > -
> > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > >  	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > > + 1);
> > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > >  
> > > -- 
> > > 2.21.0
> > > 

[-- Attachment #1.2: This is a digitally signed message part --]
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Pandiyan, Dhinakaran]

On Tue, 2019-03-12 at 14:28 -0700, Souza, Jose wrote:
> On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > wrote:
> > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is
> > > > kept
> > > > set
> > > > while PSR2 is enabled, it causes some selective updates to fail
> > > > after
> > > > got back from DC6 for the first time.
> > 
> > That's suspicious, why does a PSR1 control register have any effect
> > on
> > PSR2. Was PSR1 enabled before PSR2? 
> 
> Yes it only happens when switching from PSR1 -> PSR2, I caught this
> issue now because I had a external connector attached so display was
> never going to DC6.

I am a bit confused now :) Do you see the issue if PSR1 was never
enabled before enabling PSR2?

> > 
> > 
> > 
> > > > So lets clear this register before enabled PSR2, as it could be
> > > > set
> > > > by a previous i915 module, firmware/BIOS or by a previous mode
> > > > that
> > > > is not compatible with PSR2.
> > > 
> > > Does it happen when you don't have DMC loaded?
> > > 
> > > Because It looks like a DMC bug for me...
> > > 
> > > If by removing DMC we don't see the issue, could we please file
> > > this bug to DMC while adding a FIXME with DMC bugged version on
> > > it?
> > > 
> > > Aa: Pavana
> > > 
> > > If it doesn't happen with DMC loaded than maybe a HSD would for
> > > hw
> > > team would be good anyway.
> > > 
> > > Cc: Art.
> > > 
> > > Thanks,
> > > Rodrigo.
> > > 
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv =
> > > > dp_to_i915(intel_dp);
> > > >  	u32 val;
> > > > +	int idle_frames;
> > > > +
> > > > +	/*
> > > > +	 * Keeping this PSR1 register set while PSR2 is enabled
> > > > causes
> > > > some
> > > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > > +	 */
> > > > +	val = I915_READ(EDP_PSR_CTL);
> > > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > > +		I915_WRITE(EDP_PSR_CTL, val &
> > > > ~EDP_PSR_TP1_TP3_SEL);
> > 
> > Since PSR1 should be disabled at this point, a rmw is not
> > necessary.
> > Does this work? 
> > I915_WRITE(EDP_PSR_CTL, 0);
> > 
> > We could do the same thing in psr_exit() as well.
> 
> Write 0 also works and I'm doing RMW because I always try to save any
> writes.
Why so? Do we want to retain the old value in PSR_CTL when PSR2 is
enabled? 

> 
> No need to do it in psr_exit(), the important is do it here because
> other i915 module or BIOS could leave it set.
Right, that was an orthogonal suggestion to avoid the RMW that we do to
disable PSR1 and PSR2.

psr1 and psr2 activate functions recompute the values fully, so there
is no benefit in flipping just the enable bit in psr_exit().
> 
> > 
> > > >  
> > > >  	/* Let's use 6 as the minimum to cover all known cases
> > > > including the
> > > >  	 * off-by-one issue that HW has in some cases.
> > > >  	 */
> > > > -	int idle_frames = max(6, dev_priv-
> > > > >vbt.psr.idle_frames);
> > > > -
> > > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > >  	idle_frames = max(idle_frames, dev_priv-
> > > > >psr.sink_sync_latency
> > > > + 1);
> > > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > >  
> > > > -- 
> > > > 2.21.0
> > > > 
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 4864 bytes --]

On Tue, 2019-03-12 at 14:46 -0700, Pandiyan, Dhinakaran wrote:
> On Tue, 2019-03-12 at 14:28 -0700, Souza, Jose wrote:
> > On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > > wrote:
> > > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is
> > > > > kept
> > > > > set
> > > > > while PSR2 is enabled, it causes some selective updates to
> > > > > fail
> > > > > after
> > > > > got back from DC6 for the first time.
> > > 
> > > That's suspicious, why does a PSR1 control register have any
> > > effect
> > > on
> > > PSR2. Was PSR1 enabled before PSR2? 
> > 
> > Yes it only happens when switching from PSR1 -> PSR2, I caught this
> > issue now because I had a external connector attached so display
> > was
> > never going to DC6.
> 
> I am a bit confused now :) Do you see the issue if PSR1 was never
> enabled before enabling PSR2?

I don't see, just being cautions about how this issue could be trigged.

> 
> > > 
> > > 
> > > > > So lets clear this register before enabled PSR2, as it could
> > > > > be
> > > > > set
> > > > > by a previous i915 module, firmware/BIOS or by a previous
> > > > > mode
> > > > > that
> > > > > is not compatible with PSR2.
> > > > 
> > > > Does it happen when you don't have DMC loaded?
> > > > 
> > > > Because It looks like a DMC bug for me...
> > > > 
> > > > If by removing DMC we don't see the issue, could we please file
> > > > this bug to DMC while adding a FIXME with DMC bugged version on
> > > > it?
> > > > 
> > > > Aa: Pavana
> > > > 
> > > > If it doesn't happen with DMC loaded than maybe a HSD would for
> > > > hw
> > > > team would be good anyway.
> > > > 
> > > > Cc: Art.
> > > > 
> > > > Thanks,
> > > > Rodrigo.
> > > > 
> > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > > > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > > intel_dp
> > > > > *intel_dp)
> > > > >  {
> > > > >  	struct drm_i915_private *dev_priv =
> > > > > dp_to_i915(intel_dp);
> > > > >  	u32 val;
> > > > > +	int idle_frames;
> > > > > +
> > > > > +	/*
> > > > > +	 * Keeping this PSR1 register set while PSR2 is enabled
> > > > > causes
> > > > > some
> > > > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > > > +	 */
> > > > > +	val = I915_READ(EDP_PSR_CTL);
> > > > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > > > +		I915_WRITE(EDP_PSR_CTL, val &
> > > > > ~EDP_PSR_TP1_TP3_SEL);
> > > 
> > > Since PSR1 should be disabled at this point, a rmw is not
> > > necessary.
> > > Does this work? 
> > > I915_WRITE(EDP_PSR_CTL, 0);
> > > 
> > > We could do the same thing in psr_exit() as well.
> > 
> > Write 0 also works and I'm doing RMW because I always try to save
> > any
> > writes.
> Why so? Do we want to retain the old value in PSR_CTL when PSR2 is
> enabled? 

We don't need the old PSR_CTL value but on psr_exit() we can't set to 0
for sure as BSpec says to not modify the other registers when the
enable bit is set, it probably uses the TP SEL and TP training values
to do the PSR exit.
Not a strong argument but in here I would say is better to unset just
the one causing the issue so we can better track the issue in DMC side.

> 
> > No need to do it in psr_exit(), the important is do it here because
> > other i915 module or BIOS could leave it set.
> Right, that was an orthogonal suggestion to avoid the RMW that we do
> to
> disable PSR1 and PSR2.
> 
> psr1 and psr2 activate functions recompute the values fully, so there
> is no benefit in flipping just the enable bit in psr_exit().
> > > > >  
> > > > >  	/* Let's use 6 as the minimum to cover all known cases
> > > > > including the
> > > > >  	 * off-by-one issue that HW has in some cases.
> > > > >  	 */
> > > > > -	int idle_frames = max(6, dev_priv-
> > > > > > vbt.psr.idle_frames);
> > > > > -
> > > > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > >  	idle_frames = max(idle_frames, dev_priv-
> > > > > > psr.sink_sync_latency
> > > > > + 1);
> > > > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > > >  
> > > > > -- 
> > > > > 2.21.0
> > > > > 

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Runyan, Arthur J]

Strange.  DMC doesn't look at training patterns.  I've asked the PSR2 guys to look for any cross-connection.

> -----Original Message-----
> From: Souza, Jose
> Sent: Tuesday, 12 March, 2019 2:29 PM
> To: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>
> Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>; Aigal, Pavana A
> <pavana.a.aigal@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> PSR1 setup
> 
> On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > wrote:
> > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > > > set
> > > > while PSR2 is enabled, it causes some selective updates to fail
> > > > after
> > > > got back from DC6 for the first time.
> >
> > That's suspicious, why does a PSR1 control register have any effect
> > on
> > PSR2. Was PSR1 enabled before PSR2?
> 
> Yes it only happens when switching from PSR1 -> PSR2, I caught this
> issue now because I had a external connector attached so display was
> never going to DC6.
> 
> >
> >
> >
> > > > So lets clear this register before enabled PSR2, as it could be
> > > > set
> > > > by a previous i915 module, firmware/BIOS or by a previous mode
> > > > that
> > > > is not compatible with PSR2.
> > >
> > > Does it happen when you don't have DMC loaded?
> > >
> > > Because It looks like a DMC bug for me...
> > >
> > > If by removing DMC we don't see the issue, could we please file
> > > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > >
> > > Aa: Pavana
> > >
> > > If it doesn't happen with DMC loaded than maybe a HSD would for hw
> > > team would be good anyway.
> > >
> > > Cc: Art.
> > >
> > > Thanks,
> > > Rodrigo.
> > >
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > intel_dp
> > > > *intel_dp)
> > > >  {
> > > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > >  	u32 val;
> > > > +	int idle_frames;
> > > > +
> > > > +	/*
> > > > +	 * Keeping this PSR1 register set while PSR2 is enabled causes
> > > > some
> > > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > > +	 */
> > > > +	val = I915_READ(EDP_PSR_CTL);
> > > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > > +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);
> >
> > Since PSR1 should be disabled at this point, a rmw is not necessary.
> > Does this work?
> > I915_WRITE(EDP_PSR_CTL, 0);
> >
> > We could do the same thing in psr_exit() as well.
> 
> Write 0 also works and I'm doing RMW because I always try to save any
> writes.
> 
> No need to do it in psr_exit(), the important is do it here because
> other i915 module or BIOS could leave it set.
> 
> >
> > > >
> > > >  	/* Let's use 6 as the minimum to cover all known cases
> > > > including the
> > > >  	 * off-by-one issue that HW has in some cases.
> > > >  	 */
> > > > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > -
> > > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > >  	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > > > + 1);
> > > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > >
> > > > --
> > > > 2.21.0
> > > >
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Runyan, Arthur J]

PSR2 logic is incorrectly looking at this register bit during DC5 exit. 
Not a DMC problem, but DMC enables DC5.
I'll update Bspec to require the bit to be not set when PSR2 is used.

> -----Original Message-----
> From: Runyan, Arthur J
> Sent: Tuesday, 12 March, 2019 4:42 PM
> To: Souza, Jose <jose.souza@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>
> Cc: Aigal, Pavana A <pavana.a.aigal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> PSR1 setup
> 
> Strange.  DMC doesn't look at training patterns.  I've asked the PSR2 guys to
> look for any cross-connection.
> 
> > -----Original Message-----
> > From: Souza, Jose
> > Sent: Tuesday, 12 March, 2019 2:29 PM
> > To: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> > <dhinakaran.pandiyan@intel.com>
> > Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>; Aigal, Pavana A
> > <pavana.a.aigal@intel.com>; intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> > PSR1 setup
> >
> > On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > > wrote:
> > > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > > > > set
> > > > > while PSR2 is enabled, it causes some selective updates to fail
> > > > > after
> > > > > got back from DC6 for the first time.
> > >
> > > That's suspicious, why does a PSR1 control register have any effect
> > > on
> > > PSR2. Was PSR1 enabled before PSR2?
> >
> > Yes it only happens when switching from PSR1 -> PSR2, I caught this
> > issue now because I had a external connector attached so display was
> > never going to DC6.
> >
> > >
> > >
> > >
> > > > > So lets clear this register before enabled PSR2, as it could be
> > > > > set
> > > > > by a previous i915 module, firmware/BIOS or by a previous mode
> > > > > that
> > > > > is not compatible with PSR2.
> > > >
> > > > Does it happen when you don't have DMC loaded?
> > > >
> > > > Because It looks like a DMC bug for me...
> > > >
> > > > If by removing DMC we don't see the issue, could we please file
> > > > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > > >
> > > > Aa: Pavana
> > > >
> > > > If it doesn't happen with DMC loaded than maybe a HSD would for hw
> > > > team would be good anyway.
> > > >
> > > > Cc: Art.
> > > >
> > > > Thanks,
> > > > Rodrigo.
> > > >
> > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > > > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > > intel_dp
> > > > > *intel_dp)
> > > > >  {
> > > > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > >  	u32 val;
> > > > > +	int idle_frames;
> > > > > +
> > > > > +	/*
> > > > > +	 * Keeping this PSR1 register set while PSR2 is enabled causes
> > > > > some
> > > > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > > > +	 */
> > > > > +	val = I915_READ(EDP_PSR_CTL);
> > > > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > > > +		I915_WRITE(EDP_PSR_CTL, val &
> ~EDP_PSR_TP1_TP3_SEL);
> > >
> > > Since PSR1 should be disabled at this point, a rmw is not necessary.
> > > Does this work?
> > > I915_WRITE(EDP_PSR_CTL, 0);
> > >
> > > We could do the same thing in psr_exit() as well.
> >
> > Write 0 also works and I'm doing RMW because I always try to save any
> > writes.
> >
> > No need to do it in psr_exit(), the important is do it here because
> > other i915 module or BIOS could leave it set.
> >
> > >
> > > > >
> > > > >  	/* Let's use 6 as the minimum to cover all known cases
> > > > > including the
> > > > >  	 * off-by-one issue that HW has in some cases.
> > > > >  	 */
> > > > > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > -
> > > > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > >  	idle_frames = max(idle_frames, dev_priv-
> >psr.sink_sync_latency
> > > > > + 1);
> > > > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > > >
> > > > > --
> > > > > 2.21.0
> > > > >
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Pandiyan, Dhinakaran]

Thanks for checking, appreciate it.

-DK

> -----Original Message-----
> From: Runyan, Arthur J
> Sent: Wednesday, March 20, 2019 11:58 AM
> To: Souza, Jose <jose.souza@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> <dhinakaran.pandiyan@intel.com>
> Cc: Aigal, Pavana A <pavana.a.aigal@intel.com>; 'intel-
> gfx@lists.freedesktop.org' <intel-gfx@lists.freedesktop.org>
> Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> PSR1 setup
> 
> PSR2 logic is incorrectly looking at this register bit during DC5 exit.
> Not a DMC problem, but DMC enables DC5.
> I'll update Bspec to require the bit to be not set when PSR2 is used.
> 
> > -----Original Message-----
> > From: Runyan, Arthur J
> > Sent: Tuesday, 12 March, 2019 4:42 PM
> > To: Souza, Jose <jose.souza@intel.com>; Vivi, Rodrigo
> > <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> > <dhinakaran.pandiyan@intel.com>
> > Cc: Aigal, Pavana A <pavana.a.aigal@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption
> > after
> > PSR1 setup
> >
> > Strange.  DMC doesn't look at training patterns.  I've asked the PSR2
> > guys to look for any cross-connection.
> >
> > > -----Original Message-----
> > > From: Souza, Jose
> > > Sent: Tuesday, 12 March, 2019 2:29 PM
> > > To: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Pandiyan, Dhinakaran
> > > <dhinakaran.pandiyan@intel.com>
> > > Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>; Aigal, Pavana A
> > > <pavana.a.aigal@intel.com>; intel-gfx@lists.freedesktop.org
> > > Subject: Re: [PATCH] drm/i915: Fix PSR2 selective update corruption
> > > after
> > > PSR1 setup
> > >
> > > On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > > > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > > > wrote:
> > > > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is
> > > > > > kept set while PSR2 is enabled, it causes some selective
> > > > > > updates to fail after got back from DC6 for the first time.
> > > >
> > > > That's suspicious, why does a PSR1 control register have any
> > > > effect on PSR2. Was PSR1 enabled before PSR2?
> > >
> > > Yes it only happens when switching from PSR1 -> PSR2, I caught this
> > > issue now because I had a external connector attached so display was
> > > never going to DC6.
> > >
> > > >
> > > >
> > > >
> > > > > > So lets clear this register before enabled PSR2, as it could
> > > > > > be set by a previous i915 module, firmware/BIOS or by a
> > > > > > previous mode that is not compatible with PSR2.
> > > > >
> > > > > Does it happen when you don't have DMC loaded?
> > > > >
> > > > > Because It looks like a DMC bug for me...
> > > > >
> > > > > If by removing DMC we don't see the issue, could we please file
> > > > > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > > > >
> > > > > Aa: Pavana
> > > > >
> > > > > If it doesn't happen with DMC loaded than maybe a HSD would for
> > > > > hw team would be good anyway.
> > > > >
> > > > > Cc: Art.
> > > > >
> > > > > Thanks,
> > > > > Rodrigo.
> > > > >
> > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> > > > > >  1 file changed, 10 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > > > intel_dp
> > > > > > *intel_dp)
> > > > > >  {
> > > > > >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > > >  	u32 val;
> > > > > > +	int idle_frames;
> > > > > > +
> > > > > > +	/*
> > > > > > +	 * Keeping this PSR1 register set while PSR2 is enabled
> > > > > > +causes
> > > > > > some
> > > > > > +	 * PSR2 selective updates to fail, corrupting screen.
> > > > > > +	 */
> > > > > > +	val = I915_READ(EDP_PSR_CTL);
> > > > > > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > > > > > +		I915_WRITE(EDP_PSR_CTL, val &
> > ~EDP_PSR_TP1_TP3_SEL);
> > > >
> > > > Since PSR1 should be disabled at this point, a rmw is not necessary.
> > > > Does this work?
> > > > I915_WRITE(EDP_PSR_CTL, 0);
> > > >
> > > > We could do the same thing in psr_exit() as well.
> > >
> > > Write 0 also works and I'm doing RMW because I always try to save
> > > any writes.
> > >
> > > No need to do it in psr_exit(), the important is do it here because
> > > other i915 module or BIOS could leave it set.
> > >
> > > >
> > > > > >
> > > > > >  	/* Let's use 6 as the minimum to cover all known cases
> > > > > > including the
> > > > > >  	 * off-by-one issue that HW has in some cases.
> > > > > >  	 */
> > > > > > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > > -
> > > > > > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > >  	idle_frames = max(idle_frames, dev_priv-
> > >psr.sink_sync_latency
> > > > > > + 1);
> > > > > >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > > > >
> > > > > > --
> > > > > > 2.21.0
> > > > > >
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Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Souza, Jose]

[-- Attachment #1.1: Type: text/plain, Size: 2957 bytes --]

On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> wrote:
> > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > set
> > while PSR2 is enabled, it causes some selective updates to fail
> > after
> > got back from DC6 for the first time.
> > So lets clear this register before enabled PSR2, as it could be set
> > by a previous i915 module, firmware/BIOS or by a previous mode that
> > is not compatible with PSR2.
> 
> Does it happen when you don't have DMC loaded?
> 
> Because It looks like a DMC bug for me...
> 

BINGO, it do not happens without DMC.

> If by removing DMC we don't see the issue, could we please file
> this bug to DMC while adding a FIXME with DMC bugged version on it?

It happens with GEN9 and GEN10 and reproduced with: icl_dmc_ver1_07.bin
and kbl_dmc_ver1_04.bin

So updating the comment and commit description to:

I will update the comment and commit description to:

For some reason if this register is set and when DMC restore the state
after a DC6 exit, it causes some PSR2 selective updates to fail,
corrupting screen.
So for now lets have this workaround until DMC is fixed.

> 
> Aa: Pavana
> 
> If it doesn't happen with DMC loaded than maybe a HSD would for hw
> team would be good anyway.

I filled a bug in BSpec but in future I will do a HSD instead.

> 
> Cc: Art.
> 
> Thanks,
> Rodrigo.
> 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> >  1 file changed, 10 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 7bab6a009e0d..ae62f8124558 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >  	u32 val;
> > +	int idle_frames;
> > +
> > +	/*
> > +	 * Keeping this PSR1 register set while PSR2 is enabled causes
> > some
> > +	 * PSR2 selective updates to fail, corrupting screen.
> > +	 */
> > +	val = I915_READ(EDP_PSR_CTL);
> > +	if (val & EDP_PSR_TP1_TP3_SEL)
> > +		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_TP1_TP3_SEL);
> >  
> >  	/* Let's use 6 as the minimum to cover all known cases
> > including the
> >  	 * off-by-one issue that HW has in some cases.
> >  	 */
> > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -
> > +	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> >  	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> >  	val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> >  
> > -- 
> > 2.21.0
> > 

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

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✗ Fi.CI.SPARSE: warning for drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Patchwork]

== Series Details ==

Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup
URL   : https://patchwork.freedesktop.org/series/57900/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix PSR2 selective update corruption after PSR1 setup
-O:drivers/gpu/drm/i915/intel_psr.c:501:27: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:503:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:503:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:510:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:511:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:511:23: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.BAT: failure for drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Patchwork]

== Series Details ==

Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup
URL   : https://patchwork.freedesktop.org/series/57900/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5737 -> Patchwork_12444
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12444 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12444, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57900/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12444:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_hangcheck:
    - fi-cfl-8700k:       PASS -> DMESG-FAIL

  
Known issues
------------

  Here are the changes found in Patchwork_12444 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109315] +17

  * igt@gem_ctx_create@basic-files:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] +106

  * igt@gem_exec_basic@gtt-bsd2:
    - fi-byt-clapper:     NOTRUN -> SKIP [fdo#109271] +57

  * igt@gem_exec_basic@readonly-bsd1:
    - fi-snb-2520m:       NOTRUN -> SKIP [fdo#109271] +57
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109276] +7

  * igt@gem_exec_parse@basic-allowed:
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109289] +1

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       NOTRUN -> INCOMPLETE [fdo#107718]

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      PASS -> FAIL [fdo#108511]

  * igt@i915_selftest@live_contexts:
    - fi-icl-u2:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_addfb_basic@addfb25-y-tiled-small:
    - fi-byt-n2820:       NOTRUN -> SKIP [fdo#109271] +56

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         NOTRUN -> FAIL [fdo#103182]

  * igt@kms_busy@basic-flip-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-byt-clapper:     NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-snb-2520m:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-byt-n2820:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@dp-edid-read:
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109316] +2

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-hsw-peppy:       NOTRUN -> SKIP [fdo#109271] +46

  * igt@kms_chamelium@vga-hpd-fast:
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109309] +1

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-icl-u2:          NOTRUN -> SKIP [fdo#109285] +3

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          PASS -> FAIL [fdo#103167]
    - fi-hsw-peppy:       NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
    - fi-icl-u2:          NOTRUN -> FAIL [fdo#103167]
    - fi-byt-clapper:     NOTRUN -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +29

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         NOTRUN -> DMESG-FAIL [fdo#103182]

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110028]: https://bugs.freedesktop.org/show_bug.cgi?id=110028


Participating hosts (41 -> 43)
------------------------------

  Additional (7): fi-hsw-peppy fi-icl-u2 fi-snb-2520m fi-gdg-551 fi-icl-y fi-byt-n2820 fi-byt-clapper 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5737 -> Patchwork_12444

  CI_DRM_5737: d5bb7d77aa77996702426496078a597f30bead58 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4883: b25e06d6ddf2e42044cd9c93b613cbc7339a8c33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12444: 13891d18f16d1ac69dfbb90659ce94d470ce4d59 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

13891d18f16d drm/i915: Fix PSR2 selective update corruption after PSR1 setup

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12444/
_______________________________________________
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✗ Fi.CI.SPARSE: warning for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)
URL   : https://patchwork.freedesktop.org/series/57900/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Fix PSR2 selective update corruption after PSR1 setup
-O:drivers/gpu/drm/i915/intel_psr.c:513:27: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:515:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_psr.c:515:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:522:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:523:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_psr.c:523:23: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)
URL   : https://patchwork.freedesktop.org/series/57900/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5743 -> Patchwork_12455
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/57900/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12455 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-kbl-7500u:       NOTRUN -> SKIP [fdo#109271] +28

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
    - fi-kbl-7567u:       NOTRUN -> SKIP [fdo#109271] +33

  * igt@gem_exec_basic@gtt-bsd:
    - fi-bwr-2160:        NOTRUN -> SKIP [fdo#109271] +103

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  * igt@kms_busy@basic-flip-c:
    - fi-bwr-2160:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-kbl-7560u:       NOTRUN -> SKIP [fdo#109271] +33

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-kbl-7560u:       INCOMPLETE [fdo#103665] -> PASS

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       DMESG-WARN [fdo#103841] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS +1

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720


Participating hosts (47 -> 43)
------------------------------

  Additional (2): fi-kbl-7567u fi-bwr-2160 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5743 -> Patchwork_12455

  CI_DRM_5743: e167a588f3614da02999797b9816744e39e31ad7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4884: c46051337b972f8b5a302afb6f603df06fea527d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12455: 80de099301e5d76b7b3abd206679cdce3f0f3ae9 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

80de099301e5 drm/i915: Fix PSR2 selective update corruption after PSR1 setup

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12455/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev2)
URL   : https://patchwork.freedesktop.org/series/57900/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5743_full -> Patchwork_12455_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12455_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12455_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12455_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@all-pipes-forked-move:
    - shard-iclb:         PASS -> INCOMPLETE

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_plane@pixel-format-pipe-b-planes}:
    - shard-apl:          PASS -> FAIL

  
Known issues
------------

  Here are the changes found in Patchwork_12455_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@extended-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +5

  * igt@gem_ctx_param@invalid-param-set:
    - shard-hsw:          NOTRUN -> FAIL [fdo#109674]

  * igt@gem_exec_parse@basic-rejected:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109289] +1

  * igt@gem_mocs_settings@mocs-rc6-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] / [fdo#109287]

  * igt@gem_partial_pwrite_pread@write:
    - shard-iclb:         PASS -> TIMEOUT [fdo#109673]

  * igt@gem_pread@stolen-normal:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +132

  * igt@gem_pread@stolen-snoop:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277]

  * igt@gem_pwrite@huge-cpu-fbr:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109290]

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#107847]

  * igt@i915_pm_rps@reset:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108059]

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          PASS -> DMESG-WARN [fdo#108566]

  * igt@kms_atomic_transition@4x-modeset-transitions-fencing:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

  * igt@kms_busy@extended-modeset-hang-oldfb-render-e:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-e:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
    - shard-glk:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_ccs@pipe-c-crc-primary-basic:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] +30

  * igt@kms_chamelium@hdmi-edid-read:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284]

  * igt@kms_color@pipe-a-ctm-max:
    - shard-glk:          NOTRUN -> FAIL [fdo#108147]

  * igt@kms_color@pipe-b-ctm-blue-to-red:
    - shard-skl:          PASS -> FAIL [fdo#107201]

  * igt@kms_concurrent@pipe-d:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +4

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-glk:          NOTRUN -> FAIL [fdo#103232] +1

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-skl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-512x512-dpms:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109279]

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#105454] / [fdo#106509]

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +4

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#103833]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +11

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +15

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-glk:          PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-skl:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#105682] / [fdo#109247] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-skl:          NOTRUN -> FAIL [fdo#105683]

  * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +9

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +12

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +41

  * igt@kms_lease@possible-crtcs-filtering:
    - shard-apl:          PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +18

  * igt@kms_panel_fitting@legacy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105456]

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         PASS -> FAIL [fdo#103375]

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +4

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_psr@cursor_mmap_gtt:
    - shard-iclb:         PASS -> FAIL [fdo#107383] +1

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109441] +1

  * igt@kms_psr@psr2_primary_render:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +1

  * igt@kms_psr@psr2_suspend:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +1

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#106885]

  * igt@kms_universal_plane@universal-plane-gen9-features-pipe-e:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-hsw:          PASS -> FAIL [fdo#104894]

  * igt@kms_vrr@flip-suspend:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109502]

  * igt@prime_nv_pcopy@test2:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291] +2

  * igt@runner@aborted:
    - shard-apl:          NOTRUN -> FAIL [fdo#109373]

  
#### Possible fixes ####

  * igt@gem_exec_schedule@wide-render:
    - shard-iclb:         FAIL [fdo#109633] -> PASS

  * igt@gem_persistent_relocs@forked-thrash-inactive:
    - shard-hsw:          INCOMPLETE [fdo#103540] -> PASS

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-iclb:         DMESG-FAIL [fdo#109766] / [fdo#109801] -> PASS

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-iclb:         INCOMPLETE [fdo#107713] / [fdo#109766] / [fdo#109801] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-dpms:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          INCOMPLETE [fdo#109507] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +9

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +10

  * {igt@kms_plane@pixel-format-pipe-a-planes-source-clamping}:
    - shard-glk:          SKIP [fdo#109271] -> PASS +2

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +2

  * igt@kms_psr@suspend:
    - shard-iclb:         FAIL [fdo#107383] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-iclb:         DMESG-WARN [fdo#106885] -> PASS

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          FAIL [fdo#109016] -> PASS

  * igt@kms_setmode@basic:
    - shard-kbl:          FAIL [fdo#99912] -> PASS

  * igt@kms_universal_plane@universal-plane-pipe-b-functional:
    - shard-apl:          FAIL [fdo#103166] -> PASS +1

  * igt@kms_universal_plane@universal-plane-pipe-c-functional:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-hsw:          FAIL [fdo#104894] -> PASS

  * igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm:
    - shard-apl:          FAIL [fdo#104894] -> PASS +1

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-iclb:         FAIL [fdo#104894] -> PASS

  * igt@perf@oa-exponents:
    - shard-kbl:          FAIL [fdo#105483] -> PASS

  * igt@perf_pmu@rc6-runtime-pm:
    - shard-iclb:         FAIL [fdo#105010] -> PASS

  * igt@sw_sync@sync_expired_merge:
    - shard-iclb:         TIMEOUT [fdo#109673] -> PASS +2

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-apl:          FAIL [fdo#108597] / [fdo#108739] -> SKIP [fdo#105602] / [fdo#109271]

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
    - shard-apl:          FAIL [fdo#108145] -> DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
  [fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
  [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
  [fdo#108739]: https://bugs.freedesktop.org/show_bug.cgi?id=108739
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109287]: https://bugs.freedesktop.org/show_bug.cgi?id=109287
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109633]: https://bugs.freedesktop.org/show_bug.cgi?id=109633
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
  [fdo#109766]: https://bugs.freedesktop.org/show_bug.cgi?id=109766
  [fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
  [fdo#110032]: https://bugs.freedesktop.org/show_bug.cgi?id=110032
  [fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036 
  [fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5743 -> Patchwork_12455

  CI_DRM_5743: e167a588f3614da02999797b9816744e39e31ad7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4884: c46051337b972f8b5a302afb6f603df06fea527d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12455: 80de099301e5d76b7b3abd206679cdce3f0f3ae9 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12455/
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