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From: Marek Vasut <marek.vasut@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] clk: renesas: Fix swapped div and mul in debug output on Gen2
Date: Mon, 18 Mar 2019 06:20:56 +0100	[thread overview]
Message-ID: <20190318052057.25756-2-marek.vasut+renesas@gmail.com> (raw)
In-Reply-To: <20190318052057.25756-1-marek.vasut+renesas@gmail.com>

The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 drivers/clk/renesas/clk-rcar-gen2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index aedaab723b..34abe784fd 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -121,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 
 	case CLK_TYPE_FF:
 		rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
-		debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+		debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
 		      __func__, __LINE__,
 		      core->parent, core->mult, core->div, rate);
 		return rate;
-- 
2.20.1

  reply	other threads:[~2019-03-18  5:20 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-18  5:20 [U-Boot] [PATCH 1/3] clk: renesas: Fix SDH clock divider decoding on Gen2 Marek Vasut
2019-03-18  5:20 ` Marek Vasut [this message]
2019-03-18  5:20 ` [U-Boot] [PATCH 3/3] clk: renesas: Add support for setting MMCIF clock divider " Marek Vasut

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