[Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc0

[Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc0

[Palmer Dabbelt]

The following changes since commit d4e65539e570d5872003710b5a1064489911d33d:

  Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into staging (2019-03-17 14:10:52 +0000)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0

for you to fetch changes up to f330433b3633647b047cfa418c2ca4d18fda69c7:

  target/riscv: Fix manually parsed 16 bit insn (2019-03-17 22:21:32 -0700)

----------------------------------------------------------------
A Single RISC-V Patch for 4.0-rc0

There was a regression introduced by the decodetree conversion that has
a fairly straight-forward fix.  Since this fixes bugs that everyone has
hit I'd like to target it for rc0.

----------------------------------------------------------------
Bastian Koppelmann (1):
      target/riscv: Fix manually parsed 16 bit insn

 target/riscv/insn_trans/trans_rvc.inc.c | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

[Qemu-riscv] [PULL] target/riscv: Fix manually parsed 16 bit insn

[Palmer Dabbelt]

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Tested-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 30 ++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index bcdf64d3b705..5819f53f900e 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -44,10 +44,19 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
 {
 #ifdef TARGET_RISCV32
     /* C.FLW ( RV32FC-only ) */
-    return false;
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    arg_c_lw tmp;
+    decode_insn16_extract_cl_w(&tmp, ctx->opcode);
+    arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+    return trans_flw(ctx, &arg);
 #else
     /* C.LD ( RV64C/RV128C-only ) */
-    return false;
+    arg_c_fld tmp;
+    decode_insn16_extract_cl_d(&tmp, ctx->opcode);
+    arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+    return trans_ld(ctx, &arg);
 #endif
 }
 
@@ -67,10 +76,19 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
 {
 #ifdef TARGET_RISCV32
     /* C.FSW ( RV32FC-only ) */
-    return false;
+    REQUIRE_FPU;
+    REQUIRE_EXT(ctx, RVF);
+
+    arg_c_sw tmp;
+    decode_insn16_extract_cs_w(&tmp, ctx->opcode);
+    arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+    return trans_fsw(ctx, &arg);
 #else
     /* C.SD ( RV64C/RV128C-only ) */
-    return false;
+    arg_c_fsd tmp;
+    decode_insn16_extract_cs_d(&tmp, ctx->opcode);
+    arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+    return trans_sd(ctx, &arg);
 #endif
 }
 
@@ -88,7 +106,9 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
 {
 #ifdef TARGET_RISCV32
     /* C.JAL */
-    arg_jal arg = { .rd = 1, .imm = a->imm };
+    arg_c_j tmp;
+    decode_insn16_extract_cj(&tmp, ctx->opcode);
+    arg_jal arg = { .rd = 1, .imm = tmp.imm };
     return trans_jal(ctx, &arg);
 #else
     /* C.ADDIW */
-- 
2.19.2

Re: [Qemu-riscv] [PULL] A Single RISC-V Patch for 4.0-rc0

[Peter Maydell]

On Mon, 18 Mar 2019 at 05:28, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> The following changes since commit d4e65539e570d5872003710b5a1064489911d33d:
>
>   Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190316' into staging (2019-03-17 14:10:52 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-4.0-rc0
>
> for you to fetch changes up to f330433b3633647b047cfa418c2ca4d18fda69c7:
>
>   target/riscv: Fix manually parsed 16 bit insn (2019-03-17 22:21:32 -0700)
>
> ----------------------------------------------------------------
> A Single RISC-V Patch for 4.0-rc0
>
> There was a regression introduced by the decodetree conversion that has
> a fairly straight-forward fix.  Since this fixes bugs that everyone has
> hit I'd like to target it for rc0.
>
> ----------------------------------------------------------------
> Bastian Koppelmann (1):
>       target/riscv: Fix manually parsed 16 bit insn
>
Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM