[igt-dev] [PATCH v12 0/7] new engine discovery interface

[igt-dev] [PATCH v12 0/7] new engine discovery interface

[Andi Shyti]

Hi,

In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].

This 12th version is very different from the prvious, the basic
idea and architecture have changed once again, check the
changelog for details.

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.

Andi

v11 --> v12
===========
RFC v11: [13]
This 12th version starts from a completely different thought.
Here's the main differences:

 - The list of engines is provided in an engine_data structure
   which contains an index (useful for looping through and for
   engine/context index mapping) instead of an array of engines.

 - The list of engines is generated every time the init function
   is called and nothing is allocated in heap memory.

 - The ioctl check is done already during the initialization part
   and if the new ioctls are not implemented, then the init
   function still stores only those present in the GPU.

 - The for_each loop is implemented by re-using the previous
   'for_each_engine_class_instance()' implemented by Tvrtko.

 - The gem_topology library offers few helper functions for
   checking the engine presence, checking the implementation of
   the ioctls and executing the buffer, in order to be completely
   unaware of the driver implementation.

Thanks Tvrtko for all your inputs.

v10 --> v11
===========
RFC v10: [12]
few cosmetic changes in v11 and minor architectural details.
Thanks Tvrtko.

- the 'query_engines()' functions are static as no one is using
  them yet.

- removed the 'gem_has_engine_topology()' function because it's
  very little used, 'get_active_engines()' can be used instead.

- a minor ring -> engine renaming coming from Chris. 

v9 --> v10
==========
RFC v9: [11]
also this time quite many changes, thanks Chris for the reviews,
here the most relevant of them.

- gem_query.[ch] have been renamed to gem_engine_topology.[ch]
  and all the functions ended up there as they are referring to
  the topology of the engines.

- the functions 'get_active_engines()',
  'gem_set_context_get_engines()' and
  'igt_require_gem_engine_list()' will be the main interface to
  the gem_engine_topology library, refer to patch 2 for details.

- the define 'for_each_engine2()' doesn't expose anymore the
  iterator.

- 'gem_context_has_engine()' has been moved from ioctl_wrappers.c
  to gem_context.c.

- the gem_exec_basic exec-ctx subtest does not abort if the new
  getparam/setparam and query apis are not implemented as it can
  work with both (as it was done at the beginning).

v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:

- all the allocation in gem_query have been made in stack, not
  anymore allocated dynamically.

- removed get/set_context as it was already implemented and I
  didn't know.

- renamed some functions and variables to hopefully more
  meaningful names.

V7 --> v8
=========
RFC v7: [9]

- all functions have been moved from lib/igt_gt.{c,h} and
  lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
  Chris)

- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
  be consistent with the '2' that indicates the new 'struct
  intel_execution_engine2' data structure.

V6 --> V7
=========
RFC v6: [8]

- a new patch has been added (patch 3) which adds a new
  requirement check through the igt_require_gem_engine_list()
  function. (thanks Chris) This function will initialize the
  engine list instead of the instead of igt_require_gem() as it
  was in v6

- all the ioctls have been wrapped (thanks Chris and Antonio) and
  new library functions have been added and assert the ioctls

- gem_init_engine_list() function returns the errno from the
  GETPARAM ioctl in order to be used as a requirement. (thanks
  Chris)

- fixed few requires/asserts

- The engine list "intel_active_engines2" is allocated of the
  number of engines instead of a political 64 (thanks Antonio).

- some parameter renaming in gem_has_ring_by_idx(). (thanks
  Chris).

- the original "intel_execution_engines2" has not been renamed,
  because it is used to create subtests before even executing any
  test/ioctl. By renaming it, some subtest generations failed.
  (thanks Petri)

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
  to figure otu whether the new interface has been implemented.
  This way the for_each_engine_ctx() is able to work with new and
  old kernel uapi (thanks Chris)

V4 --> V5
=========
RFC v4: [6]

- the engine list is now built in 'igt_require_gem()' instead of
  '__open_driver()' so that we keep this discovery method
  specific to the i915 driver (thanks Chris).

- All the query/setparam structures dynamic allocation based on
  the number of engines, now are politically allocated 64 times,
  to avoid extra ioctl calls that retrieve the engine number
  (thanks Chris)

- use igt_ioctl instead of ioctl (thanks Chris)

- allocate intel_execution_engines2 dynamically instead of
  statically (thanks Tvrtko)

- simplify the test in 'gem_exec_basic()' so that simply checks
  the presence of the engine instead of executing a buffer
  (thank Chris)

- a new patch has been added (patch 3) that extends the
  'gem_has_ring()' boolean function. The new version sets the
  index as it's mapped in the kernel.The previous function is now
  a wrapper to the new function.

V3 --> V4
=========
PATCH v3: [3]

- re-architectured the discovery mechanism based on Tvrtko's
  sugestion and reviews.. In this version the discovery is done
  during the device opening and stored in a NULL terminated
  array, which replaces the existing intel_execution_engines2
  that is mainly used as a reference.

V2 --> V3
=========
RFC v2: [2]

- removed a standalone gem_query_engines_demo test and added the
  exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).

- fixed most of Tvrtko's comments in [5], which consist in
  putting the mallocs igt_assert and ictls in igt_require and few
  refactoring (thanks Tvrtko).

V1 --> V2
=========
RFC v1: [1]

- added a demo test that simply queries the driver about the
  engines and executes a buffer (thanks Tvrtko)

- refactored the for_each_engine_ctx() macro so that what in the
  previous version was done by the "bind" function, now it's done
  in the first iteration. (Thanks Crhis)

- removed the "gem_has_ring_ctx()" because it was out of the
  scope.

- rename functions to more meaningful names

[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html
[11] https://lists.freedesktop.org/archives/igt-dev/2019-February/009277.html
[12] https://lists.freedesktop.org/archives/igt-dev/2019-March/010197.html
[13] https://lists.freedesktop.org/archives/igt-dev/2019-March/010467.html

Andi Shyti (7):
  lib/igt_gt: remove unnecessary argument
  lib: ioctl_wrappers: reach engines by index as well
  lib: move gem_context_has_engine from ioctl_wrappers to gem_context
  include/drm-uapi: import i915_drm.h header file
  lib/i915: add gem_engine_topology library
  lib/igt_gt: use for_each_engine_class_instance to loop through active
    engines
  tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

 include/drm-uapi/i915_drm.h    | 404 +++++++++++++++++++++++++++------
 lib/Makefile.sources           |   2 +
 lib/i915/gem_context.c         |  21 ++
 lib/i915/gem_context.h         |   2 +
 lib/i915/gem_engine_topology.c | 210 +++++++++++++++++
 lib/i915/gem_engine_topology.h |  52 +++++
 lib/igt_gt.h                   |  11 +-
 lib/ioctl_wrappers.c           |  19 --
 lib/ioctl_wrappers.h           |   3 +-
 lib/meson.build                |   1 +
 tests/i915/gem_exec_basic.c    |  15 ++
 tests/perf_pmu.c               |  25 +-
 12 files changed, 656 insertions(+), 109 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

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[igt-dev] [PATCH v12 1/7] lib/igt_gt: remove unnecessary argument

[Andi Shyti]

__for_each_engine_class_instance(fd, e) doesn't need and doesn't
use the fd argument. Remove it.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h     | 2 +-
 tests/perf_pmu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..475c0b3c3cc6 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(fd__, e__) \
+#define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
 #define for_each_engine_class_instance(fd__, e__) \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index aa5b99212ac5..45291298c021 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1693,7 +1693,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(fd, e) {
+	__for_each_engine_class_instance(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1897,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(render_fd, e) {
+		__for_each_engine_class_instance(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

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[igt-dev] [PATCH v12 2/7] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti]

With the new engine query method engines are reachable through
an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.

The previous 'gem_has_ring()' function becomes a wrapper to the new
'gem_context_has_engine()'.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/ioctl_wrappers.c | 4 +++-
 lib/ioctl_wrappers.h | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 39920f8707d2..a2597e282704 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,7 +1252,7 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
@@ -1268,6 +1268,8 @@ bool gem_has_ring(int fd, unsigned ring)
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
 	execbuf.flags = ring;
+	execbuf.rsvd1 = ctx;
+
 	return __gem_execbuf(fd, &execbuf) == -ENOENT;
 }
 
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f0be26080da6..935043617eb1 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,13 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(f, r) gem_context_has_engine(f, r, 0)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;
-- 
2.20.1

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[igt-dev] [PATCH v12 3/7] lib: move gem_context_has_engine from ioctl_wrappers to gem_context

[Andi Shyti]

Function 'gem_has_ring()' has been renamed to
'gem_context_has_engine()' which acts more on an engine in
context domain. Move it to the gem_context library where it is
more appropriate.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/i915/gem_context.c | 21 +++++++++++++++++++++
 lib/i915/gem_context.h |  2 ++
 lib/ioctl_wrappers.c   | 21 ---------------------
 lib/ioctl_wrappers.h   |  1 -
 4 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e920..5e2e31e91384 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
 {
 	igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
 }
+
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 exec;
+
+	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+		if (engine & (3 << 13) && !gem_has_bsd2(fd))
+			return false;
+	}
+
+	memset(&exec, 0, sizeof(exec));
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&exec);
+	execbuf.buffer_count = 1;
+	execbuf.flags = engine;
+	execbuf.rsvd1 = ctx;
+
+	return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..dd64ebf17fbd 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
 int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
 void gem_context_set_priority(int fd, uint32_t ctx, int prio);
 
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
+
 #endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a2597e282704..280fdd624529 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,27 +1252,6 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
-{
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 exec;
-
-	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
-	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
-		if (ring & (3 << 13) && !gem_has_bsd2(fd))
-			return false;
-	}
-
-	memset(&exec, 0, sizeof(exec));
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&exec);
-	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
-	execbuf.rsvd1 = ctx;
-
-	return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
 /**
  * gem_require_ring:
  * @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 935043617eb1..1ebad10f28b0 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,7 +142,6 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
-- 
2.20.1

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[igt-dev] [PATCH v12 4/7] include/drm-uapi: import i915_drm.h header file

[Andi Shyti]

This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 include/drm-uapi/i915_drm.h | 404 +++++++++++++++++++++++++++++-------
 1 file changed, 331 insertions(+), 73 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 43fb8ede2fe0..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -99,9 +119,14 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_VIDEO		= 2,
 	I915_ENGINE_CLASS_VIDEO_ENHANCE	= 3,
 
+	/* should be kept compact */
+
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -319,6 +344,9 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
+/* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -367,6 +395,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -377,6 +406,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -476,6 +507,7 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_ENABLED	(1ul << 0)
 #define   I915_SCHEDULER_CAP_PRIORITY	(1ul << 1)
 #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
+#define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 3)
 
 #define I915_PARAM_HUC_STATUS		 42
 
@@ -559,6 +591,14 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT	52
 
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+/* Must be kept compact -- no holes and well documented */
+
 typedef struct drm_i915_getparam {
 	__s32 param;
 	/*
@@ -574,6 +614,7 @@ typedef struct drm_i915_getparam {
 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 #define I915_SETPARAM_NUM_USED_FENCES                     4
+/* Must be kept compact -- no holes */
 
 typedef struct drm_i915_setparam {
 	int param;
@@ -972,7 +1013,7 @@ struct drm_i915_gem_execbuffer2 {
 	 * struct drm_i915_gem_exec_fence *fences.
 	 */
 	__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK              (7<<0)
+#define I915_EXEC_RING_MASK              (0x3f)
 #define I915_EXEC_DEFAULT                (0<<0)
 #define I915_EXEC_RENDER                 (1<<0)
 #define I915_EXEC_BSD                    (2<<0)
@@ -1078,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_ARRAY   (1<<19)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT		(1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1120,32 +1170,34 @@ struct drm_i915_gem_busy {
 	 * as busy may become idle before the ioctl is completed.
 	 *
 	 * Furthermore, if the object is busy, which engine is busy is only
-	 * provided as a guide. There are race conditions which prevent the
-	 * report of which engines are busy from being always accurate.
-	 * However, the converse is not true. If the object is idle, the
-	 * result of the ioctl, that all engines are idle, is accurate.
+	 * provided as a guide and only indirectly by reporting its class
+	 * (there may be more than one engine in each class). There are race
+	 * conditions which prevent the report of which engines are busy from
+	 * being always accurate.  However, the converse is not true. If the
+	 * object is idle, the result of the ioctl, that all engines are idle,
+	 * is accurate.
 	 *
 	 * The returned dword is split into two fields to indicate both
-	 * the engines on which the object is being read, and the
-	 * engine on which it is currently being written (if any).
+	 * the engine classess on which the object is being read, and the
+	 * engine class on which it is currently being written (if any).
 	 *
 	 * The low word (bits 0:15) indicate if the object is being written
 	 * to by any engine (there can only be one, as the GEM implicit
 	 * synchronisation rules force writes to be serialised). Only the
-	 * engine for the last write is reported.
+	 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
+	 * 1 not 0 etc) for the last write is reported.
 	 *
-	 * The high word (bits 16:31) are a bitmask of which engines are
-	 * currently reading from the object. Multiple engines may be
+	 * The high word (bits 16:31) are a bitmask of which engines classes
+	 * are currently reading from the object. Multiple engines may be
 	 * reading from the object simultaneously.
 	 *
-	 * The value of each engine is the same as specified in the
-	 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
-	 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
-	 * the I915_EXEC_RENDER engine for execution, and so it is never
+	 * The value of each engine class is the same as specified in the
+	 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+	 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
 	 * reported as active itself. Some hardware may have parallel
 	 * execution engines, e.g. multiple media engines, which are
-	 * mapped to the same identifier in the EXECBUFFER2 ioctl and
-	 * so are not separately reported for busyness.
+	 * mapped to the same class identifier and so are not separately
+	 * reported for busyness.
 	 *
 	 * Caveat emptor:
 	 * Only the boolean result of this query is reliable; that is whether
@@ -1412,65 +1464,18 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
-	__u32 pad;
-};
-
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
-	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE	(1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+	(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1511,6 +1516,43 @@ struct drm_i915_gem_context_param {
  * On creation, all new contexts are marked as recoverable.
  */
 #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retrieved and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0xa
+/* Must be kept compact -- no holes and well documented */
+
 	__u64 value;
 };
 
@@ -1543,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
 	__u16 engine_instance;
 
 	/*
-	 * Unused for now. Must be cleared to zero.
+	 * Unknown flags must be cleared to zero.
 	 */
 	__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
 
 	/*
 	 * Mask of slices to enable for the context. Valid values are a subset
@@ -1573,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz16; /* reserved for future use; must be zero */
+	__u32 flags; /* all undefined flags must be zero */
+
+	__u64 engines_mask; /* selection mask of engines[] */
+
+	__u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz;
+
+	__u16 master_class;
+	__u16 master_instance;
+
+	__u64 sibling_mask;
+	__u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+	__u64 extensions; \
+	struct { \
+		__u16 engine_class; \
+		__u16 engine_instance; \
+	} class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+	struct i915_user_extension base;
+	__u32 clone_id;
+	__u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS	(1u << 0)
+#define I915_CONTEXT_CLONE_SCHED	(1u << 1)
+#define I915_CONTEXT_CLONE_SSEU		(1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE	(1u << 3)
+#define I915_CONTEXT_CLONE_VM		(1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES	(1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+	__u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
@@ -1734,6 +1946,8 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
+/* Must be kept compact -- no holes and well documented */
 
 	/*
 	 * When set to zero by userspace, this is filled with the size of the
@@ -1831,6 +2045,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 engine_class;
+
+	/** Engine instance number. */
+	__u16 engine_instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

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[igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Andi Shyti]

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The library provides three helper functions:

1. gem_topology_has_engine(): checks if the engine is present by
   querying the driver in a way that the caller function wouldn't
   know if the above ioctls are implemented.

2. gem_set_eb_flags(): sets the execution buffer flag depending
   whether it refers to context-engine mapping or not.

3. gem_context_execbuf(): is a wrapper that executes the buffer
   in a way that the calling function doesn't know about the
   ioctls in the driver.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 210 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  52 ++++++++
 lib/meson.build                |   1 +
 4 files changed, 265 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..e836b3745e04
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = SIZEOF_QUERY;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void set_ctx_param_engines(struct intel_engine_data *ed)
+{
+	struct i915_context_param_engines *ctx_engine;
+	struct drm_i915_gem_context_param ctx_param;
+	uint8_t buff[SIZEOF_CTX_PARAM] = { };
+	int i;
+
+	ctx_engine = (struct i915_context_param_engines *) buff;
+
+	ctx_engine->extensions = 0;
+	for (i = 0; i < ed->nengines; i++) {
+		ctx_engine->class_instance[i].engine_class =
+							ed->engines[i].class;
+		ctx_engine->class_instance[i].engine_instance =
+							ed->engines[i].instance;
+	}
+
+	ctx_param.size   = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
+	ctx_param.value  = to_user_pointer(ctx_engine);
+	ctx_param.ctx_id = ed->ctx;
+	ctx_param.param  = I915_CONTEXT_PARAM_ENGINES;
+
+	gem_context_set_param(ed->fd, &ctx_param);
+}
+
+static void init_engine_list(struct intel_engine_data *ed)
+{
+	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
+	struct drm_i915_query_engine_info *query_engine;
+	unsigned char query_buffer[SIZEOF_QUERY] = { };
+	int i;
+
+	query_engine = (struct drm_i915_query_engine_info *) query_buffer;
+	query_engines(ed->fd, query_engine);
+
+	for (i = 0; i < query_engine->num_engines; i++) {
+		char *name;
+		__u16 class = query_engine->engines[i].engine_class;
+		__u16 instance = query_engine->engines[i].engine_instance;
+
+		ed->engines[i].class = class;
+		ed->engines[i].instance = instance;
+
+		/* if we don't recognise the class, then we mark it as "unk" */
+		if (class >= ARRAY_SIZE(class_names))
+			igt_assert(asprintf(&name, "unk-%d:%d",
+					    class, instance) > 0);
+		else
+			igt_assert(asprintf(&name, "%s%d",
+					    class_names[class], instance) > 0);
+
+		ed->engines[i].name = name;
+	}
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+		.ctx_id = ctx_id,
+	};
+	struct intel_engine_data engine_data = {
+		.n = 0,
+		.fd = fd,
+		.ctx = ctx_id,
+	};
+
+	if (__gem_context_get_param(fd, &ctx_param)) {
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_engine_class_instance(e2) {
+			if (!gem_has_engine(fd, e2->class, e2->instance))
+				continue;
+
+			engine_data.engines[engine_data.nengines].name =
+								e2->name;
+			engine_data.engines[engine_data.nengines].instance =
+								e2->instance;
+			engine_data.engines[engine_data.nengines].class =
+								e2->class;
+			engine_data.nengines++;
+		}
+
+		return engine_data;
+	}
+
+	init_engine_list(&engine_data);
+
+	if (ctx_param.size == sizeof(struct i915_context_param_engines))
+		set_ctx_param_engines(&engine_data);
+
+	return engine_data;
+}
+
+bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
+			     uint8_t i, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	if (!e)
+		return false;
+
+	if (__gem_context_get_param(fd, &ctx_param))
+		return gem_has_engine(fd, e->class, e->instance);
+
+	return gem_context_has_engine(fd, i, ctx);
+}
+
+void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
+		      struct intel_execution_engine2 e2,
+		      uint8_t engine, uint32_t ctx)
+{
+	struct drm_i915_gem_context_param ctx_param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	if (__gem_context_get_param(fd, &ctx_param)) {
+		eb->flags |= (I915_EXEC_RING_MASK & engine);
+		eb->rsvd1 = ctx;
+	} else {
+		eb->flags |= gem_class_instance_to_eb_flags(fd, e2.class,
+							    e2.instance);
+	}
+}
+
+int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			  struct intel_execution_engine2 e2,
+			  uint8_t engine, uint32_t ctx)
+{
+	gem_set_eb_flags(fd, eb, e2, engine, ctx);
+	return __gem_execbuf(fd, eb);
+}
+
+void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			 struct intel_execution_engine2 e2,
+			 uint8_t index_map, uint32_t ctx)
+{
+	igt_assert_eq(__gem_context_execbuf(fd, eb, e2, index_map, ctx), 0);
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..657b9397a181
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+
+struct intel_engine_data {
+	int fd;
+	uint32_t ctx;
+
+	uint32_t nengines;
+	uint32_t n;
+	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
+			     uint8_t i, uint32_t ctx);
+
+void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
+		      struct intel_execution_engine2 e2,
+		      uint8_t engine, uint32_t ctx);
+int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			  struct intel_execution_engine2 e2,
+			  uint8_t engine, uint32_t ctx);
+void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
+			 struct intel_execution_engine2 e2,
+			 uint8_t index_map, uint32_t ctx);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

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[igt-dev] [PATCH v12 6/7] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Andi Shyti]

Extend the 'for_each_engine_class_instance' so that it can loop
only through active engines.

The 'for_each_engine_class_instance()' define starts its loop
from generating a 'struct intel_engine_data' that contains only
the current engines and it loops through the list.

A new parameter is added which refers to the context, to which
engines ar bound.

Update tests/perf_pmu.c that uses the
'for_each_engine_class_instance()' loop.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h     |  9 ++++++---
 tests/perf_pmu.c | 21 +++++++++++----------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..22baabce7bb0 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -117,8 +117,11 @@ void gem_require_engine(int gem_fd,
 #define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+#include "i915/gem_engine_topology.h"
+
+#define for_each_engine_class_instance(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+		((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
+			i__.n++)
 
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 45291298c021..1b02192201e8 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_engine_class_instance(gem_fd, 0, e_) {
 		if (e == e_)
 			busy_idx = i;
 
@@ -473,15 +473,16 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 static void
 __submit_spin_batch(int gem_fd, igt_spin_t *spin,
 		    const struct intel_execution_engine2 *e,
-		    int offset)
+		    int offset,
+		    unsigned int i)
 {
 	struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
 
 	eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
-	eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
+	eb.flags |= I915_EXEC_NO_RELOC;
 	eb.batch_start_offset += offset;
 
-	gem_execbuf(gem_fd, &eb);
+	gem_context_execbuf(gem_fd, &eb, *e, i, 0);
 }
 
 static void
@@ -497,11 +498,11 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_engine_class_instance(gem_fd, 0, e_) {
 		if (e == e_)
 			idle_idx = i;
 		else if (spin)
-			__submit_spin_batch(gem_fd, spin, e_, 64);
+			__submit_spin_batch(gem_fd, spin, e_, 64, i + 1);
 		else
 			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
 
@@ -554,9 +555,9 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	for_each_engine_class_instance(gem_fd, 0, e) {
 		if (spin)
-			__submit_spin_batch(gem_fd, spin, e, 64);
+			__submit_spin_batch(gem_fd, spin, e, 64, i + 1);
 		else
 			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
 
@@ -1597,7 +1598,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 
 				/* Restart the spinbatch. */
 				__rearm_spin_batch(spin);
-				__submit_spin_batch(gem_fd, spin, e, 0);
+				__submit_spin_batch(gem_fd, spin, e, 0, 0);
 
 				/* PWM busy sleep. */
 				loop_busy = igt_nsec_elapsed(&start);
@@ -1683,7 +1684,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		for_each_engine_class_instance(fd, 0, e)
 			num_engines++;
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH v12 7/7] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

[Andi Shyti]

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with 'gem_topology_has_engine()'.

The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/i915/gem_exec_basic.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..0f437a1aef72 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,21 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-ctx") {
+		uint32_t ctx_id;
+		struct intel_execution_engine2 *e2;
+		uint8_t index_map = 0;
+
+		ctx_id = gem_context_create(fd);
+
+		for_each_engine_class_instance(fd, ctx_id, e2)
+			igt_assert(gem_topology_has_engine(fd, e2,
+							   ++index_map,
+							   ctx_id));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.20.1

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[igt-dev] ✗ Fi.CI.BAT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58154/
State : failure

== Summary ==

Applying: lib/igt_gt: remove unnecessary argument
Applying: lib: ioctl_wrappers: reach engines by index as well
Applying: lib: move gem_context_has_engine from ioctl_wrappers to gem_context
Applying: include/drm-uapi: import i915_drm.h header file
Using index info to reconstruct a base tree...
M	include/drm-uapi/i915_drm.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm-uapi/i915_drm.h
CONFLICT (content): Merge conflict in include/drm-uapi/i915_drm.h
Patch failed at 0004 include/drm-uapi: import i915_drm.h header file
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Chris Wilson]

Quoting Andi Shyti (2019-03-18 23:28:10)
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The library provides three helper functions:
> 
> 1. gem_topology_has_engine(): checks if the engine is present by
>    querying the driver in a way that the caller function wouldn't
>    know if the above ioctls are implemented.
> 
> 2. gem_set_eb_flags(): sets the execution buffer flag depending
>    whether it refers to context-engine mapping or not.
> 
> 3. gem_context_execbuf(): is a wrapper that executes the buffer
>    in a way that the calling function doesn't know about the
>    ioctls in the driver.

You are not going to get me to use gem_context_execbuf, or
gem_set_eb_flags(). I just want a function that returns the flags for a
given engine in this context, as 99% of the time I already expect to
have the right flags.
-Chris
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Re: [igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Andi Shyti]

> > 1. gem_topology_has_engine(): checks if the engine is present by
> >    querying the driver in a way that the caller function wouldn't
> >    know if the above ioctls are implemented.
> > 
> > 2. gem_set_eb_flags(): sets the execution buffer flag depending
> >    whether it refers to context-engine mapping or not.
> > 
> > 3. gem_context_execbuf(): is a wrapper that executes the buffer
> >    in a way that the calling function doesn't know about the
> >    ioctls in the driver.
> 
> You are not going to get me to use gem_context_execbuf, or
> gem_set_eb_flags(). I just want a function that returns the flags for a
> given engine in this context, as 99% of the time I already expect to
> have the right flags.

That's fine, I thought it might be cleaner to have wrappers
around that abstracts whatever is below. But anyway that's an
easy fix just make a gem_get_eb_flags instead of a
gem_set_eb_flags.

The thing that I like less is that the chain of calls starts
getting too long and hard to follow.

On the other hand, the amount of thngs to be done before calling
an execbuf would starts being too demanding (therefore hard to
follow).

I think this check should be done directly by execbuf, so that
the caller function would be completely agnostic. But this
requires quite some re-work around, which definitely goes far 
beyond the purpose of this patchset.

Andi
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Re: [igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Tvrtko Ursulin]

On 18/03/2019 23:28, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The library provides three helper functions:
> 
> 1. gem_topology_has_engine(): checks if the engine is present by
>     querying the driver in a way that the caller function wouldn't
>     know if the above ioctls are implemented.
> 
> 2. gem_set_eb_flags(): sets the execution buffer flag depending
>     whether it refers to context-engine mapping or not.
> 
> 3. gem_context_execbuf(): is a wrapper that executes the buffer
>     in a way that the calling function doesn't know about the
>     ioctls in the driver.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 210 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  52 ++++++++
>   lib/meson.build                |   1 +
>   4 files changed, 265 insertions(+)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..e836b3745e04
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,210 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = SIZEOF_QUERY;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void set_ctx_param_engines(struct intel_engine_data *ed)
> +{
> +	struct i915_context_param_engines *ctx_engine;
> +	struct drm_i915_gem_context_param ctx_param;
> +	uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +	int i;
> +
> +	ctx_engine = (struct i915_context_param_engines *) buff;

Tiny detail - you could move assignment to declaration of you reorder them.

> +
> +	ctx_engine->extensions = 0;

No need since cleared when declared.

> +	for (i = 0; i < ed->nengines; i++) {
> +		ctx_engine->class_instance[i].engine_class =
> +							ed->engines[i].class;
> +		ctx_engine->class_instance[i].engine_instance =
> +							ed->engines[i].instance;

Could make the assignments more readable by having a pointer p = 
&ctx_engine->class_instance[0] and p++ in the for loop.

> +	}
> +
> +	ctx_param.size   = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
> +	ctx_param.value  = to_user_pointer(ctx_engine);
> +	ctx_param.ctx_id = ed->ctx;
> +	ctx_param.param  = I915_CONTEXT_PARAM_ENGINES;
> +
> +	gem_context_set_param(ed->fd, &ctx_param);
> +}
> +
> +static void init_engine_list(struct intel_engine_data *ed)
> +{
> +	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> +	struct drm_i915_query_engine_info *query_engine;
> +	unsigned char query_buffer[SIZEOF_QUERY] = { };

You used uint8_t above. I don't mind which one as long as it is consistent.

> +	int i;
> +
> +	query_engine = (struct drm_i915_query_engine_info *) query_buffer;

Could also assign in the declaration.

> +	query_engines(ed->fd, query_engine);
> +
> +	for (i = 0; i < query_engine->num_engines; i++) {
> +		char *name;
> +		__u16 class = query_engine->engines[i].engine_class;
> +		__u16 instance = query_engine->engines[i].engine_instance;
> +
> +		ed->engines[i].class = class;
> +		ed->engines[i].instance = instance;
> +
> +		/* if we don't recognise the class, then we mark it as "unk" */
> +		if (class >= ARRAY_SIZE(class_names))
> +			igt_assert(asprintf(&name, "unk-%d:%d",
> +					    class, instance) > 0);
> +		else
> +			igt_assert(asprintf(&name, "%s%d",
> +					    class_names[class], instance) > 0);

Names leak per iterator I think. Bummer, apart from using a big static 
table of all possible names, and borrowing those pointers here, I don't 
have any better ideas at the moment. Might actually be okay.

> +
> +		ed->engines[i].name = name;
> +	}
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +	};
> +	struct intel_engine_data engine_data = {
> +		.n = 0,

No need.

> +		.fd = fd,
> +		.ctx = ctx_id,
> +	};
> +
> +	if (__gem_context_get_param(fd, &ctx_param)) {
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_engine_class_instance(e2) {
> +			if (!gem_has_engine(fd, e2->class, e2->instance))
> +				continue;
> +
> +			engine_data.engines[engine_data.nengines].name =
> +								e2->name;
> +			engine_data.engines[engine_data.nengines].instance =
> +								e2->instance;
> +			engine_data.engines[engine_data.nengines].class =
> +								e2->class;

Also could keep a pointer to engine_data.engines[<current>] for more 
readable assignments.

> +			engine_data.nengines++;
> +		}
> +
> +		return engine_data;
> +	}
> +
> +	init_engine_list(&engine_data);

As far as I can see you missed the use case where we want to iterate 
over engines already defined in the context engine map.

So I think if the above __gem_context_get_param succeeds with non-zero 
size returned, you need to build engine_data based on those engines.

> +
> +	if (ctx_param.size == sizeof(struct i915_context_param_engines))
> +		set_ctx_param_engines(&engine_data);
> +

So this would change to something like:

if (ret == 0 && ctx_param.size == 0)
	init_engine_list(&engine_data);
	set_map = true;
else if (ret == 0)
	init_engine_list_from_ctx_engine_map(&engine_data, ctx_param);
else
	init_engine_list_from_static_tables(..);
	set_map = true;

if (set_map)
	set_ctx_param(...);

> +	return engine_data;
> +}
> +
> +bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
> +			     uint8_t i, uint32_t ctx)
> +{

Why do we need this helper?

> +	struct drm_i915_gem_context_param ctx_param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +	};
> +
> +	if (!e)
> +		return false;
> +
> +	if (__gem_context_get_param(fd, &ctx_param))
> +		return gem_has_engine(fd, e->class, e->instance);
> +
> +	return gem_context_has_engine(fd, i, ctx);
> +}
> +
> +void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +		      struct intel_execution_engine2 e2,
> +		      uint8_t engine, uint32_t ctx)
> +{
> +	struct drm_i915_gem_context_param ctx_param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +	};
> +
> +	if (__gem_context_get_param(fd, &ctx_param)) {
> +		eb->flags |= (I915_EXEC_RING_MASK & engine);
> +		eb->rsvd1 = ctx;
> +	} else {
> +		eb->flags |= gem_class_instance_to_eb_flags(fd, e2.class,
> +							    e2.instance);
> +	}
> +}

Store flags in struct intel_execution_engine2 while building the list 
and then just eb->flags |= e2->eb_flags in tests?

> +
> +int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +			  struct intel_execution_engine2 e2,
> +			  uint8_t engine, uint32_t ctx)
> +{
> +	gem_set_eb_flags(fd, eb, e2, engine, ctx);
> +	return __gem_execbuf(fd, eb);
> +}
> +
> +void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +			 struct intel_execution_engine2 e2,
> +			 uint8_t index_map, uint32_t ctx)
> +{
> +	igt_assert_eq(__gem_context_execbuf(fd, eb, e2, index_map, ctx), 0);
> +}

Probably not want these two either.

> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..657b9397a181
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,52 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "igt_gt.h"
> +
> +struct intel_engine_data {
> +	int fd;
> +	uint32_t ctx;
> +
> +	uint32_t nengines;
> +	uint32_t n;

This is the current engine index? Could it come handy to also have a 
pointer to current engine in the iterator? Will see in later patches..

> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +bool gem_topology_has_engine(int fd, struct intel_execution_engine2 *e,
> +			     uint8_t i, uint32_t ctx);
> +
> +void gem_set_eb_flags(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +		      struct intel_execution_engine2 e2,
> +		      uint8_t engine, uint32_t ctx);
> +int __gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +			  struct intel_execution_engine2 e2,
> +			  uint8_t engine, uint32_t ctx);
> +void gem_context_execbuf(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +			 struct intel_execution_engine2 e2,
> +			 uint8_t index_map, uint32_t ctx);
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> 

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v12 6/7] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Tvrtko Ursulin]

On 18/03/2019 23:28, Andi Shyti wrote:
> Extend the 'for_each_engine_class_instance' so that it can loop
> only through active engines.
> 
> The 'for_each_engine_class_instance()' define starts its loop
> from generating a 'struct intel_engine_data' that contains only
> the current engines and it loops through the list.
> 
> A new parameter is added which refers to the context, to which
> engines ar bound.
> 
> Update tests/perf_pmu.c that uses the
> 'for_each_engine_class_instance()' loop.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/igt_gt.h     |  9 ++++++---
>   tests/perf_pmu.c | 21 +++++++++++----------
>   2 files changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..22baabce7bb0 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -117,8 +117,11 @@ void gem_require_engine(int gem_fd,
>   #define __for_each_engine_class_instance(e__) \
>   	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
>   
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> +#include "i915/gem_engine_topology.h"
> +
> +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +		((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> +			i__.n++)
>   
>   #endif /* IGT_GT_H */
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 45291298c021..1b02192201e8 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_engine_class_instance(gem_fd, 0, e_) {

How much churn it would be to drop for_each_engine_class_instance and 
convert the for_each_engine_physical macro to use the new scheme?

I am thinking about ending with two macros:

for_each_engine_physical(fd, e) // or not e, if it is in the iterator?

for_each_engine_context(fd, ctx, e) // when tests are using contexts

The former would just be:

#define for_each_engine_physical(fd) for_each_engine_context(fd, 0)

Chris your opinion?

Regards,

Tvrtko

>   		if (e == e_)
>   			busy_idx = i;
>   
> @@ -473,15 +473,16 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   static void
>   __submit_spin_batch(int gem_fd, igt_spin_t *spin,
>   		    const struct intel_execution_engine2 *e,
> -		    int offset)
> +		    int offset,
> +		    unsigned int i)
>   {
>   	struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
>   
>   	eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
> -	eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
> +	eb.flags |= I915_EXEC_NO_RELOC;
>   	eb.batch_start_offset += offset;
>   
> -	gem_execbuf(gem_fd, &eb);
> +	gem_context_execbuf(gem_fd, &eb, *e, i, 0);
>   }
>   
>   static void
> @@ -497,11 +498,11 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_engine_class_instance(gem_fd, 0, e_) {
>   		if (e == e_)
>   			idle_idx = i;
>   		else if (spin)
> -			__submit_spin_batch(gem_fd, spin, e_, 64);
> +			__submit_spin_batch(gem_fd, spin, e_, 64, i + 1);
>   		else
>   			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
>   
> @@ -554,9 +555,9 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	for_each_engine_class_instance(gem_fd, 0, e) {
>   		if (spin)
> -			__submit_spin_batch(gem_fd, spin, e, 64);
> +			__submit_spin_batch(gem_fd, spin, e, 64, i + 1);
>   		else
>   			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
>   
> @@ -1597,7 +1598,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   				/* Restart the spinbatch. */
>   				__rearm_spin_batch(spin);
> -				__submit_spin_batch(gem_fd, spin, e, 0);
> +				__submit_spin_batch(gem_fd, spin, e, 0, 0);
>   
>   				/* PWM busy sleep. */
>   				loop_busy = igt_nsec_elapsed(&start);
> @@ -1683,7 +1684,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		for_each_engine_class_instance(fd, 0, e)
>   			num_engines++;
>   	}
>   
> 
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Re: [igt-dev] [PATCH v12 6/7] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Andi Shyti]

Hi Tvrtko,

> > -	for_each_engine_class_instance(gem_fd, e_) {
> > +	for_each_engine_class_instance(gem_fd, 0, e_) {
> 
> How much churn it would be to drop for_each_engine_class_instance and
> convert the for_each_engine_physical macro to use the new scheme?
> 
> I am thinking about ending with two macros:
> 
> for_each_engine_physical(fd, e) // or not e, if it is in the iterator?
> 
> for_each_engine_context(fd, ctx, e) // when tests are using contexts
> 
> The former would just be:
> 
> #define for_each_engine_physical(fd) for_each_engine_context(fd, 0)
> 
> Chris your opinion?

We've been discussing this, this is what I suggested offline :)

Maybe I wasn't clear then :)

But yes, I definitely agree.

Andi
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Re: [igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Andi Shyti]

Hi Tvrtko,

I agree with everything... few comments.

> > +	if (__gem_context_get_param(fd, &ctx_param)) {
> > +		const struct intel_execution_engine2 *e2;
> > +
> > +		igt_debug("using pre-allocated engine list\n");
> > +
> > +		__for_each_engine_class_instance(e2) {
> > +			if (!gem_has_engine(fd, e2->class, e2->instance))
> > +				continue;
> > +
> > +			engine_data.engines[engine_data.nengines].name =
> > +								e2->name;
> > +			engine_data.engines[engine_data.nengines].instance =
> > +								e2->instance;
> > +			engine_data.engines[engine_data.nengines].class =
> > +								e2->class;
> 
> Also could keep a pointer to engine_data.engines[<current>] for more
> readable assignments.
> 
> > +			engine_data.nengines++;
> > +		}
> > +
> > +		return engine_data;
> > +	}
> > +
> > +	init_engine_list(&engine_data);
> 
> As far as I can see you missed the use case where we want to iterate over
> engines already defined in the context engine map.
> 
> So I think if the above __gem_context_get_param succeeds with non-zero size
> returned, you need to build engine_data based on those engines.

Don't I get the engine list anyway? Do you man that
DRM_I915_QUERY_ENGINE_INFO might have a different list from
I915_CONTEXT_PARAM_ENGINES?

> > +	if (__gem_context_get_param(fd, &ctx_param)) {
> > +		eb->flags |= (I915_EXEC_RING_MASK & engine);
> > +		eb->rsvd1 = ctx;
> > +	} else {
> > +		eb->flags |= gem_class_instance_to_eb_flags(fd, e2.class,
> > +							    e2.instance);
> > +	}
> > +}
> 
> Store flags in struct intel_execution_engine2 while building the list and
> then just eb->flags |= e2->eb_flags in tests?

You are recommending to extend the 'intel_execution_engine2' (that
would make my life so very easy), I've been asked not to touch
that structure.

Then, I will add the flags value in the 'intel_execution_engine2'
definition.

> > +struct intel_engine_data {
> > +	int fd;
> > +	uint32_t ctx;
> > +
> > +	uint32_t nengines;
> > +	uint32_t n;
> 
> This is the current engine index? Could it come handy to also have a pointer
> to current engine in the iterator? Will see in later patches..

Actually not, in earlier version I had the pointer, but never
used, so that I removed it.

> Regards,

Thanks a lot,
Andi

> Tvrtko
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Re: [igt-dev] [PATCH v12 5/7] lib/i915: add gem_engine_topology library

[Tvrtko Ursulin]

On 19/03/2019 10:44, Andi Shyti wrote:
> Hi Tvrtko,
> 
> I agree with everything... few comments.
> 
>>> +	if (__gem_context_get_param(fd, &ctx_param)) {
>>> +		const struct intel_execution_engine2 *e2;
>>> +
>>> +		igt_debug("using pre-allocated engine list\n");
>>> +
>>> +		__for_each_engine_class_instance(e2) {
>>> +			if (!gem_has_engine(fd, e2->class, e2->instance))
>>> +				continue;
>>> +
>>> +			engine_data.engines[engine_data.nengines].name =
>>> +								e2->name;
>>> +			engine_data.engines[engine_data.nengines].instance =
>>> +								e2->instance;
>>> +			engine_data.engines[engine_data.nengines].class =
>>> +								e2->class;
>>
>> Also could keep a pointer to engine_data.engines[<current>] for more
>> readable assignments.
>>
>>> +			engine_data.nengines++;
>>> +		}
>>> +
>>> +		return engine_data;
>>> +	}
>>> +
>>> +	init_engine_list(&engine_data);
>>
>> As far as I can see you missed the use case where we want to iterate over
>> engines already defined in the context engine map.
>>
>> So I think if the above __gem_context_get_param succeeds with non-zero size
>> returned, you need to build engine_data based on those engines.
> 
> Don't I get the engine list anyway? Do you man that
> DRM_I915_QUERY_ENGINE_INFO might have a different list from
> I915_CONTEXT_PARAM_ENGINES?

Yes, context may be configured to a subset of physical engines. That's 
Chris' use case of preparing his own context and then being able to 
iterate over it.

>>> +	if (__gem_context_get_param(fd, &ctx_param)) {
>>> +		eb->flags |= (I915_EXEC_RING_MASK & engine);
>>> +		eb->rsvd1 = ctx;
>>> +	} else {
>>> +		eb->flags |= gem_class_instance_to_eb_flags(fd, e2.class,
>>> +							    e2.instance);
>>> +	}
>>> +}
>>
>> Store flags in struct intel_execution_engine2 while building the list and
>> then just eb->flags |= e2->eb_flags in tests?
> 
> You are recommending to extend the 'intel_execution_engine2' (that
> would make my life so very easy), I've been asked not to touch
> that structure.
> 
> Then, I will add the flags value in the 'intel_execution_engine2'
> definition.

If you have explicit ask from Chris on how to do it, then follow his 
idea. That's usually the quickest way upstream. :)

> 
>>> +struct intel_engine_data {
>>> +	int fd;
>>> +	uint32_t ctx;
>>> +
>>> +	uint32_t nengines;
>>> +	uint32_t n;
>>
>> This is the current engine index? Could it come handy to also have a pointer
>> to current engine in the iterator? Will see in later patches..
> 
> Actually not, in earlier version I had the pointer, but never
> used, so that I removed it.

I guess it depends on whether pointer to current engine is a parameter 
in the for loop iterator and tests have to declare it, or we allow tests 
to not bother and use the implicit iterator object to access it.

For me it is 50-50 which way we go.

Regards,

Tvrtko
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[igt-dev] ✗ Fi.CI.BAT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/59185/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5889 -> IGTPW_2817
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2817 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2817, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/59185/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2817:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_wait@basic-busy-all:
    - fi-blb-e6850:       PASS -> FAIL +1
    - fi-bwr-2160:        PASS -> FAIL +1
    - fi-pnv-d510:        PASS -> FAIL +1

  * igt@gem_wait@basic-wait-all:
    - fi-gdg-551:         PASS -> FAIL +1

  
Known issues
------------

  Here are the changes found in IGTPW_2817 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-icl-y:           PASS -> FAIL [fdo#103375]

  * igt@i915_selftest@live_contexts:
    - fi-bdw-gvtdvm:      PASS -> DMESG-FAIL [fdo#110235 ]

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - fi-glk-dsi:         PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          PASS -> FAIL [fdo#103167]

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS +1

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 
  [fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (49 -> 41)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (9): fi-kbl-7567u fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-ivb-3770 fi-bdw-samus fi-skl-6600u 


Build changes
-------------

    * IGT: IGT_4932 -> IGTPW_2817

  CI_DRM_5889: 7cb7ad99a4f507f6025706637baae5fd16e491eb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2817: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2817/
  IGT_4932: 08cf63a8fac11e3594b57580331fb319241a0d69 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2817/
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[igt-dev] ✗ Fi.CI.BAT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/56638/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5599 -> IGTPW_2401
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2401 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2401, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56638/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2401:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7567u:       PASS -> FAIL +2

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_reloc@basic-write-gtt:
    - {fi-icl-y}:         NOTRUN -> INCOMPLETE

  
Known issues
------------

  Here are the changes found in IGTPW_2401 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]

  * igt@gem_exec_suspend@basic-s3:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602] +1

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7500u:       NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-skl-6700hq:      PASS -> DMESG-WARN [fdo#105998]

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-kbl-7567u:       PASS -> DMESG-FAIL [fdo#105079]

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#108529]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] -> PASS

  * igt@i915_selftest@live_workarounds:
    - {fi-icl-u3}:        INCOMPLETE [fdo#109626] -> PASS
    - {fi-icl-u2}:        INCOMPLETE [fdo#109626] -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       DMESG-FAIL [fdo#109627] -> PASS

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS +2

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105998]: https://bugs.freedesktop.org/show_bug.cgi?id=105998
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109226]: https://bugs.freedesktop.org/show_bug.cgi?id=109226
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109527]: https://bugs.freedesktop.org/show_bug.cgi?id=109527
  [fdo#109626]: https://bugs.freedesktop.org/show_bug.cgi?id=109626
  [fdo#109627]: https://bugs.freedesktop.org/show_bug.cgi?id=109627


Participating hosts (43 -> 44)
------------------------------

  Additional (7): fi-skl-6260u fi-whl-u fi-ivb-3770 fi-icl-y fi-kbl-7560u fi-bsw-kefka fi-snb-2600 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4824 -> IGTPW_2401

  CI_DRM_5599: 39119c9b385742d49446c25d6902864a60eda6b6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2401: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2401/
  IGT_4824: e55d439a9ba744227fb4c9d727338276b78871d4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@exec-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2401/
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igt-dev mailing list
igt-dev@lists.freedesktop.org
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