[igt-dev] [PATCH v13 0/9] new engine discovery interface

[igt-dev] [PATCH v13 0/9] new engine discovery interface

[Andi Shyti]

Hi,

In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.

Andi

v12 --> v13
===========
RFC v12: [14]
This patch is also very different from the previous other than
some reorganization of the code these are the main changes:

 - the previous version lacked the case when the context had its
   engines mapped. checks in the following order

	if the driver doesn't have the new API
		-> get the engines from the static list
	if the driver has the API but the context has nothing mapped
		-> get the engines from "query" and map them
	if the driver has the API and the context has engines mapped
		-> get the engines from the context

 - the helper functions have been removed as they were of no use.

v11 --> v12
===========
RFC v11: [13]
This 12th version starts from a completely different thought.
Here's the main differences:

 - The list of engines is provided in an engine_data structure
   which contains an index (useful for looping through and for
   engine/context index mapping) instead of an array of engines.

 - The list of engines is generated every time the init function
   is called and nothing is allocated in heap memory.

 - The ioctl check is done already during the initialization part
   and if the new ioctls are not implemented, then the init
   function still stores only those present in the GPU.

 - The for_each loop is implemented by re-using the previous
   'for_each_engine_class_instance()' implemented by Tvrtko.

 - The gem_topology library offers few helper functions for
   checking the engine presence, checking the implementation of
   the ioctls and executing the buffer, in order to be completely
   unaware of the driver implementation.

Thanks Tvrtko for all your inputs.

v10 --> v11
===========
RFC v10: [12]
few cosmetic changes in v11 and minor architectural details.
Thanks Tvrtko.

- the 'query_engines()' functions are static as no one is using
  them yet.

- removed the 'gem_has_engine_topology()' function because it's
  very little used, 'get_active_engines()' can be used instead.

- a minor ring -> engine renaming coming from Chris. 

v9 --> v10
==========
RFC v9: [11]
also this time quite many changes, thanks Chris for the reviews,
here the most relevant of them.

- gem_query.[ch] have been renamed to gem_engine_topology.[ch]
  and all the functions ended up there as they are referring to
  the topology of the engines.

- the functions 'get_active_engines()',
  'gem_set_context_get_engines()' and
  'igt_require_gem_engine_list()' will be the main interface to
  the gem_engine_topology library, refer to patch 2 for details.

- the define 'for_each_engine2()' doesn't expose anymore the
  iterator.

- 'gem_context_has_engine()' has been moved from ioctl_wrappers.c
  to gem_context.c.

- the gem_exec_basic exec-ctx subtest does not abort if the new
  getparam/setparam and query apis are not implemented as it can
  work with both (as it was done at the beginning).

v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:

- all the allocation in gem_query have been made in stack, not
  anymore allocated dynamically.

- removed get/set_context as it was already implemented and I
  didn't know.

- renamed some functions and variables to hopefully more
  meaningful names.

V7 --> v8
=========
RFC v7: [9]

- all functions have been moved from lib/igt_gt.{c,h} and
  lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
  Chris)

- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
  be consistent with the '2' that indicates the new 'struct
  intel_execution_engine2' data structure.

V6 --> V7
=========
RFC v6: [8]

- a new patch has been added (patch 3) which adds a new
  requirement check through the igt_require_gem_engine_list()
  function. (thanks Chris) This function will initialize the
  engine list instead of the instead of igt_require_gem() as it
  was in v6

- all the ioctls have been wrapped (thanks Chris and Antonio) and
  new library functions have been added and assert the ioctls

- gem_init_engine_list() function returns the errno from the
  GETPARAM ioctl in order to be used as a requirement. (thanks
  Chris)

- fixed few requires/asserts

- The engine list "intel_active_engines2" is allocated of the
  number of engines instead of a political 64 (thanks Antonio).

- some parameter renaming in gem_has_ring_by_idx(). (thanks
  Chris).

- the original "intel_execution_engines2" has not been renamed,
  because it is used to create subtests before even executing any
  test/ioctl. By renaming it, some subtest generations failed.
  (thanks Petri)

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
  to figure otu whether the new interface has been implemented.
  This way the for_each_engine_ctx() is able to work with new and
  old kernel uapi (thanks Chris)

V4 --> V5
=========
RFC v4: [6]

- the engine list is now built in 'igt_require_gem()' instead of
  '__open_driver()' so that we keep this discovery method
  specific to the i915 driver (thanks Chris).

- All the query/setparam structures dynamic allocation based on
  the number of engines, now are politically allocated 64 times,
  to avoid extra ioctl calls that retrieve the engine number
  (thanks Chris)

- use igt_ioctl instead of ioctl (thanks Chris)

- allocate intel_execution_engines2 dynamically instead of
  statically (thanks Tvrtko)

- simplify the test in 'gem_exec_basic()' so that simply checks
  the presence of the engine instead of executing a buffer
  (thank Chris)

- a new patch has been added (patch 3) that extends the
  'gem_has_ring()' boolean function. The new version sets the
  index as it's mapped in the kernel.The previous function is now
  a wrapper to the new function.

V3 --> V4
=========
PATCH v3: [3]

- re-architectured the discovery mechanism based on Tvrtko's
  sugestion and reviews.. In this version the discovery is done
  during the device opening and stored in a NULL terminated
  array, which replaces the existing intel_execution_engines2
  that is mainly used as a reference.

V2 --> V3
=========
RFC v2: [2]

- removed a standalone gem_query_engines_demo test and added the
  exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).

- fixed most of Tvrtko's comments in [5], which consist in
  putting the mallocs igt_assert and ictls in igt_require and few
  refactoring (thanks Tvrtko).

V1 --> V2
=========
RFC v1: [1]

- added a demo test that simply queries the driver about the
  engines and executes a buffer (thanks Tvrtko)

- refactored the for_each_engine_ctx() macro so that what in the
  previous version was done by the "bind" function, now it's done
  in the first iteration. (Thanks Crhis)

- removed the "gem_has_ring_ctx()" because it was out of the
  scope.

- rename functions to more meaningful names

[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html
[11] https://lists.freedesktop.org/archives/igt-dev/2019-February/009277.html
[12] https://lists.freedesktop.org/archives/igt-dev/2019-March/010197.html
[13] https://lists.freedesktop.org/archives/igt-dev/2019-March/010467.html
[14] https://lists.freedesktop.org/archives/igt-dev/2019-March/010776.html

Andi Shyti (9):
  lib/igt_gt: remove unnecessary argument
  lib: ioctl_wrappers: reach engines by index as well
  lib: move gem_context_has_engine from ioctl_wrappers to gem_context
  include/drm-uapi: import i915_drm.h header file
  lib: igt_gt: use flags in intel_execution_engines2
  lib/i915: add gem_engine_topology library
  lib/igt_gt: use for_each_engine_class_instance to loop through active
    engines
  tests: perf_pmu: use the flag value embedded in
    intel_execution_engines2
  tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

 include/drm-uapi/i915_drm.h    | 361 +++++++++++++++++++++++++++------
 lib/Makefile.sources           |   2 +
 lib/i915/gem_context.c         |  21 ++
 lib/i915/gem_context.h         |   2 +
 lib/i915/gem_engine_topology.c | 192 ++++++++++++++++++
 lib/i915/gem_engine_topology.h |  41 ++++
 lib/igt_gt.h                   |  14 +-
 lib/ioctl_wrappers.c           |  19 --
 lib/ioctl_wrappers.h           |   3 +-
 lib/meson.build                |   1 +
 tests/i915/gem_exec_basic.c    |  13 ++
 tests/perf_pmu.c               |  45 ++--
 12 files changed, 608 insertions(+), 106 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

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[igt-dev] [PATCH v13 1/9] lib/igt_gt: remove unnecessary argument

[Andi Shyti]

__for_each_engine_class_instance(fd, e) doesn't need and doesn't
use the fd argument. Remove it.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h     | 2 +-
 tests/perf_pmu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..475c0b3c3cc6 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(fd__, e__) \
+#define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
 #define for_each_engine_class_instance(fd__, e__) \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index aa5b99212ac5..45291298c021 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1693,7 +1693,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(fd, e) {
+	__for_each_engine_class_instance(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1897,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(render_fd, e) {
+		__for_each_engine_class_instance(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

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[igt-dev] [PATCH v13 2/9] lib: ioctl_wrappers: reach engines by index as well

[Andi Shyti]

With the new engine query method engines are reachable through
an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.

The previous 'gem_has_ring()' function becomes a wrapper to the new
'gem_context_has_engine()'.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/ioctl_wrappers.c | 4 +++-
 lib/ioctl_wrappers.h | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 39920f8707d2..a2597e282704 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,7 +1252,7 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
@@ -1268,6 +1268,8 @@ bool gem_has_ring(int fd, unsigned ring)
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
 	execbuf.flags = ring;
+	execbuf.rsvd1 = ctx;
+
 	return __gem_execbuf(fd, &execbuf) == -ENOENT;
 }
 
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f0be26080da6..935043617eb1 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,13 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
+bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(f, r) gem_context_has_engine(f, r, 0)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;
-- 
2.20.1

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[igt-dev] [PATCH v13 3/9] lib: move gem_context_has_engine from ioctl_wrappers to gem_context

[Andi Shyti]

Function 'gem_has_ring()' has been renamed to
'gem_context_has_engine()' which acts more on an engine in
context domain. Move it to the gem_context library where it is
more appropriate.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/i915/gem_context.c | 21 +++++++++++++++++++++
 lib/i915/gem_context.h |  2 ++
 lib/ioctl_wrappers.c   | 21 ---------------------
 lib/ioctl_wrappers.h   |  1 -
 4 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e920..5e2e31e91384 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
 {
 	igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
 }
+
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 exec;
+
+	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+		if (engine & (3 << 13) && !gem_has_bsd2(fd))
+			return false;
+	}
+
+	memset(&exec, 0, sizeof(exec));
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&exec);
+	execbuf.buffer_count = 1;
+	execbuf.flags = engine;
+	execbuf.rsvd1 = ctx;
+
+	return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..dd64ebf17fbd 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
 int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
 void gem_context_set_priority(int fd, uint32_t ctx, int prio);
 
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
+
 #endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a2597e282704..280fdd624529 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1252,27 +1252,6 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)
-{
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 exec;
-
-	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
-	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
-		if (ring & (3 << 13) && !gem_has_bsd2(fd))
-			return false;
-	}
-
-	memset(&exec, 0, sizeof(exec));
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&exec);
-	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
-	execbuf.rsvd1 = ctx;
-
-	return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
 /**
  * gem_require_ring:
  * @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 935043617eb1..1ebad10f28b0 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,7 +142,6 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
-- 
2.20.1

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[igt-dev] [PATCH v13 4/9] include/drm-uapi: import i915_drm.h header file

[Andi Shyti]

This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 include/drm-uapi/i915_drm.h | 361 ++++++++++++++++++++++++++++++------
 1 file changed, 304 insertions(+), 57 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 4ae1c6ff6ae6..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -104,6 +124,9 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -321,6 +344,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
 /* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -370,6 +395,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -380,6 +406,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -563,6 +591,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT	52
 
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -1085,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_ARRAY   (1<<19)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT		(1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1421,65 +1464,18 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
-	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE	(1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+	(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1520,7 +1516,43 @@ struct drm_i915_gem_context_param {
  * On creation, all new contexts are marked as recoverable.
  */
 #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retrieved and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0xa
 /* Must be kept compact -- no holes and well documented */
+
 	__u64 value;
 };
 
@@ -1553,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
 	__u16 engine_instance;
 
 	/*
-	 * Unused for now. Must be cleared to zero.
+	 * Unknown flags must be cleared to zero.
 	 */
 	__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
 
 	/*
 	 * Mask of slices to enable for the context. Valid values are a subset
@@ -1583,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz16; /* reserved for future use; must be zero */
+	__u32 flags; /* all undefined flags must be zero */
+
+	__u64 engines_mask; /* selection mask of engines[] */
+
+	__u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz;
+
+	__u16 master_class;
+	__u16 master_instance;
+
+	__u64 sibling_mask;
+	__u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+	__u64 extensions; \
+	struct { \
+		__u16 engine_class; \
+		__u16 engine_instance; \
+	} class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+	struct i915_user_extension base;
+	__u32 clone_id;
+	__u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS	(1u << 0)
+#define I915_CONTEXT_CLONE_SCHED	(1u << 1)
+#define I915_CONTEXT_CLONE_SSEU		(1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE	(1u << 3)
+#define I915_CONTEXT_CLONE_VM		(1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES	(1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+	__u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
@@ -1744,6 +1946,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -1842,6 +2045,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 engine_class;
+
+	/** Engine instance number. */
+	__u16 engine_instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

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[igt-dev] [PATCH v13 5/9] lib: igt_gt: use flags in intel_execution_engines2

[Andi Shyti]

Having a variable flags declared in the
'intel_execution_engines2' structure comes very handy when
handling engines that are configurable in different ways.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..9f28af8cfb5c 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
+	uint64_t flags;
 } intel_execution_engines2[];
 
 unsigned int
-- 
2.20.1

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[igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 192 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  41 +++++++
 lib/meson.build                |   1 +
 4 files changed, 236 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..4ddd9ca98b49
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = SIZEOF_QUERY;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void map_engine_context(struct intel_engine_data *ed,
+			       struct drm_i915_gem_context_param *ctx_param)
+{
+	struct i915_context_param_engines *ctx_engine =
+			(struct i915_context_param_engines*) ctx_param->value;
+	int i = 0;
+
+	for (typeof(ctx_engine->class_instance[0]) *p =
+					&ctx_engine->class_instance[0];
+						i < ed->nengines; i++, p++) {
+		p->engine_class = ed->engines[i].class;
+		p->engine_instance = ed->engines[i].instance;
+	}
+
+	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
+
+	gem_context_set_param(ed->fd, ctx_param);
+}
+
+static void dup_engine(struct intel_execution_engine2 *e2, const char *name,
+		       uint16_t class, uint16_t instance, uint8_t flags)
+{
+	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
+	char *__name;
+
+	/* if we don't recognise the class, then we mark it as "unk" */
+	if (name) {
+		e2->name = name;
+	} else {
+		if (class >= ARRAY_SIZE(class_names))
+			igt_assert(asprintf(&__name, "unk-%d:%d",
+					    class, instance) > 0);
+		else
+			igt_assert(asprintf(&__name, "%s%d",
+					    class_names[class], instance) > 0);
+
+		e2->name = __name;
+	}
+
+	e2->class    = class;
+	e2->instance = instance;
+	e2->flags    = flags;
+
+}
+
+static void query_engine_list(struct intel_engine_data *ed)
+{
+	uint8_t query_buffer[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine =
+			(struct drm_i915_query_engine_info *) query_buffer;
+	int i;
+
+	query_engines(ed->fd, query_engine);
+
+	for (i = 0; i < query_engine->num_engines; i++)
+		dup_engine(&ed->engines[i], NULL,
+			   query_engine->engines[i].engine_class,
+			   query_engine->engines[i].engine_instance, i + 1);
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	struct intel_engine_data engine_data = {
+		.fd = fd,
+		.ctx = ctx_id,
+	};
+	uint8_t buff[SIZEOF_CTX_PARAM] = { };
+	struct i915_context_param_engines *cengine =
+				(struct i915_context_param_engines *) buff;
+	struct drm_i915_gem_context_param cparam = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+		.ctx_id = ctx_id,
+		.size = SIZEOF_CTX_PARAM,
+		.value = to_user_pointer(cengine),
+	};
+	int ret, i;
+
+	cparam.value = to_user_pointer(cengine);
+
+	ret = __gem_context_get_param(fd, &cparam);
+
+	if (ret) {
+		/* if kernel does not support engine/context mapping */
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_engine_class_instance(e2) {
+			uint64_t flags;
+
+			if (!gem_has_engine(fd, e2->class, e2->instance))
+				continue;
+
+			flags = gem_class_instance_to_eb_flags(fd, e2->class,
+							       e2->instance);
+
+			dup_engine(&engine_data.engines[engine_data.nengines],
+				   e2->name, e2->class, e2->instance, flags);
+
+			engine_data.nengines++;
+		}
+
+	} else if (cparam.size == sizeof(struct i915_context_param_engines)) {
+		/* else if context doesn't have mapped engines */
+		query_engine_list(&engine_data);
+		map_engine_context(&engine_data, &cparam);
+
+	} else {
+		/* context has a list of mapped engines */
+
+		uint8_t nengines = (cparam.size -
+				sizeof(struct i915_context_param_engines)) /
+				sizeof(cengine->class_instance[0]);
+
+		for (i = 0; i < nengines - 1; i++)
+			dup_engine(&engine_data.engines[i], NULL,
+				   cengine->class_instance[i].engine_class,
+				   cengine->class_instance[i].engine_instance,
+				   i + 1);
+
+		engine_data.nengines = i;
+	}
+
+	return engine_data;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..544621683e15
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "i915_drm.h"
+#include "igt_gt.h"
+
+struct intel_engine_data {
+	int fd;
+	uint32_t ctx;
+
+	uint32_t nengines;
+	uint32_t n;
+	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

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[igt-dev] [PATCH v13 7/9] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Andi Shyti]

Extend the 'for_each_engine_class_instance' so that it can loop
only through active engines.

The 'for_each_engine_class_instance()' define starts its loop
from generating a 'struct intel_engine_data' that contains only
the current engines and it loops through the list.

A new parameter is added which refers to the context, to which
engines ar bound.

For back compatibility the previous version of the loop
definition has been renamed to 'for_each_engine_physical', which
uses the default context 0.

Update tests/perf_pmu.c that uses the
'for_each_engine_physical()' loop.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.h     | 11 ++++++++---
 tests/perf_pmu.c |  8 ++++----
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 9f28af8cfb5c..691cbb11ee0a 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -118,8 +118,13 @@ void gem_require_engine(int gem_fd,
 #define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+#include "i915/gem_engine_topology.h"
+
+#define for_each_engine_class_instance(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+		((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
+			i__.n++)
+
+#define for_each_engine_physical(f, e) for_each_engine_class_instance(f, 0, e)
 
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 45291298c021..79adeb2c8f3f 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_engine_physical(gem_fd, e_) {
 		if (e == e_)
 			busy_idx = i;
 
@@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
+	for_each_engine_physical(gem_fd, e_) {
 		if (e == e_)
 			idle_idx = i;
 		else if (spin)
@@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	for_each_engine_physical(gem_fd, e) {
 		if (spin)
 			__submit_spin_batch(gem_fd, spin, e, 64);
 		else
@@ -1683,7 +1683,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		for_each_engine_physical(fd, e)
 			num_engines++;
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH v13 8/9] tests: perf_pmu: use the flag value embedded in intel_execution_engines2

[Andi Shyti]

Now we have flags in the 'intel_execution_engines2' and it's set
by the for_each iterator. Use it!

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/perf_pmu.c | 33 ++++++++++++++-------------------
 1 file changed, 14 insertions(+), 19 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 79adeb2c8f3f..a6558bda9d7b 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -158,11 +158,6 @@ static unsigned int measured_usleep(unsigned int usec)
 	return igt_nsec_elapsed(&ts);
 }
 
-static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
-{
-	return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
-}
-
 #define TEST_BUSY (1)
 #define FLAG_SYNC (2)
 #define TEST_TRAILING_IDLE (4)
@@ -267,7 +262,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e->flags);
 	else
 		spin = NULL;
 
@@ -316,7 +311,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	sleep(2);
 
-	spin = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = __spin_sync(gem_fd, 0, e->flags);
 
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
@@ -359,11 +354,11 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 * re-submission in execlists mode. Make sure busyness is correctly
 	 * reported with the engine busy, and after the engine went idle.
 	 */
-	spin[0] = __spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin[0] = __spin_sync(gem_fd, 0, e->flags);
 	usleep(500e3);
 	spin[1] = __igt_spin_batch_new(gem_fd,
 				       .ctx = ctx,
-				       .engine = e2ring(gem_fd, e));
+				       .engine = e->flags);
 
 	/*
 	 * Open PMU as fast as possible after the second spin batch in attempt
@@ -445,7 +440,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	igt_assert_eq(i, num_engines);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e->flags);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
 	if (flags & TEST_TRAILING_IDLE)
@@ -478,7 +473,7 @@ __submit_spin_batch(int gem_fd, igt_spin_t *spin,
 	struct drm_i915_gem_execbuffer2 eb = spin->execbuf;
 
 	eb.flags &= ~(0x3f | I915_EXEC_BSD_MASK);
-	eb.flags |= e2ring(gem_fd, e) | I915_EXEC_NO_RELOC;
+	eb.flags = e->flags | I915_EXEC_NO_RELOC;
 	eb.batch_start_offset += offset;
 
 	gem_execbuf(gem_fd, &eb);
@@ -503,7 +498,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 		else if (spin)
 			__submit_spin_batch(gem_fd, spin, e_, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
+			spin = __spin_poll(gem_fd, 0, e_->flags);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
 	}
@@ -558,7 +553,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 		if (spin)
 			__submit_spin_batch(gem_fd, spin, e, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
+			spin = __spin_poll(gem_fd, 0, e->flags);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	}
@@ -602,7 +597,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
 	if (flags & TEST_BUSY)
-		spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+		spin = spin_sync(gem_fd, 0, e->flags);
 	else
 		spin = NULL;
 
@@ -689,7 +684,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
 
 	eb.buffer_count = 2;
 	eb.buffers_ptr = to_user_pointer(obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/**
 	 * Start the semaphore wait PMU and after some known time let the above
@@ -845,7 +840,7 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e) | I915_EXEC_SECURE;
+	eb.flags = e->flags | I915_EXEC_SECURE;
 
 	for_each_pipe_with_valid_output(&data.display, p, output) {
 		struct igt_helper_process waiter = { };
@@ -936,7 +931,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	fd[1] = open_pmu(config);
 
-	spin = spin_sync(gem_fd, 0, e2ring(gem_fd, e));
+	spin = spin_sync(gem_fd, 0, e->flags);
 
 	val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
 	slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1465,7 +1460,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
 
 	eb.buffer_count = 1;
 	eb.buffers_ptr = to_user_pointer(&obj);
-	eb.flags = e2ring(gem_fd, e);
+	eb.flags = e->flags;
 
 	/*
 	 * This test is probabilistic so run in a few times to increase the
@@ -1570,7 +1565,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
 		igt_spin_t *spin;
 
 		/* Allocate our spin batch and idle it. */
-		spin = igt_spin_batch_new(gem_fd, .engine = e2ring(gem_fd, e));
+		spin = igt_spin_batch_new(gem_fd, .engine = e->flags);
 		igt_spin_batch_end(spin);
 		gem_sync(gem_fd, spin->handle);
 
-- 
2.20.1

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[igt-dev] [PATCH v13 9/9] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

[Andi Shyti]

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with 'gem_topology_has_engine()'.

The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/i915/gem_exec_basic.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..c4a489bdd100 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,19 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-ctx") {
+		uint32_t ctx_id;
+		struct intel_execution_engine2 *e2;
+
+		ctx_id = gem_context_create(fd);
+
+		for_each_engine_class_instance(fd, ctx_id, e2)
+			igt_assert(gem_context_has_engine(fd, e2->flags,
+							  ctx_id));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.20.1

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[igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58207/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5775 -> IGTPW_2663
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58207/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2663:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_tiled_blits@basic:
    - {fi-icl-y}:         PASS -> FAIL

  
Known issues
------------

  Here are the changes found in IGTPW_2663 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109315] +17

  * igt@amdgpu/amd_prime@amd-to-i915:
    - fi-kbl-x1275:       NOTRUN -> SKIP [fdo#109271] +45

  * igt@gem_ctx_create@basic-files:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] +106

  * igt@gem_exec_basic@gtt-bsd1:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109276] +7

  * igt@gem_exec_basic@readonly-bsd2:
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] +76

  * igt@gem_exec_parse@basic-rejected:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109289] +1

  * igt@gem_exec_store@basic-bsd2:
    - fi-hsw-4770:        NOTRUN -> SKIP [fdo#109271] +41

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      PASS -> FAIL [fdo#108511]

  * igt@i915_selftest@live_contexts:
    - fi-icl-u3:          NOTRUN -> DMESG-FAIL [fdo#108569]

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         NOTRUN -> FAIL [fdo#103182] +1
    - fi-bsw-n3050:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_busy@basic-flip-c:
    - fi-gdg-551:         NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-bsw-n3050:       NOTRUN -> SKIP [fdo#109271] +62

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-hsw-peppy:       NOTRUN -> SKIP [fdo#109271] +46
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109284] +8

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-j4205:       NOTRUN -> SKIP [fdo#109271] +47

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-icl-u3:          NOTRUN -> SKIP [fdo#109285] +3

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          NOTRUN -> FAIL [fdo#103167]
    - fi-hsw-peppy:       NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]

  * igt@kms_psr@primary_mmap_gtt:
    - fi-cfl-8109u:       NOTRUN -> SKIP [fdo#109271] +37

  * igt@kms_psr@primary_page_flip:
    - fi-apl-guc:         NOTRUN -> SKIP [fdo#109271] +50

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         PASS -> FAIL [fdo#104008]

  * igt@runner@aborted:
    - fi-bxt-dsi:         NOTRUN -> FAIL [fdo#109516]
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720


Participating hosts (36 -> 41)
------------------------------

  Additional (11): fi-bxt-dsi fi-bsw-n3050 fi-hsw-peppy fi-apl-guc fi-hsw-4770 fi-kbl-x1275 fi-bxt-j4205 fi-gdg-551 fi-icl-u3 fi-pnv-d510 fi-cfl-8109u 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

    * IGT: IGT_4890 -> IGTPW_2663

  CI_DRM_5775: 3ead1aea2137c77a4fe00637dca589736397d885 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2663: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
  IGT_4890: 6d4d6949a099521003de252358601d22115e27ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@exec-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
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Re: [igt-dev] [PATCH v13 2/9] lib: ioctl_wrappers: reach engines by index as well

[Chris Wilson]

Quoting Andi Shyti (2019-03-19 23:44:34)
> With the new engine query method engines are reachable through
> an index and context they are combined with.
> 
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> 
> The previous 'gem_has_ring()' function becomes a wrapper to the new
> 'gem_context_has_engine()'.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  lib/ioctl_wrappers.c | 4 +++-
>  lib/ioctl_wrappers.h | 4 +++-
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 39920f8707d2..a2597e282704 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1252,7 +1252,7 @@ void igt_require_gem(int fd)
>         igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
>  }
>  
> -bool gem_has_ring(int fd, unsigned ring)
> +bool gem_context_has_engine(int fd, unsigned ring, unsigned ctx)

Make this (fd, ctx, engine) and squash in with the second patch to move
it to gem_context and you can have my r-b for immediate application.
-Chris
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[igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface

[Patchwork]

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58207/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5775_full -> IGTPW_2663_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2663_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2663_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58207/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2663_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf_pmu@busy-accuracy-2-vecs0:
    - shard-apl:          NOTRUN -> FAIL

  * igt@perf_pmu@busy-double-start-bcs0:
    - shard-kbl:          PASS -> FAIL +62

  * igt@perf_pmu@busy-idle-vcs0:
    - shard-snb:          PASS -> FAIL +11

  * igt@perf_pmu@busy-idle-vecs0:
    - shard-glk:          PASS -> FAIL +35

  * igt@perf_pmu@busy-start-vcs0:
    - shard-kbl:          NOTRUN -> FAIL

  * igt@perf_pmu@busy-vecs0:
    - shard-hsw:          NOTRUN -> FAIL

  * igt@perf_pmu@render-node-busy-idle-bcs0:
    - shard-hsw:          PASS -> FAIL +21

  * igt@perf_pmu@semaphore-wait-vcs0:
    - shard-apl:          PASS -> FAIL +36

  
New tests
---------

  New tests have been introduced between CI_DRM_5775_full and IGTPW_2663_full:

### New IGT tests (1) ###

  * igt@gem_exec_basic@exec-ctx:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_2663_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_fence_thrash@bo-copy:
    - shard-hsw:          PASS -> INCOMPLETE [fdo#103540]

  * igt@kms_busy@basic-flip-e:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_busy@basic-modeset-d:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_busy@extended-modeset-hang-newfb-render-c:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956] +2

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-snb:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
    - shard-glk:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-apl:          PASS -> FAIL [fdo#103232] +3
    - shard-kbl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-apl:          PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#104873]

  * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
    - shard-glk:          PASS -> FAIL [fdo#103184]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-kbl:          PASS -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-glk:          PASS -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-glk:          PASS -> FAIL [fdo#103167] / [fdo#105682]

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +9

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-hsw:          NOTRUN -> SKIP [fdo#109271] +35

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +16

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +21

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_setmode@basic:
    - shard-apl:          PASS -> FAIL [fdo#99912]
    - shard-hsw:          PASS -> FAIL [fdo#99912]
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
    - shard-kbl:          PASS -> FAIL [fdo#104894] +1

  * igt@kms_vblank@pipe-c-ts-continuation-modeset-hang:
    - shard-apl:          PASS -> FAIL [fdo#104894] +3

  * igt@perf_pmu@busy-double-start-vcs0:
    - shard-apl:          PASS -> FAIL [fdo#105106]
    - shard-snb:          PASS -> FAIL [fdo#105106] +1
    - shard-hsw:          PASS -> FAIL [fdo#105106]

  * igt@perf_pmu@rc6:
    - shard-kbl:          PASS -> SKIP [fdo#109271]

  
#### Possible fixes ####

  * igt@gem_eio@reset-stress:
    - shard-snb:          FAIL [fdo#109661] -> PASS

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          SKIP [fdo#109271] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-hsw:          DMESG-WARN [fdo#107956] -> PASS
    - shard-kbl:          DMESG-WARN [fdo#107956] -> PASS
    - shard-snb:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-random:
    - shard-apl:          FAIL [fdo#103232] -> PASS +5

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-apl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_cursor_crc@cursor-256x85-sliding:
    - shard-kbl:          FAIL [fdo#103232] -> PASS +2

  * igt@kms_cursor_crc@cursor-size-change:
    - shard-glk:          FAIL [fdo#103232] -> PASS

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          INCOMPLETE [fdo#103540] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-apl:          FAIL [fdo#103167] -> PASS +5

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-kbl:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-glk:          FAIL [fdo#103167] -> PASS +7

  * {igt@kms_plane@plane-position-covered-pipe-a-planes}:
    - shard-glk:          FAIL [fdo#110038] -> PASS
    - shard-apl:          FAIL [fdo#110038] -> PASS

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-glk:          FAIL [fdo#108145] -> PASS

  * {igt@kms_plane_multiple@atomic-pipe-c-tiling-x}:
    - shard-glk:          FAIL [fdo#110037] -> PASS +2

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          FAIL [fdo#109016] -> PASS

  * {igt@kms_universal_plane@universal-plane-pipe-a-functional}:
    - shard-apl:          FAIL [fdo#110037] -> PASS +2

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          FAIL [fdo#104894] -> PASS +1
    - shard-kbl:          FAIL [fdo#104894] -> PASS +1

  
#### Warnings ####

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-glk:          FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105106]: https://bugs.freedesktop.org/show_bug.cgi?id=105106
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
  [fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
  [fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 5)
------------------------------

  Missing    (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u 


Build changes
-------------

    * IGT: IGT_4890 -> IGTPW_2663
    * Piglit: piglit_4509 -> None

  CI_DRM_5775: 3ead1aea2137c77a4fe00637dca589736397d885 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2663: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
  IGT_4890: 6d4d6949a099521003de252358601d22115e27ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Tvrtko Ursulin]

On 19/03/2019 23:44, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 192 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  41 +++++++
>   lib/meson.build                |   1 +
>   4 files changed, 236 insertions(+)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..4ddd9ca98b49
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,192 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = SIZEOF_QUERY;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void map_engine_context(struct intel_engine_data *ed,
> +			       struct drm_i915_gem_context_param *ctx_param)

We normally name functions so it is more obvious on what they operate. 
In this case it is a context so I'd call it context/ctx_map_engines(ctx, 
engines).

> +{
> +	struct i915_context_param_engines *ctx_engine =
> +			(struct i915_context_param_engines*) ctx_param->value;
> +	int i = 0;
> +
> +	for (typeof(ctx_engine->class_instance[0]) *p =
> +					&ctx_engine->class_instance[0];
> +						i < ed->nengines; i++, p++) {
> +		p->engine_class = ed->engines[i].class;
> +		p->engine_instance = ed->engines[i].instance;
> +	}
> +
> +	ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
> +
> +	gem_context_set_param(ed->fd, ctx_param);
> +}
> +
> +static void dup_engine(struct intel_execution_engine2 *e2, const char *name,
> +		       uint16_t class, uint16_t instance, uint8_t flags)

Function is not duplicating anything so name is confusing. init_engine / 
engine_init ?

> +{
> +	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> +	char *__name;
> +
> +	/* if we don't recognise the class, then we mark it as "unk" */
> +	if (name) {
> +		e2->name = name;
> +	} else {
> +		if (class >= ARRAY_SIZE(class_names))
> +			igt_assert(asprintf(&__name, "unk-%d:%d",
> +					    class, instance) > 0);
> +		else
> +			igt_assert(asprintf(&__name, "%s%d",
> +					    class_names[class], instance) > 0);
> +
> +		e2->name = __name;

We discussed on the IRC how names can be borrowed from the static engine 
table, which we have to keep maintaining due CI limitations anyway. That 
way all leaks are solved.

So you would just replace the above with a name lookup against the 
static table and use that pointer.

> +	}
> +
> +	e2->class    = class;
> +	e2->instance = instance;
> +	e2->flags    = flags;
> +
> +}
> +
> +static void query_engine_list(struct intel_engine_data *ed)
> +{
> +	uint8_t query_buffer[SIZEOF_QUERY] = { };
> +	struct drm_i915_query_engine_info *query_engine =
> +			(struct drm_i915_query_engine_info *) query_buffer;
> +	int i;
> +
> +	query_engines(ed->fd, query_engine);
> +
> +	for (i = 0; i < query_engine->num_engines; i++)
> +		dup_engine(&ed->engines[i], NULL,
> +			   query_engine->engines[i].engine_class,
> +			   query_engine->engines[i].engine_instance, i + 1);
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	struct intel_engine_data engine_data = {
> +		.fd = fd,
> +		.ctx = ctx_id,
> +	};
> +	uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +	struct i915_context_param_engines *cengine =
> +				(struct i915_context_param_engines *) buff;
> +	struct drm_i915_gem_context_param cparam = {

We normally call this param in IGT so maybe check and make it consistent 
if so.

> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +		.size = SIZEOF_CTX_PARAM,
> +		.value = to_user_pointer(cengine),
> +	};
> +	int ret, i;
> +
> +	cparam.value = to_user_pointer(cengine);

Already initialized above.

> +
> +	ret = __gem_context_get_param(fd, &cparam);
> +
> +	if (ret) {
> +		/* if kernel does not support engine/context mapping */
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_engine_class_instance(e2) {
> +			uint64_t flags;
> +
> +			if (!gem_has_engine(fd, e2->class, e2->instance))
> +				continue;
> +
> +			flags = gem_class_instance_to_eb_flags(fd, e2->class,
> +							       e2->instance);
> +
> +			dup_engine(&engine_data.engines[engine_data.nengines],
> +				   e2->name, e2->class, e2->instance, flags);
> +
> +			engine_data.nengines++;
> +		}
> +
> +	} else if (cparam.size == sizeof(struct i915_context_param_engines)) {

This should be "== 0" since Chris has special plans for the other.

> +		/* else if context doesn't have mapped engines */
> +		query_engine_list(&engine_data);
> +		map_engine_context(&engine_data, &cparam);
> +
> +	} else {
> +		/* context has a list of mapped engines */
> +
> +		uint8_t nengines = (cparam.size -
> +				sizeof(struct i915_context_param_engines)) /
> +				sizeof(cengine->class_instance[0]);
> +
> +		for (i = 0; i < nengines - 1; i++)

nengines - 1 is not right I think, just nengines.

> +			dup_engine(&engine_data.engines[i], NULL,
> +				   cengine->class_instance[i].engine_class,
> +				   cengine->class_instance[i].engine_instance,
> +				   i + 1);

Just "i" since index zero is not special any longer.

> +
> +		engine_data.nengines = i;
> +	}
> +
> +	return engine_data;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..544621683e15
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,41 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "i915_drm.h"
> +#include "igt_gt.h"
> +
> +struct intel_engine_data {
> +	int fd;
> +	uint32_t ctx;
> +
> +	uint32_t nengines;
> +	uint32_t n;
> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> 

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v13 5/9] lib: igt_gt: use flags in intel_execution_engines2

[Tvrtko Ursulin]

On 19/03/2019 23:44, Andi Shyti wrote:
> Having a variable flags declared in the
> 'intel_execution_engines2' structure comes very handy when
> handling engines that are configurable in different ways.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/igt_gt.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..9f28af8cfb5c 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
>   	int instance;
> +	uint64_t flags;
>   } intel_execution_engines2[];
>   
>   unsigned int
> 

I'd squash this into next patch since it is not useful on it's own.

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Chris Wilson]

Quoting Andi Shyti (2019-03-19 23:44:38)
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  lib/Makefile.sources           |   2 +
>  lib/i915/gem_engine_topology.c | 192 +++++++++++++++++++++++++++++++++
>  lib/i915/gem_engine_topology.h |  41 +++++++
>  lib/meson.build                |   1 +
>  4 files changed, 236 insertions(+)
>  create mode 100644 lib/i915/gem_engine_topology.c
>  create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =             \
>         i915/gem_ring.c \
>         i915/gem_mman.c \
>         i915/gem_mman.h \
> +       i915/gem_engine_topology.c      \
> +       i915/gem_engine_topology.h      \
>         i915_3d.h               \
>         i915_reg.h              \
>         i915_pciids.h           \
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..4ddd9ca98b49
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,192 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM       offsetof(struct i915_context_param_engines, \
> +                                       class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY           offsetof(struct drm_i915_query_engine_info, \
> +                                       engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +       int err = 0;
> +
> +       if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +               err = -errno;
> +
> +       errno = 0;
> +       return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +       igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +                         struct drm_i915_query_engine_info *query_engines)
> +{
> +       struct drm_i915_query_item item = { };
> +       struct drm_i915_query query = { };
> +
> +       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +       query.items_ptr = to_user_pointer(&item);
> +       query.num_items = 1;
> +       item.length = SIZEOF_QUERY;
> +
> +       item.data_ptr = to_user_pointer(query_engines);
> +
> +       gem_query(fd, &query);
> +}
> +
> +static void map_engine_context(struct intel_engine_data *ed,
> +                              struct drm_i915_gem_context_param *ctx_param)
> +{
> +       struct i915_context_param_engines *ctx_engine =
> +                       (struct i915_context_param_engines*) ctx_param->value;
> +       int i = 0;
> +
> +       for (typeof(ctx_engine->class_instance[0]) *p =
> +                                       &ctx_engine->class_instance[0];
> +                                               i < ed->nengines; i++, p++) {
> +               p->engine_class = ed->engines[i].class;
> +               p->engine_instance = ed->engines[i].instance;
> +       }
> +
> +       ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i + 1]);
> +
> +       gem_context_set_param(ed->fd, ctx_param);
> +}
> +
> +static void dup_engine(struct intel_execution_engine2 *e2, const char *name,
> +                      uint16_t class, uint16_t instance, uint8_t flags)
> +{
> +       const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> +       char *__name;
> +
> +       /* if we don't recognise the class, then we mark it as "unk" */
> +       if (name) {
> +               e2->name = name;
> +       } else {
> +               if (class >= ARRAY_SIZE(class_names))
> +                       igt_assert(asprintf(&__name, "unk-%d:%d",
> +                                           class, instance) > 0);
> +               else
> +                       igt_assert(asprintf(&__name, "%s%d",
> +                                           class_names[class], instance) > 0);
> +
> +               e2->name = __name;
> +       }
> +
> +       e2->class    = class;
> +       e2->instance = instance;
> +       e2->flags    = flags;
> +
> +}
> +
> +static void query_engine_list(struct intel_engine_data *ed)
> +{
> +       uint8_t query_buffer[SIZEOF_QUERY] = { };
> +       struct drm_i915_query_engine_info *query_engine =
> +                       (struct drm_i915_query_engine_info *) query_buffer;
> +       int i;
> +
> +       query_engines(ed->fd, query_engine);
> +
> +       for (i = 0; i < query_engine->num_engines; i++)
> +               dup_engine(&ed->engines[i], NULL,
> +                          query_engine->engines[i].engine_class,
> +                          query_engine->engines[i].engine_instance, i + 1);
> +
> +       ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +       struct intel_engine_data engine_data = {
> +               .fd = fd,
> +               .ctx = ctx_id,
> +       };
> +       uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +       struct i915_context_param_engines *cengine =
> +                               (struct i915_context_param_engines *) buff;

Oi, noet. And just a single tab indent.

> +       struct drm_i915_gem_context_param cparam = {
> +               .param = I915_CONTEXT_PARAM_ENGINES,
> +               .ctx_id = ctx_id,
> +               .size = SIZEOF_CTX_PARAM,
> +               .value = to_user_pointer(cengine),
> +       };
> +       int ret, i;
> +
> +       cparam.value = to_user_pointer(cengine);
> +
> +       ret = __gem_context_get_param(fd, &cparam);
> +
> +       if (ret) {
> +               /* if kernel does not support engine/context mapping */
> +               const struct intel_execution_engine2 *e2;

Hmm, how does this distinguish against too many engines (more than can
fit into buf?). Both return -EINVAL iirc?

> +               igt_debug("using pre-allocated engine list\n");
> +
> +               __for_each_engine_class_instance(e2) {
> +                       uint64_t flags;
> +
> +                       if (!gem_has_engine(fd, e2->class, e2->instance))
> +                               continue;
> +
> +                       flags = gem_class_instance_to_eb_flags(fd, e2->class,
> +                                                              e2->instance);
> +
> +                       dup_engine(&engine_data.engines[engine_data.nengines],
> +                                  e2->name, e2->class, e2->instance, flags);
> +
> +                       engine_data.nengines++;
> +               }
> +
> +       } else if (cparam.size == sizeof(struct i915_context_param_engines)) {
> +               /* else if context doesn't have mapped engines */

No, that is cparam.size == 0.

sizeof(engines) is 0 valid engines, as constructed by the user, so
should be respected.

> +               query_engine_list(&engine_data);
> +               map_engine_context(&engine_data, &cparam);
> +
> +       } else {
> +               /* context has a list of mapped engines */
> +
> +               uint8_t nengines = (cparam.size -
> +                               sizeof(struct i915_context_param_engines)) /
> +                               sizeof(cengine->class_instance[0]);
> +
> +               for (i = 0; i < nengines - 1; i++)

Pardon?

> +                       dup_engine(&engine_data.engines[i], NULL,
> +                                  cengine->class_instance[i].engine_class,
> +                                  cengine->class_instance[i].engine_instance,
> +                                  i + 1);

This seems very suspect. If class/instance doesn't map to a known
engine, dup_engine() should be figuring it out, as the engine[] is
entirely at the arbitrary whim of the user.

> +               engine_data.nengines = i;
> +       }
> +
> +       return engine_data;
> +}

> +#include "i915_drm.h"
> +#include "igt_gt.h"
> +
> +struct intel_engine_data {
> +       int fd;
> +       uint32_t ctx;
> +
> +       uint32_t nengines;
> +       uint32_t n;
> +       struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};

This is the _iter. Pull the for_each_foo() into this patch so we can see
how it is put together.

At which point, do we need the (fd,ctx) here since they are parameters to
the for_each() and so available later?

Missing _iter_fini. Polish the for_each_foo() a bit more.
-Chris
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Re: [igt-dev] [PATCH v13 7/9] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Tvrtko Ursulin]

On 19/03/2019 23:44, Andi Shyti wrote:
> Extend the 'for_each_engine_class_instance' so that it can loop
> only through active engines.
> 
> The 'for_each_engine_class_instance()' define starts its loop
> from generating a 'struct intel_engine_data' that contains only
> the current engines and it loops through the list.
> 
> A new parameter is added which refers to the context, to which
> engines ar bound.
> 
> For back compatibility the previous version of the loop
> definition has been renamed to 'for_each_engine_physical', which
> uses the default context 0.
> 
> Update tests/perf_pmu.c that uses the
> 'for_each_engine_physical()' loop.

Here we had a misunderstanding. :) When talking about 
for_each_engine_physical, I actually meant for_each_physical_engine.

I was suggesting to replace the existing implementation of the latter 
with the new scheme, and was asking if the churn to existing tests would 
be too big.

It is what we want I think, since that way we get coverage on all 
engines in existing test cases.

If you do this, and also add vcs2 to the static table in this series, 
and we send a series with complete media scalability patches to the 
list, then with some Test-with: magic you may see how perf_pmu, and even 
all the other for_each_physical_engined test create and exercise new 
subtests on Icelakes.

Regards,

Tvrtko

> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/igt_gt.h     | 11 ++++++++---
>   tests/perf_pmu.c |  8 ++++----
>   2 files changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 9f28af8cfb5c..691cbb11ee0a 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -118,8 +118,13 @@ void gem_require_engine(int gem_fd,
>   #define __for_each_engine_class_instance(e__) \
>   	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
>   
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> +#include "i915/gem_engine_topology.h"
> +
> +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +		((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> +			i__.n++)
> +
> +#define for_each_engine_physical(f, e) for_each_engine_class_instance(f, 0, e)
>   
>   #endif /* IGT_GT_H */
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 45291298c021..79adeb2c8f3f 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_engine_physical(gem_fd, e_) {
>   		if (e == e_)
>   			busy_idx = i;
>   
> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> +	for_each_engine_physical(gem_fd, e_) {
>   		if (e == e_)
>   			idle_idx = i;
>   		else if (spin)
> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	for_each_engine_physical(gem_fd, e) {
>   		if (spin)
>   			__submit_spin_batch(gem_fd, spin, e, 64);
>   		else
> @@ -1683,7 +1683,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		for_each_engine_physical(fd, e)
>   			num_engines++;
>   	}
>   
> 
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Re: [igt-dev] [PATCH v13 7/9] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-20 10:04:50)
> 
> On 19/03/2019 23:44, Andi Shyti wrote:
> If you do this, and also add vcs2 to the static table in this series, 

Can we give the static table every class with up to MAX_INSTANCE^2?
Shotgun approach.
-Chris
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Re: [igt-dev] [PATCH v13 7/9] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Tvrtko Ursulin]

On 20/03/2019 10:09, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-03-20 10:04:50)
>>
>> On 19/03/2019 23:44, Andi Shyti wrote:
>> If you do this, and also add vcs2 to the static table in this series,
> 
> Can we give the static table every class with up to MAX_INSTANCE^2?
> Shotgun approach.

Problem is test enumeration is driven of it and we are not allowed to 
access the device in that phase. And I don't think we want to enumerate 
a gazillion of subtests just to make the static table future proof.

So I was thinking Andi would be adding an assert in the code which 
borrows the name from the static table so we notice it needs to be 
expanded for new engines.

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v13 7/9] lib/igt_gt: use for_each_engine_class_instance to loop through active engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-20 10:33:43)
> 
> On 20/03/2019 10:09, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-03-20 10:04:50)
> >>
> >> On 19/03/2019 23:44, Andi Shyti wrote:
> >> If you do this, and also add vcs2 to the static table in this series,
> > 
> > Can we give the static table every class with up to MAX_INSTANCE^2?
> > Shotgun approach.
> 
> Problem is test enumeration is driven of it and we are not allowed to 
> access the device in that phase. And I don't think we want to enumerate 
> a gazillion of subtests just to make the static table future proof.

Having a few hundred unreported tests should not be an issue. And should
be a motivator for someone else to fix their problem if it was. And CI
folk, it is a problem in the static partition design.
 
> So I was thinking Andi would be adding an assert in the code which 
> borrows the name from the static table so we notice it needs to be 
> expanded for new engines.

And then we are always behind and having to keep internal forks, instead
of futureproofing as much as we can get away with.
-Chris
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

> > +{
> > +	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> > +	char *__name;
> > +
> > +	/* if we don't recognise the class, then we mark it as "unk" */
> > +	if (name) {
> > +		e2->name = name;
> > +	} else {
> > +		if (class >= ARRAY_SIZE(class_names))
> > +			igt_assert(asprintf(&__name, "unk-%d:%d",
> > +					    class, instance) > 0);
> > +		else
> > +			igt_assert(asprintf(&__name, "%s%d",
> > +					    class_names[class], instance) > 0);
> > +
> > +		e2->name = __name;
> 
> We discussed on the IRC how names can be borrowed from the static engine
> table, which we have to keep maintaining due CI limitations anyway. That way
> all leaks are solved.
> 
> So you would just replace the above with a name lookup against the static
> table and use that pointer.

Yes, this is the tax we need to pay for having counts name inside
intel_execution_engine2.

I can take the pointer from our intel_exectuion_engines2 array,
and then we wouldn't have "unk<class>:<instance>".

As I said the best thing here would be to remove the "const" and
be able to use all the string functions.

> > +	} else if (cparam.size == sizeof(struct i915_context_param_engines)) {
> 
> This should be "== 0" since Chris has special plans for the other.
> 
> > +		/* else if context doesn't have mapped engines */
> > +		query_engine_list(&engine_data);
> > +		map_engine_context(&engine_data, &cparam);
> > +
> > +	} else {
> > +		/* context has a list of mapped engines */
> > +
> > +		uint8_t nengines = (cparam.size -
> > +				sizeof(struct i915_context_param_engines)) /
> > +				sizeof(cengine->class_instance[0]);
> > +
> > +		for (i = 0; i < nengines - 1; i++)
> 
> nengines - 1 is not right I think, just nengines.
> 
> > +			dup_engine(&engine_data.engines[i], NULL,
> > +				   cengine->class_instance[i].engine_class,
> > +				   cengine->class_instance[i].engine_instance,
> > +				   i + 1);
> 
> Just "i" since index zero is not special any longer.

I was running on a messed up kernel that and was receiving weird
values :/

Andi
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

> > +       uint8_t buff[SIZEOF_CTX_PARAM] = { };
> > +       struct i915_context_param_engines *cengine =
> > +                               (struct i915_context_param_engines *) buff;
> 
> Oi, noet. And just a single tab indent.

Yes, I messed up a few things in this version and as I was writing
to Tvrtko, also the kernel I was running had some stuff that were
screwing up the ioctls values.

> > +       struct drm_i915_gem_context_param cparam = {
> > +               .param = I915_CONTEXT_PARAM_ENGINES,
> > +               .ctx_id = ctx_id,
> > +               .size = SIZEOF_CTX_PARAM,
> > +               .value = to_user_pointer(cengine),
> > +       };
> > +       int ret, i;
> > +
> > +       cparam.value = to_user_pointer(cengine);
> > +
> > +       ret = __gem_context_get_param(fd, &cparam);
> > +
> > +       if (ret) {
> > +               /* if kernel does not support engine/context mapping */
> > +               const struct intel_execution_engine2 *e2;
> 
> Hmm, how does this distinguish against too many engines (more than can
> fit into buf?). Both return -EINVAL iirc?

I haven't found in the driver where we return -EINVAL for having
too many engines. Have I missed it somewhere?

> No, that is cparam.size == 0.
...
> Pardon?

please, don't mind this bits, I was experimenting with the driver
and forgot some stuff inside :)

> > +                       dup_engine(&engine_data.engines[i], NULL,
> > +                                  cengine->class_instance[i].engine_class,
> > +                                  cengine->class_instance[i].engine_instance,
> > +                                  i + 1);
> 
> This seems very suspect. If class/instance doesn't map to a known
> engine, dup_engine() should be figuring it out, as the engine[] is
> entirely at the arbitrary whim of the user.

it does, right? we know the list of engines and we assign
"unk<class>:<instance>" if the engine is not recognised.

Am I missing something?

In any case, I'm still going to change it and compare all class
instances against the intel_execution_engines2 array.

Or do you mean that we shouldn't have the engine at all in the
list I am creating... at the end that's what comes from the
driver.

> > +struct intel_engine_data {
> > +       int fd;
> > +       uint32_t ctx;
> > +
> > +       uint32_t nengines;
> > +       uint32_t n;
> > +       struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> > +};
> 
> This is the _iter. Pull the for_each_foo() into this patch so we can see
> how it is put together.
> 
> At which point, do we need the (fd,ctx) here since they are parameters to
> the for_each() and so available later?

they are useful for my functions... well... little advantage, no
need indeed.

I didn't see this as an iter structure rather than a data
structure (just an 'n' that increments for helping the for_each),
that we could use in other occasions other than looping thorugh.

> Missing _iter_fini. Polish the for_each_foo() a bit more.

_iter_fini? You mean an iter_end to clean up things? Do we need
it? Is there anything to clean up?
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Chris Wilson]

Quoting Andi Shyti (2019-03-20 10:49:13)
> > > +       uint8_t buff[SIZEOF_CTX_PARAM] = { };
> > > +       struct i915_context_param_engines *cengine =
> > > +                               (struct i915_context_param_engines *) buff;
> > 
> > Oi, noet. And just a single tab indent.
> 
> Yes, I messed up a few things in this version and as I was writing
> to Tvrtko, also the kernel I was running had some stuff that were
> screwing up the ioctls values.
> 
> > > +       struct drm_i915_gem_context_param cparam = {
> > > +               .param = I915_CONTEXT_PARAM_ENGINES,
> > > +               .ctx_id = ctx_id,
> > > +               .size = SIZEOF_CTX_PARAM,
> > > +               .value = to_user_pointer(cengine),
> > > +       };
> > > +       int ret, i;
> > > +
> > > +       cparam.value = to_user_pointer(cengine);
> > > +
> > > +       ret = __gem_context_get_param(fd, &cparam);
> > > +
> > > +       if (ret) {
> > > +               /* if kernel does not support engine/context mapping */
> > > +               const struct intel_execution_engine2 *e2;
> > 
> > Hmm, how does this distinguish against too many engines (more than can
> > fit into buf?). Both return -EINVAL iirc?
> 
> I haven't found in the driver where we return -EINVAL for having
> too many engines. Have I missed it somewhere?

If we cannot fit the ctx->engines[] into the cparam.size we also report
-EINVAL. I'm wondering if we should establish a different errno
convention for that.

> > > +                       dup_engine(&engine_data.engines[i], NULL,
> > > +                                  cengine->class_instance[i].engine_class,
> > > +                                  cengine->class_instance[i].engine_instance,
> > > +                                  i + 1);
> > 
> > This seems very suspect. If class/instance doesn't map to a known
> > engine, dup_engine() should be figuring it out, as the engine[] is
> > entirely at the arbitrary whim of the user.
> 
> it does, right? we know the list of engines and we assign
> "unk<class>:<instance>" if the engine is not recognised.
> 
> Am I missing something?

I want to handle virtual engines somehow :)

> In any case, I'm still going to change it and compare all class
> instances against the intel_execution_engines2 array.
> 
> Or do you mean that we shouldn't have the engine at all in the
> list I am creating... at the end that's what comes from the
> driver.

Here I was just saying '+1' is obsolete.

> > > +struct intel_engine_data {
> > > +       int fd;
> > > +       uint32_t ctx;
> > > +
> > > +       uint32_t nengines;
> > > +       uint32_t n;
> > > +       struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> > > +};
> > 
> > This is the _iter. Pull the for_each_foo() into this patch so we can see
> > how it is put together.
> > 
> > At which point, do we need the (fd,ctx) here since they are parameters to
> > the for_each() and so available later?
> 
> they are useful for my functions... well... little advantage, no
> need indeed.
> 
> I didn't see this as an iter structure rather than a data
> structure (just an 'n' that increments for helping the for_each),
> that we could use in other occasions other than looping thorugh.
> 
> > Missing _iter_fini. Polish the for_each_foo() a bit more.
> 
> _iter_fini? You mean an iter_end to clean up things? Do we need
> it? Is there anything to clean up?

Did I not see asprintf? Anyway Tvrtko suggested that they can all be
static names, so no, there shouldn't be much to clean up, but that is
one huge struct to be passing around the stack!!!
-Chris
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Tvrtko Ursulin]

On 20/03/2019 10:49, Andi Shyti wrote:
>>> +{
>>> +	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
>>> +	char *__name;
>>> +
>>> +	/* if we don't recognise the class, then we mark it as "unk" */
>>> +	if (name) {
>>> +		e2->name = name;
>>> +	} else {
>>> +		if (class >= ARRAY_SIZE(class_names))
>>> +			igt_assert(asprintf(&__name, "unk-%d:%d",
>>> +					    class, instance) > 0);
>>> +		else
>>> +			igt_assert(asprintf(&__name, "%s%d",
>>> +					    class_names[class], instance) > 0);
>>> +
>>> +		e2->name = __name;
>>
>> We discussed on the IRC how names can be borrowed from the static engine
>> table, which we have to keep maintaining due CI limitations anyway. That way
>> all leaks are solved.
>>
>> So you would just replace the above with a name lookup against the static
>> table and use that pointer.
> 
> Yes, this is the tax we need to pay for having counts name inside
> intel_execution_engine2.
> 
> I can take the pointer from our intel_exectuion_engines2 array,
> and then we wouldn't have "unk<class>:<instance>".
> 
> As I said the best thing here would be to remove the "const" and
> be able to use all the string functions.

Or, as long as we are depending on the static array being a superset, 
you could store a list of pointers to static array entries in the 
dynamic engine_data list, instead of copying over elements?

>>> +	} else if (cparam.size == sizeof(struct i915_context_param_engines)) {
>>
>> This should be "== 0" since Chris has special plans for the other.
>>
>>> +		/* else if context doesn't have mapped engines */
>>> +		query_engine_list(&engine_data);
>>> +		map_engine_context(&engine_data, &cparam);
>>> +
>>> +	} else {
>>> +		/* context has a list of mapped engines */
>>> +
>>> +		uint8_t nengines = (cparam.size -
>>> +				sizeof(struct i915_context_param_engines)) /
>>> +				sizeof(cengine->class_instance[0]);
>>> +
>>> +		for (i = 0; i < nengines - 1; i++)
>>
>> nengines - 1 is not right I think, just nengines.
>>
>>> +			dup_engine(&engine_data.engines[i], NULL,
>>> +				   cengine->class_instance[i].engine_class,
>>> +				   cengine->class_instance[i].engine_instance,
>>> +				   i + 1);
>>
>> Just "i" since index zero is not special any longer.
> 
> I was running on a messed up kernel that and was receiving weird
> values :/

If you are using my media branch and it is broken in some respect please 
report the details!

Regards,

Tvrtko
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

On Wed, Mar 20, 2019 at 10:59:05AM +0000, Chris Wilson wrote:
> Quoting Andi Shyti (2019-03-20 10:49:13)
> > > > +       uint8_t buff[SIZEOF_CTX_PARAM] = { };
> > > > +       struct i915_context_param_engines *cengine =
> > > > +                               (struct i915_context_param_engines *) buff;
> > > 
> > > Oi, noet. And just a single tab indent.
> > 
> > Yes, I messed up a few things in this version and as I was writing
> > to Tvrtko, also the kernel I was running had some stuff that were
> > screwing up the ioctls values.
> > 
> > > > +       struct drm_i915_gem_context_param cparam = {
> > > > +               .param = I915_CONTEXT_PARAM_ENGINES,
> > > > +               .ctx_id = ctx_id,
> > > > +               .size = SIZEOF_CTX_PARAM,
> > > > +               .value = to_user_pointer(cengine),
> > > > +       };
> > > > +       int ret, i;
> > > > +
> > > > +       cparam.value = to_user_pointer(cengine);
> > > > +
> > > > +       ret = __gem_context_get_param(fd, &cparam);
> > > > +
> > > > +       if (ret) {
> > > > +               /* if kernel does not support engine/context mapping */
> > > > +               const struct intel_execution_engine2 *e2;
> > > 
> > > Hmm, how does this distinguish against too many engines (more than can
> > > fit into buf?). Both return -EINVAL iirc?
> > 
> > I haven't found in the driver where we return -EINVAL for having
> > too many engines. Have I missed it somewhere?
> 
> If we cannot fit the ctx->engines[] into the cparam.size we also report
> -EINVAL. I'm wondering if we should establish a different errno
> convention for that.
> 
> > > > +                       dup_engine(&engine_data.engines[i], NULL,
> > > > +                                  cengine->class_instance[i].engine_class,
> > > > +                                  cengine->class_instance[i].engine_instance,
> > > > +                                  i + 1);
> > > 
> > > This seems very suspect. If class/instance doesn't map to a known
> > > engine, dup_engine() should be figuring it out, as the engine[] is
> > > entirely at the arbitrary whim of the user.
> > 
> > it does, right? we know the list of engines and we assign
> > "unk<class>:<instance>" if the engine is not recognised.
> > 
> > Am I missing something?
> 
> I want to handle virtual engines somehow :)
> 
> > In any case, I'm still going to change it and compare all class
> > instances against the intel_execution_engines2 array.
> > 
> > Or do you mean that we shouldn't have the engine at all in the
> > list I am creating... at the end that's what comes from the
> > driver.
> 
> Here I was just saying '+1' is obsolete.
> 
> > > > +struct intel_engine_data {
> > > > +       int fd;
> > > > +       uint32_t ctx;
> > > > +
> > > > +       uint32_t nengines;
> > > > +       uint32_t n;
> > > > +       struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> > > > +};
> > > 
> > > This is the _iter. Pull the for_each_foo() into this patch so we can see
> > > how it is put together.
> > > 
> > > At which point, do we need the (fd,ctx) here since they are parameters to
> > > the for_each() and so available later?
> > 
> > they are useful for my functions... well... little advantage, no
> > need indeed.
> > 
> > I didn't see this as an iter structure rather than a data
> > structure (just an 'n' that increments for helping the for_each),
> > that we could use in other occasions other than looping thorugh.
> > 
> > > Missing _iter_fini. Polish the for_each_foo() a bit more.
> > 
> > _iter_fini? You mean an iter_end to clean up things? Do we need
> > it? Is there anything to clean up?
> 
> Did I not see asprintf? Anyway Tvrtko suggested that they can all be
> static names, so no, there shouldn't be much to clean up, but that is
> one huge struct to be passing around the stack!!!

in any case, I thought about the clean up, but it wouldn't fix
anything anyway, because if the for_each is interrupted, we would
never ever clean up and leak anything inside.

I somehow ignored asprintf because I always thought that pointing
to static names is not future proof enough (I considered that one
day we will get rid of intel_execution_engines2 array, while
this way we are binding to it even more. I don't know what is
worse :) ).

A solution is to expand the struct intel_execution_engine2, by
removing the "const" in front of the name so that we can have
more flexibility at assigning names.

Another solution would be having the engine_data structure as a
global structure that contains all informations and it's
allocated outside the for_each. We can have functions inside it
like init, get_next, and so on, instead of using it just as a
mere leaking iterator.

> -Chris
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Chris Wilson]

Quoting Andi Shyti (2019-03-20 11:13:16)
> On Wed, Mar 20, 2019 at 10:59:05AM +0000, Chris Wilson wrote:
> Another solution would be having the engine_data structure as a
> global structure that contains all informations and it's
> allocated outside the for_each. We can have functions inside it
> like init, get_next, and so on, instead of using it just as a
> mere leaking iterator.

You can't use a single global, as I need nested iterators.

Don't worry about interrupted loops leaking, it's par for the course for
igt_assert() as we don't have full setup/cleanup (igt_try {} igt_catch
{} igt_finally {} anyone?).
-Chris
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

> > > > +	const char *class_names[] = { "rcs", "bcs", "vcs", "vecs" };
> > > > +	char *__name;
> > > > +
> > > > +	/* if we don't recognise the class, then we mark it as "unk" */
> > > > +	if (name) {
> > > > +		e2->name = name;
> > > > +	} else {
> > > > +		if (class >= ARRAY_SIZE(class_names))
> > > > +			igt_assert(asprintf(&__name, "unk-%d:%d",
> > > > +					    class, instance) > 0);
> > > > +		else
> > > > +			igt_assert(asprintf(&__name, "%s%d",
> > > > +					    class_names[class], instance) > 0);
> > > > +
> > > > +		e2->name = __name;
> > > 
> > > We discussed on the IRC how names can be borrowed from the static engine
> > > table, which we have to keep maintaining due CI limitations anyway. That way
> > > all leaks are solved.
> > > 
> > > So you would just replace the above with a name lookup against the static
> > > table and use that pointer.
> > 
> > Yes, this is the tax we need to pay for having counts name inside
> > intel_execution_engine2.
> > 
> > I can take the pointer from our intel_exectuion_engines2 array,
> > and then we wouldn't have "unk<class>:<instance>".
> > 
> > As I said the best thing here would be to remove the "const" and
> > be able to use all the string functions.
> 
> Or, as long as we are depending on the static array being a superset, you
> could store a list of pointers to static array entries in the dynamic
> engine_data list, instead of copying over elements?

Your first suggestion is somehow cleaner :)

> > > > +	} else if (cparam.size == sizeof(struct i915_context_param_engines)) {
> > > 
> > > This should be "== 0" since Chris has special plans for the other.
> > > 
> > > > +		/* else if context doesn't have mapped engines */
> > > > +		query_engine_list(&engine_data);
> > > > +		map_engine_context(&engine_data, &cparam);
> > > > +
> > > > +	} else {
> > > > +		/* context has a list of mapped engines */
> > > > +
> > > > +		uint8_t nengines = (cparam.size -
> > > > +				sizeof(struct i915_context_param_engines)) /
> > > > +				sizeof(cengine->class_instance[0]);
> > > > +
> > > > +		for (i = 0; i < nengines - 1; i++)
> > > 
> > > nengines - 1 is not right I think, just nengines.
> > > 
> > > > +			dup_engine(&engine_data.engines[i], NULL,
> > > > +				   cengine->class_instance[i].engine_class,
> > > > +				   cengine->class_instance[i].engine_instance,
> > > > +				   i + 1);
> > > 
> > > Just "i" since index zero is not special any longer.
> > 
> > I was running on a messed up kernel that and was receiving weird
> > values :/
> 
> If you are using my media branch and it is broken in some respect please
> report the details!

I will report when I find something, but in this case I had some
patches on top and in the middle that were messing things up, a
clean install fixed it :)

Andi
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Re: [igt-dev] [PATCH v13 6/9] lib/i915: add gem_engine_topology library

[Andi Shyti]

On Wed, Mar 20, 2019 at 11:18:47AM +0000, Chris Wilson wrote:
> Quoting Andi Shyti (2019-03-20 11:13:16)
> > On Wed, Mar 20, 2019 at 10:59:05AM +0000, Chris Wilson wrote:
> > Another solution would be having the engine_data structure as a
> > global structure that contains all informations and it's
> > allocated outside the for_each. We can have functions inside it
> > like init, get_next, and so on, instead of using it just as a
> > mere leaking iterator.
> 
> You can't use a single global, as I need nested iterators.

Sorry, I didn't mean a single global structure, but a "global" in
the sense used by everyone "data structure". tests would
use/allocate/iterate/create/destroy engine_data instead of
intel_execution_engine2.

Anyway, I'll keep it easy for now :)

Cheers,
Andi

> Don't worry about interrupted loops leaking, it's par for the course for
> igt_assert() as we don't have full setup/cleanup (igt_try {} igt_catch
> {} igt_finally {} anyone?).
> -Chris
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