* [igt-dev] [PATCH v14 0/5] new engine discovery interface
@ 2019-03-21 1:00 Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 1/5] lib/igt_gt: remove unnecessary argument Andi Shyti
` (6 more replies)
0 siblings, 7 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
Hi,
In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].
Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.
Andi
v13 --> v14
===========
PATCH v13: [15]
minor changes this time:
- squashed patch 2 and 3 (from v13) with a little rename and
added Chris r-b
- fixed some index issues and string assignement leaks
- squashed patches 5, 6, 7 and 8 from v13
v12 --> v13
===========
PATCH v12: [14]
This patch is also very different from the previous other than
some reorganization of the code these are the main changes:
- the previous version lacked the case when the context had its
engines mapped. checks in the following order
if the driver doesn't have the new API
-> get the engines from the static list
if the driver has the API but the context has nothing mapped
-> get the engines from "query" and map them
if the driver has the API and the context has engines mapped
-> get the engines from the context
- the helper functions have been removed as they were of no use.
v11 --> v12
===========
PATCH v11: [13]
This 12th version starts from a completely different thought.
Here's the main differences:
- The list of engines is provided in an engine_data structure
which contains an index (useful for looping through and for
engine/context index mapping) instead of an array of engines.
- The list of engines is generated every time the init function
is called and nothing is allocated in heap memory.
- The ioctl check is done already during the initialization part
and if the new ioctls are not implemented, then the init
function still stores only those present in the GPU.
- The for_each loop is implemented by re-using the previous
'for_each_engine_class_instance()' implemented by Tvrtko.
- The gem_topology library offers few helper functions for
checking the engine presence, checking the implementation of
the ioctls and executing the buffer, in order to be completely
unaware of the driver implementation.
Thanks Tvrtko for all your inputs.
v10 --> v11
===========
RFC v10: [12]
few cosmetic changes in v11 and minor architectural details.
Thanks Tvrtko.
- the 'query_engines()' functions are static as no one is using
them yet.
- removed the 'gem_has_engine_topology()' function because it's
very little used, 'get_active_engines()' can be used instead.
- a minor ring -> engine renaming coming from Chris.
v9 --> v10
==========
RFC v9: [11]
also this time quite many changes, thanks Chris for the reviews,
here the most relevant of them.
- gem_query.[ch] have been renamed to gem_engine_topology.[ch]
and all the functions ended up there as they are referring to
the topology of the engines.
- the functions 'get_active_engines()',
'gem_set_context_get_engines()' and
'igt_require_gem_engine_list()' will be the main interface to
the gem_engine_topology library, refer to patch 2 for details.
- the define 'for_each_engine2()' doesn't expose anymore the
iterator.
- 'gem_context_has_engine()' has been moved from ioctl_wrappers.c
to gem_context.c.
- the gem_exec_basic exec-ctx subtest does not abort if the new
getparam/setparam and query apis are not implemented as it can
work with both (as it was done at the beginning).
v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:
- all the allocation in gem_query have been made in stack, not
anymore allocated dynamically.
- removed get/set_context as it was already implemented and I
didn't know.
- renamed some functions and variables to hopefully more
meaningful names.
V7 --> v8
=========
RFC v7: [9]
- all functions have been moved from lib/igt_gt.{c,h} and
lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
Chris)
- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
be consistent with the '2' that indicates the new 'struct
intel_execution_engine2' data structure.
V6 --> V7
=========
RFC v6: [8]
- a new patch has been added (patch 3) which adds a new
requirement check through the igt_require_gem_engine_list()
function. (thanks Chris) This function will initialize the
engine list instead of the instead of igt_require_gem() as it
was in v6
- all the ioctls have been wrapped (thanks Chris and Antonio) and
new library functions have been added and assert the ioctls
- gem_init_engine_list() function returns the errno from the
GETPARAM ioctl in order to be used as a requirement. (thanks
Chris)
- fixed few requires/asserts
- The engine list "intel_active_engines2" is allocated of the
number of engines instead of a political 64 (thanks Antonio).
- some parameter renaming in gem_has_ring_by_idx(). (thanks
Chris).
- the original "intel_execution_engines2" has not been renamed,
because it is used to create subtests before even executing any
test/ioctl. By renaming it, some subtest generations failed.
(thanks Petri)
V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
to figure otu whether the new interface has been implemented.
This way the for_each_engine_ctx() is able to work with new and
old kernel uapi (thanks Chris)
V4 --> V5
=========
RFC v4: [6]
- the engine list is now built in 'igt_require_gem()' instead of
'__open_driver()' so that we keep this discovery method
specific to the i915 driver (thanks Chris).
- All the query/setparam structures dynamic allocation based on
the number of engines, now are politically allocated 64 times,
to avoid extra ioctl calls that retrieve the engine number
(thanks Chris)
- use igt_ioctl instead of ioctl (thanks Chris)
- allocate intel_execution_engines2 dynamically instead of
statically (thanks Tvrtko)
- simplify the test in 'gem_exec_basic()' so that simply checks
the presence of the engine instead of executing a buffer
(thank Chris)
- a new patch has been added (patch 3) that extends the
'gem_has_ring()' boolean function. The new version sets the
index as it's mapped in the kernel.The previous function is now
a wrapper to the new function.
V3 --> V4
=========
PATCH v3: [3]
- re-architectured the discovery mechanism based on Tvrtko's
sugestion and reviews.. In this version the discovery is done
during the device opening and stored in a NULL terminated
array, which replaces the existing intel_execution_engines2
that is mainly used as a reference.
V2 --> V3
=========
RFC v2: [2]
- removed a standalone gem_query_engines_demo test and added the
exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).
- fixed most of Tvrtko's comments in [5], which consist in
putting the mallocs igt_assert and ictls in igt_require and few
refactoring (thanks Tvrtko).
V1 --> V2
=========
RFC v1: [1]
- added a demo test that simply queries the driver about the
engines and executes a buffer (thanks Tvrtko)
- refactored the for_each_engine_ctx() macro so that what in the
previous version was done by the "bind" function, now it's done
in the first iteration. (Thanks Crhis)
- removed the "gem_has_ring_ctx()" because it was out of the
scope.
- rename functions to more meaningful names
[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html
[11] https://lists.freedesktop.org/archives/igt-dev/2019-February/009277.html
[12] https://lists.freedesktop.org/archives/igt-dev/2019-March/010197.html
[13] https://lists.freedesktop.org/archives/igt-dev/2019-March/010467.html
[14] https://lists.freedesktop.org/archives/igt-dev/2019-March/010776.html
[15] https://lists.freedesktop.org/archives/igt-dev/2019-March/010827.html
Andi Shyti (5):
lib/igt_gt: remove unnecessary argument
lib: ioctl_wrappers: reach engines by index as well
include/drm-uapi: import i915_drm.h header file
lib/i915: add gem_engine_topology library and for_each loop definition
tests: gem_exec_basic: add "exec-ctx" buffer execution demo test
include/drm-uapi/i915_drm.h | 361 +++++++++++++++++++++++++++------
lib/Makefile.sources | 2 +
lib/i915/gem_context.c | 21 ++
lib/i915/gem_context.h | 2 +
lib/i915/gem_engine_topology.c | 184 +++++++++++++++++
lib/i915/gem_engine_topology.h | 38 ++++
lib/igt_gt.h | 12 +-
lib/ioctl_wrappers.c | 19 --
lib/ioctl_wrappers.h | 3 +-
lib/meson.build | 1 +
tests/i915/gem_exec_basic.c | 13 ++
tests/perf_pmu.c | 12 +-
12 files changed, 581 insertions(+), 87 deletions(-)
create mode 100644 lib/i915/gem_engine_topology.c
create mode 100644 lib/i915/gem_engine_topology.h
--
2.20.1
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH v14 1/5] lib/igt_gt: remove unnecessary argument
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
@ 2019-03-21 1:00 ` Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
` (5 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
__for_each_engine_class_instance(fd, e) doesn't need and doesn't
use the fd argument. Remove it.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
lib/igt_gt.h | 2 +-
tests/perf_pmu.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..475c0b3c3cc6 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
igt_require(gem_has_engine(gem_fd, class, instance));
}
-#define __for_each_engine_class_instance(fd__, e__) \
+#define __for_each_engine_class_instance(e__) \
for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
#define for_each_engine_class_instance(fd__, e__) \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 1a08f564b066..4f552bc2ae28 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1693,7 +1693,7 @@ igt_main
igt_subtest("invalid-init")
invalid_init();
- __for_each_engine_class_instance(fd, e) {
+ __for_each_engine_class_instance(e) {
const unsigned int pct[] = { 2, 50, 98 };
/**
@@ -1897,7 +1897,7 @@ igt_main
gem_quiescent_gpu(fd);
}
- __for_each_engine_class_instance(render_fd, e) {
+ __for_each_engine_class_instance(e) {
igt_subtest_group {
igt_fixture {
gem_require_engine(render_fd,
--
2.20.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 1/5] lib/igt_gt: remove unnecessary argument Andi Shyti
@ 2019-03-21 1:00 ` Andi Shyti
2019-03-21 1:05 ` Chris Wilson
2019-03-21 7:06 ` Tvrtko Ursulin
2019-03-21 1:00 ` [igt-dev] [PATCH v14 3/5] include/drm-uapi: import i915_drm.h header file Andi Shyti
` (4 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
With the new engine query method engines are reachable through
an index and context they are combined with.
The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.
The function has been moved from lib/ioctl_wappers to
lib/i915/gem_context where it is more appropriate.
The previous 'gem_has_ring()' function becomes a wrapper to the
new 'gem_context_has_engine()'.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/i915/gem_context.c | 21 +++++++++++++++++++++
lib/i915/gem_context.h | 2 ++
lib/ioctl_wrappers.c | 19 -------------------
lib/ioctl_wrappers.h | 3 ++-
4 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 16004685e920..5e2e31e91384 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
{
igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
}
+
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
+{
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 exec;
+
+ /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
+ if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+ if (engine & (3 << 13) && !gem_has_bsd2(fd))
+ return false;
+ }
+
+ memset(&exec, 0, sizeof(exec));
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&exec);
+ execbuf.buffer_count = 1;
+ execbuf.flags = engine;
+ execbuf.rsvd1 = ctx;
+
+ return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..dd64ebf17fbd 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
void gem_context_set_priority(int fd, uint32_t ctx, int prio);
+bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
+
#endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a66eb4bc0f4f..3f8f0874bc4b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
}
-bool gem_has_ring(int fd, unsigned ring)
-{
- struct drm_i915_gem_execbuffer2 execbuf;
- struct drm_i915_gem_exec_object2 exec;
-
- /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
- if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
- if (ring & (3 << 13) && !gem_has_bsd2(fd))
- return false;
- }
-
- memset(&exec, 0, sizeof(exec));
- memset(&execbuf, 0, sizeof(execbuf));
- execbuf.buffers_ptr = to_user_pointer(&exec);
- execbuf.buffer_count = 1;
- execbuf.flags = ring;
- return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
/**
* gem_require_ring:
* @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ad93daffcfd5..8770e591e790 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
/* check functions which auto-skip tests by calling igt_skip() */
void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
void gem_require_ring(int fd, unsigned ring);
bool gem_has_mocs_registers(int fd);
void gem_require_mocs_registers(int fd);
+#define gem_has_ring(f, r) gem_context_has_engine(f, r, 0)
+
/* prime */
struct local_dma_buf_sync {
uint64_t flags;
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH v14 3/5] include/drm-uapi: import i915_drm.h header file
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 1/5] lib/igt_gt: remove unnecessary argument Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
@ 2019-03-21 1:00 ` Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
` (3 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
include/drm-uapi/i915_drm.h | 361 ++++++++++++++++++++++++++++++------
1 file changed, 304 insertions(+), 57 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 4ae1c6ff6ae6..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+ __u64 next_extension;
+ __u64 name;
+};
+
/*
* MOCS indexes used for GPU surfaces, defining the cacheability of the
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -104,6 +124,9 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_INVALID = -1
};
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
@@ -321,6 +344,8 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
+#define DRM_I915_GEM_VM_CREATE 0x3a
+#define DRM_I915_GEM_VM_DESTROY 0x3b
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -370,6 +395,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -380,6 +406,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -563,6 +591,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1085,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT (1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1421,65 +1464,18 @@ struct drm_i915_gem_wait {
};
struct drm_i915_gem_context_create {
- /* output: id of new context*/
- __u32 ctx_id;
- __u32 pad;
-};
-
-struct drm_i915_gem_context_destroy {
- __u32 ctx_id;
- __u32 pad;
-};
-
-struct drm_i915_reg_read {
- /*
- * Register offset.
- * For 64bit wide registers where the upper 32bits don't immediately
- * follow the lower 32bits, the offset of the lower 32bits must
- * be specified
- */
- __u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
- __u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- * single instruction 8byte read, in order to workaround that pass
- * flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
- __u32 ctx_id;
- __u32 flags;
-
- /* All resets since boot/module reload, for all contexts */
- __u32 reset_count;
-
- /* Number of batches lost when active in GPU, for this context */
- __u32 batch_active;
-
- /* Number of batches lost pending for execution, for this context */
- __u32 batch_pending;
-
+ __u32 ctx_id; /* output: id of new context*/
__u32 pad;
};
-struct drm_i915_gem_userptr {
- __u64 user_ptr;
- __u64 user_size;
+struct drm_i915_gem_context_create_ext {
+ __u32 ctx_id; /* output: id of new context*/
__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
- /**
- * Returned handle for the object.
- *
- * Object handles are nonzero.
- */
- __u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+ (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+ __u64 extensions;
};
struct drm_i915_gem_context_param {
@@ -1520,7 +1516,43 @@ struct drm_i915_gem_context_param {
* On creation, all new contexts are marked as recoverable.
*/
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
+
+ /*
+ * The id of the associated virtual memory address space (ppGTT) of
+ * this context. Can be retrieved and passed to another context
+ * (on the same fd) for both to use the same ppGTT and so share
+ * address layouts, and avoid reloading the page tables on context
+ * switches between themselves.
+ *
+ * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+ */
+#define I915_CONTEXT_PARAM_VM 0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ * engine_class: I915_ENGINE_CLASS_INVALID,
+ * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES 0xa
/* Must be kept compact -- no holes and well documented */
+
__u64 value;
};
@@ -1553,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
- * Unused for now. Must be cleared to zero.
+ * Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
@@ -1583,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+ struct i915_user_extension base;
+
+ __u16 engine_index;
+ __u16 mbz16; /* reserved for future use; must be zero */
+ __u32 flags; /* all undefined flags must be zero */
+
+ __u64 engines_mask; /* selection mask of engines[] */
+
+ __u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+ struct i915_user_extension base;
+
+ __u16 engine_index;
+ __u16 mbz;
+
+ __u16 master_class;
+ __u16 master_instance;
+
+ __u64 sibling_mask;
+ __u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+ __u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+ struct {
+ __u16 engine_class; /* see enum drm_i915_gem_engine_class */
+ __u16 engine_instance;
+ } class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+ __u64 extensions; \
+ struct { \
+ __u16 engine_class; \
+ __u16 engine_instance; \
+ } class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+ struct i915_user_extension base;
+ struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+ struct i915_user_extension base;
+ __u32 clone_id;
+ __u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS (1u << 0)
+#define I915_CONTEXT_CLONE_SCHED (1u << 1)
+#define I915_CONTEXT_CLONE_SSEU (1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE (1u << 3)
+#define I915_CONTEXT_CLONE_VM (1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES (1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+ __u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+ __u32 ctx_id;
+ __u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+ __u64 extensions;
+ __u32 flags;
+ __u32 id;
+};
+
+struct drm_i915_reg_read {
+ /*
+ * Register offset.
+ * For 64bit wide registers where the upper 32bits don't immediately
+ * follow the lower 32bits, the offset of the lower 32bits must
+ * be specified
+ */
+ __u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+ __u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ * single instruction 8byte read, in order to workaround that pass
+ * flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+ __u32 ctx_id;
+ __u32 flags;
+
+ /* All resets since boot/module reload, for all contexts */
+ __u32 reset_count;
+
+ /* Number of batches lost when active in GPU, for this context */
+ __u32 batch_active;
+
+ /* Number of batches lost pending for execution, for this context */
+ __u32 batch_pending;
+
+ __u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+ __u64 user_ptr;
+ __u64 user_size;
+ __u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
@@ -1744,6 +1946,7 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
/* Must be kept compact -- no holes and well documented */
/*
@@ -1842,6 +2045,50 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+ /** Engine class as in enum drm_i915_gem_engine_class. */
+ __u16 engine_class;
+
+ /** Engine instance number. */
+ __u16 engine_instance;
+
+ /** Reserved field. */
+ __u32 rsvd0;
+
+ /** Engine flags. */
+ __u64 flags;
+
+ /** Capabilities of this engine. */
+ __u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
+
+ /** Reserved fields. */
+ __u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+ /** Number of struct drm_i915_engine_info structs following. */
+ __u32 num_engines;
+
+ /** MBZ */
+ __u32 rsvd[3];
+
+ /** Marker for drm_i915_engine_info structures. */
+ struct drm_i915_engine_info engines[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.20.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
` (2 preceding siblings ...)
2019-03-21 1:00 ` [igt-dev] [PATCH v14 3/5] include/drm-uapi: import i915_drm.h header file Andi Shyti
@ 2019-03-21 1:00 ` Andi Shyti
2019-03-21 7:18 ` Tvrtko Ursulin
2019-03-21 7:32 ` Chris Wilson
2019-03-21 1:00 ` [igt-dev] [PATCH v14 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test Andi Shyti
` (2 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.
The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.
The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.
Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()'.
Update accordingly tests/perf_pmu.c, that uses the
'for_each_engine_class_instance()' loop.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
lib/Makefile.sources | 2 +
lib/i915/gem_engine_topology.c | 184 +++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 38 +++++++
lib/igt_gt.h | 10 +-
lib/meson.build | 1 +
tests/perf_pmu.c | 8 +-
6 files changed, 236 insertions(+), 7 deletions(-)
create mode 100644 lib/i915/gem_engine_topology.c
create mode 100644 lib/i915/gem_engine_topology.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list = \
i915/gem_ring.c \
i915/gem_mman.c \
i915/gem_mman.h \
+ i915/gem_engine_topology.c \
+ i915/gem_engine_topology.h \
i915_3d.h \
i915_reg.h \
i915_pciids.h \
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..791af8777956
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
+ class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
+ engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+ int err = 0;
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+ err = -errno;
+
+ errno = 0;
+ return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+ igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+ struct drm_i915_query_engine_info *query_engines)
+{
+ struct drm_i915_query_item item = { };
+ struct drm_i915_query query = { };
+
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ query.items_ptr = to_user_pointer(&item);
+ query.num_items = 1;
+ item.length = SIZEOF_QUERY;
+
+ item.data_ptr = to_user_pointer(query_engines);
+
+ gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+ struct drm_i915_gem_context_param *ctx_param)
+{
+ struct i915_context_param_engines *ctx_engine =
+ (struct i915_context_param_engines*) ctx_param->value;
+ int i = 0;
+
+ for (typeof(ctx_engine->class_instance[0]) *p =
+ &ctx_engine->class_instance[0];
+ i < ed->nengines; i++, p++) {
+ p->engine_class = ed->engines[i].class;
+ p->engine_instance = ed->engines[i].instance;
+ }
+
+ ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
+
+ gem_context_set_param(fd, ctx_param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2, const char *name,
+ uint16_t class, uint16_t instance, uint8_t flags)
+{
+ static const char *unk_name = "unk";
+
+ e2->class = class;
+ e2->instance = instance;
+ e2->flags = flags;
+
+ if (name) {
+ e2->name = name;
+ } else {
+ const struct intel_execution_engine2 *__e2;
+
+ __for_each_engine_class_instance(__e2)
+ if (__e2->class == class && __e2->instance == instance)
+ break;
+
+ e2->name = __e2->name ? __e2->name : unk_name;
+ }
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+ uint8_t query_buffer[SIZEOF_QUERY] = { };
+ struct drm_i915_query_engine_info *query_engine =
+ (struct drm_i915_query_engine_info *) query_buffer;
+ int i;
+
+ query_engines(fd, query_engine);
+
+ for (i = 0; i < query_engine->num_engines; i++)
+ init_engine(&ed->engines[i], NULL,
+ query_engine->engines[i].engine_class,
+ query_engine->engines[i].engine_instance, i);
+
+ ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+ struct intel_engine_data engine_data;
+ uint8_t buff[SIZEOF_CTX_PARAM] = { };
+
+ struct i915_context_param_engines *engines =
+ (struct i915_context_param_engines *) buff;
+
+ struct drm_i915_gem_context_param param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .ctx_id = ctx_id,
+ .size = SIZEOF_CTX_PARAM,
+ .value = to_user_pointer(engines),
+ };
+
+ int i;
+
+ if (__gem_context_get_param(fd, ¶m)) {
+ /* if kernel does not support engine/context mapping */
+ const struct intel_execution_engine2 *e2;
+
+ igt_debug("using pre-allocated engine list\n");
+
+ __for_each_engine_class_instance(e2) {
+ uint64_t flags;
+
+ if (!gem_has_engine(fd, e2->class, e2->instance))
+ continue;
+
+ flags = gem_class_instance_to_eb_flags(fd, e2->class,
+ e2->instance);
+
+ init_engine(&engine_data.engines[engine_data.nengines],
+ e2->name, e2->class, e2->instance, flags);
+
+ engine_data.nengines++;
+ }
+
+ } else if (!param.size) {
+ /* else if context doesn't have mapped engines */
+ query_engine_list(fd, &engine_data);
+ ctx_map_engines(fd, &engine_data, ¶m);
+
+ } else {
+ /* context has a list of mapped engines */
+
+ uint8_t nengines = (param.size -
+ sizeof(struct i915_context_param_engines)) /
+ sizeof(engines->class_instance[0]);
+
+ for (i = 0; i < nengines; i++)
+ init_engine(&engine_data.engines[i], NULL,
+ engines->class_instance[i].engine_class,
+ engines->class_instance[i].engine_instance,
+ i);
+
+ engine_data.nengines = i;
+ }
+
+ return engine_data;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..31fa3dcaa48c
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "i915_drm.h"
+#include "igt_gt.h"
+
+struct intel_engine_data {
+ uint32_t nengines;
+ uint32_t n;
+ struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..84ea4af5392d 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
const char *name;
int class;
int instance;
+ uint64_t flags;
} intel_execution_engines2[];
unsigned int
@@ -117,8 +118,11 @@ void gem_require_engine(int gem_fd,
#define __for_each_engine_class_instance(e__) \
for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-#define for_each_engine_class_instance(fd__, e__) \
- for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
- for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+#include "i915/gem_engine_topology.h"
+
+#define for_each_engine_class_instance(fd__, ctx__, e__) \
+ for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+ ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
+ i__.n++)
#endif /* IGT_GT_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
'i915/gem_submission.c',
'i915/gem_ring.c',
'i915/gem_mman.c',
+ 'i915/gem_engine_topology.c',
'igt_color_encoding.c',
'igt_debugfs.c',
'igt_device.c',
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4f552bc2ae28..c9c63405cdde 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
i = 0;
fd[0] = -1;
- for_each_engine_class_instance(gem_fd, e_) {
+ for_each_engine_class_instance(gem_fd, 0, e_) {
if (e == e_)
busy_idx = i;
@@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
unsigned int idle_idx, i;
i = 0;
- for_each_engine_class_instance(gem_fd, e_) {
+ for_each_engine_class_instance(gem_fd, 0, e_) {
if (e == e_)
idle_idx = i;
else if (spin)
@@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
unsigned int i;
i = 0;
- for_each_engine_class_instance(gem_fd, e) {
+ for_each_engine_class_instance(gem_fd, 0, e) {
if (spin)
__submit_spin_batch(gem_fd, spin, e, 64);
else
@@ -1683,7 +1683,7 @@ igt_main
igt_require_gem(fd);
igt_require(i915_type_id() > 0);
- for_each_engine_class_instance(fd, e)
+ for_each_engine_class_instance(fd, 0, e)
num_engines++;
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [igt-dev] [PATCH v14 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
` (3 preceding siblings ...)
2019-03-21 1:00 ` [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
@ 2019-03-21 1:00 ` Andi Shyti
2019-03-21 1:29 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
2019-03-21 9:01 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 1:00 UTC (permalink / raw)
To: IGT dev; +Cc: Andi Shyti
The "exec-ctx" is a demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with 'gem_topology_has_engine()'.
The "exec-ctx" subtest simply gets the list of engines, binds
them to a context and executes a buffer. This is done through a
new "for_each_engine2" loop which iterates through the
engines.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
tests/i915/gem_exec_basic.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..c4a489bdd100 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,19 @@ igt_main
gtt(fd, e->exec_id | e->flags);
}
+ igt_subtest("exec-ctx") {
+ uint32_t ctx_id;
+ struct intel_execution_engine2 *e2;
+
+ ctx_id = gem_context_create(fd);
+
+ for_each_engine_class_instance(fd, ctx_id, e2)
+ igt_assert(gem_context_has_engine(fd, e2->flags,
+ ctx_id));
+
+ gem_context_destroy(fd, ctx_id);
+ }
+
igt_fixture {
igt_stop_hang_detector();
close(fd);
--
2.20.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well
2019-03-21 1:00 ` [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
@ 2019-03-21 1:05 ` Chris Wilson
2019-03-21 10:12 ` Andi Shyti
2019-03-21 7:06 ` Tvrtko Ursulin
1 sibling, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2019-03-21 1:05 UTC (permalink / raw)
To: Andi Shyti, IGT dev; +Cc: Andi Shyti
Quoting Andi Shyti (2019-03-21 01:00:12)
> With the new engine query method engines are reachable through
> an index and context they are combined with.
>
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> The function has been moved from lib/ioctl_wappers to
> lib/i915/gem_context where it is more appropriate.
>
> The previous 'gem_has_ring()' function becomes a wrapper to the
> new 'gem_context_has_engine()'.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> lib/i915/gem_context.c | 21 +++++++++++++++++++++
> lib/i915/gem_context.h | 2 ++
> lib/ioctl_wrappers.c | 19 -------------------
> lib/ioctl_wrappers.h | 3 ++-
> 4 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
> index 16004685e920..5e2e31e91384 100644
> --- a/lib/i915/gem_context.c
> +++ b/lib/i915/gem_context.c
> @@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
> {
> igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
> }
> +
> +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
It's still BACKWARDS!!!!
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
` (4 preceding siblings ...)
2019-03-21 1:00 ` [igt-dev] [PATCH v14 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test Andi Shyti
@ 2019-03-21 1:29 ` Patchwork
2019-03-21 9:01 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-03-21 1:29 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/58304/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5785 -> IGTPW_2676
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58304/revisions/1/mbox/
Known issues
------------
Here are the changes found in IGTPW_2676 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: PASS -> DMESG-FAIL [fdo#110210]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182] +1
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: FAIL [fdo#104008] -> PASS
#### Warnings ####
* igt@i915_selftest@live_contexts:
- fi-icl-u3: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569]
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (47 -> 40)
------------------------------
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* IGT: IGT_4894 -> IGTPW_2676
CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2676: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2676/
IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_exec_basic@exec-ctx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2676/
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well
2019-03-21 1:00 ` [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
2019-03-21 1:05 ` Chris Wilson
@ 2019-03-21 7:06 ` Tvrtko Ursulin
1 sibling, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2019-03-21 7:06 UTC (permalink / raw)
To: Andi Shyti, IGT dev; +Cc: Andi Shyti
On 21/03/2019 01:00, Andi Shyti wrote:
> With the new engine query method engines are reachable through
> an index and context they are combined with.
>
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> The function has been moved from lib/ioctl_wappers to
> lib/i915/gem_context where it is more appropriate.
>
> The previous 'gem_has_ring()' function becomes a wrapper to the
> new 'gem_context_has_engine()'.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> lib/i915/gem_context.c | 21 +++++++++++++++++++++
> lib/i915/gem_context.h | 2 ++
> lib/ioctl_wrappers.c | 19 -------------------
> lib/ioctl_wrappers.h | 3 ++-
> 4 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
> index 16004685e920..5e2e31e91384 100644
> --- a/lib/i915/gem_context.c
> +++ b/lib/i915/gem_context.c
> @@ -275,3 +275,24 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
> {
> igt_assert(__gem_context_set_priority(fd, ctx_id, prio) == 0);
> }
> +
> +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
What Chris said and uin32_t for ctx is the usual type.
> +{
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 exec;
> +
> + /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
> + if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
> + if (engine & (3 << 13) && !gem_has_bsd2(fd))
> + return false;
> + }
This will luckily be a no-op on engine maps due bits so high never set
but I wonder if at least a comment is warranted.
Regards,
Tvrtko
> +
> + memset(&exec, 0, sizeof(exec));
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = to_user_pointer(&exec);
> + execbuf.buffer_count = 1;
> + execbuf.flags = engine;
> + execbuf.rsvd1 = ctx;
> +
> + return __gem_execbuf(fd, &execbuf) == -ENOENT;
> +}
> diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
> index aef68dda6b26..dd64ebf17fbd 100644
> --- a/lib/i915/gem_context.h
> +++ b/lib/i915/gem_context.h
> @@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
> int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
> void gem_context_set_priority(int fd, uint32_t ctx, int prio);
>
> +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx);
> +
> #endif /* GEM_CONTEXT_H */
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index a66eb4bc0f4f..3f8f0874bc4b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
> igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
> }
>
> -bool gem_has_ring(int fd, unsigned ring)
> -{
> - struct drm_i915_gem_execbuffer2 execbuf;
> - struct drm_i915_gem_exec_object2 exec;
> -
> - /* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
> - if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
> - if (ring & (3 << 13) && !gem_has_bsd2(fd))
> - return false;
> - }
> -
> - memset(&exec, 0, sizeof(exec));
> - memset(&execbuf, 0, sizeof(execbuf));
> - execbuf.buffers_ptr = to_user_pointer(&exec);
> - execbuf.buffer_count = 1;
> - execbuf.flags = ring;
> - return __gem_execbuf(fd, &execbuf) == -ENOENT;
> -}
> -
> /**
> * gem_require_ring:
> * @fd: open i915 drm file descriptor
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index ad93daffcfd5..8770e591e790 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
>
> /* check functions which auto-skip tests by calling igt_skip() */
> void gem_require_caching(int fd);
> -bool gem_has_ring(int fd, unsigned ring);
> void gem_require_ring(int fd, unsigned ring);
> bool gem_has_mocs_registers(int fd);
> void gem_require_mocs_registers(int fd);
>
> +#define gem_has_ring(f, r) gem_context_has_engine(f, r, 0)
> +
> /* prime */
> struct local_dma_buf_sync {
> uint64_t flags;
>
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igt-dev@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 1:00 ` [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
@ 2019-03-21 7:18 ` Tvrtko Ursulin
2019-03-21 11:23 ` Andi Shyti
2019-03-21 7:32 ` Chris Wilson
1 sibling, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2019-03-21 7:18 UTC (permalink / raw)
To: Andi Shyti, IGT dev; +Cc: Andi Shyti
On 21/03/2019 01:00, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
>
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
>
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
>
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()'.
>
> Update accordingly tests/perf_pmu.c, that uses the
> 'for_each_engine_class_instance()' loop.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
> lib/Makefile.sources | 2 +
> lib/i915/gem_engine_topology.c | 184 +++++++++++++++++++++++++++++++++
> lib/i915/gem_engine_topology.h | 38 +++++++
> lib/igt_gt.h | 10 +-
> lib/meson.build | 1 +
> tests/perf_pmu.c | 8 +-
> 6 files changed, 236 insertions(+), 7 deletions(-)
> create mode 100644 lib/i915/gem_engine_topology.c
> create mode 100644 lib/i915/gem_engine_topology.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list = \
> i915/gem_ring.c \
> i915/gem_mman.c \
> i915/gem_mman.h \
> + i915/gem_engine_topology.c \
> + i915/gem_engine_topology.h \
> i915_3d.h \
> i915_reg.h \
> i915_pciids.h \
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..791af8777956
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
> + class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
> + engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> + int err = 0;
> +
> + if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> + err = -errno;
> +
> + errno = 0;
> + return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> + igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> + struct drm_i915_query_engine_info *query_engines)
> +{
> + struct drm_i915_query_item item = { };
> + struct drm_i915_query query = { };
> +
> + item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> + query.items_ptr = to_user_pointer(&item);
> + query.num_items = 1;
> + item.length = SIZEOF_QUERY;
> +
> + item.data_ptr = to_user_pointer(query_engines);
> +
> + gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> + struct drm_i915_gem_context_param *ctx_param)
> +{
> + struct i915_context_param_engines *ctx_engine =
> + (struct i915_context_param_engines*) ctx_param->value;
> + int i = 0;
> +
> + for (typeof(ctx_engine->class_instance[0]) *p =
> + &ctx_engine->class_instance[0];
> + i < ed->nengines; i++, p++) {
> + p->engine_class = ed->engines[i].class;
> + p->engine_instance = ed->engines[i].instance;
> + }
> +
> + ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
> +
> + gem_context_set_param(fd, ctx_param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> + uint16_t class, uint16_t instance, uint8_t flags)
I'd probably use u64 for flags to match the structure.
> +{
> + static const char *unk_name = "unk";
> +
> + e2->class = class;
> + e2->instance = instance;
> + e2->flags = flags;
> +
> + if (name) {
> + e2->name = name;
This path is used only for the legacy fall back mode so I am
contemplating whether is is even worth having the name passed in.
The if you find a virtual engine in the list (
I915_ENGINE_CLASS_INVALID/I915_ENGINE_CLASS_INVALID_VIRTUAL) you could
set the name to "virtual" or something.
Now listen to this.. how about we export the engine names via the query
API? Primarily I was thinking to distinguish difference instance of
virtual, but then it would also lessen the reliance on the static map.
Thoughts?
> + } else {
> + const struct intel_execution_engine2 *__e2;
> +
> + __for_each_engine_class_instance(__e2)
> + if (__e2->class == class && __e2->instance == instance)
> + break;
> +
> + e2->name = __e2->name ? __e2->name : unk_name;
> + }
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> + uint8_t query_buffer[SIZEOF_QUERY] = { };
> + struct drm_i915_query_engine_info *query_engine =
> + (struct drm_i915_query_engine_info *) query_buffer;
> + int i;
> +
> + query_engines(fd, query_engine);
> +
> + for (i = 0; i < query_engine->num_engines; i++)
> + init_engine(&ed->engines[i], NULL,
> + query_engine->engines[i].engine_class,
> + query_engine->engines[i].engine_instance, i);
> +
> + ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> + struct intel_engine_data engine_data;
> + uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +
> + struct i915_context_param_engines *engines =
> + (struct i915_context_param_engines *) buff;
> +
> + struct drm_i915_gem_context_param param = {
> + .param = I915_CONTEXT_PARAM_ENGINES,
> + .ctx_id = ctx_id,
> + .size = SIZEOF_CTX_PARAM,
> + .value = to_user_pointer(engines),
> + };
> +
> + int i;
> +
> + if (__gem_context_get_param(fd, ¶m)) {
> + /* if kernel does not support engine/context mapping */
> + const struct intel_execution_engine2 *e2;
> +
> + igt_debug("using pre-allocated engine list\n");
> +
> + __for_each_engine_class_instance(e2) {
> + uint64_t flags;
> +
> + if (!gem_has_engine(fd, e2->class, e2->instance))
> + continue;
> +
> + flags = gem_class_instance_to_eb_flags(fd, e2->class,
> + e2->instance);
> +
> + init_engine(&engine_data.engines[engine_data.nengines],
> + e2->name, e2->class, e2->instance, flags);
> +
> + engine_data.nengines++;
> + }
> +
> + } else if (!param.size) {
> + /* else if context doesn't have mapped engines */
> + query_engine_list(fd, &engine_data);
> + ctx_map_engines(fd, &engine_data, ¶m);
> +
> + } else {
> + /* context has a list of mapped engines */
> +
> + uint8_t nengines = (param.size -
> + sizeof(struct i915_context_param_engines)) /
> + sizeof(engines->class_instance[0]);
I'd probably just use unsigned int.
> +
> + for (i = 0; i < nengines; i++)
> + init_engine(&engine_data.engines[i], NULL,
> + engines->class_instance[i].engine_class,
> + engines->class_instance[i].engine_instance,
> + i);
> +
> + engine_data.nengines = i;
> + }
> +
> + return engine_data;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..31fa3dcaa48c
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "i915_drm.h"
> +#include "igt_gt.h"
> +
> +struct intel_engine_data {
> + uint32_t nengines;
> + uint32_t n;
> + struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..84ea4af5392d 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
> const char *name;
> int class;
> int instance;
> + uint64_t flags;
> } intel_execution_engines2[];
>
> unsigned int
> @@ -117,8 +118,11 @@ void gem_require_engine(int gem_fd,
> #define __for_each_engine_class_instance(e__) \
> for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
>
> -#define for_each_engine_class_instance(fd__, e__) \
> - for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> - for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> +#include "i915/gem_engine_topology.h"
> +
> +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> + for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> + ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> + i__.n++)
Do we want a context parameter in this helper, or even this helper at
all? I thought we can end up with only two, for_each_physical_engine and
for_each_context_engine - but I guess it is open for discussion.
>
> #endif /* IGT_GT_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 0eb5585d72b9..3cc52f97c8bf 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
> 'i915/gem_submission.c',
> 'i915/gem_ring.c',
> 'i915/gem_mman.c',
> + 'i915/gem_engine_topology.c',
> 'igt_color_encoding.c',
> 'igt_debugfs.c',
> 'igt_device.c',
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 4f552bc2ae28..c9c63405cdde 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> i = 0;
> fd[0] = -1;
> - for_each_engine_class_instance(gem_fd, e_) {
> + for_each_engine_class_instance(gem_fd, 0, e_) {
> if (e == e_)
> busy_idx = i;
>
> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> unsigned int idle_idx, i;
>
> i = 0;
> - for_each_engine_class_instance(gem_fd, e_) {
> + for_each_engine_class_instance(gem_fd, 0, e_) {
> if (e == e_)
> idle_idx = i;
> else if (spin)
> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
> unsigned int i;
>
> i = 0;
> - for_each_engine_class_instance(gem_fd, e) {
> + for_each_engine_class_instance(gem_fd, 0, e) {
> if (spin)
> __submit_spin_batch(gem_fd, spin, e, 64);
> else
> @@ -1683,7 +1683,7 @@ igt_main
> igt_require_gem(fd);
> igt_require(i915_type_id() > 0);
>
> - for_each_engine_class_instance(fd, e)
> + for_each_engine_class_instance(fd, 0, e)
> num_engines++;
> }
>
>
Looks like this would work. Just the question of virtual engine, set of
chosen iterators, and maybe some nits.
Regards,
Tvrtko
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 1:00 ` [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
2019-03-21 7:18 ` Tvrtko Ursulin
@ 2019-03-21 7:32 ` Chris Wilson
2019-03-21 11:38 ` Andi Shyti
1 sibling, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2019-03-21 7:32 UTC (permalink / raw)
To: Andi Shyti, IGT dev; +Cc: Andi Shyti
Quoting Andi Shyti (2019-03-21 01:00:14)
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
>
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
>
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
>
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()'.
>
> Update accordingly tests/perf_pmu.c, that uses the
> 'for_each_engine_class_instance()' loop.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
> lib/Makefile.sources | 2 +
> lib/i915/gem_engine_topology.c | 184 +++++++++++++++++++++++++++++++++
> lib/i915/gem_engine_topology.h | 38 +++++++
> lib/igt_gt.h | 10 +-
> lib/meson.build | 1 +
> tests/perf_pmu.c | 8 +-
> 6 files changed, 236 insertions(+), 7 deletions(-)
> create mode 100644 lib/i915/gem_engine_topology.c
> create mode 100644 lib/i915/gem_engine_topology.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index cf2720981707..757bd7a17ebe 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list = \
> i915/gem_ring.c \
> i915/gem_mman.c \
> i915/gem_mman.h \
> + i915/gem_engine_topology.c \
> + i915/gem_engine_topology.h \
> i915_3d.h \
> i915_reg.h \
> i915_pciids.h \
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..791af8777956
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
> + class_instance[I915_EXEC_RING_MASK + 1])
> +#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
> + engines[I915_EXEC_RING_MASK + 1])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> + int err = 0;
> +
> + if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> + err = -errno;
> +
> + errno = 0;
> + return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> + igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> + struct drm_i915_query_engine_info *query_engines)
Pass in the length of the query_engines block i.e. don't just assume
item.length. And I'm still worrying about what happens when it is
greater than 64 engines.
> +{
> + struct drm_i915_query_item item = { };
> + struct drm_i915_query query = { };
> +
> + item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> + query.items_ptr = to_user_pointer(&item);
> + query.num_items = 1;
> + item.length = SIZEOF_QUERY;
> +
> + item.data_ptr = to_user_pointer(query_engines);
> +
> + gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> + struct drm_i915_gem_context_param *ctx_param)
> +{
> + struct i915_context_param_engines *ctx_engine =
> + (struct i915_context_param_engines*) ctx_param->value;
> + int i = 0;
> +
> + for (typeof(ctx_engine->class_instance[0]) *p =
> + &ctx_engine->class_instance[0];
> + i < ed->nengines; i++, p++) {
> + p->engine_class = ed->engines[i].class;
> + p->engine_instance = ed->engines[i].instance;
> + }
> +
> + ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
> +
> + gem_context_set_param(fd, ctx_param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> + uint16_t class, uint16_t instance, uint8_t flags)
> +{
> + static const char *unk_name = "unk";
> +
> + e2->class = class;
> + e2->instance = instance;
> + e2->flags = flags;
> +
> + if (name) {
> + e2->name = name;
> + } else {
> + const struct intel_execution_engine2 *__e2;
> +
> + __for_each_engine_class_instance(__e2)
> + if (__e2->class == class && __e2->instance == instance)
> + break;
> +
> + e2->name = __e2->name ? __e2->name : unk_name;
> + }
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> + uint8_t query_buffer[SIZEOF_QUERY] = { };
> + struct drm_i915_query_engine_info *query_engine =
> + (struct drm_i915_query_engine_info *) query_buffer;
> + int i;
> +
> + query_engines(fd, query_engine);
> +
> + for (i = 0; i < query_engine->num_engines; i++)
> + init_engine(&ed->engines[i], NULL,
> + query_engine->engines[i].engine_class,
> + query_engine->engines[i].engine_instance, i);
> +
> + ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> + struct intel_engine_data engine_data;
> + uint8_t buff[SIZEOF_CTX_PARAM] = { };
> +
> + struct i915_context_param_engines *engines =
> + (struct i915_context_param_engines *) buff;
> +
> + struct drm_i915_gem_context_param param = {
> + .param = I915_CONTEXT_PARAM_ENGINES,
> + .ctx_id = ctx_id,
> + .size = SIZEOF_CTX_PARAM,
> + .value = to_user_pointer(engines),
> + };
> +
> + int i;
> +
> + if (__gem_context_get_param(fd, ¶m)) {
> + /* if kernel does not support engine/context mapping */
We also take this path if we have more than 64 engines.
> + const struct intel_execution_engine2 *e2;
> +
> + igt_debug("using pre-allocated engine list\n");
> +
> + __for_each_engine_class_instance(e2) {
> + uint64_t flags;
> +
> + if (!gem_has_engine(fd, e2->class, e2->instance))
> + continue;
> +
> + flags = gem_class_instance_to_eb_flags(fd, e2->class,
> + e2->instance);
You added the field to the static struct, you might as well populate it
as well, and just use e2->flags. And then you wouldn't even need to
repeat the computation for gem_has_engine.
> + init_engine(&engine_data.engines[engine_data.nengines],
> + e2->name, e2->class, e2->instance, flags);
> +
> + engine_data.nengines++;
engine_data was never zeroed.
> + }
> +
> + } else if (!param.size) {
> + /* else if context doesn't have mapped engines */
> + query_engine_list(fd, &engine_data);
> + ctx_map_engines(fd, &engine_data, ¶m);
Why isn't this just memset(&engine_data, 0, sizeof(engine_data)) ?
> + } else {
> + /* context has a list of mapped engines */
> +
> + uint8_t nengines = (param.size -
> + sizeof(struct i915_context_param_engines)) /
> + sizeof(engines->class_instance[0]);
> +
> + for (i = 0; i < nengines; i++)
> + init_engine(&engine_data.engines[i], NULL,
> + engines->class_instance[i].engine_class,
> + engines->class_instance[i].engine_instance,
> + i);
> +
> + engine_data.nengines = i;
> + }
> +
> + return engine_data;
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..31fa3dcaa48c
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "i915_drm.h"
> +#include "igt_gt.h"
> +
> +struct intel_engine_data {
> + uint32_t nengines;
> + uint32_t n;
> + struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..84ea4af5392d 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
And we need to break away from igt_gt.h, these will all be good inside
gem_engine_topology.h I think.
> @@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
> const char *name;
> int class;
> int instance;
> + uint64_t flags;
> } intel_execution_engines2[];
>
> unsigned int
> @@ -117,8 +118,11 @@ void gem_require_engine(int gem_fd,
> #define __for_each_engine_class_instance(e__) \
> for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
>
> -#define for_each_engine_class_instance(fd__, e__) \
> - for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> - for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> +#include "i915/gem_engine_topology.h"
> +
> +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> + for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> + ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> + i__.n++)
for (...; \
...; \
...)
^ align with (
-Chris
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
` (5 preceding siblings ...)
2019-03-21 1:29 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
@ 2019-03-21 9:01 ` Patchwork
6 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-03-21 9:01 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/58304/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5785_full -> IGTPW_2676_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_2676_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2676_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58304/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2676_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_exec_basic@exec-ctx} (NEW):
- shard-apl: NOTRUN -> FAIL
* igt@perf_pmu@busy-check-all-vcs0:
- shard-snb: PASS -> FAIL +71
* igt@perf_pmu@busy-hang-rcs0:
- shard-hsw: PASS -> FAIL +92
* igt@perf_pmu@cpu-hotplug:
- shard-snb: NOTRUN -> FAIL +5
* igt@perf_pmu@init-sema-bcs0:
- shard-kbl: NOTRUN -> FAIL +5
* igt@perf_pmu@init-sema-vcs0:
- shard-hsw: NOTRUN -> FAIL +3
* igt@perf_pmu@init-wait-vcs1:
- shard-apl: PASS -> FAIL +96
* igt@perf_pmu@multi-client-rcs0:
- shard-kbl: PASS -> FAIL +106
* igt@perf_pmu@multi-client-vcs0:
- shard-glk: NOTRUN -> FAIL +3
* igt@perf_pmu@other-read-4:
- shard-glk: PASS -> FAIL +89
#### Warnings ####
* igt@drm_mm@topdown:
- shard-hsw: PASS -> ( 2 PASS ) +76
* igt@perf_pmu@busy-start-vcs1:
- shard-snb: SKIP [fdo#109271] -> FAIL +58
* igt@perf_pmu@idle-no-semaphores-vcs1:
- shard-apl: SKIP [fdo#109271] -> FAIL +12
* igt@perf_pmu@idle-vcs1:
- shard-glk: SKIP [fdo#109271] -> FAIL +16
* igt@perf_pmu@semaphore-wait-idle-vcs0:
- shard-hsw: SKIP [fdo#109271] -> FAIL +44
New tests
---------
New tests have been introduced between CI_DRM_5785_full and IGTPW_2676_full:
### New IGT tests (1) ###
* igt@gem_exec_basic@exec-ctx:
- Statuses : 5 fail(s)
- Exec time: [0.05, 0.09] s
Known issues
------------
Here are the changes found in IGTPW_2676_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_param@invalid-param-set:
- shard-hsw: NOTRUN -> FAIL [fdo#109674]
* igt@gem_exec_schedule@deep-bsd:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +39
* igt@gem_pwrite@stolen-normal:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +41
* igt@gem_softpin@softpin:
- shard-glk: NOTRUN -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-apl: PASS -> FAIL [fdo#109660] +1
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: PASS -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-hang-newfb-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_concurrent@pipe-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +14
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +5
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_scaling@pipe-c-plane-scaling:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: PASS -> FAIL [fdo#104894] +1
- shard-kbl: PASS -> FAIL [fdo#104894] +1
#### Possible fixes ####
* igt@gem_exec_parallel@blt-fds:
- shard-snb: INCOMPLETE [fdo#105411] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS +1
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* {igt@kms_plane@pixel-format-pipe-c-planes}:
- shard-glk: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098] +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
[fdo#109674]: https://bugs.freedesktop.org/show_bug.cgi?id=109674
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 5)
------------------------------
Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u
Build changes
-------------
* IGT: IGT_4894 -> IGTPW_2676
* Piglit: piglit_4509 -> None
CI_DRM_5785: 1e3d80c25878b7d97ad6c0680a452d55baeb28e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2676: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2676/
IGT_4894: fedd92f4022837e2c20e472b65bd7d0849f484a3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2676/
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well
2019-03-21 1:05 ` Chris Wilson
@ 2019-03-21 10:12 ` Andi Shyti
0 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 10:12 UTC (permalink / raw)
To: Chris Wilson; +Cc: IGT dev, Andi Shyti
> > +
> > +bool gem_context_has_engine(int fd, unsigned engine, unsigned ctx)
>
> It's still BACKWARDS!!!!
OK :)
Andi
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 7:18 ` Tvrtko Ursulin
@ 2019-03-21 11:23 ` Andi Shyti
2019-03-21 11:39 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 11:23 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti
> > +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
> > + uint16_t class, uint16_t instance, uint8_t flags)
>
> I'd probably use u64 for flags to match the structure.
yes, flags it's u64, I used u8 because the flags we use is never
supposed to be higher than than 3f. But sure, can make it u64.
> > +{
> > + static const char *unk_name = "unk";
> > +
> > + e2->class = class;
> > + e2->instance = instance;
> > + e2->flags = flags;
> > +
> > + if (name) {
> > + e2->name = name;
>
> This path is used only for the legacy fall back mode so I am contemplating
> whether is is even worth having the name passed in.
yes, just wanted to be consistent. At the biginning the
dup_engine had a bigger role, but then I demoted it to just doing
this.
> The if you find a virtual engine in the list (
> I915_ENGINE_CLASS_INVALID/I915_ENGINE_CLASS_INVALID_VIRTUAL) you could set
> the name to "virtual" or something.
do we really need a name of the type "virtual-<engine>"?
> Now listen to this.. how about we export the engine names via the query API?
> Primarily I was thinking to distinguish difference instance of virtual, but
> then it would also lessen the reliance on the static map. Thoughts?
Do you mean that the name would be provided by the driver?
Other than improving the debug information, is the name
formatting giving any advantage if we can distinguish by
class/instance/flags?
We can't use it anyway for test creation.
[...]
> > + uint8_t nengines = (param.size -
> > + sizeof(struct i915_context_param_engines)) /
> > + sizeof(engines->class_instance[0]);
>
> I'd probably just use unsigned int.
Oh... I have set u32 in the intel_engine_data, I didn't reliase,
I assume that nengines would never be higher than 64 (if that
happens we can't handle it here).
But Chris is considering the case we will have more tha 64
engines, I can set it to u32, of course.
[...]
> > +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> > + for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> > + ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> > + i__.n++)
>
> Do we want a context parameter in this helper, or even this helper at all? I
> thought we can end up with only two, for_each_physical_engine and
> for_each_context_engine - but I guess it is open for discussion.
I don't know of possible use cases that do or don't need ctx
outside the for_each...().
If you don't see any use of the context index outside the
for_each I can create the context inside the init_list function.
But, I have a little concern about the destraction of that
context. If the for_each... gets interrupted in the middle of the
loop, we lose the context.
[...]
> > @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> > i = 0;
> > fd[0] = -1;
> > - for_each_engine_class_instance(gem_fd, e_) {
> > + for_each_engine_class_instance(gem_fd, 0, e_) {
> > if (e == e_)
> > busy_idx = i;
> > @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> > unsigned int idle_idx, i;
> > i = 0;
> > - for_each_engine_class_instance(gem_fd, e_) {
> > + for_each_engine_class_instance(gem_fd, 0, e_) {
> > if (e == e_)
> > idle_idx = i;
> > else if (spin)
> > @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
> > unsigned int i;
> > i = 0;
> > - for_each_engine_class_instance(gem_fd, e) {
> > + for_each_engine_class_instance(gem_fd, 0, e) {
> > if (spin)
> > __submit_spin_batch(gem_fd, spin, e, 64);
> > else
> > @@ -1683,7 +1683,7 @@ igt_main
> > igt_require_gem(fd);
> > igt_require(i915_type_id() > 0);
> > - for_each_engine_class_instance(fd, e)
> > + for_each_engine_class_instance(fd, 0, e)
> > num_engines++;
> > }
> >
>
> Looks like this would work. Just the question of virtual engine, set of
> chosen iterators, and maybe some nits.
Yes, as we discussed, right after this patchset I will do the
for_each_physical.
What are the nits? I love nits :)
Andi
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 7:32 ` Chris Wilson
@ 2019-03-21 11:38 ` Andi Shyti
0 siblings, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 11:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: IGT dev, Andi Shyti
Hi Chris,
> > +static void query_engines(int fd,
> > + struct drm_i915_query_engine_info *query_engines)
>
> Pass in the length of the query_engines block i.e. don't just assume
> item.length. And I'm still worrying about what happens when it is
> greater than 64 engines.
OK, looks the same to me, but sure, I can set item.length
outside query_engines().
> > + if (__gem_context_get_param(fd, ¶m)) {
> > + /* if kernel does not support engine/context mapping */
>
> We also take this path if we have more than 64 engines.
But I haven't found anywhere in the get_param() and
i915_query_ioctl() in the driver where this case is considered.
Don't we receive -EINVAL only when "args->size < size"?
The set_engines would fail if we try to do that. I don't see this
a plausible thing to happen (unless, of course, I missed it,
which is very likely).
In any case, we don't have an error control in engine_data and we
would never understand whether there is somthing screwed up.
I was thinking that I can add in the structure an "error"
variable so that we quit the loop if something wrong happens,
e.g. we receive size > 3f.
> > + __for_each_engine_class_instance(e2) {
> > + uint64_t flags;
> > +
> > + if (!gem_has_engine(fd, e2->class, e2->instance))
> > + continue;
> > +
> > + flags = gem_class_instance_to_eb_flags(fd, e2->class,
> > + e2->instance);
>
> You added the field to the static struct, you might as well populate it
> as well, and just use e2->flags. And then you wouldn't even need to
> repeat the computation for gem_has_engine.
makes sense.
> > +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> > +
> > +#endif /* GEM_ENGINE_TOPOLOGY_H */
> > diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> > index 475c0b3c3cc6..84ea4af5392d 100644
> > --- a/lib/igt_gt.h
> > +++ b/lib/igt_gt.h
>
> And we need to break away from igt_gt.h, these will all be good inside
> gem_engine_topology.h I think.
I was thinking the same, but given that all the for_each are in
igt_gt.h I guess that's the right place for consistence, unless
we move all the for_each, until we will get rid of all the
legacy.
Andi
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 11:23 ` Andi Shyti
@ 2019-03-21 11:39 ` Tvrtko Ursulin
2019-03-21 11:54 ` Chris Wilson
2019-03-21 12:18 ` Andi Shyti
0 siblings, 2 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2019-03-21 11:39 UTC (permalink / raw)
To: Andi Shyti; +Cc: IGT dev, Andi Shyti
On 21/03/2019 11:23, Andi Shyti wrote:
>>> +static void init_engine(struct intel_execution_engine2 *e2, const char *name,
>>> + uint16_t class, uint16_t instance, uint8_t flags)
>>
>> I'd probably use u64 for flags to match the structure.
>
> yes, flags it's u64, I used u8 because the flags we use is never
> supposed to be higher than than 3f. But sure, can make it u64.
>
>>> +{
>>> + static const char *unk_name = "unk";
>>> +
>>> + e2->class = class;
>>> + e2->instance = instance;
>>> + e2->flags = flags;
>>> +
>>> + if (name) {
>>> + e2->name = name;
>>
>> This path is used only for the legacy fall back mode so I am contemplating
>> whether is is even worth having the name passed in.
>
> yes, just wanted to be consistent. At the biginning the
> dup_engine had a bigger role, but then I demoted it to just doing
> this.
>
>> The if you find a virtual engine in the list (
>> I915_ENGINE_CLASS_INVALID/I915_ENGINE_CLASS_INVALID_VIRTUAL) you could set
>> the name to "virtual" or something.
>
> do we really need a name of the type "virtual-<engine>"?
Probably not. Plain "virtual" sounds ok.
>
>> Now listen to this.. how about we export the engine names via the query API?
>> Primarily I was thinking to distinguish difference instance of virtual, but
>> then it would also lessen the reliance on the static map. Thoughts?
>
> Do you mean that the name would be provided by the driver?
>
> Other than improving the debug information, is the name
> formatting giving any advantage if we can distinguish by
> class/instance/flags?
>
> We can't use it anyway for test creation.
Yeah, just need to skip it during for_each_physical_engine.
>
> [...]
>
>>> + uint8_t nengines = (param.size -
>>> + sizeof(struct i915_context_param_engines)) /
>>> + sizeof(engines->class_instance[0]);
>>
>> I'd probably just use unsigned int.
>
> Oh... I have set u32 in the intel_engine_data, I didn't reliase,
> I assume that nengines would never be higher than 64 (if that
> happens we can't handle it here).
>
> But Chris is considering the case we will have more tha 64
> engines, I can set it to u32, of course.
>
> [...]
>
>>> +#define for_each_engine_class_instance(fd__, ctx__, e__) \
>>> + for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
>>> + ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
>>> + i__.n++)
>>
>> Do we want a context parameter in this helper, or even this helper at all? I
>> thought we can end up with only two, for_each_physical_engine and
>> for_each_context_engine - but I guess it is open for discussion.
>
> I don't know of possible use cases that do or don't need ctx
> outside the for_each...().
>
> If you don't see any use of the context index outside the
> for_each I can create the context inside the init_list function.
>
> But, I have a little concern about the destraction of that
> context. If the for_each... gets interrupted in the middle of the
> loop, we lose the context.
I am not following how we lose the context?
I was just discussing of our desired end game in therms of number and
signature for for_each_.. iterators.
For me for_each_physical_engine doesn't need the context since it is
about physical engines - not engine from the engine map. Maybe that one
should even have some asserts then to make sure someone hasn't
re-configured the default context.
And we have __for_each_physical_engine which uses the static table, for
subtest enumeration.
Then for_each_context_engine is the fully featured one, which has the
context id in parameters.
Can we solve all use cases with those three or we need mode?
Chris?
>
> [...]
>
>>> @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>>> i = 0;
>>> fd[0] = -1;
>>> - for_each_engine_class_instance(gem_fd, e_) {
>>> + for_each_engine_class_instance(gem_fd, 0, e_) {
>>> if (e == e_)
>>> busy_idx = i;
>>> @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>>> unsigned int idle_idx, i;
>>> i = 0;
>>> - for_each_engine_class_instance(gem_fd, e_) {
>>> + for_each_engine_class_instance(gem_fd, 0, e_) {
>>> if (e == e_)
>>> idle_idx = i;
>>> else if (spin)
>>> @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>>> unsigned int i;
>>> i = 0;
>>> - for_each_engine_class_instance(gem_fd, e) {
>>> + for_each_engine_class_instance(gem_fd, 0, e) {
>>> if (spin)
>>> __submit_spin_batch(gem_fd, spin, e, 64);
>>> else
>>> @@ -1683,7 +1683,7 @@ igt_main
>>> igt_require_gem(fd);
>>> igt_require(i915_type_id() > 0);
>>> - for_each_engine_class_instance(fd, e)
>>> + for_each_engine_class_instance(fd, 0, e)
>>> num_engines++;
>>> }
>>>
>>
>> Looks like this would work. Just the question of virtual engine, set of
>> chosen iterators, and maybe some nits.
>
> Yes, as we discussed, right after this patchset I will do the
> for_each_physical.
>
> What are the nits? I love nits :)
Just things like types and coding style. :) And some more details from
Chris' review.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 11:39 ` Tvrtko Ursulin
@ 2019-03-21 11:54 ` Chris Wilson
2019-03-21 11:57 ` Chris Wilson
2019-03-21 12:18 ` Andi Shyti
1 sibling, 1 reply; 22+ messages in thread
From: Chris Wilson @ 2019-03-21 11:54 UTC (permalink / raw)
To: Andi Shyti, Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti
Quoting Tvrtko Ursulin (2019-03-21 11:39:35)
> I was just discussing of our desired end game in therms of number and
> signature for for_each_.. iterators.
>
> For me for_each_physical_engine doesn't need the context since it is
> about physical engines - not engine from the engine map. Maybe that one
> should even have some asserts then to make sure someone hasn't
> re-configured the default context.
Ok, I'd buy that we don't need to restrict for_each_physical to the
ctx->engines[]. But that implies to me that for_each_physical should set
its engines on the context, and that be a documented side-effect. Which
should be perfectly fine with users of that iface.
> And we have __for_each_physical_engine which uses the static table, for
> subtest enumeration.
Still sadly required.
> Then for_each_context_engine is the fully featured one, which has the
> context id in parameters.
>
> Can we solve all use cases with those three or we need mode?
__for_each_static_engine
for_each_legacy_ring
for_each_physical_engine
for_each_[context]_engine
You could convince me that we never need to iterate over the legacy ABI,
as all such legacy testing can be confined to __for_each_static_engine
subtests. And I could accept that for_each_context_engine is merely a
fiction of the ctx->engines[] ABI tests.
So imo the most important iterators are:
__for_each_static_engine # for subtest definition
for_each_physical_engine # for actual workload construction
Aside from that,
gem_context_set_engine(ctx, class, instance)
/* maps ctx->engines[0] = { class, instance } */
is about all we need to specific execution outside of tests that know
they have a ctx->engines[] to work with (e.g. load balancing)
igt_require(gem_context_set_engines(ctx, ci, count)) would be fine for
new tests that need to define a workload across multiple engines.
I do like the direction the physical iterators are taking; construct the
table and return it as an iterator, that should see us through the ABI
transition smoothly. And in 10 years, you can kill off the legacy :-p
-Chris
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 11:54 ` Chris Wilson
@ 2019-03-21 11:57 ` Chris Wilson
0 siblings, 0 replies; 22+ messages in thread
From: Chris Wilson @ 2019-03-21 11:57 UTC (permalink / raw)
To: Andi Shyti, Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti
Quoting Chris Wilson (2019-03-21 11:54:49)
> Quoting Tvrtko Ursulin (2019-03-21 11:39:35)
> > I was just discussing of our desired end game in therms of number and
> > signature for for_each_.. iterators.
> >
> > For me for_each_physical_engine doesn't need the context since it is
> > about physical engines - not engine from the engine map. Maybe that one
> > should even have some asserts then to make sure someone hasn't
> > re-configured the default context.
>
> Ok, I'd buy that we don't need to restrict for_each_physical to the
> ctx->engines[]. But that implies to me that for_each_physical should set
> its engines on the context, and that be a documented side-effect. Which
> should be perfectly fine with users of that iface.
>
> > And we have __for_each_physical_engine which uses the static table, for
> > subtest enumeration.
>
> Still sadly required.
>
> > Then for_each_context_engine is the fully featured one, which has the
> > context id in parameters.
> >
> > Can we solve all use cases with those three or we need mode?
>
> __for_each_static_engine
>
> for_each_legacy_ring
> for_each_physical_engine
> for_each_[context]_engine
>
> You could convince me that we never need to iterate over the legacy ABI,
> as all such legacy testing can be confined to __for_each_static_engine
> subtests. And I could accept that for_each_context_engine is merely a
> fiction of the ctx->engines[] ABI tests.
>
> So imo the most important iterators are:
> __for_each_static_engine # for subtest definition
> for_each_physical_engine # for actual workload construction
>
> Aside from that,
> gem_context_set_engine(ctx, class, instance)
> /* maps ctx->engines[0] = { class, instance } */
> is about all we need to specific execution outside of tests that know
> they have a ctx->engines[] to work with (e.g. load balancing)
>
> igt_require(gem_context_set_engines(ctx, ci, count)) would be fine for
> new tests that need to define a workload across multiple engines.
>
> I do like the direction the physical iterators are taking; construct the
> table and return it as an iterator, that should see us through the ABI
> transition smoothly. And in 10 years, you can kill off the legacy :-p
I will also say that it will become quickly apparent if we've missed
anything as the changes ripple through the tests, so don't worry too
much about it. :)
-Chris
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
2019-03-21 11:39 ` Tvrtko Ursulin
2019-03-21 11:54 ` Chris Wilson
@ 2019-03-21 12:18 ` Andi Shyti
1 sibling, 0 replies; 22+ messages in thread
From: Andi Shyti @ 2019-03-21 12:18 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti
Hi Tvrtko,
> > > > +{
> > > > + static const char *unk_name = "unk";
> > > > +
> > > > + e2->class = class;
> > > > + e2->instance = instance;
> > > > + e2->flags = flags;
> > > > +
> > > > + if (name) {
> > > > + e2->name = name;
> > >
> > > This path is used only for the legacy fall back mode so I am contemplating
> > > whether is is even worth having the name passed in.
> >
> > yes, just wanted to be consistent. At the biginning the
> > dup_engine had a bigger role, but then I demoted it to just doing
> > this.
> >
> > > The if you find a virtual engine in the list (
> > > I915_ENGINE_CLASS_INVALID/I915_ENGINE_CLASS_INVALID_VIRTUAL) you could set
> > > the name to "virtual" or something.
> >
> > do we really need a name of the type "virtual-<engine>"?
>
> Probably not. Plain "virtual" sounds ok.
OK!
> > > > +#define for_each_engine_class_instance(fd__, ctx__, e__) \
> > > > + for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> > > > + ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
> > > > + i__.n++)
> > >
> > > Do we want a context parameter in this helper, or even this helper at all? I
> > > thought we can end up with only two, for_each_physical_engine and
> > > for_each_context_engine - but I guess it is open for discussion.
> >
> > I don't know of possible use cases that do or don't need ctx
> > outside the for_each...().
> >
> > If you don't see any use of the context index outside the
> > for_each I can create the context inside the init_list function.
> >
> > But, I have a little concern about the destraction of that
> > context. If the for_each... gets interrupted in the middle of the
> > loop, we lose the context.
>
> I am not following how we lose the context?
OK, you are talking about for_each_physical... sorry, sometimes I
might get lost.
> I was just discussing of our desired end game in therms of number and
> signature for for_each_.. iterators.
>
> For me for_each_physical_engine doesn't need the context since it is about
> physical engines - not engine from the engine map. Maybe that one should
> even have some asserts then to make sure someone hasn't re-configured the
> default context.
>
> And we have __for_each_physical_engine which uses the static table, for
> subtest enumeration.
>
> Then for_each_context_engine is the fully featured one, which has the
> context id in parameters.
>
> Can we solve all use cases with those three or we need mode?
Of course yes, We will have in this case these three:
__for_each_physical_engine(e)
for_each_physical_engine(fd, e) /* doesn't need context */
for_each_engine_class_instance(fd, ctx, e)
PS
What I meant before is that that we could have a
for_each_engine_class_instance(fd, e)
where the context is created inside the for_each, but in case of:
for_each_engine_class_instance(fd, e) { /* <--- creates context in intel_init_engine_list() */
if (<any_condition>)
break; /* <---- we don't have time to call gem_context_destroy() */
}
But you were referring to physical engines, and in that case
there are no issues.
> > > > @@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> > > > i = 0;
> > > > fd[0] = -1;
> > > > - for_each_engine_class_instance(gem_fd, e_) {
> > > > + for_each_engine_class_instance(gem_fd, 0, e_) {
> > > > if (e == e_)
> > > > busy_idx = i;
> > > > @@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> > > > unsigned int idle_idx, i;
> > > > i = 0;
> > > > - for_each_engine_class_instance(gem_fd, e_) {
> > > > + for_each_engine_class_instance(gem_fd, 0, e_) {
> > > > if (e == e_)
> > > > idle_idx = i;
> > > > else if (spin)
> > > > @@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
> > > > unsigned int i;
> > > > i = 0;
> > > > - for_each_engine_class_instance(gem_fd, e) {
> > > > + for_each_engine_class_instance(gem_fd, 0, e) {
> > > > if (spin)
> > > > __submit_spin_batch(gem_fd, spin, e, 64);
> > > > else
> > > > @@ -1683,7 +1683,7 @@ igt_main
> > > > igt_require_gem(fd);
> > > > igt_require(i915_type_id() > 0);
> > > > - for_each_engine_class_instance(fd, e)
> > > > + for_each_engine_class_instance(fd, 0, e)
> > > > num_engines++;
> > > > }
> > > >
> > >
> > > Looks like this would work. Just the question of virtual engine, set of
> > > chosen iterators, and maybe some nits.
> >
> > Yes, as we discussed, right after this patchset I will do the
> > for_each_physical.
> >
> > What are the nits? I love nits :)
>
> Just things like types and coding style. :) And some more details from
> Chris' review.
Thanks!
Andi
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igt-dev@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface
2019-03-28 19:21 [igt-dev] [RFC v16 0/8] " Andi Shyti
@ 2019-03-29 7:40 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-03-29 7:40 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/58689/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5832_full -> IGTPW_2730_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_2730_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2730_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58689/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2730_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@most-busy-check-all-rcs0:
- shard-kbl: PASS -> FAIL +1
- shard-apl: PASS -> FAIL +1
- shard-snb: PASS -> FAIL +1
- shard-hsw: PASS -> FAIL +1
* igt@perf_pmu@most-busy-idle-check-all-rcs0:
- shard-glk: PASS -> FAIL +1
#### Warnings ####
* igt@gem_wait@await-vebox:
- shard-snb: SKIP [fdo#109271] -> FAIL +4
New tests
---------
New tests have been introduced between CI_DRM_5832_full and IGTPW_2730_full:
### New IGT tests (2) ###
* igt@gem_exec_basic@exec-engines-ctx:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@exec-physical-engines-ctx:
- Statuses : 5 pass(s)
- Exec time: [0.0, 0.00] s
Known issues
------------
Here are the changes found in IGTPW_2730_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
- shard-apl: PASS -> FAIL [fdo#109660]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_atomic_transition@6x-modeset-transitions-fencing:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-hsw: PASS -> DMESG-WARN [fdo#110222]
- shard-kbl: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@fbc:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +14
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363] +1
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-apl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +96
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm:
- shard-apl: PASS -> FAIL [fdo#104894] +2
* igt@kms_vblank@pipe-c-ts-continuation-modeset-hang:
- shard-kbl: PASS -> FAIL [fdo#104894]
* igt@perf_pmu@busy-hang-vcs1:
- shard-apl: NOTRUN -> SKIP [fdo#109271]
* igt@tools_test@tools_test:
- shard-hsw: PASS -> SKIP [fdo#109271]
#### Possible fixes ####
* igt@gem_wait@await-bsd2:
- shard-apl: SKIP [fdo#109271] -> PASS +9
* igt@gem_wait@wait-bsd2:
- shard-snb: SKIP [fdo#109271] -> PASS +7
* igt@gem_wait@write-busy-bsd2:
- shard-hsw: SKIP [fdo#109271] -> PASS +9
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: DMESG-WARN [fdo#110222] -> PASS
- shard-hsw: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-glk: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-kbl: FAIL [fdo#103232] -> PASS
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-glk: FAIL [fdo#107791] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: FAIL [fdo#103167] -> PASS
- shard-kbl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
- shard-glk: FAIL [fdo#103167] -> PASS
* {igt@kms_plane@pixel-format-pipe-b-planes-source-clamping}:
- shard-glk: SKIP [fdo#109271] -> PASS +8
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-a-ts-continuation-modeset:
- shard-apl: FAIL [fdo#104894] -> PASS
- shard-kbl: FAIL [fdo#104894] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 5)
------------------------------
Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u
Build changes
-------------
* IGT: IGT_4911 -> IGTPW_2730
* Piglit: piglit_4509 -> None
CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2730: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface
2019-03-21 16:05 [igt-dev] [PATCH v15 0/5] " Andi Shyti
@ 2019-03-22 9:02 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-03-22 9:02 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/58365/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5789_full -> IGTPW_2684_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_2684_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2684_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58365/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2684_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-snb: PASS -> DMESG-WARN
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-hsw: PASS -> DMESG-WARN
- shard-kbl: PASS -> DMESG-WARN
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: NOTRUN -> DMESG-WARN
* igt@perf_pmu@busy-check-all-vcs0:
- shard-kbl: PASS -> FAIL +7
- shard-hsw: PASS -> FAIL +4
* igt@perf_pmu@busy-check-all-vecs0:
- shard-apl: PASS -> FAIL +5
- shard-glk: PASS -> FAIL +3
* igt@perf_pmu@busy-idle-check-all-bcs0:
- shard-snb: PASS -> FAIL +1
* igt@perf_pmu@busy-idle-check-all-vcs0:
- shard-glk: NOTRUN -> FAIL
New tests
---------
New tests have been introduced between CI_DRM_5789_full and IGTPW_2684_full:
### New IGT tests (1) ###
* igt@gem_exec_basic@exec-ctx:
- Statuses : 5 pass(s)
- Exec time: [0.0, 0.00] s
Known issues
------------
Here are the changes found in IGTPW_2684_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-clear:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@gem_ctx_sseu@invalid-args:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +19
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_wait@write-busy-bsd2:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +40
* igt@kms_atomic_transition@6x-modeset-transitions-fencing:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-glk: NOTRUN -> FAIL [fdo#106641]
* igt@kms_busy@basic-flip-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_color@pipe-c-ctm-max:
- shard-glk: NOTRUN -> FAIL [fdo#108147] +1
* igt@kms_color@pipe-c-degamma:
- shard-glk: NOTRUN -> FAIL [fdo#104782] +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-glk: NOTRUN -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-kbl: PASS -> FAIL [fdo#109350]
- shard-apl: PASS -> FAIL [fdo#109350]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +55
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +122
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +71
* igt@kms_invalid_dotclock:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#109373]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145]
- shard-kbl: PASS -> FAIL [fdo#108145]
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-f:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
- shard-apl: PASS -> FAIL [fdo#104894] +1
* igt@perf_pmu@busy-check-all-vcs0:
- shard-snb: PASS -> FAIL [fdo#105106] +1
* igt@runner@aborted:
- shard-glk: NOTRUN -> FAIL [fdo#109373] / [k.org#202321]
#### Possible fixes ####
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: FAIL [fdo#108686] -> PASS
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-apl: DMESG-WARN -> PASS
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-hsw: DMESG-WARN -> PASS +1
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: DMESG-WARN -> PASS +1
- shard-snb: DMESG-WARN -> PASS
* igt@kms_cursor_crc@cursor-128x42-sliding:
- shard-kbl: FAIL [fdo#103232] -> PASS +1
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-hsw: FAIL [fdo#99912] -> PASS
* igt@perf_pmu@rc6-runtime-pm-long:
- shard-apl: FAIL [fdo#105010] -> PASS
- shard-kbl: FAIL [fdo#105010] -> PASS
* igt@tools_test@tools_test:
- shard-snb: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite:
- shard-hsw: INCOMPLETE [fdo#103540] -> SKIP [fdo#109271]
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
[fdo#105106]: https://bugs.freedesktop.org/show_bug.cgi?id=105106
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109350]: https://bugs.freedesktop.org/show_bug.cgi?id=109350
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 5)
------------------------------
Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u
Build changes
-------------
* IGT: IGT_4896 -> IGTPW_2684
* Piglit: piglit_4509 -> None
CI_DRM_5789: 93b3614e8c493860dc63c3028460efb02036c6ea @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2684: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
IGT_4896: 0f9c061247fb7aba21c9459f19f437927a28f32c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2684/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface
2019-03-19 23:44 [igt-dev] [PATCH v13 0/9] " Andi Shyti
@ 2019-03-20 9:35 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-03-20 9:35 UTC (permalink / raw)
To: Andi Shyti; +Cc: igt-dev
== Series Details ==
Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/58207/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5775_full -> IGTPW_2663_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_2663_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_2663_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58207/revisions/1/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_2663_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf_pmu@busy-accuracy-2-vecs0:
- shard-apl: NOTRUN -> FAIL
* igt@perf_pmu@busy-double-start-bcs0:
- shard-kbl: PASS -> FAIL +62
* igt@perf_pmu@busy-idle-vcs0:
- shard-snb: PASS -> FAIL +11
* igt@perf_pmu@busy-idle-vecs0:
- shard-glk: PASS -> FAIL +35
* igt@perf_pmu@busy-start-vcs0:
- shard-kbl: NOTRUN -> FAIL
* igt@perf_pmu@busy-vecs0:
- shard-hsw: NOTRUN -> FAIL
* igt@perf_pmu@render-node-busy-idle-bcs0:
- shard-hsw: PASS -> FAIL +21
* igt@perf_pmu@semaphore-wait-vcs0:
- shard-apl: PASS -> FAIL +36
New tests
---------
New tests have been introduced between CI_DRM_5775_full and IGTPW_2663_full:
### New IGT tests (1) ###
* igt@gem_exec_basic@exec-ctx:
- Statuses : 5 pass(s)
- Exec time: [0.0, 0.00] s
Known issues
------------
Here are the changes found in IGTPW_2663_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_fence_thrash@bo-copy:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@kms_busy@basic-flip-e:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@basic-modeset-d:
- shard-glk: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-hsw: PASS -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-snb: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: NOTRUN -> FAIL [fdo#108145]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +3
- shard-kbl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-glk: PASS -> FAIL [fdo#103184]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-kbl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-glk: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +9
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +35
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +16
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +21
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
- shard-hsw: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
- shard-kbl: PASS -> FAIL [fdo#104894] +1
* igt@kms_vblank@pipe-c-ts-continuation-modeset-hang:
- shard-apl: PASS -> FAIL [fdo#104894] +3
* igt@perf_pmu@busy-double-start-vcs0:
- shard-apl: PASS -> FAIL [fdo#105106]
- shard-snb: PASS -> FAIL [fdo#105106] +1
- shard-hsw: PASS -> FAIL [fdo#105106]
* igt@perf_pmu@rc6:
- shard-kbl: PASS -> SKIP [fdo#109271]
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-snb: FAIL [fdo#109661] -> PASS
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
- shard-snb: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-apl: FAIL [fdo#103232] -> PASS +5
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-kbl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +5
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-kbl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
- shard-glk: FAIL [fdo#103167] -> PASS +7
* {igt@kms_plane@plane-position-covered-pipe-a-planes}:
- shard-glk: FAIL [fdo#110038] -> PASS
- shard-apl: FAIL [fdo#110038] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-c-tiling-x}:
- shard-glk: FAIL [fdo#110037] -> PASS +2
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: FAIL [fdo#109016] -> PASS
* {igt@kms_universal_plane@universal-plane-pipe-a-functional}:
- shard-apl: FAIL [fdo#110037] -> PASS +2
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: FAIL [fdo#104894] -> PASS +1
- shard-kbl: FAIL [fdo#104894] -> PASS +1
#### Warnings ####
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105106]: https://bugs.freedesktop.org/show_bug.cgi?id=105106
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
[fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
[fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 5)
------------------------------
Missing (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u
Build changes
-------------
* IGT: IGT_4890 -> IGTPW_2663
* Piglit: piglit_4509 -> None
CI_DRM_5775: 3ead1aea2137c77a4fe00637dca589736397d885 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2663: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
IGT_4890: 6d4d6949a099521003de252358601d22115e27ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2663/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2019-03-29 7:40 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-21 1:00 [igt-dev] [PATCH v14 0/5] new engine discovery interface Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 1/5] lib/igt_gt: remove unnecessary argument Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 2/5] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
2019-03-21 1:05 ` Chris Wilson
2019-03-21 10:12 ` Andi Shyti
2019-03-21 7:06 ` Tvrtko Ursulin
2019-03-21 1:00 ` [igt-dev] [PATCH v14 3/5] include/drm-uapi: import i915_drm.h header file Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
2019-03-21 7:18 ` Tvrtko Ursulin
2019-03-21 11:23 ` Andi Shyti
2019-03-21 11:39 ` Tvrtko Ursulin
2019-03-21 11:54 ` Chris Wilson
2019-03-21 11:57 ` Chris Wilson
2019-03-21 12:18 ` Andi Shyti
2019-03-21 7:32 ` Chris Wilson
2019-03-21 11:38 ` Andi Shyti
2019-03-21 1:00 ` [igt-dev] [PATCH v14 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test Andi Shyti
2019-03-21 1:29 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
2019-03-21 9:01 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-03-28 19:21 [igt-dev] [RFC v16 0/8] " Andi Shyti
2019-03-29 7:40 ` [igt-dev] ✗ Fi.CI.IGT: failure for " Patchwork
2019-03-21 16:05 [igt-dev] [PATCH v15 0/5] " Andi Shyti
2019-03-22 9:02 ` [igt-dev] ✗ Fi.CI.IGT: failure for " Patchwork
2019-03-19 23:44 [igt-dev] [PATCH v13 0/9] " Andi Shyti
2019-03-20 9:35 ` [igt-dev] ✗ Fi.CI.IGT: failure for " Patchwork
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