* [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs
@ 2019-03-22 0:03 Rodrigo Vivi
2019-03-22 0:03 ` [CI 2/6] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx
From: James Ausmus <james.ausmus@intel.com>
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for
proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
include/drm/i915_pciids.h | 7 +++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7a6054eadb8e..be028b5d80b2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -730,6 +730,15 @@ static const struct intel_device_info intel_icelake_11_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
+static const struct intel_device_info intel_elkhartlake_info = {
+ GEN11_FEATURES,
+ PLATFORM(INTEL_ICELAKE),
+ .is_alpha_support = 1,
+ .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
+ .ppgtt_type = INTEL_PPGTT_FULL,
+ .ppgtt_size = 36,
+};
+
#undef GEN
#undef PLATFORM
@@ -799,6 +808,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
+ INTEL_EHL_IDS(&intel_elkhartlake_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 291b5e3fa59c..c7cdbfc4d033 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -498,4 +498,11 @@
INTEL_VGA_DEVICE(0x8A70, info), \
INTEL_VGA_DEVICE(0x8A53, info)
+/* EHL */
+#define INTEL_EHL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4500, info), \
+ INTEL_VGA_DEVICE(0x4571, info), \
+ INTEL_VGA_DEVICE(0x4551, info), \
+ INTEL_VGA_DEVICE(0x4541, info)
+
#endif /* _I915_PCIIDS_H */
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 2/6] drm/i915/ehl: Add ElkhartLake platform
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
@ 2019-03-22 0:03 ` Rodrigo Vivi
2019-03-22 0:03 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
4 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fefcb39aefc4..787fa2b255aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2320,6 +2320,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index be028b5d80b2..eecaf2259b84 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -732,7 +732,7 @@ static const struct intel_device_info intel_icelake_11_info = {
static const struct intel_device_info intel_elkhartlake_info = {
GEN11_FEATURES,
- PLATFORM(INTEL_ICELAKE),
+ PLATFORM(INTEL_ELKHARTLAKE),
.is_alpha_support = 1,
.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
.ppgtt_type = INTEL_PPGTT_FULL,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index eddf83807957..db00110cbb2e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -57,6 +57,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(COFFEELAKE),
PLATFORM_NAME(CANNONLAKE),
PLATFORM_NAME(ICELAKE),
+ PLATFORM_NAME(ELKHARTLAKE),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6234570a9b17..98acefaacec9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -73,6 +73,7 @@ enum intel_platform {
INTEL_CANNONLAKE,
/* gen11 */
INTEL_ICELAKE,
+ INTEL_ELKHARTLAKE,
INTEL_MAX_PLATFORMS
};
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 3/6] drm/i915/ehl: Add dpll mgr
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 0:03 ` [CI 2/6] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
@ 2019-03-22 0:03 ` Rodrigo Vivi
2019-03-22 0:03 ` [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index dfe6a7114d56..eeb659946203 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3245,6 +3245,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info ehl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr ehl_pll_mgr = {
+ .dpll_info = ehl_plls,
+ .get_dpll = icl_get_dpll,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3258,7 +3270,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ELKHARTLAKE(dev_priv))
+ dpll_mgr = &ehl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv))
dpll_mgr = &cnl_pll_mgr;
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 0:03 ` [CI 2/6] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-22 0:03 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
@ 2019-03-22 0:03 ` Rodrigo Vivi
2019-03-22 9:28 ` Jani Nikula
2019-03-22 0:03 ` [CI 5/6] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7c15b428ff84..008560ef4db0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14713,7 +14713,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_C);
+ icl_dsi_init(dev_priv);
+ } else if (INTEL_GEN(dev_priv) >= 11) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 5/6] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (2 preceding siblings ...)
2019-03-22 0:03 ` [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
@ 2019-03-22 0:03 ` Rodrigo Vivi
2019-03-22 0:03 ` [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
EHL has a different number of subslices.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index db00110cbb2e..e0ac908bb4e9 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
+ if (IS_ELKHARTLAKE(dev_priv)) {
+ sseu->max_slices = 1;
+ sseu->max_subslices = 4;
+ sseu->max_eus_per_subslice = 8;
+ } else {
+ sseu->max_slices = 1;
+ sseu->max_subslices = 8;
+ sseu->max_eus_per_subslice = 8;
+ }
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (3 preceding siblings ...)
2019-03-22 0:03 ` [CI 5/6] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
@ 2019-03-22 0:03 ` Rodrigo Vivi
2019-03-22 0:08 ` [PATCH] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 2:04 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
EHL uses the same firmware as ICL.
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index e8ac04c33e29..862a8f686ef5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -486,7 +486,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 12) {
/* Allow to load fw via parameter using the last known size */
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
- } else if (IS_ICELAKE(dev_priv)) {
+ } else if (IS_GEN(dev_priv, 11)) {
csr->fw_path = ICL_CSR_PATH;
csr->required_version = ICL_CSR_VERSION_REQUIRED;
csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH] drm/i915/ehl: Add EHL platform info and PCI IDs
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (4 preceding siblings ...)
2019-03-22 0:03 ` [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
@ 2019-03-22 0:08 ` Rodrigo Vivi
2019-03-22 2:04 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 0:08 UTC (permalink / raw)
To: intel-gfx
From: James Ausmus <james.ausmus@intel.com>
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for
proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&_FEATURES.
- Added ppgtt type and size after rework from Bob and Chris
v4: (Rodrigo): - remove ppgtt type added on v3. Jose pointed it is not
needed.
Cc: Bob Paauwe <bob.j.paauwe@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 9 +++++++++
include/drm/i915_pciids.h | 7 +++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7a6054eadb8e..fa99d68cbe7d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -730,6 +730,14 @@ static const struct intel_device_info intel_icelake_11_info = {
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
+static const struct intel_device_info intel_elkhartlake_info = {
+ GEN11_FEATURES,
+ PLATFORM(INTEL_ICELAKE),
+ .is_alpha_support = 1,
+ .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
+ .ppgtt_size = 36,
+};
+
#undef GEN
#undef PLATFORM
@@ -799,6 +807,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
+ INTEL_EHL_IDS(&intel_elkhartlake_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 291b5e3fa59c..c7cdbfc4d033 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -498,4 +498,11 @@
INTEL_VGA_DEVICE(0x8A70, info), \
INTEL_VGA_DEVICE(0x8A53, info)
+/* EHL */
+#define INTEL_EHL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4500, info), \
+ INTEL_VGA_DEVICE(0x4571, info), \
+ INTEL_VGA_DEVICE(0x4551, info), \
+ INTEL_VGA_DEVICE(0x4541, info)
+
#endif /* _I915_PCIIDS_H */
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2)
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
` (5 preceding siblings ...)
2019-03-22 0:08 ` [PATCH] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
@ 2019-03-22 2:04 ` Patchwork
6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-03-22 2:04 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2)
URL : https://patchwork.freedesktop.org/series/58386/
State : failure
== Summary ==
Applying: drm/i915/ehl: Add EHL platform info and PCI IDs
Applying: drm/i915/ehl: Add ElkhartLake platform
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_pci.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915/ehl: Add ElkhartLake platform
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL
2019-03-22 0:03 ` [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
@ 2019-03-22 9:28 ` Jani Nikula
0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2019-03-22 9:28 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Lucas De Marchi
On Thu, 21 Mar 2019, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Configure the correct set of outputs for EHL. EHL has three DDI's
> plus MIPI.
Broken record, we don't have MIPI, we have MIPI DSI or just DSI.
Similarly, we don't have VESA, we have VESA DP or just DP.
BR,
Jani.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7c15b428ff84..008560ef4db0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14713,7 +14713,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + icl_dsi_init(dev_priv);
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
--
Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [CI 3/6] drm/i915/ehl: Add dpll mgr
2019-03-22 17:58 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
@ 2019-03-22 17:58 ` Rodrigo Vivi
0 siblings, 0 replies; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-22 17:58 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index dfe6a7114d56..eeb659946203 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3245,6 +3245,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info ehl_plls[] = {
+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr ehl_pll_mgr = {
+ .dpll_info = ehl_plls,
+ .get_dpll = icl_get_dpll,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3258,7 +3270,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ELKHARTLAKE(dev_priv))
+ dpll_mgr = &ehl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv))
dpll_mgr = &cnl_pll_mgr;
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [CI 3/6] drm/i915/ehl: Add dpll mgr
2019-03-15 17:57 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
@ 2019-03-16 0:18 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2019-03-16 0:18 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Intel Graphics, Lucas De Marchi
On Fri, Mar 15, 2019 at 10:57 AM Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>
> From: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Elkhart Lake has a different set of PLLs as compared to Ice Lake,
> although programming them is very similar.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-4-rodrigo.vivi@intel.com
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index b3fb221c2532..a9feb119c19f 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
> +static const struct dpll_info ehl_plls[] = {
> + { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> + { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
Sorry, I merged a patch earlier today and icl_pll_funcs is gone. It
should be combo_pll_funcs here.
Lucas De Marchi
> + { },
> +};
> +
> +static const struct intel_dpll_mgr ehl_pll_mgr = {
> + .dpll_info = ehl_plls,
> + .get_dpll = icl_get_dpll,
> + .dump_hw_state = icl_dump_hw_state,
> +};
> +
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
> @@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (IS_ELKHARTLAKE(dev_priv))
> + dpll_mgr = &ehl_pll_mgr;
> + else if (INTEL_GEN(dev_priv) >= 11)
> dpll_mgr = &icl_pll_mgr;
> else if (IS_CANNONLAKE(dev_priv))
> dpll_mgr = &cnl_pll_mgr;
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [CI 3/6] drm/i915/ehl: Add dpll mgr
2019-03-15 17:57 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
@ 2019-03-15 17:57 ` Rodrigo Vivi
2019-03-16 0:18 ` Lucas De Marchi
0 siblings, 1 reply; 12+ messages in thread
From: Rodrigo Vivi @ 2019-03-15 17:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Lucas De Marchi <lucas.demarchi@intel.com>
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-4-rodrigo.vivi@intel.com
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index b3fb221c2532..a9feb119c19f 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3246,6 +3246,18 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
.dump_hw_state = icl_dump_hw_state,
};
+static const struct dpll_info ehl_plls[] = {
+ { "DPLL 0", &icl_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
+ { "DPLL 1", &icl_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
+ { },
+};
+
+static const struct intel_dpll_mgr ehl_pll_mgr = {
+ .dpll_info = ehl_plls,
+ .get_dpll = icl_get_dpll,
+ .dump_hw_state = icl_dump_hw_state,
+};
+
/**
* intel_shared_dpll_init - Initialize shared DPLLs
* @dev: drm device
@@ -3259,7 +3271,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ELKHARTLAKE(dev_priv))
+ dpll_mgr = &ehl_pll_mgr;
+ else if (INTEL_GEN(dev_priv) >= 11)
dpll_mgr = &icl_pll_mgr;
else if (IS_CANNONLAKE(dev_priv))
dpll_mgr = &cnl_pll_mgr;
--
2.20.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-03-22 17:58 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-22 0:03 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 0:03 ` [CI 2/6] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-22 0:03 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-22 0:03 ` [CI 4/6] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
2019-03-22 9:28 ` Jani Nikula
2019-03-22 0:03 ` [CI 5/6] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
2019-03-22 0:03 ` [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
2019-03-22 0:08 ` [PATCH] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 2:04 ` ✗ Fi.CI.BAT: failure for series starting with drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
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2019-03-22 17:58 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-22 17:58 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-15 17:57 [CI 1/6] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-15 17:57 ` [CI 3/6] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-16 0:18 ` Lucas De Marchi
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