* [PATCH 1/9] drm/i915: rename raw reg access functions
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-25 22:41 ` Paulo Zanoni
` (2 more replies)
2019-03-25 21:49 ` [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore Daniele Ceraolo Spurio
` (11 subsequent siblings)
12 siblings, 3 replies; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
They now work on uncore, so use raw_uncore_ prefix. Also move them to
uncore.h
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 32 ++-----------------
drivers/gpu/drm/i915/i915_vgpu.c | 6 ++--
drivers/gpu/drm/i915/intel_uncore.c | 48 ++++++++++++++---------------
drivers/gpu/drm/i915/intel_uncore.h | 27 ++++++++++++++++
4 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e30f7b19b51..558d40f07ffe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3507,32 +3507,6 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
-#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
- i915_reg_t reg) \
-{ \
- return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
-}
-
-#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
- i915_reg_t reg, uint##x##_t val) \
-{ \
- write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
-}
-__raw_read(8, b)
-__raw_read(16, w)
-__raw_read(32, l)
-__raw_read(64, q)
-
-__raw_write(8, b)
-__raw_write(16, w)
-__raw_write(32, l)
-__raw_write(64, q)
-
-#undef __raw_read
-#undef __raw_write
-
/* These are untraced mmio-accessors that are only valid to be used inside
* critical sections, such as inside IRQ handlers, where forcewake is explicitly
* controlled.
@@ -3559,9 +3533,9 @@ __raw_write(64, q)
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
-#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
-#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
-#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
+#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
+#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
/* "Broadcast RGB" property */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 3d0b493e4200..94d3992b599d 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,17 +66,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
- magic = __raw_i915_read64(uncore, vgtif_reg(magic));
+ magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
if (magic != VGT_MAGIC)
return;
- version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
+ version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
if (version_major < VGT_VERSION_MAJOR) {
DRM_INFO("VGT interface version mismatch!\n");
return;
}
- dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
+ dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
dev_priv->vgpu.active = true;
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1816eeae3ba9..3f74889c4212 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -31,7 +31,7 @@
#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define GT_FIFO_TIMEOUT_MS 10
-#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
+#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
static const char * const forcewake_domain_names[] = {
"render",
@@ -279,7 +279,7 @@ static inline u32 gt_thread_status(struct intel_uncore *uncore)
{
u32 val;
- val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
+ val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
return val;
@@ -306,7 +306,7 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
static inline u32 fifo_free_entries(struct intel_uncore *uncore)
{
- u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
+ u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
return count & GT_FIFO_FREE_ENTRIES_MASK;
}
@@ -451,7 +451,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv) ||
IS_BROADWELL(dev_priv) ||
INTEL_GEN(dev_priv) >= 9) {
- dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
+ dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
HSW_EDRAM_CAP);
/* NB: We can't write IDICR yet because we do not have gt funcs
@@ -470,11 +470,11 @@ fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
u32 dbg;
- dbg = __raw_i915_read32(uncore, FPGA_DBG);
+ dbg = __raw_uncore_read32(uncore, FPGA_DBG);
if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
return false;
- __raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
return true;
}
@@ -484,11 +484,11 @@ vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
u32 cer;
- cer = __raw_i915_read32(uncore, CLAIM_ER);
+ cer = __raw_uncore_read32(uncore, CLAIM_ER);
if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
return false;
- __raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
+ __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
return true;
}
@@ -498,11 +498,11 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
{
u32 fifodbg;
- fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
+ fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
if (unlikely(fifodbg)) {
DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
- __raw_i915_write32(uncore, GTFIFODBG, fifodbg);
+ __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
}
return fifodbg;
@@ -537,10 +537,10 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
/* WaDisableShadowRegForCpd:chv */
if (IS_CHERRYVIEW(i915)) {
- __raw_i915_write32(uncore, GTFIFOCTL,
- __raw_i915_read32(uncore, GTFIFOCTL) |
- GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
- GT_FIFO_CTL_RC6_POLICY_STALL);
+ __raw_uncore_write32(uncore, GTFIFOCTL,
+ __raw_uncore_read32(uncore, GTFIFOCTL) |
+ GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+ GT_FIFO_CTL_RC6_POLICY_STALL);
}
iosf_mbi_punit_acquire();
@@ -1068,7 +1068,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
* the chip from rc6 before touching it for real. MI_MODE is masked,
* hence harmless to write 0 into. */
- __raw_i915_write32(uncore, MI_MODE, 0);
+ __raw_uncore_write32(uncore, MI_MODE, 0);
}
static void
@@ -1110,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
static u##x \
gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
- val = __raw_i915_read##x(uncore, reg); \
+ val = __raw_uncore_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
}
@@ -1119,7 +1119,7 @@ static u##x \
gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
ilk_dummy_write(uncore); \
- val = __raw_i915_read##x(uncore, reg); \
+ val = __raw_uncore_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
}
@@ -1189,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
if (fw_engine) \
__force_wake_auto(uncore, fw_engine); \
- val = __raw_i915_read##x(uncore, reg); \
+ val = __raw_uncore_read##x(uncore, reg); \
GEN6_READ_FOOTER; \
}
#define __gen6_read(x) __gen_read(gen6, x)
@@ -1226,7 +1226,7 @@ __gen6_read(64)
static void \
gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
- __raw_i915_write##x(uncore, reg, val); \
+ __raw_uncore_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
}
@@ -1235,7 +1235,7 @@ static void \
gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
ilk_dummy_write(uncore); \
- __raw_i915_write##x(uncore, reg, val); \
+ __raw_uncore_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
}
@@ -1271,7 +1271,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
GEN6_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE(offset)) \
__gen6_gt_wait_for_fifo(uncore); \
- __raw_i915_write##x(uncore, reg, val); \
+ __raw_uncore_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
@@ -1283,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
if (fw_engine) \
__force_wake_auto(uncore, fw_engine); \
- __raw_i915_write##x(uncore, reg, val); \
+ __raw_uncore_write##x(uncore, reg, val); \
GEN6_WRITE_FOOTER; \
}
#define __gen8_write(x) __gen_write(gen8, x)
@@ -1470,7 +1470,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
* before the ecobus check.
*/
- __raw_i915_write32(uncore, FORCEWAKE, 0);
+ __raw_uncore_write32(uncore, FORCEWAKE, 0);
__raw_posting_read(uncore, ECOBUS);
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
@@ -1478,7 +1478,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
spin_lock_irq(&uncore->lock);
fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
- ecobus = __raw_i915_read32(uncore, ECOBUS);
+ ecobus = __raw_uncore_read32(uncore, ECOBUS);
fw_domains_put(uncore, FORCEWAKE_RENDER);
spin_unlock_irq(&uncore->lock);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index d345e5ab04a5..f7670cbc41c9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -215,6 +215,33 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
2, timeout_ms, NULL);
}
+/* register access functions */
+#define __raw_read(x__, s__) \
+static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
+ i915_reg_t reg) \
+{ \
+ return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
+}
+
+#define __raw_write(x__, s__) \
+static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
+ i915_reg_t reg, u##x__ val) \
+{ \
+ write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
+}
+__raw_read(8, b)
+__raw_read(16, w)
+__raw_read(32, l)
+__raw_read(64, q)
+
+__raw_write(8, b)
+__raw_write(16, w)
+__raw_write(32, l)
+__raw_write(64, q)
+
+#undef __raw_read
+#undef __raw_write
+
#define raw_reg_read(base, reg) \
readl(base + i915_mmio_reg_offset(reg))
#define raw_reg_write(base, reg, value) \
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 1/9] drm/i915: rename raw reg access functions
2019-03-25 21:49 ` [PATCH 1/9] drm/i915: rename raw reg access functions Daniele Ceraolo Spurio
@ 2019-03-25 22:41 ` Paulo Zanoni
2019-03-25 22:57 ` Chris Wilson
2019-03-26 4:18 ` kbuild test robot
2019-03-26 4:37 ` kbuild test robot
2 siblings, 1 reply; 27+ messages in thread
From: Paulo Zanoni @ 2019-03-25 22:41 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> They now work on uncore, so use raw_uncore_ prefix. Also move them to
> uncore.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 32 ++-----------------
> drivers/gpu/drm/i915/i915_vgpu.c | 6 ++--
> drivers/gpu/drm/i915/intel_uncore.c | 48 ++++++++++++++---------------
> drivers/gpu/drm/i915/intel_uncore.h | 27 ++++++++++++++++
> 4 files changed, 57 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4e30f7b19b51..558d40f07ffe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3507,32 +3507,6 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
> #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
> #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
>
> -#define __raw_read(x, s) \
> -static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
> - i915_reg_t reg) \
> -{ \
> - return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -
> -#define __raw_write(x, s) \
> -static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
> - i915_reg_t reg, uint##x##_t val) \
> -{ \
> - write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> -}
> -__raw_read(8, b)
> -__raw_read(16, w)
> -__raw_read(32, l)
> -__raw_read(64, q)
> -
> -__raw_write(8, b)
> -__raw_write(16, w)
> -__raw_write(32, l)
> -__raw_write(64, q)
> -
> -#undef __raw_read
> -#undef __raw_write
> -
> /* These are untraced mmio-accessors that are only valid to be used inside
> * critical sections, such as inside IRQ handlers, where forcewake is explicitly
> * controlled.
> @@ -3559,9 +3533,9 @@ __raw_write(64, q)
> * therefore generally be serialised, by either the dev_priv->uncore.lock or
> * a more localised lock guarding all access to that bank of registers.
> */
> -#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
> -#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
> -#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
> +#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
> +#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
> +#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
> #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
>
> /* "Broadcast RGB" property */
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
> index 3d0b493e4200..94d3992b599d 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.c
> +++ b/drivers/gpu/drm/i915/i915_vgpu.c
> @@ -66,17 +66,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
>
> BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
>
> - magic = __raw_i915_read64(uncore, vgtif_reg(magic));
> + magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
> if (magic != VGT_MAGIC)
> return;
>
> - version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
> + version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
> if (version_major < VGT_VERSION_MAJOR) {
> DRM_INFO("VGT interface version mismatch!\n");
> return;
> }
>
> - dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
> + dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
>
> dev_priv->vgpu.active = true;
> DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 1816eeae3ba9..3f74889c4212 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -31,7 +31,7 @@
> #define FORCEWAKE_ACK_TIMEOUT_MS 50
> #define GT_FIFO_TIMEOUT_MS 10
>
> -#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
> +#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
Now the person trying to figure out what __raw_posting_read() does will
have to chase __raw_uncore_read32(), which is not even greppable. I'm
not sure this is an improvement to our codebase, but the neatness of
just passing everything does have some value. Not really a big deal, so
I'm not blocking merging on this.
>
> static const char * const forcewake_domain_names[] = {
> "render",
> @@ -279,7 +279,7 @@ static inline u32 gt_thread_status(struct intel_uncore *uncore)
> {
> u32 val;
>
> - val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
> + val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
> val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
>
> return val;
> @@ -306,7 +306,7 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
>
> static inline u32 fifo_free_entries(struct intel_uncore *uncore)
> {
> - u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
> + u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
>
> return count & GT_FIFO_FREE_ENTRIES_MASK;
> }
> @@ -451,7 +451,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
> if (IS_HASWELL(dev_priv) ||
> IS_BROADWELL(dev_priv) ||
> INTEL_GEN(dev_priv) >= 9) {
> - dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
> + dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
> HSW_EDRAM_CAP);
Indentation is now broken for this line above.
With those 2 super important details addressed or not:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> /* NB: We can't write IDICR yet because we do not have gt funcs
> @@ -470,11 +470,11 @@ fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> {
> u32 dbg;
>
> - dbg = __raw_i915_read32(uncore, FPGA_DBG);
> + dbg = __raw_uncore_read32(uncore, FPGA_DBG);
> if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
> return false;
>
> - __raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
> + __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
>
> return true;
> }
> @@ -484,11 +484,11 @@ vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
> {
> u32 cer;
>
> - cer = __raw_i915_read32(uncore, CLAIM_ER);
> + cer = __raw_uncore_read32(uncore, CLAIM_ER);
> if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
> return false;
>
> - __raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
> + __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
>
> return true;
> }
> @@ -498,11 +498,11 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
> {
> u32 fifodbg;
>
> - fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
> + fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
>
> if (unlikely(fifodbg)) {
> DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
> - __raw_i915_write32(uncore, GTFIFODBG, fifodbg);
> + __raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
> }
>
> return fifodbg;
> @@ -537,10 +537,10 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
>
> /* WaDisableShadowRegForCpd:chv */
> if (IS_CHERRYVIEW(i915)) {
> - __raw_i915_write32(uncore, GTFIFOCTL,
> - __raw_i915_read32(uncore, GTFIFOCTL) |
> - GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> - GT_FIFO_CTL_RC6_POLICY_STALL);
> + __raw_uncore_write32(uncore, GTFIFOCTL,
> + __raw_uncore_read32(uncore, GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
> }
>
> iosf_mbi_punit_acquire();
> @@ -1068,7 +1068,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
> /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
> * the chip from rc6 before touching it for real. MI_MODE is masked,
> * hence harmless to write 0 into. */
> - __raw_i915_write32(uncore, MI_MODE, 0);
> + __raw_uncore_write32(uncore, MI_MODE, 0);
> }
>
> static void
> @@ -1110,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> static u##x \
> gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
> GEN2_READ_HEADER(x); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN2_READ_FOOTER; \
> }
>
> @@ -1119,7 +1119,7 @@ static u##x \
> gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
> GEN2_READ_HEADER(x); \
> ilk_dummy_write(uncore); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN2_READ_FOOTER; \
> }
>
> @@ -1189,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
> fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
> if (fw_engine) \
> __force_wake_auto(uncore, fw_engine); \
> - val = __raw_i915_read##x(uncore, reg); \
> + val = __raw_uncore_read##x(uncore, reg); \
> GEN6_READ_FOOTER; \
> }
> #define __gen6_read(x) __gen_read(gen6, x)
> @@ -1226,7 +1226,7 @@ __gen6_read(64)
> static void \
> gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
> GEN2_WRITE_HEADER; \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN2_WRITE_FOOTER; \
> }
>
> @@ -1235,7 +1235,7 @@ static void \
> gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
> GEN2_WRITE_HEADER; \
> ilk_dummy_write(uncore); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN2_WRITE_FOOTER; \
> }
>
> @@ -1271,7 +1271,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
> GEN6_WRITE_HEADER; \
> if (NEEDS_FORCE_WAKE(offset)) \
> __gen6_gt_wait_for_fifo(uncore); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN6_WRITE_FOOTER; \
> }
>
> @@ -1283,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
> fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
> if (fw_engine) \
> __force_wake_auto(uncore, fw_engine); \
> - __raw_i915_write##x(uncore, reg, val); \
> + __raw_uncore_write##x(uncore, reg, val); \
> GEN6_WRITE_FOOTER; \
> }
> #define __gen8_write(x) __gen_write(gen8, x)
> @@ -1470,7 +1470,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> * before the ecobus check.
> */
>
> - __raw_i915_write32(uncore, FORCEWAKE, 0);
> + __raw_uncore_write32(uncore, FORCEWAKE, 0);
> __raw_posting_read(uncore, ECOBUS);
>
> fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> @@ -1478,7 +1478,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>
> spin_lock_irq(&uncore->lock);
> fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
> - ecobus = __raw_i915_read32(uncore, ECOBUS);
> + ecobus = __raw_uncore_read32(uncore, ECOBUS);
> fw_domains_put(uncore, FORCEWAKE_RENDER);
> spin_unlock_irq(&uncore->lock);
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index d345e5ab04a5..f7670cbc41c9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -215,6 +215,33 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
> 2, timeout_ms, NULL);
> }
>
> +/* register access functions */
> +#define __raw_read(x__, s__) \
> +static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
> + i915_reg_t reg) \
> +{ \
> + return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +
> +#define __raw_write(x__, s__) \
> +static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
> + i915_reg_t reg, u##x__ val) \
> +{ \
> + write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
> +}
> +__raw_read(8, b)
> +__raw_read(16, w)
> +__raw_read(32, l)
> +__raw_read(64, q)
> +
> +__raw_write(8, b)
> +__raw_write(16, w)
> +__raw_write(32, l)
> +__raw_write(64, q)
> +
> +#undef __raw_read
> +#undef __raw_write
> +
> #define raw_reg_read(base, reg) \
> readl(base + i915_mmio_reg_offset(reg))
> #define raw_reg_write(base, reg, value) \
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 1/9] drm/i915: rename raw reg access functions
2019-03-25 22:41 ` Paulo Zanoni
@ 2019-03-25 22:57 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2019-03-25 22:57 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Paulo Zanoni, intel-gfx
Quoting Paulo Zanoni (2019-03-25 22:41:55)
> Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 1816eeae3ba9..3f74889c4212 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -31,7 +31,7 @@
> > #define FORCEWAKE_ACK_TIMEOUT_MS 50
> > #define GT_FIFO_TIMEOUT_MS 10
> >
> > -#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
> > +#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
>
> Now the person trying to figure out what __raw_posting_read() does will
> have to chase __raw_uncore_read32(), which is not even greppable. I'm
> not sure this is an improvement to our codebase, but the neatness of
> just passing everything does have some value. Not really a big deal, so
> I'm not blocking merging on this.
By the time you get down to __raw_versions, you should have established the
pattern in the higher level functions to figure out that by this point
this is just a convenient wrapper around readl. I hope.
Note, you can kill __raw_posting_read() which should help.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/9] drm/i915: rename raw reg access functions
2019-03-25 21:49 ` [PATCH 1/9] drm/i915: rename raw reg access functions Daniele Ceraolo Spurio
2019-03-25 22:41 ` Paulo Zanoni
@ 2019-03-26 4:18 ` kbuild test robot
2019-03-26 4:37 ` kbuild test robot
2 siblings, 0 replies; 27+ messages in thread
From: kbuild test robot @ 2019-03-26 4:18 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all, Paulo Zanoni
[-- Attachment #1: Type: text/plain, Size: 17845 bytes --]
Hi Daniele,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190325]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x003-201912 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
^~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
arch/x86/include/asm/io.h:59:17: error: conflicting types for 'readl'
build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
^
arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
static inline type name(const volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readl' was here
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:234:1: note: in expansion of macro '__raw_read'
__raw_read(32, l)
^~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
arch/x86/include/asm/io.h:65:18: warning: conflicting types for 'writeb'
build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:65:18: error: static declaration of 'writeb' follows non-static declaration
build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeb' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:237:1: note: in expansion of macro '__raw_write'
__raw_write(8, b)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
arch/x86/include/asm/io.h:66:18: warning: conflicting types for 'writew'
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:66:18: error: static declaration of 'writew' follows non-static declaration
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writew' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:238:1: note: in expansion of macro '__raw_write'
__raw_write(16, w)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
arch/x86/include/asm/io.h:67:18: warning: conflicting types for 'writel'
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:67:18: error: static declaration of 'writel' follows non-static declaration
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writel' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:239:1: note: in expansion of macro '__raw_write'
__raw_write(32, l)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
>> arch/x86/include/asm/io.h:97:17: error: conflicting types for 'readq'
build_mmio_read(readq, "q", u64, "=r", :"memory")
^
arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
static inline type name(const volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readq' was here
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
__raw_read(64, q)
^~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu/drm/i915/i915_vma.h:28,
from drivers/gpu/drm/i915/intel_guc.h:36,
from drivers/gpu/drm/i915/intel_guc.c:25:
>> arch/x86/include/asm/io.h:99:18: warning: conflicting types for 'writeq'
build_mmio_write(writeq, "q", u64, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
>> arch/x86/include/asm/io.h:99:18: error: static declaration of 'writeq' follows non-static declaration
build_mmio_write(writeq, "q", u64, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeq' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
__raw_write(64, q)
^~~~~~~~~~~
cc1: some warnings being treated as errors
--
^
arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
static inline type name(const volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readl' was here
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:234:1: note: in expansion of macro '__raw_read'
__raw_read(32, l)
^~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu//drm/i915/i915_vma.h:28,
from drivers/gpu//drm/i915/intel_guc.h:36,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
arch/x86/include/asm/io.h:65:18: warning: conflicting types for 'writeb'
build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:65:18: error: static declaration of 'writeb' follows non-static declaration
build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeb' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:237:1: note: in expansion of macro '__raw_write'
__raw_write(8, b)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu//drm/i915/i915_vma.h:28,
from drivers/gpu//drm/i915/intel_guc.h:36,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
arch/x86/include/asm/io.h:66:18: warning: conflicting types for 'writew'
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:66:18: error: static declaration of 'writew' follows non-static declaration
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writew' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:238:1: note: in expansion of macro '__raw_write'
__raw_write(16, w)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu//drm/i915/i915_vma.h:28,
from drivers/gpu//drm/i915/intel_guc.h:36,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
arch/x86/include/asm/io.h:67:18: warning: conflicting types for 'writel'
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
arch/x86/include/asm/io.h:67:18: error: static declaration of 'writel' follows non-static declaration
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writel' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:239:1: note: in expansion of macro '__raw_write'
__raw_write(32, l)
^~~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu//drm/i915/i915_vma.h:28,
from drivers/gpu//drm/i915/intel_guc.h:36,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
>> arch/x86/include/asm/io.h:97:17: error: conflicting types for 'readq'
build_mmio_read(readq, "q", u64, "=r", :"memory")
^
arch/x86/include/asm/io.h:48:20: note: in definition of macro 'build_mmio_read'
static inline type name(const volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:223:9: note: previous implicit declaration of 'readq' was here
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
__raw_read(64, q)
^~~~~~~~~~
In file included from include/linux/io.h:25:0,
from include/linux/io-mapping.h:24,
from drivers/gpu//drm/i915/i915_vma.h:28,
from drivers/gpu//drm/i915/intel_guc.h:36,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
>> arch/x86/include/asm/io.h:99:18: warning: conflicting types for 'writeq'
build_mmio_write(writeq, "q", u64, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
>> arch/x86/include/asm/io.h:99:18: error: static declaration of 'writeq' follows non-static declaration
build_mmio_write(writeq, "q", u64, "r", :"memory")
^
arch/x86/include/asm/io.h:53:20: note: in definition of macro 'build_mmio_write'
static inline void name(type val, volatile void __iomem *addr) \
^~~~
In file included from drivers/gpu//drm/i915/intel_guc.h:28:0,
from drivers/gpu//drm/i915/intel_uc.h:27,
from drivers/gpu//drm/i915/intel_uc.c:25:
drivers/gpu//drm/i915/intel_uncore.h:230:2: note: previous implicit declaration of 'writeq' was here
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu//drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
__raw_write(64, q)
^~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/readq +97 arch/x86/include/asm/io.h
93093d099 arch/x86/include/asm/io.h Ingo Molnar 2008-11-30 96
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15 @97 build_mmio_read(readq, "q", u64, "=r", :"memory")
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15 98 build_mmio_read(__readq, "q", u64, "=r", )
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15 @99 build_mmio_write(writeq, "q", u64, "r", :"memory")
6469a0ee0 arch/x86/include/asm/io.h Andy Shevchenko 2018-05-15 100 build_mmio_write(__writeq, "q", u64, "r", )
c1f64a580 include/asm-x86/io.h Linus Torvalds 2008-05-27 101
:::::: The code at line 97 was first introduced by commit
:::::: 6469a0ee0a06b2ea1f5afbb1d5a3feed017d4c7a x86/io: Define readq()/writeq() to use 64-bit type
:::::: TO: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
:::::: CC: Ingo Molnar <mingo@kernel.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 1/9] drm/i915: rename raw reg access functions
2019-03-25 21:49 ` [PATCH 1/9] drm/i915: rename raw reg access functions Daniele Ceraolo Spurio
2019-03-25 22:41 ` Paulo Zanoni
2019-03-26 4:18 ` kbuild test robot
@ 2019-03-26 4:37 ` kbuild test robot
2 siblings, 0 replies; 27+ messages in thread
From: kbuild test robot @ 2019-03-26 4:37 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all, Paulo Zanoni
[-- Attachment #1: Type: text/plain, Size: 2726 bytes --]
Hi Daniele,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190325]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x011-201912 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All error/warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_guc.c:25:
drivers/gpu/drm/i915/intel_uncore.h: In function '__raw_uncore_read64':
>> drivers/gpu/drm/i915/intel_uncore.h:223:9: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
>> drivers/gpu/drm/i915/intel_uncore.h:235:1: note: in expansion of macro '__raw_read'
__raw_read(64, q)
^~~~~~~~~~
drivers/gpu/drm/i915/intel_uncore.h: In function '__raw_uncore_write64':
>> drivers/gpu/drm/i915/intel_uncore.h:230:2: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
>> drivers/gpu/drm/i915/intel_uncore.h:240:1: note: in expansion of macro '__raw_write'
__raw_write(64, q)
^~~~~~~~~~~
cc1: some warnings being treated as errors
vim +223 drivers/gpu/drm/i915/intel_uncore.h
217
218 /* register access functions */
219 #define __raw_read(x__, s__) \
220 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
221 i915_reg_t reg) \
222 { \
> 223 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
224 }
225
226 #define __raw_write(x__, s__) \
227 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
228 i915_reg_t reg, u##x__ val) \
229 { \
> 230 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
231 }
232 __raw_read(8, b)
233 __raw_read(16, w)
234 __raw_read(32, l)
> 235 __raw_read(64, q)
236
237 __raw_write(8, b)
238 __raw_write(16, w)
239 __raw_write(32, l)
> 240 __raw_write(64, q)
241
---
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
2019-03-25 21:49 ` [PATCH 1/9] drm/i915: rename raw reg access functions Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-26 0:13 ` Paulo Zanoni
2019-03-26 12:47 ` Michal Wajdeczko
2019-03-25 21:49 ` [PATCH 3/9] drm/i915: add uncore flags for unclaimed mmio Daniele Ceraolo Spurio
` (10 subsequent siblings)
12 siblings, 2 replies; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
We have several cases where we don't have forcewake (older gens, GVT and
planned display-only uncore), so, instead of checking every time against
the various condition, save the info in a flag and use that.
Note that this patch also change the behavior for gen5 with vpgu
enabled, but this is not an issue since we don't support vgpu on gen5.
v2: split out from previous path, fix check for missing case (Paulo)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_uncore.c | 31 +++++++++++++++++++----------
drivers/gpu/drm/i915/intel_uncore.h | 3 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 3f74889c4212..0259a61a745f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1391,7 +1391,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore_to_i915(uncore);
- if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
+ if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
return;
if (INTEL_GEN(i915) >= 11) {
@@ -1590,6 +1590,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
i915_check_vgpu(i915);
+ if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
+ uncore->flags |= UNCORE_HAS_FORCEWAKE;
+
intel_uncore_edram_detect(i915);
intel_uncore_fw_domains_init(uncore);
__intel_uncore_early_sanitize(uncore, 0);
@@ -1598,12 +1601,14 @@ int intel_uncore_init(struct intel_uncore *uncore)
uncore->pmic_bus_access_nb.notifier_call =
i915_pmic_bus_access_notifier;
- if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
- } else if (IS_GEN(i915, 5)) {
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+ if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
+ if (IS_GEN(i915, 5)) {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
+ } else {
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
+ ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
+ }
} else if (IS_GEN_RANGE(i915, 6, 7)) {
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
@@ -1912,7 +1917,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
} else if (INTEL_GEN(dev_priv) >= 6) {
fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
} else {
- WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+ /* on devices with FW we expect to hit one of the above cases */
+ if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
+ MISSING_CASE(INTEL_GEN(dev_priv));
+
fw_domains = 0;
}
@@ -1938,7 +1946,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
} else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
fw_domains = FORCEWAKE_RENDER;
} else {
- WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
+ /* on devices with FW we expect to hit one of the above cases */
+ if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
+ MISSING_CASE(INTEL_GEN(dev_priv));
+
fw_domains = 0;
}
@@ -1969,7 +1980,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
WARN_ON(!op);
- if (intel_vgpu_active(dev_priv))
+ if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
return 0;
if (op & FW_REG_READ)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index f7670cbc41c9..4947542c6ea7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -127,6 +127,9 @@ struct intel_uncore {
} user_forcewake;
int unclaimed_mmio_check;
+
+ u32 flags;
+#define UNCORE_HAS_FORCEWAKE BIT(0)
};
/* Iterate over initialised fw domains */
--
2.20.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore
2019-03-25 21:49 ` [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore Daniele Ceraolo Spurio
@ 2019-03-26 0:13 ` Paulo Zanoni
2019-03-26 12:47 ` Michal Wajdeczko
1 sibling, 0 replies; 27+ messages in thread
From: Paulo Zanoni @ 2019-03-26 0:13 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> We have several cases where we don't have forcewake (older gens, GVT and
> planned display-only uncore), so, instead of checking every time against
> the various condition, save the info in a flag and use that.
>
> Note that this patch also change the behavior for gen5 with vpgu
> enabled, but this is not an issue since we don't support vgpu on gen5.
>
> v2: split out from previous path, fix check for missing case (Paulo)
Much better as a separate patch. Thanks.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 31 +++++++++++++++++++----------
> drivers/gpu/drm/i915/intel_uncore.h | 3 +++
> 2 files changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 3f74889c4212..0259a61a745f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1391,7 +1391,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore_to_i915(uncore);
>
> - if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
> return;
>
> if (INTEL_GEN(i915) >= 11) {
> @@ -1590,6 +1590,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
>
> i915_check_vgpu(i915);
>
> + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
> + uncore->flags |= UNCORE_HAS_FORCEWAKE;
> +
> intel_uncore_edram_detect(i915);
> intel_uncore_fw_domains_init(uncore);
> __intel_uncore_early_sanitize(uncore, 0);
> @@ -1598,12 +1601,14 @@ int intel_uncore_init(struct intel_uncore *uncore)
> uncore->pmic_bus_access_nb.notifier_call =
> i915_pmic_bus_access_notifier;
>
> - if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> - } else if (IS_GEN(i915, 5)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
> + if (IS_GEN(i915, 5)) {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + } else {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> + }
> } else if (IS_GEN_RANGE(i915, 6, 7)) {
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
>
> @@ -1912,7 +1917,10 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> } else if (INTEL_GEN(dev_priv) >= 6) {
> fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + /* on devices with FW we expect to hit one of the above cases */
> + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> + MISSING_CASE(INTEL_GEN(dev_priv));
> +
> fw_domains = 0;
> }
>
> @@ -1938,7 +1946,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> fw_domains = FORCEWAKE_RENDER;
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + /* on devices with FW we expect to hit one of the above cases */
> + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> + MISSING_CASE(INTEL_GEN(dev_priv));
> +
> fw_domains = 0;
> }
>
> @@ -1969,7 +1980,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
>
> WARN_ON(!op);
>
> - if (intel_vgpu_active(dev_priv))
> + if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
> return 0;
>
> if (op & FW_REG_READ)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index f7670cbc41c9..4947542c6ea7 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -127,6 +127,9 @@ struct intel_uncore {
> } user_forcewake;
>
> int unclaimed_mmio_check;
> +
> + u32 flags;
> +#define UNCORE_HAS_FORCEWAKE BIT(0)
> };
>
> /* Iterate over initialised fw domains */
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^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore
2019-03-25 21:49 ` [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore Daniele Ceraolo Spurio
2019-03-26 0:13 ` Paulo Zanoni
@ 2019-03-26 12:47 ` Michal Wajdeczko
2019-03-26 21:48 ` Chris Wilson
1 sibling, 1 reply; 27+ messages in thread
From: Michal Wajdeczko @ 2019-03-26 12:47 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio; +Cc: Paulo Zanoni
On Mon, 25 Mar 2019 22:49:33 +0100, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> We have several cases where we don't have forcewake (older gens, GVT and
> planned display-only uncore), so, instead of checking every time against
> the various condition, save the info in a flag and use that.
>
> Note that this patch also change the behavior for gen5 with vpgu
> enabled, but this is not an issue since we don't support vgpu on gen5.
>
> v2: split out from previous path, fix check for missing case (Paulo)
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 31 +++++++++++++++++++----------
> drivers/gpu/drm/i915/intel_uncore.h | 3 +++
> 2 files changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 3f74889c4212..0259a61a745f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1391,7 +1391,7 @@ static void intel_uncore_fw_domains_init(struct
> intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore_to_i915(uncore);
> - if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
> return;
> if (INTEL_GEN(i915) >= 11) {
> @@ -1590,6 +1590,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
> i915_check_vgpu(i915);
> + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
> + uncore->flags |= UNCORE_HAS_FORCEWAKE;
> +
> intel_uncore_edram_detect(i915);
> intel_uncore_fw_domains_init(uncore);
> __intel_uncore_early_sanitize(uncore, 0);
> @@ -1598,12 +1601,14 @@ int intel_uncore_init(struct intel_uncore
> *uncore)
> uncore->pmic_bus_access_nb.notifier_call =
> i915_pmic_bus_access_notifier;
> - if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> - } else if (IS_GEN(i915, 5)) {
> - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
> + if (IS_GEN(i915, 5)) {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> + } else {
> + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> + ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> + }
> } else if (IS_GEN_RANGE(i915, 6, 7)) {
> ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
> @@ -1912,7 +1917,10 @@ intel_uncore_forcewake_for_read(struct
> drm_i915_private *dev_priv,
> } else if (INTEL_GEN(dev_priv) >= 6) {
> fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + /* on devices with FW we expect to hit one of the above cases */
> + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> + MISSING_CASE(INTEL_GEN(dev_priv));
> +
> fw_domains = 0;
> }
> @@ -1938,7 +1946,10 @@ intel_uncore_forcewake_for_write(struct
> drm_i915_private *dev_priv,
> } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> fw_domains = FORCEWAKE_RENDER;
> } else {
> - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> + /* on devices with FW we expect to hit one of the above cases */
> + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> + MISSING_CASE(INTEL_GEN(dev_priv));
> +
> fw_domains = 0;
> }
> @@ -1969,7 +1980,7 @@ intel_uncore_forcewake_for_reg(struct
> drm_i915_private *dev_priv,
> WARN_ON(!op);
> - if (intel_vgpu_active(dev_priv))
> + if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
nit: as this condition is used in few places, maybe we can add nice helper:
static inline bool intel_uncore_has_forcewake(struct intel_uncore *uncore)
{
return uncore->flags & UNCORE_HAS_FORCEWAKE;
}
Michal
> return 0;
> if (op & FW_REG_READ)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
> b/drivers/gpu/drm/i915/intel_uncore.h
> index f7670cbc41c9..4947542c6ea7 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -127,6 +127,9 @@ struct intel_uncore {
> } user_forcewake;
> int unclaimed_mmio_check;
> +
> + u32 flags;
> +#define UNCORE_HAS_FORCEWAKE BIT(0)
> };
> /* Iterate over initialised fw domains */
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore
2019-03-26 12:47 ` Michal Wajdeczko
@ 2019-03-26 21:48 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2019-03-26 21:48 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Michal Wajdeczko, intel-gfx; +Cc: Paulo Zanoni
Quoting Michal Wajdeczko (2019-03-26 12:47:00)
> On Mon, 25 Mar 2019 22:49:33 +0100, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
> > We have several cases where we don't have forcewake (older gens, GVT and
> > planned display-only uncore), so, instead of checking every time against
> > the various condition, save the info in a flag and use that.
> >
> > Note that this patch also change the behavior for gen5 with vpgu
> > enabled, but this is not an issue since we don't support vgpu on gen5.
> >
> > v2: split out from previous path, fix check for missing case (Paulo)
> >
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 31 +++++++++++++++++++----------
> > drivers/gpu/drm/i915/intel_uncore.h | 3 +++
> > 2 files changed, 24 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 3f74889c4212..0259a61a745f 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1391,7 +1391,7 @@ static void intel_uncore_fw_domains_init(struct
> > intel_uncore *uncore)
> > {
> > struct drm_i915_private *i915 = uncore_to_i915(uncore);
> > - if (INTEL_GEN(i915) <= 5 || intel_vgpu_active(i915))
> > + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
> > return;
> > if (INTEL_GEN(i915) >= 11) {
> > @@ -1590,6 +1590,9 @@ int intel_uncore_init(struct intel_uncore *uncore)
> > i915_check_vgpu(i915);
> > + if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
> > + uncore->flags |= UNCORE_HAS_FORCEWAKE;
> > +
> > intel_uncore_edram_detect(i915);
> > intel_uncore_fw_domains_init(uncore);
> > __intel_uncore_early_sanitize(uncore, 0);
> > @@ -1598,12 +1601,14 @@ int intel_uncore_init(struct intel_uncore
> > *uncore)
> > uncore->pmic_bus_access_nb.notifier_call =
> > i915_pmic_bus_access_notifier;
> > - if (IS_GEN_RANGE(i915, 2, 4) || intel_vgpu_active(i915)) {
> > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> > - ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> > - } else if (IS_GEN(i915, 5)) {
> > - ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> > - ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> > + if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
> > + if (IS_GEN(i915, 5)) {
> > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
> > + ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
> > + } else {
> > + ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
> > + ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
> > + }
> > } else if (IS_GEN_RANGE(i915, 6, 7)) {
> > ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
> > @@ -1912,7 +1917,10 @@ intel_uncore_forcewake_for_read(struct
> > drm_i915_private *dev_priv,
> > } else if (INTEL_GEN(dev_priv) >= 6) {
> > fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
> > } else {
> > - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> > + /* on devices with FW we expect to hit one of the above cases */
> > + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> > + MISSING_CASE(INTEL_GEN(dev_priv));
> > +
> > fw_domains = 0;
> > }
> > @@ -1938,7 +1946,10 @@ intel_uncore_forcewake_for_write(struct
> > drm_i915_private *dev_priv,
> > } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> > fw_domains = FORCEWAKE_RENDER;
> > } else {
> > - WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> > + /* on devices with FW we expect to hit one of the above cases */
> > + if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
> > + MISSING_CASE(INTEL_GEN(dev_priv));
> > +
> > fw_domains = 0;
> > }
> > @@ -1969,7 +1980,7 @@ intel_uncore_forcewake_for_reg(struct
> > drm_i915_private *dev_priv,
> > WARN_ON(!op);
> > - if (intel_vgpu_active(dev_priv))
> > + if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
>
> nit: as this condition is used in few places, maybe we can add nice helper:
>
> static inline bool intel_uncore_has_forcewake(struct intel_uncore *uncore)
> {
> return uncore->flags & UNCORE_HAS_FORCEWAKE;
> }
Did a quick pass to apply the nit and quieten checkpatch and pushed.
Thanks,
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 3/9] drm/i915: add uncore flags for unclaimed mmio
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
2019-03-25 21:49 ` [PATCH 1/9] drm/i915: rename raw reg access functions Daniele Ceraolo Spurio
2019-03-25 21:49 ` [PATCH 2/9] drm/i915: add HAS_FORCEWAKE flag to uncore Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-26 0:19 ` Paulo Zanoni
2019-03-25 21:49 ` [PATCH 4/9] drm/i915: take a ref to the rpm in the uncore structure Daniele Ceraolo Spurio
` (9 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Save the HW capabilities to avoid having to jump back to dev_priv
every time.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 57 ++++++++++---------
drivers/gpu/drm/i915/intel_uncore.h | 7 ++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 ++---
6 files changed, 47 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5465b99b4392..85e80701a4c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2854,7 +2854,7 @@ static int intel_runtime_suspend(struct device *kdev)
enable_rpm_wakeref_asserts(dev_priv);
intel_runtime_pm_cleanup(dev_priv);
- if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
+ if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
dev_priv->runtime_pm.suspended = true;
@@ -2908,7 +2908,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_opregion_notify_adapter(dev_priv, PCI_D0);
dev_priv->runtime_pm.suspended = false;
- if (intel_uncore_unclaimed_mmio(dev_priv))
+ if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
if (INTEL_GEN(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 008560ef4db0..9a9b78c120b1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13533,7 +13533,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
* so enable debugging for the next modeset - and hope we catch
* the culprit.
*/
- intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
}
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 57ed49dc19c4..125662c64934 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -270,7 +270,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
* periodically arm the mmio checker to see if we are triggering
* any invalid access.
*/
- intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
+ intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
for_each_engine(engine, dev_priv, id) {
struct hangcheck hc;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0259a61a745f..1a327828f220 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -509,18 +509,17 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
}
static bool
-check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
+check_for_unclaimed_mmio(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
- if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
+ if (uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED)
ret |= fpga_check_for_unclaimed_mmio(uncore);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ if (uncore->flags & UNCORE_HAS_DBG_UNCLAIMED)
ret |= vlv_check_for_unclaimed_mmio(uncore);
- if (IS_GEN_RANGE(dev_priv, 6, 7))
+ if (uncore->flags & UNCORE_HAS_FIFO)
ret |= gen6_check_for_fifo_debug(uncore);
return ret;
@@ -529,14 +528,12 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
unsigned int restore_forcewake)
{
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
-
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(i915))
+ if (check_for_unclaimed_mmio(uncore))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
- if (IS_CHERRYVIEW(i915)) {
+ if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
__raw_uncore_write32(uncore, GTFIFOCTL,
__raw_uncore_read32(uncore, GTFIFOCTL) |
GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
@@ -549,7 +546,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
spin_lock_irq(&uncore->lock);
uncore->funcs.force_wake_get(uncore, restore_forcewake);
- if (IS_GEN_RANGE(i915, 6, 7))
+ if (uncore->flags & UNCORE_HAS_FIFO)
uncore->fifo_count = fifo_free_entries(uncore);
spin_unlock_irq(&uncore->lock);
}
@@ -668,12 +665,10 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
*/
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
{
- struct drm_i915_private *i915 = uncore_to_i915(uncore);
-
spin_lock_irq(&uncore->lock);
if (!--uncore->user_forcewake.count) {
- if (intel_uncore_unclaimed_mmio(i915))
- dev_info(i915->drm.dev,
+ if (intel_uncore_unclaimed_mmio(uncore))
+ dev_info(uncore_to_i915(uncore)->drm.dev,
"Invalid mmio detected during user access\n");
uncore->unclaimed_mmio_check =
@@ -1072,12 +1067,12 @@ ilk_dummy_write(struct intel_uncore *uncore)
}
static void
-__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+__unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
const bool before)
{
- if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
+ if (WARN(check_for_unclaimed_mmio(uncore) && !before,
"Unclaimed %s register 0x%x\n",
read ? "read from" : "write to",
i915_mmio_reg_offset(reg)))
@@ -1086,7 +1081,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
}
static inline void
-unclaimed_reg_debug(struct drm_i915_private *dev_priv,
+unclaimed_reg_debug(struct intel_uncore *uncore,
const i915_reg_t reg,
const bool read,
const bool before)
@@ -1094,7 +1089,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
if (likely(!i915_modparams.mmio_debug))
return;
- __unclaimed_reg_debug(dev_priv, reg, read, before);
+ __unclaimed_reg_debug(uncore, reg, read, before);
}
#define GEN2_READ_HEADER(x) \
@@ -1145,10 +1140,10 @@ __gen2_read(64)
u##x val = 0; \
assert_rpm_wakelock_held(dev_priv); \
spin_lock_irqsave(&uncore->lock, irqflags); \
- unclaimed_reg_debug(dev_priv, reg, true, true)
+ unclaimed_reg_debug(uncore, reg, true, true)
#define GEN6_READ_FOOTER \
- unclaimed_reg_debug(dev_priv, reg, true, false); \
+ unclaimed_reg_debug(uncore, reg, true, false); \
spin_unlock_irqrestore(&uncore->lock, irqflags); \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
@@ -1259,10 +1254,10 @@ __gen2_write(32)
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
assert_rpm_wakelock_held(dev_priv); \
spin_lock_irqsave(&uncore->lock, irqflags); \
- unclaimed_reg_debug(dev_priv, reg, false, true)
+ unclaimed_reg_debug(uncore, reg, false, true)
#define GEN6_WRITE_FOOTER \
- unclaimed_reg_debug(dev_priv, reg, false, false); \
+ unclaimed_reg_debug(uncore, reg, false, false); \
spin_unlock_irqrestore(&uncore->lock, irqflags)
#define __gen6_write(x) \
@@ -1638,6 +1633,15 @@ int intel_uncore_init(struct intel_uncore *uncore)
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
}
+ if (HAS_FPGA_DBG_UNCLAIMED(i915))
+ uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
+
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
+
+ if (IS_GEN_RANGE(i915, 6, 7))
+ uncore->flags |= UNCORE_HAS_FIFO;
+
iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
return 0;
@@ -1869,15 +1873,14 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
return ret;
}
-bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
+bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
{
- return check_for_unclaimed_mmio(dev_priv);
+ return check_for_unclaimed_mmio(uncore);
}
bool
-intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
+intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
bool ret = false;
spin_lock_irq(&uncore->lock);
@@ -1885,7 +1888,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
if (unlikely(uncore->unclaimed_mmio_check <= 0))
goto out;
- if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
+ if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
if (!i915_modparams.mmio_debug) {
DRM_DEBUG("Unclaimed register detected, "
"enabling oneshot unclaimed register reporting. "
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 4947542c6ea7..9a2c4f3b87f2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -130,6 +130,9 @@ struct intel_uncore {
u32 flags;
#define UNCORE_HAS_FORCEWAKE BIT(0)
+#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
+#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
+#define UNCORE_HAS_FIFO BIT(3)
};
/* Iterate over initialised fw domains */
@@ -149,8 +152,8 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
int intel_uncore_init(struct intel_uncore *uncore);
void intel_uncore_prune(struct intel_uncore *uncore);
-bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
-bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
+bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
+bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
void intel_uncore_fini(struct intel_uncore *uncore);
void intel_uncore_suspend(struct intel_uncore *uncore);
void intel_uncore_resume_early(struct intel_uncore *uncore);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index c69a1bad8933..799aeedac91b 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -244,6 +244,7 @@ static int live_forcewake_domains(void *arg)
{
#define FW_RANGE 0x40000
struct drm_i915_private *dev_priv = arg;
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long *valid;
u32 offset;
int err;
@@ -263,31 +264,31 @@ static int live_forcewake_domains(void *arg)
if (!valid)
return -ENOMEM;
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- check_for_unclaimed_mmio(dev_priv);
+ check_for_unclaimed_mmio(uncore);
for (offset = 0; offset < FW_RANGE; offset += 4) {
i915_reg_t reg = { offset };
(void)I915_READ_FW(reg);
- if (!check_for_unclaimed_mmio(dev_priv))
+ if (!check_for_unclaimed_mmio(uncore))
set_bit(offset, valid);
}
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
err = 0;
for_each_set_bit(offset, valid, FW_RANGE) {
i915_reg_t reg = { offset };
iosf_mbi_punit_acquire();
- intel_uncore_forcewake_reset(&dev_priv->uncore);
+ intel_uncore_forcewake_reset(uncore);
iosf_mbi_punit_release();
- check_for_unclaimed_mmio(dev_priv);
+ check_for_unclaimed_mmio(uncore);
(void)I915_READ(reg);
- if (check_for_unclaimed_mmio(dev_priv)) {
+ if (check_for_unclaimed_mmio(uncore)) {
pr_err("Unclaimed mmio read to register 0x%04x\n",
offset);
err = -EINVAL;
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 3/9] drm/i915: add uncore flags for unclaimed mmio
2019-03-25 21:49 ` [PATCH 3/9] drm/i915: add uncore flags for unclaimed mmio Daniele Ceraolo Spurio
@ 2019-03-26 0:19 ` Paulo Zanoni
0 siblings, 0 replies; 27+ messages in thread
From: Paulo Zanoni @ 2019-03-26 0:19 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Em seg, 2019-03-25 às 14:49 -0700, Daniele Ceraolo Spurio escreveu:
> Save the HW capabilities to avoid having to jump back to dev_priv
> every time.
>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 57 ++++++++++---------
> drivers/gpu/drm/i915/intel_uncore.h | 7 ++-
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 15 ++---
> 6 files changed, 47 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5465b99b4392..85e80701a4c6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2854,7 +2854,7 @@ static int intel_runtime_suspend(struct device *kdev)
> enable_rpm_wakeref_asserts(dev_priv);
> intel_runtime_pm_cleanup(dev_priv);
>
> - if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
> + if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
> DRM_ERROR("Unclaimed access detected prior to suspending\n");
>
> dev_priv->runtime_pm.suspended = true;
> @@ -2908,7 +2908,7 @@ static int intel_runtime_resume(struct device *kdev)
>
> intel_opregion_notify_adapter(dev_priv, PCI_D0);
> dev_priv->runtime_pm.suspended = false;
> - if (intel_uncore_unclaimed_mmio(dev_priv))
> + if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
>
> if (INTEL_GEN(dev_priv) >= 11) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 008560ef4db0..9a9b78c120b1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13533,7 +13533,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
> * so enable debugging for the next modeset - and hope we catch
> * the culprit.
> */
> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
> intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index 57ed49dc19c4..125662c64934 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -270,7 +270,7 @@ static void i915_hangcheck_elapsed(struct work_struct *work)
> * periodically arm the mmio checker to see if we are triggering
> * any invalid access.
> */
> - intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
> + intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>
> for_each_engine(engine, dev_priv, id) {
> struct hangcheck hc;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0259a61a745f..1a327828f220 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -509,18 +509,17 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
> }
>
> static bool
> -check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
> +check_for_unclaimed_mmio(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> bool ret = false;
>
> - if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
> + if (uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED)
> ret |= fpga_check_for_unclaimed_mmio(uncore);
>
> - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> + if (uncore->flags & UNCORE_HAS_DBG_UNCLAIMED)
> ret |= vlv_check_for_unclaimed_mmio(uncore);
>
> - if (IS_GEN_RANGE(dev_priv, 6, 7))
> + if (uncore->flags & UNCORE_HAS_FIFO)
> ret |= gen6_check_for_fifo_debug(uncore);
>
> return ret;
> @@ -529,14 +528,12 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
> static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
> unsigned int restore_forcewake)
> {
> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
> -
> /* clear out unclaimed reg detection bit */
> - if (check_for_unclaimed_mmio(i915))
> + if (check_for_unclaimed_mmio(uncore))
> DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
>
> /* WaDisableShadowRegForCpd:chv */
> - if (IS_CHERRYVIEW(i915)) {
> + if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
> __raw_uncore_write32(uncore, GTFIFOCTL,
> __raw_uncore_read32(uncore, GTFIFOCTL) |
> GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> @@ -549,7 +546,7 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
> spin_lock_irq(&uncore->lock);
> uncore->funcs.force_wake_get(uncore, restore_forcewake);
>
> - if (IS_GEN_RANGE(i915, 6, 7))
> + if (uncore->flags & UNCORE_HAS_FIFO)
> uncore->fifo_count = fifo_free_entries(uncore);
> spin_unlock_irq(&uncore->lock);
> }
> @@ -668,12 +665,10 @@ void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)
> */
> void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)
> {
> - struct drm_i915_private *i915 = uncore_to_i915(uncore);
> -
> spin_lock_irq(&uncore->lock);
> if (!--uncore->user_forcewake.count) {
> - if (intel_uncore_unclaimed_mmio(i915))
> - dev_info(i915->drm.dev,
> + if (intel_uncore_unclaimed_mmio(uncore))
> + dev_info(uncore_to_i915(uncore)->drm.dev,
> "Invalid mmio detected during user access\n");
>
> uncore->unclaimed_mmio_check =
> @@ -1072,12 +1067,12 @@ ilk_dummy_write(struct intel_uncore *uncore)
> }
>
> static void
> -__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> +__unclaimed_reg_debug(struct intel_uncore *uncore,
> const i915_reg_t reg,
> const bool read,
> const bool before)
> {
> - if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
> + if (WARN(check_for_unclaimed_mmio(uncore) && !before,
> "Unclaimed %s register 0x%x\n",
> read ? "read from" : "write to",
> i915_mmio_reg_offset(reg)))
> @@ -1086,7 +1081,7 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> }
>
> static inline void
> -unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> +unclaimed_reg_debug(struct intel_uncore *uncore,
> const i915_reg_t reg,
> const bool read,
> const bool before)
> @@ -1094,7 +1089,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
> if (likely(!i915_modparams.mmio_debug))
> return;
>
> - __unclaimed_reg_debug(dev_priv, reg, read, before);
> + __unclaimed_reg_debug(uncore, reg, read, before);
> }
>
> #define GEN2_READ_HEADER(x) \
> @@ -1145,10 +1140,10 @@ __gen2_read(64)
> u##x val = 0; \
> assert_rpm_wakelock_held(dev_priv); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> - unclaimed_reg_debug(dev_priv, reg, true, true)
> + unclaimed_reg_debug(uncore, reg, true, true)
>
> #define GEN6_READ_FOOTER \
> - unclaimed_reg_debug(dev_priv, reg, true, false); \
> + unclaimed_reg_debug(uncore, reg, true, false); \
> spin_unlock_irqrestore(&uncore->lock, irqflags); \
> trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
> return val
> @@ -1259,10 +1254,10 @@ __gen2_write(32)
> trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> assert_rpm_wakelock_held(dev_priv); \
> spin_lock_irqsave(&uncore->lock, irqflags); \
> - unclaimed_reg_debug(dev_priv, reg, false, true)
> + unclaimed_reg_debug(uncore, reg, false, true)
>
> #define GEN6_WRITE_FOOTER \
> - unclaimed_reg_debug(dev_priv, reg, false, false); \
> + unclaimed_reg_debug(uncore, reg, false, false); \
> spin_unlock_irqrestore(&uncore->lock, irqflags)
>
> #define __gen6_write(x) \
> @@ -1638,6 +1633,15 @@ int intel_uncore_init(struct intel_uncore *uncore)
> ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> }
>
> + if (HAS_FPGA_DBG_UNCLAIMED(i915))
> + uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> +
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
> +
> + if (IS_GEN_RANGE(i915, 6, 7))
> + uncore->flags |= UNCORE_HAS_FIFO;
> +
> iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>
> return 0;
> @@ -1869,15 +1873,14 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> {
> - return check_for_unclaimed_mmio(dev_priv);
> + return check_for_unclaimed_mmio(uncore);
> }
>
> bool
> -intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
> +intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> bool ret = false;
>
> spin_lock_irq(&uncore->lock);
> @@ -1885,7 +1888,7 @@ intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
> if (unlikely(uncore->unclaimed_mmio_check <= 0))
> goto out;
>
> - if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
> + if (unlikely(intel_uncore_unclaimed_mmio(uncore))) {
> if (!i915_modparams.mmio_debug) {
> DRM_DEBUG("Unclaimed register detected, "
> "enabling oneshot unclaimed register reporting. "
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 4947542c6ea7..9a2c4f3b87f2 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -130,6 +130,9 @@ struct intel_uncore {
>
> u32 flags;
> #define UNCORE_HAS_FORCEWAKE BIT(0)
> +#define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
> +#define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
> +#define UNCORE_HAS_FIFO BIT(3)
> };
>
> /* Iterate over initialised fw domains */
> @@ -149,8 +152,8 @@ forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
> void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
> int intel_uncore_init(struct intel_uncore *uncore);
> void intel_uncore_prune(struct intel_uncore *uncore);
> -bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
> -bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
> +bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
> +bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
> void intel_uncore_fini(struct intel_uncore *uncore);
> void intel_uncore_suspend(struct intel_uncore *uncore);
> void intel_uncore_resume_early(struct intel_uncore *uncore);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index c69a1bad8933..799aeedac91b 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -244,6 +244,7 @@ static int live_forcewake_domains(void *arg)
> {
> #define FW_RANGE 0x40000
> struct drm_i915_private *dev_priv = arg;
> + struct intel_uncore *uncore = &dev_priv->uncore;
> unsigned long *valid;
> u32 offset;
> int err;
> @@ -263,31 +264,31 @@ static int live_forcewake_domains(void *arg)
> if (!valid)
> return -ENOMEM;
>
> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>
> - check_for_unclaimed_mmio(dev_priv);
> + check_for_unclaimed_mmio(uncore);
> for (offset = 0; offset < FW_RANGE; offset += 4) {
> i915_reg_t reg = { offset };
>
> (void)I915_READ_FW(reg);
> - if (!check_for_unclaimed_mmio(dev_priv))
> + if (!check_for_unclaimed_mmio(uncore))
> set_bit(offset, valid);
> }
>
> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>
> err = 0;
> for_each_set_bit(offset, valid, FW_RANGE) {
> i915_reg_t reg = { offset };
>
> iosf_mbi_punit_acquire();
> - intel_uncore_forcewake_reset(&dev_priv->uncore);
> + intel_uncore_forcewake_reset(uncore);
> iosf_mbi_punit_release();
>
> - check_for_unclaimed_mmio(dev_priv);
> + check_for_unclaimed_mmio(uncore);
>
> (void)I915_READ(reg);
> - if (check_for_unclaimed_mmio(dev_priv)) {
> + if (check_for_unclaimed_mmio(uncore)) {
> pr_err("Unclaimed mmio read to register 0x%04x\n",
> offset);
> err = -EINVAL;
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 4/9] drm/i915: take a ref to the rpm in the uncore structure
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 3/9] drm/i915: add uncore flags for unclaimed mmio Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-25 21:49 ` [PATCH 5/9] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
` (8 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Remove a bit of pointer dancing in the reg access path.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_drv.h | 17 ++++++++++++-----
drivers/gpu/drm/i915/intel_uncore.c | 16 +++++++++-------
drivers/gpu/drm/i915/intel_uncore.h | 3 +++
3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 862dc73bfbef..c41c7a64dcec 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2270,20 +2270,27 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
static inline void
-assert_rpm_device_not_suspended(struct drm_i915_private *i915)
+assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
{
- WARN_ONCE(i915->runtime_pm.suspended,
+ WARN_ONCE(rpm->suspended,
"Device suspended during HW access\n");
}
static inline void
-assert_rpm_wakelock_held(struct drm_i915_private *i915)
+__assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
{
- assert_rpm_device_not_suspended(i915);
- WARN_ONCE(!atomic_read(&i915->runtime_pm.wakeref_count),
+ assert_rpm_device_not_suspended(rpm);
+ WARN_ONCE(!atomic_read(&rpm->wakeref_count),
"RPM wakelock ref not held during HW access");
}
+static inline void
+assert_rpm_wakelock_held(struct drm_i915_private *i915)
+{
+ __assert_rpm_wakelock_held(&i915->runtime_pm);
+}
+
+
/**
* disable_rpm_wakeref_asserts - disable the RPM assert checks
* @i915: i915 device instance
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1a327828f220..527c264436dd 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -342,7 +342,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
unsigned long irqflags;
- assert_rpm_device_not_suspended(uncore_to_i915(uncore));
+ assert_rpm_device_not_suspended(uncore->rpm);
if (xchg(&domain->active, false))
return HRTIMER_RESTART;
@@ -623,7 +623,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
if (!uncore->funcs.force_wake_get)
return;
- assert_rpm_wakelock_held(uncore_to_i915(uncore));
+ __assert_rpm_wakelock_held(uncore->rpm);
spin_lock_irqsave(&uncore->lock, irqflags);
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -777,7 +777,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!uncore->funcs.force_wake_get)
return;
- assert_rpm_wakelock_held(uncore_to_i915(uncore));
+ __assert_rpm_wakelock_held(uncore->rpm);
fw_domains &= uncore->fw_domains;
WARN(fw_domains & ~uncore->fw_domains_active,
@@ -1095,7 +1095,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
#define GEN2_READ_HEADER(x) \
struct intel_uncore *uncore = &dev_priv->uncore; \
u##x val = 0; \
- assert_rpm_wakelock_held(dev_priv);
+ __assert_rpm_wakelock_held(uncore->rpm);
#define GEN2_READ_FOOTER \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
@@ -1138,7 +1138,7 @@ __gen2_read(64)
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
u##x val = 0; \
- assert_rpm_wakelock_held(dev_priv); \
+ __assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, true, true)
@@ -1213,7 +1213,7 @@ __gen6_read(64)
#define GEN2_WRITE_HEADER \
struct intel_uncore *uncore = &dev_priv->uncore; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
- assert_rpm_wakelock_held(dev_priv); \
+ __assert_rpm_wakelock_held(uncore->rpm); \
#define GEN2_WRITE_FOOTER
@@ -1252,7 +1252,7 @@ __gen2_write(32)
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
- assert_rpm_wakelock_held(dev_priv); \
+ __assert_rpm_wakelock_held(uncore->rpm); \
spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(uncore, reg, false, true)
@@ -1596,6 +1596,8 @@ int intel_uncore_init(struct intel_uncore *uncore)
uncore->pmic_bus_access_nb.notifier_call =
i915_pmic_bus_access_notifier;
+ uncore->rpm = &i915->runtime_pm;
+
if (!(uncore->flags & UNCORE_HAS_FORCEWAKE)) {
if (IS_GEN(i915, 5)) {
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 9a2c4f3b87f2..324f197b37c0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -32,6 +32,7 @@
#include "i915_reg.h"
struct drm_i915_private;
+struct i915_runtime_pm;
struct intel_uncore;
enum forcewake_domain_id {
@@ -95,6 +96,8 @@ struct intel_forcewake_range {
struct intel_uncore {
void __iomem *regs;
+ struct i915_runtime_pm *rpm;
+
spinlock_t lock; /** lock is also taken in irq contexts. */
const struct intel_forcewake_range *fw_domains_table;
--
2.20.1
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 5/9] drm/i915: switch uncore mmio funcs to use intel_uncore
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 4/9] drm/i915: take a ref to the rpm in the uncore structure Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-25 21:49 ` [PATCH 6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore Daniele Ceraolo Spurio
` (7 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The full read/write ops can now work on the intel_uncore struct.
Introduce intel_uncore_read/write functions working on intel_uncore
and switch the I915_READ/WRITE macro to internally call those.
v2: no change
v3: add intel_uncore_read/write functions (Chris), update commit msg
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 49 ++++-----
drivers/gpu/drm/i915/intel_uncore.c | 18 ++--
drivers/gpu/drm/i915/intel_uncore.h | 106 +++++++++++++++++--
drivers/gpu/drm/i915/selftests/mock_uncore.c | 4 +-
4 files changed, 130 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 558d40f07ffe..5b5ec7a5c386 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3465,18 +3465,21 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}
-#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
-#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
+#define __I915_REG_OP(op__, dev_priv__, ...) \
+ intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
-#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
-#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
-#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
-#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
+#define I915_READ8(reg__) __I915_REG_OP(read8, dev_priv, (reg__))
+#define I915_WRITE8(reg__, val__) __I915_REG_OP(write8, dev_priv, (reg__), (val__))
-#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
-#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
-#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
-#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
+#define I915_READ16(reg__) __I915_REG_OP(read16, dev_priv, (reg__))
+#define I915_WRITE16(reg__, val__) __I915_REG_OP(write16, dev_priv, (reg__), (val__))
+#define I915_READ16_NOTRACE(reg__) __I915_REG_OP(read16_notrace, dev_priv, (reg__))
+#define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
+
+#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
+#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
+#define I915_READ_NOTRACE(reg__) __I915_REG_OP(read_notrace, dev_priv, (reg__))
+#define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
* will be implemented using 2 32-bit writes in an arbitrary order with
@@ -3492,20 +3495,12 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
*
* You have been warned.
*/
-#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
-
-#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
- u32 upper, lower, old_upper, loop = 0; \
- upper = I915_READ(upper_reg); \
- do { \
- old_upper = upper; \
- lower = I915_READ(lower_reg); \
- upper = I915_READ(upper_reg); \
- } while (upper != old_upper && loop++ < 2); \
- (u64)upper << 32 | lower; })
+#define I915_READ64(reg__) __I915_REG_OP(read64, dev_priv, (reg__))
+#define I915_READ64_2x32(lower_reg__, upper_reg__) \
+ __I915_REG_OP(read64_2x32, dev_priv, (lower_reg__), (upper_reg__))
-#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
-#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
+#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
+#define POSTING_READ16(reg__) __I915_REG_OP(posting_read16, dev_priv, (reg__))
/* These are untraced mmio-accessors that are only valid to be used inside
* critical sections, such as inside IRQ handlers, where forcewake is explicitly
@@ -3533,10 +3528,10 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
-#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
-#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
-#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
-#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
+#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
+#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __I915_REG_OP(write64_fw, dev_priv, (reg__), (val__))
+#define POSTING_READ_FW(reg__) __I915_REG_OP(posting_read_fw, dev_priv, (reg__))
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 527c264436dd..900791c7b413 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1093,7 +1093,6 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
}
#define GEN2_READ_HEADER(x) \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u##x val = 0; \
__assert_rpm_wakelock_held(uncore->rpm);
@@ -1103,7 +1102,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore,
#define __gen2_read(x) \
static u##x \
-gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
val = __raw_uncore_read##x(uncore, reg); \
GEN2_READ_FOOTER; \
@@ -1111,7 +1110,7 @@ gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
#define __gen5_read(x) \
static u##x \
-gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
GEN2_READ_HEADER(x); \
ilk_dummy_write(uncore); \
val = __raw_uncore_read##x(uncore, reg); \
@@ -1134,7 +1133,6 @@ __gen2_read(64)
#undef GEN2_READ_HEADER
#define GEN6_READ_HEADER(x) \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
u##x val = 0; \
@@ -1178,7 +1176,7 @@ static inline void __force_wake_auto(struct intel_uncore *uncore,
#define __gen_read(func, x) \
static u##x \
-func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
+func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_READ_HEADER(x); \
fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
@@ -1211,7 +1209,6 @@ __gen6_read(64)
#undef GEN6_READ_HEADER
#define GEN2_WRITE_HEADER \
- struct intel_uncore *uncore = &dev_priv->uncore; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
__assert_rpm_wakelock_held(uncore->rpm); \
@@ -1219,7 +1216,7 @@ __gen6_read(64)
#define __gen2_write(x) \
static void \
-gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
__raw_uncore_write##x(uncore, reg, val); \
GEN2_WRITE_FOOTER; \
@@ -1227,7 +1224,7 @@ gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
#define __gen5_write(x) \
static void \
-gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN2_WRITE_HEADER; \
ilk_dummy_write(uncore); \
__raw_uncore_write##x(uncore, reg, val); \
@@ -1248,7 +1245,6 @@ __gen2_write(32)
#undef GEN2_WRITE_HEADER
#define GEN6_WRITE_HEADER \
- struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
@@ -1262,7 +1258,7 @@ __gen2_write(32)
#define __gen6_write(x) \
static void \
-gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
GEN6_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE(offset)) \
__gen6_gt_wait_for_fifo(uncore); \
@@ -1272,7 +1268,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
#define __gen_write(func, x) \
static void \
-func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
+func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_WRITE_HEADER; \
fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 324f197b37c0..42a00920996d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -69,20 +69,20 @@ struct intel_uncore_funcs {
void (*force_wake_put)(struct intel_uncore *uncore,
enum forcewake_domains domains);
- u8 (*mmio_readb)(struct drm_i915_private *dev_priv,
+ u8 (*mmio_readb)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u16 (*mmio_readw)(struct drm_i915_private *dev_priv,
+ u16 (*mmio_readw)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u32 (*mmio_readl)(struct drm_i915_private *dev_priv,
+ u32 (*mmio_readl)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- u64 (*mmio_readq)(struct drm_i915_private *dev_priv,
+ u64 (*mmio_readq)(struct intel_uncore *uncore,
i915_reg_t r, bool trace);
- void (*mmio_writeb)(struct drm_i915_private *dev_priv,
+ void (*mmio_writeb)(struct intel_uncore *uncore,
i915_reg_t r, u8 val, bool trace);
- void (*mmio_writew)(struct drm_i915_private *dev_priv,
+ void (*mmio_writew)(struct intel_uncore *uncore,
i915_reg_t r, u16 val, bool trace);
- void (*mmio_writel)(struct drm_i915_private *dev_priv,
+ void (*mmio_writel)(struct intel_uncore *uncore,
i915_reg_t r, u32 val, bool trace);
};
@@ -251,6 +251,98 @@ __raw_write(64, q)
#undef __raw_read
#undef __raw_write
+#define __uncore_read(name__, x__, s__, trace__) \
+static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
+ i915_reg_t reg) \
+{ \
+ return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
+}
+
+#define __uncore_write(name__, x__, s__, trace__) \
+static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
+ i915_reg_t reg, u##x__ val) \
+{ \
+ uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
+}
+
+__uncore_read(read8, 8, b, true)
+__uncore_read(read16, 16, w, true)
+__uncore_read(read, 32, l, true)
+__uncore_read(read16_notrace, 16, w, false)
+__uncore_read(read_notrace, 32, l, false)
+
+__uncore_write(write8, 8, b, true)
+__uncore_write(write16, 16, w, true)
+__uncore_write(write, 32, l, true)
+__uncore_write(write_notrace, 32, l, false)
+
+/* Be very careful with read/write 64-bit values. On 32-bit machines, they
+ * will be implemented using 2 32-bit writes in an arbitrary order with
+ * an arbitrary delay between them. This can cause the hardware to
+ * act upon the intermediate value, possibly leading to corruption and
+ * machine death. For this reason we do not support I915_WRITE64, or
+ * uncore->funcs.mmio_writeq.
+ *
+ * When reading a 64-bit value as two 32-bit values, the delay may cause
+ * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
+ * occasionally a 64-bit register does not actually support a full readq
+ * and must be read using two 32-bit reads.
+ *
+ * You have been warned.
+ */
+__uncore_read(read64, 64, q, true)
+
+static inline u64
+intel_uncore_read64_2x32(struct intel_uncore *uncore,
+ i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+ u32 upper, lower, old_upper, loop = 0;
+ upper = intel_uncore_read(uncore, upper_reg);
+ do {
+ old_upper = upper;
+ lower = intel_uncore_read(uncore, lower_reg);
+ upper = intel_uncore_read(uncore, upper_reg);
+ } while (upper != old_upper && loop++ < 2);
+ return (u64)upper << 32 | lower;
+}
+
+#define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
+#define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
+
+#undef __uncore_read
+#undef __uncore_write
+
+/* These are untraced mmio-accessors that are only valid to be used inside
+ * critical sections, such as inside IRQ handlers, where forcewake is explicitly
+ * controlled.
+ *
+ * Think twice, and think again, before using these.
+ *
+ * As an example, these accessors can possibly be used between:
+ *
+ * spin_lock_irq(&uncore->lock);
+ * intel_uncore_forcewake_get__locked();
+ *
+ * and
+ *
+ * intel_uncore_forcewake_put__locked();
+ * spin_unlock_irq(&uncore->lock);
+ *
+ *
+ * Note: some registers may not need forcewake held, so
+ * intel_uncore_forcewake_{get,put} can be omitted, see
+ * intel_uncore_forcewake_for_reg().
+ *
+ * Certain architectures will die if the same cacheline is concurrently accessed
+ * by different clients (e.g. on Ivybridge). Access to registers should
+ * therefore generally be serialised, by either the dev_priv->uncore.lock or
+ * a more localised lock guarding all access to that bank of registers.
+ */
+#define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
+#define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
+#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
+#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
+
#define raw_reg_read(base, reg) \
readl(base + i915_mmio_reg_offset(reg))
#define raw_reg_write(base, reg, value) \
diff --git a/drivers/gpu/drm/i915/selftests/mock_uncore.c b/drivers/gpu/drm/i915/selftests/mock_uncore.c
index c3896c1fd551..ff8999c63a12 100644
--- a/drivers/gpu/drm/i915/selftests/mock_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/mock_uncore.c
@@ -26,14 +26,14 @@
#define __nop_write(x) \
static void \
-nop_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { }
+nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
__nop_write(8)
__nop_write(16)
__nop_write(32)
#define __nop_read(x) \
static u##x \
-nop_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { return 0; }
+nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
__nop_read(8)
__nop_read(16)
__nop_read(32)
--
2.20.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 5/9] drm/i915: switch uncore mmio funcs to use intel_uncore Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-26 9:20 ` kbuild test robot
2019-03-25 21:49 ` [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore Daniele Ceraolo Spurio
` (6 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The intel_uncore structure is the owner of FW, so subclass the
function to it.
While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 11 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 21 +++++------
drivers/gpu/drm/i915/intel_guc.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 13 +++----
drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++----------
drivers/gpu/drm/i915/intel_uncore.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
8 files changed, 46 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index a00a807a1d55..76630fbe51b6 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -327,6 +327,7 @@ int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ struct intel_uncore *uncore = &dev_priv->uncore;
struct intel_vgpu_submission *s = &vgpu->submission;
enum forcewake_domains fw;
i915_reg_t reg;
@@ -351,21 +352,21 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
* otherwise device can go to RC6 state and interrupt invalidation
* process
*/
- fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
+ fw = intel_uncore_forcewake_for_reg(uncore, reg,
FW_REG_READ | FW_REG_WRITE);
if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
fw |= FORCEWAKE_RENDER;
- intel_uncore_forcewake_get(&dev_priv->uncore, fw);
+ intel_uncore_forcewake_get(uncore, fw);
- I915_WRITE_FW(reg, 0x1);
+ intel_uncore_write_fw(uncore, reg, 0x1);
- if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
+ if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))
gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
else
vgpu_vreg_t(vgpu, reg) = 0;
- intel_uncore_forcewake_put(&dev_priv->uncore, fw);
+ intel_uncore_forcewake_put(uncore, fw);
gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index c5b417327132..eb0fe9a58481 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -888,6 +888,7 @@ static inline u32
read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
int subslice, i915_reg_t reg)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 mcr_slice_subslice_mask;
u32 mcr_slice_subslice_select;
u32 default_mcr_s_ss_select;
@@ -909,33 +910,33 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(dev_priv);
- fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
FW_REG_READ);
- fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+ fw_domains |= intel_uncore_forcewake_for_reg(uncore,
GEN8_MCR_SELECTOR,
FW_REG_READ | FW_REG_WRITE);
- spin_lock_irq(&dev_priv->uncore.lock);
- intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
- mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+ mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
default_mcr_s_ss_select);
mcr &= ~mcr_slice_subslice_mask;
mcr |= mcr_slice_subslice_select;
- I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
- ret = I915_READ_FW(reg);
+ ret = intel_uncore_read_fw(uncore, reg);
mcr &= ~mcr_slice_subslice_mask;
mcr |= default_mcr_s_ss_select;
- I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
- intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
- spin_unlock_irq(&dev_priv->uncore.lock);
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irq(&uncore->lock);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index f2b4eaee8d52..dcb88e7b79c4 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -54,7 +54,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
for (i = 0; i < guc->send_regs.count; i++) {
- fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+ fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
guc_send_reg(guc, i),
FW_REG_READ | FW_REG_WRITE);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a9fff971129e..e5e030f4f43f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9959,6 +9959,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
const i915_reg_t reg)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u64 time_hw, prev_hw, overflow_hw;
unsigned int fw_domains;
unsigned long flags;
@@ -9980,10 +9981,10 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))
return 0;
- fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
- spin_lock_irqsave(&dev_priv->uncore.lock, flags);
- intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw_domains);
+ spin_lock_irqsave(&uncore->lock, flags);
+ intel_uncore_forcewake_get__locked(uncore, fw_domains);
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -10002,7 +10003,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
}
overflow_hw = BIT_ULL(32);
- time_hw = I915_READ_FW(reg);
+ time_hw = intel_uncore_read_fw(uncore, reg);
}
/*
@@ -10024,8 +10025,8 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
time_hw += dev_priv->gt_pm.rc6.cur_residency[i];
dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;
- intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw_domains);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+ intel_uncore_forcewake_put__locked(uncore, fw_domains);
+ spin_unlock_irqrestore(&uncore->lock, flags);
return mul_u64_u32_div(time_hw, mul, div);
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 900791c7b413..8265c00bad65 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1841,7 +1841,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
{
struct intel_uncore *uncore = &dev_priv->uncore;
unsigned fw =
- intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
+ intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
u32 reg_value;
int ret;
@@ -1904,23 +1904,23 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore)
}
static enum forcewake_domains
-intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
+intel_uncore_forcewake_for_read(struct intel_uncore *uncore,
i915_reg_t reg)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
u32 offset = i915_mmio_reg_offset(reg);
enum forcewake_domains fw_domains;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(i915) >= 11) {
fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
- } else if (HAS_FWTABLE(dev_priv)) {
+ } else if (HAS_FWTABLE(i915)) {
fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
- } else if (INTEL_GEN(dev_priv) >= 6) {
+ } else if (INTEL_GEN(i915) >= 6) {
fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
} else {
/* on devices with FW we expect to hit one of the above cases */
if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
- MISSING_CASE(INTEL_GEN(dev_priv));
+ MISSING_CASE(INTEL_GEN(i915));
fw_domains = 0;
}
@@ -1931,25 +1931,25 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
}
static enum forcewake_domains
-intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
+intel_uncore_forcewake_for_write(struct intel_uncore *uncore,
i915_reg_t reg)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
u32 offset = i915_mmio_reg_offset(reg);
enum forcewake_domains fw_domains;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(i915) >= 11) {
fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
- } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
+ } else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) {
fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
- } else if (IS_GEN(dev_priv, 8)) {
+ } else if (IS_GEN(i915, 8)) {
fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
- } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
+ } else if (IS_GEN_RANGE(i915, 6, 7)) {
fw_domains = FORCEWAKE_RENDER;
} else {
/* on devices with FW we expect to hit one of the above cases */
if (unlikely(uncore->flags & UNCORE_HAS_FORCEWAKE))
- MISSING_CASE(INTEL_GEN(dev_priv));
+ MISSING_CASE(INTEL_GEN(i915));
fw_domains = 0;
}
@@ -1974,21 +1974,21 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
* callers to do FIFO management on their own or risk losing writes.
*/
enum forcewake_domains
-intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
+intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
i915_reg_t reg, unsigned int op)
{
enum forcewake_domains fw_domains = 0;
WARN_ON(!op);
- if (!(dev_priv->uncore.flags & UNCORE_HAS_FORCEWAKE))
+ if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
return 0;
if (op & FW_REG_READ)
- fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);
+ fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
if (op & FW_REG_WRITE)
- fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);
+ fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
return fw_domains;
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 42a00920996d..a7cea6a9fd79 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -169,7 +169,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
enum forcewake_domains
-intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
+intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
i915_reg_t reg, unsigned int op);
#define FW_REG_READ (1)
#define FW_REG_WRITE (2)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index e758bbf50617..a04dbc58ec1c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -905,7 +905,7 @@ wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
unsigned int i;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- fw |= intel_uncore_forcewake_for_reg(dev_priv,
+ fw |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
wa->reg,
FW_REG_READ |
FW_REG_WRITE);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 799aeedac91b..ee0bc91f7664 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -184,7 +184,7 @@ static int live_forcewake_ops(void *arg)
if (!engine->default_state)
continue;
- fw_domains = intel_uncore_forcewake_for_reg(i915, mmio,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
FW_REG_READ);
if (!fw_domains)
continue;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore
2019-03-25 21:49 ` [PATCH 6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore Daniele Ceraolo Spurio
@ 2019-03-26 9:20 ` kbuild test robot
0 siblings, 0 replies; 27+ messages in thread
From: kbuild test robot @ 2019-03-26 9:20 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all, Paulo Zanoni
[-- Attachment #1: Type: text/plain, Size: 28435 bytes --]
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190326]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info'
net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info'
kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf'
include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found
include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip'
include/linux/iio/hw-consumer.h:1: warning: no structured comments found
include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry'
include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints'
include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb'
drivers/slimbus/stream.c:1: warning: no structured comments found
include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device'
drivers/target/target_core_device.c:1: warning: no structured comments found
drivers/usb/typec/bus.c:1: warning: no structured comments found
drivers/usb/typec/class.c:1: warning: no structured comments found
include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family'
fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete'
fs/file_table.c:1: warning: no structured comments found
fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end'
fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:183: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:374: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:375: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'end' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:866: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3104: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:375: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Function parameter or member 'ih' not described in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1: warning: no structured comments found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:128: warning: Incorrect use of kernel-doc format: Documentation Makefile include scripts source @atomic_obj
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj_lock' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: no structured comments found
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_pin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_unpin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_res_obj' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_get_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_import_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vunmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_mmap' not described in 'drm_driver'
include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found
drivers/gpu/drm/scheduler/sched_main.c:376: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:377: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:420: warning: Function parameter or member 'full_recovery' not described in 'drm_sched_start'
>> drivers/gpu/drm/i915/intel_uncore.c:1980: warning: Function parameter or member 'uncore' not described in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/intel_uncore.c:1980: warning: Excess function parameter 'dev_priv' description in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/i915_vma.h:50: warning: cannot understand function prototype: 'struct i915_vma '
drivers/gpu/drm/i915/i915_vma.h:1: warning: no structured comments found
drivers/gpu/drm/i915/intel_guc_fwif.h:536: warning: cannot understand function prototype: 'struct guc_log_buffer_state '
drivers/gpu/drm/i915/i915_trace.h:1: warning: no structured comments found
drivers/gpu/drm/i915/i915_reg.h:156: warning: bad line:
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'hw_id' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'max_active_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'supported_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:142: warning: Function parameter or member 'output_port' not described in 'komeda_component_output'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'component' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'crtc' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'plane' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'wb_conn' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'changed_active_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'affected_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'compiz' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'wb_layer' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'improc' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'ctrlr' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'funcs' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:321: warning: Function parameter or member 'pipe' not described in 'komeda_pipeline_state'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'dev' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'reg_base' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'chip' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'mclk' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'n_pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_plane.c:1: warning: no structured comments found
include/linux/skbuff.h:876: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'list' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'head_frag' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encapsulation' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_valid' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'vlan_present' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_level' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff'
include/net/sock.h:238: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_portpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_cookie' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_listener' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.rmem_alloc' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.len' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.head' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.tail' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_wq_raw' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.upper' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.lower' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gso_partial_features' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'switchdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'name_assign_type' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'mpls_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xdp_prog' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'qdisc_hash' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state'
Documentation/admin-guide/cgroup-v2.rst:1509: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1511: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1512: WARNING: Block quote ends without a blank line; unexpected unindent.
include/linux/interrupt.h:252: WARNING: Inline emphasis start-string without end-string.
include/net/mac80211.h:1214: ERROR: Unexpected indentation.
include/net/mac80211.h:1221: WARNING: Block quote ends without a blank line; unexpected unindent.
include/linux/wait.h:110: WARNING: Block quote ends without a blank line; unexpected unindent.
vim +1980 drivers/gpu/drm/i915/intel_uncore.c
3756685a Tvrtko Ursulin 2016-04-12 1961
3756685a Tvrtko Ursulin 2016-04-12 1962 /**
3756685a Tvrtko Ursulin 2016-04-12 1963 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
3756685a Tvrtko Ursulin 2016-04-12 1964 * a register
3756685a Tvrtko Ursulin 2016-04-12 1965 * @dev_priv: pointer to struct drm_i915_private
3756685a Tvrtko Ursulin 2016-04-12 1966 * @reg: register in question
3756685a Tvrtko Ursulin 2016-04-12 1967 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
3756685a Tvrtko Ursulin 2016-04-12 1968 *
3756685a Tvrtko Ursulin 2016-04-12 1969 * Returns a set of forcewake domains required to be taken with for example
3756685a Tvrtko Ursulin 2016-04-12 1970 * intel_uncore_forcewake_get for the specified register to be accessible in the
3756685a Tvrtko Ursulin 2016-04-12 1971 * specified mode (read, write or read/write) with raw mmio accessors.
3756685a Tvrtko Ursulin 2016-04-12 1972 *
3756685a Tvrtko Ursulin 2016-04-12 1973 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
3756685a Tvrtko Ursulin 2016-04-12 1974 * callers to do FIFO management on their own or risk losing writes.
3756685a Tvrtko Ursulin 2016-04-12 1975 */
3756685a Tvrtko Ursulin 2016-04-12 1976 enum forcewake_domains
1388c063 Daniele Ceraolo Spurio 2019-03-25 1977 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
3756685a Tvrtko Ursulin 2016-04-12 1978 i915_reg_t reg, unsigned int op)
3756685a Tvrtko Ursulin 2016-04-12 1979 {
3756685a Tvrtko Ursulin 2016-04-12 @1980 enum forcewake_domains fw_domains = 0;
3756685a Tvrtko Ursulin 2016-04-12 1981
3756685a Tvrtko Ursulin 2016-04-12 1982 WARN_ON(!op);
3756685a Tvrtko Ursulin 2016-04-12 1983
1388c063 Daniele Ceraolo Spurio 2019-03-25 1984 if (!(uncore->flags & UNCORE_HAS_FORCEWAKE))
895833bd Tvrtko Ursulin 2016-10-04 1985 return 0;
895833bd Tvrtko Ursulin 2016-10-04 1986
3756685a Tvrtko Ursulin 2016-04-12 1987 if (op & FW_REG_READ)
1388c063 Daniele Ceraolo Spurio 2019-03-25 1988 fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
3756685a Tvrtko Ursulin 2016-04-12 1989
3756685a Tvrtko Ursulin 2016-04-12 1990 if (op & FW_REG_WRITE)
1388c063 Daniele Ceraolo Spurio 2019-03-25 1991 fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
3756685a Tvrtko Ursulin 2016-04-12 1992
3756685a Tvrtko Ursulin 2016-04-12 1993 return fw_domains;
3756685a Tvrtko Ursulin 2016-04-12 1994 }
26e7a2a1 Chris Wilson 2017-02-13 1995
:::::: The code at line 1980 was first introduced by commit
:::::: 3756685a18e6aa74ca3484192b64f4f8a11c8bb5 drm/i915: Only grab correct forcewake for the engine with execlists
:::::: TO: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
:::::: CC: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 6597 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 6/9] drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-25 22:09 ` Chris Wilson
2019-03-26 15:12 ` kbuild test robot
2019-03-25 21:49 ` [PATCH 8/9] drm/i915: switch intel_wait_for_register " Daniele Ceraolo Spurio
` (5 subsequent siblings)
12 siblings, 2 replies; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The intel_uncore structure is the owner of register access, so
subclass the function to it.
While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_reset.c | 36 ++++++++++++++-----------
drivers/gpu/drm/i915/intel_dpio_phy.c | 3 ++-
drivers/gpu/drm/i915/intel_engine_cs.c | 10 +++----
drivers/gpu/drm/i915/intel_guc.c | 11 ++++----
drivers/gpu/drm/i915/intel_huc_fw.c | 22 ++++++++-------
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++-------
drivers/gpu/drm/i915/intel_uncore.c | 8 +++---
drivers/gpu/drm/i915/intel_uncore.h | 13 ++++++---
10 files changed, 71 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index 0aea19cefe4a..17f802a8f8f0 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -245,10 +245,12 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
unsigned int engine_mask,
unsigned int retry)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
int ret;
- I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
- ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ intel_uncore_write_fw(uncore, ILK_GDSR,
+ ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
ILK_GRDOM_RESET_ENABLE, 0,
5000, 0,
NULL);
@@ -257,8 +259,9 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
goto out;
}
- I915_WRITE_FW(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- ret = __intel_wait_for_register_fw(dev_priv, ILK_GDSR,
+ intel_uncore_write_fw(uncore, ILK_GDSR,
+ ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
ILK_GRDOM_RESET_ENABLE, 0,
5000, 0,
NULL);
@@ -268,8 +271,8 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
}
out:
- I915_WRITE_FW(ILK_GDSR, 0);
- POSTING_READ_FW(ILK_GDSR);
+ intel_uncore_write_fw(uncore, ILK_GDSR, 0);
+ intel_uncore_posting_read_fw(uncore, ILK_GDSR);
return ret;
}
@@ -277,6 +280,7 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
u32 hw_domain_mask)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
int err;
/*
@@ -284,10 +288,10 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
* for fifo space for the write or forcewake the chip for
* the read
*/
- I915_WRITE_FW(GEN6_GDRST, hw_domain_mask);
+ intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
/* Wait for the device to ack the reset requests */
- err = __intel_wait_for_register_fw(dev_priv,
+ err = __intel_wait_for_register_fw(uncore,
GEN6_GDRST, hw_domain_mask, 0,
500, 0,
NULL);
@@ -330,6 +334,7 @@ static int gen6_reset_engines(struct drm_i915_private *i915,
static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u8 vdbox_sfc_access = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
@@ -377,10 +382,9 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,
* ends up being locked to the engine we want to reset, we have to reset
* it as well (we will unlock it once the reset sequence is completed).
*/
- I915_WRITE_FW(sfc_forced_lock,
- I915_READ_FW(sfc_forced_lock) | sfc_forced_lock_bit);
+ intel_uncore_rmw_or_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
- if (__intel_wait_for_register_fw(dev_priv,
+ if (__intel_wait_for_register_fw(uncore,
sfc_forced_lock_ack,
sfc_forced_lock_ack_bit,
sfc_forced_lock_ack_bit,
@@ -389,7 +393,7 @@ static u32 gen11_lock_sfc(struct drm_i915_private *dev_priv,
return 0;
}
- if (I915_READ_FW(sfc_usage) & sfc_usage_bit)
+ if (intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit)
return sfc_reset_bit;
return 0;
@@ -465,13 +469,13 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct intel_uncore *uncore = &engine->i915->uncore;
int ret;
- I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
- _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+ intel_uncore_write_fw(uncore, RING_RESET_CTL(engine->mmio_base),
+ _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
- ret = __intel_wait_for_register_fw(dev_priv,
+ ret = __intel_wait_for_register_fw(uncore,
RING_RESET_CTL(engine->mmio_base),
RESET_CTL_READY_TO_RESET,
RESET_CTL_READY_TO_RESET,
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 95cb8b154f87..a0591b64070b 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -383,7 +383,8 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
* The flag should get set in 100us according to the HW team, but
* use 1ms due to occasional timeouts observed with that.
*/
- if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+ if (intel_wait_for_register_fw(&dev_priv->uncore,
+ BXT_PORT_CL1CM_DW0(phy),
PHY_RESERVED | PHY_POWER_GOOD,
PHY_POWER_GOOD,
1))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index eb0fe9a58481..c936c6df34e4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -817,20 +817,20 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
int intel_engine_stop_cs(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct intel_uncore *uncore = &engine->i915->uncore;
const u32 base = engine->mmio_base;
const i915_reg_t mode = RING_MI_MODE(base);
int err;
- if (INTEL_GEN(dev_priv) < 3)
+ if (INTEL_GEN(engine->i915) < 3)
return -ENODEV;
GEM_TRACE("%s\n", engine->name);
- I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
+ intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
err = 0;
- if (__intel_wait_for_register_fw(dev_priv,
+ if (__intel_wait_for_register_fw(uncore,
mode, MODE_IDLE, MODE_IDLE,
1000, 0,
NULL)) {
@@ -839,7 +839,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
}
/* A final mmio read to let GPU writes be hopefully flushed to memory */
- POSTING_READ_FW(mode);
+ intel_uncore_posting_read_fw(uncore, mode);
return err;
}
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index dcb88e7b79c4..fb9af193dbfc 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -398,6 +398,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
u32 *response_buf, u32 response_buf_size)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 status;
int i;
int ret;
@@ -414,12 +415,12 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
mutex_lock(&guc->send_mutex);
- intel_uncore_forcewake_get(&dev_priv->uncore, guc->send_regs.fw_domains);
+ intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
for (i = 0; i < len; i++)
- I915_WRITE(guc_send_reg(guc, i), action[i]);
+ intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);
- POSTING_READ(guc_send_reg(guc, i - 1));
+ intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
intel_guc_notify(guc);
@@ -427,7 +428,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
* No GuC command should ever take longer than 10ms.
* Fast commands should still complete in 10us.
*/
- ret = __intel_wait_for_register_fw(dev_priv,
+ ret = __intel_wait_for_register_fw(uncore,
guc_send_reg(guc, 0),
INTEL_GUC_MSG_TYPE_MASK,
INTEL_GUC_MSG_TYPE_RESPONSE <<
@@ -454,7 +455,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
ret = INTEL_GUC_MSG_TO_DATA(status);
out:
- intel_uncore_forcewake_put(&dev_priv->uncore, guc->send_regs.fw_domains);
+ intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
mutex_unlock(&guc->send_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 92799b8502f5..2c7a44303b7f 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -106,41 +106,43 @@ static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
struct drm_i915_private *dev_priv = huc_to_i915(huc);
+ struct intel_uncore *uncore = &dev_priv->uncore;
unsigned long offset = 0;
u32 size;
int ret;
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
/* Set the source address for the uCode */
offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
huc_fw->header_offset;
- I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
- I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+ intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
+ intel_uncore_write(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
/* Hardware doesn't look at destination address for HuC. Set it to 0,
* but still program the correct address space.
*/
- I915_WRITE(DMA_ADDR_1_LOW, 0);
- I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+ intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);
+ intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
size = huc_fw->header_size + huc_fw->ucode_size;
- I915_WRITE(DMA_COPY_SIZE, size);
+ intel_uncore_write(uncore, DMA_COPY_SIZE, size);
/* Start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
+ intel_uncore_write(uncore, DMA_CTRL,
+ _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
/* Wait for DMA to finish */
- ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
+ ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
/* Disable the bits once DMA is over */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
+ intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 5a733e711355..422685d120e9 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -348,7 +348,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
I915_WRITE_FW(GMBUS4, irq_enable);
- ret = intel_wait_for_register_fw(dev_priv,
+ ret = intel_wait_for_register_fw(&dev_priv->uncore,
GMBUS2, GMBUS_ACTIVE, 0,
10);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e5e030f4f43f..9a6eb2ef5f48 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9687,7 +9687,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- if (__intel_wait_for_register_fw(dev_priv,
+ if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
500, 0, NULL)) {
DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
@@ -9735,7 +9735,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
- if (__intel_wait_for_register_fw(dev_priv,
+ if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
fast_timeout_us, slow_timeout_ms,
NULL)) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 359d6af1a0b9..5103bada8900 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2051,23 +2051,23 @@ int intel_ring_cacheline_align(struct i915_request *rq)
static void gen6_bsd_submit_request(struct i915_request *request)
{
- struct drm_i915_private *dev_priv = request->i915;
+ struct intel_uncore *uncore = &request->i915->uncore;
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
/* Every tail move must follow the sequence below */
/* Disable notification that the ring is IDLE. The GT
* will then assume that it is busy and bring it out of rc6.
*/
- I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
/* Clear the context id. Here be magic! */
- I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
+ intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
/* Wait for the ring not to be idle, i.e. for it to wake up. */
- if (__intel_wait_for_register_fw(dev_priv,
+ if (__intel_wait_for_register_fw(uncore,
GEN6_BSD_SLEEP_PSMI_CONTROL,
GEN6_BSD_SLEEP_INDICATOR,
0,
@@ -2080,10 +2080,10 @@ static void gen6_bsd_submit_request(struct i915_request *request)
/* Let the ring send IDLE messages to the GT again,
* and so let it sleep to conserve power when idle.
*/
- I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
- _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
+ intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
+ _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
static int mi_flush_dw(struct i915_request *rq, u32 flags)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 8265c00bad65..3f38b344f58b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1783,7 +1783,7 @@ int i915_reg_read_ioctl(struct drm_device *dev,
*
* Returns 0 if the register matches the desired condition, or -ETIMEOUT.
*/
-int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register_fw(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
@@ -1792,7 +1792,7 @@ int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
u32 *out_value)
{
u32 uninitialized_var(reg_value);
-#define done (((reg_value = I915_READ_FW(reg)) & mask) == value)
+#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
int ret;
/* Catch any overuse of this function */
@@ -1850,7 +1850,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
spin_lock_irq(&uncore->lock);
intel_uncore_forcewake_get__locked(uncore, fw);
- ret = __intel_wait_for_register_fw(dev_priv,
+ ret = __intel_wait_for_register_fw(uncore,
reg, mask, value,
fast_timeout_us, 0, ®_value);
@@ -1858,7 +1858,7 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
spin_unlock_irq(&uncore->lock);
if (ret && slow_timeout_ms)
- ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
+ ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, reg),
(reg_value & mask) == value,
slow_timeout_ms * 1000, 10, 1000);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index a7cea6a9fd79..b0a2bc772c79 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -206,7 +206,7 @@ int intel_wait_for_register(struct drm_i915_private *dev_priv,
return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
timeout_ms, NULL);
}
-int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register_fw(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
@@ -214,13 +214,13 @@ int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
unsigned int slow_timeout_ms,
u32 *out_value);
static inline
-int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
+int intel_wait_for_register_fw(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
unsigned int timeout_ms)
{
- return __intel_wait_for_register_fw(dev_priv, reg, mask, value,
+ return __intel_wait_for_register_fw(uncore, reg, mask, value,
2, timeout_ms, NULL);
}
@@ -343,6 +343,13 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
#define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
+static inline void intel_uncore_rmw_or_fw(struct intel_uncore *uncore,
+ i915_reg_t reg, u32 or_val)
+{
+ intel_uncore_write_fw(uncore, reg,
+ intel_uncore_read_fw(uncore, reg) | or_val);
+}
+
#define raw_reg_read(base, reg) \
readl(base + i915_mmio_reg_offset(reg))
#define raw_reg_write(base, reg, value) \
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore
2019-03-25 21:49 ` [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore Daniele Ceraolo Spurio
@ 2019-03-25 22:09 ` Chris Wilson
2019-03-26 15:12 ` kbuild test robot
1 sibling, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2019-03-25 22:09 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-25 21:49:38)
> +static inline void intel_uncore_rmw_or_fw(struct intel_uncore *uncore,
> + i915_reg_t reg, u32 or_val)
> +{
> + intel_uncore_write_fw(uncore, reg,
> + intel_uncore_read_fw(uncore, reg) | or_val);
> +}
Considering how frequently this could be used (display code, I'm looking
at you), I'd make this out-of-line and do a full rmw.
intel_uncore_rmw(uncore, reg, u32 mask, u32 or)
{
u32 val;
val = intel_uncore_read(uncore, reg);
val &= mask;
val |= or;
intel_uncore_write(uncore, reg, val);
}
Ok, now I see that you did the _fw variant. Yeah, that could probably
start off inline :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore
2019-03-25 21:49 ` [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore Daniele Ceraolo Spurio
2019-03-25 22:09 ` Chris Wilson
@ 2019-03-26 15:12 ` kbuild test robot
1 sibling, 0 replies; 27+ messages in thread
From: kbuild test robot @ 2019-03-26 15:12 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all, Paulo Zanoni
[-- Attachment #1: Type: text/plain, Size: 30409 bytes --]
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190326]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info'
net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info'
kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf'
include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found
include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip'
include/linux/iio/hw-consumer.h:1: warning: no structured comments found
include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry'
include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints'
include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb'
drivers/slimbus/stream.c:1: warning: no structured comments found
include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device'
drivers/target/target_core_device.c:1: warning: no structured comments found
drivers/usb/typec/bus.c:1: warning: no structured comments found
drivers/usb/typec/class.c:1: warning: no structured comments found
include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family'
fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete'
fs/file_table.c:1: warning: no structured comments found
fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end'
fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:183: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:374: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:375: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'end' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:866: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3104: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:375: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Function parameter or member 'ih' not described in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1: warning: no structured comments found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:128: warning: Incorrect use of kernel-doc format: Documentation Makefile include scripts source @atomic_obj
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj_lock' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: no structured comments found
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_pin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_unpin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_res_obj' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_get_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_import_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vunmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_mmap' not described in 'drm_driver'
include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found
drivers/gpu/drm/scheduler/sched_main.c:376: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:377: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:420: warning: Function parameter or member 'full_recovery' not described in 'drm_sched_start'
>> drivers/gpu/drm/i915/intel_uncore.c:1794: warning: Function parameter or member 'uncore' not described in '__intel_wait_for_register_fw'
drivers/gpu/drm/i915/intel_uncore.c:1794: warning: Excess function parameter 'dev_priv' description in '__intel_wait_for_register_fw'
drivers/gpu/drm/i915/intel_uncore.c:1980: warning: Function parameter or member 'uncore' not described in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/intel_uncore.c:1980: warning: Excess function parameter 'dev_priv' description in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/i915_vma.h:50: warning: cannot understand function prototype: 'struct i915_vma '
drivers/gpu/drm/i915/i915_vma.h:1: warning: no structured comments found
drivers/gpu/drm/i915/intel_guc_fwif.h:536: warning: cannot understand function prototype: 'struct guc_log_buffer_state '
drivers/gpu/drm/i915/i915_trace.h:1: warning: no structured comments found
drivers/gpu/drm/i915/i915_reg.h:156: warning: bad line:
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'hw_id' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'max_active_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'supported_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:142: warning: Function parameter or member 'output_port' not described in 'komeda_component_output'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'component' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'crtc' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'plane' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'wb_conn' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'changed_active_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'affected_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'compiz' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'wb_layer' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'improc' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'ctrlr' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'funcs' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:321: warning: Function parameter or member 'pipe' not described in 'komeda_pipeline_state'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'dev' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'reg_base' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'chip' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'mclk' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'n_pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_plane.c:1: warning: no structured comments found
include/linux/skbuff.h:876: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'list' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'head_frag' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encapsulation' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_valid' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'vlan_present' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_level' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff'
include/net/sock.h:238: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_portpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_cookie' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_listener' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.rmem_alloc' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.len' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.head' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.tail' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_wq_raw' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.upper' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.lower' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gso_partial_features' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'switchdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'name_assign_type' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'mpls_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xdp_prog' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'qdisc_hash' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state'
Documentation/admin-guide/cgroup-v2.rst:1509: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1511: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1512: WARNING: Block quote ends without a blank line; unexpected unindent.
include/linux/interrupt.h:252: WARNING: Inline emphasis start-string without end-string.
include/net/mac80211.h:1214: ERROR: Unexpected indentation.
vim +1794 drivers/gpu/drm/i915/intel_uncore.c
907b28c56e Chris Wilson 2013-07-19 1759
e34b0345e6 Michel Thierry 2018-04-05 1760 /**
1d1a9774e4 Michal Wajdeczko 2017-04-07 1761 * __intel_wait_for_register_fw - wait until register matches expected state
1758b90e38 Chris Wilson 2016-06-30 1762 * @dev_priv: the i915 device
1758b90e38 Chris Wilson 2016-06-30 1763 * @reg: the register to read
1758b90e38 Chris Wilson 2016-06-30 1764 * @mask: mask to apply to register value
1758b90e38 Chris Wilson 2016-06-30 1765 * @value: expected value
1d1a9774e4 Michal Wajdeczko 2017-04-07 1766 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1d1a9774e4 Michal Wajdeczko 2017-04-07 1767 * @slow_timeout_ms: slow timeout in millisecond
1d1a9774e4 Michal Wajdeczko 2017-04-07 1768 * @out_value: optional placeholder to hold registry value
1758b90e38 Chris Wilson 2016-06-30 1769 *
1758b90e38 Chris Wilson 2016-06-30 1770 * This routine waits until the target register @reg contains the expected
3d466cd67e Daniel Vetter 2016-07-15 1771 * @value after applying the @mask, i.e. it waits until ::
3d466cd67e Daniel Vetter 2016-07-15 1772 *
3d466cd67e Daniel Vetter 2016-07-15 1773 * (I915_READ_FW(reg) & mask) == value
3d466cd67e Daniel Vetter 2016-07-15 1774 *
1d1a9774e4 Michal Wajdeczko 2017-04-07 1775 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
6976e74b5f Michal Wajdeczko 2017-04-10 1776 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
84d84cb7e2 Chris Wilson 2017-04-11 1777 * must be not larger than 20,0000 microseconds.
1758b90e38 Chris Wilson 2016-06-30 1778 *
1758b90e38 Chris Wilson 2016-06-30 1779 * Note that this routine assumes the caller holds forcewake asserted, it is
1758b90e38 Chris Wilson 2016-06-30 1780 * not suitable for very long waits. See intel_wait_for_register() if you
1758b90e38 Chris Wilson 2016-06-30 1781 * wish to wait without holding forcewake for the duration (i.e. you expect
1758b90e38 Chris Wilson 2016-06-30 1782 * the wait to be slow).
1758b90e38 Chris Wilson 2016-06-30 1783 *
1758b90e38 Chris Wilson 2016-06-30 1784 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1758b90e38 Chris Wilson 2016-06-30 1785 */
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1786 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1758b90e38 Chris Wilson 2016-06-30 1787 i915_reg_t reg,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1788 u32 mask,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1789 u32 value,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1790 unsigned int fast_timeout_us,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1791 unsigned int slow_timeout_ms,
1d1a9774e4 Michal Wajdeczko 2017-04-07 1792 u32 *out_value)
1758b90e38 Chris Wilson 2016-06-30 1793 {
ff26ffa8ee Daniel Vetter 2017-05-10 @1794 u32 uninitialized_var(reg_value);
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1795 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1796 int ret;
1d1a9774e4 Michal Wajdeczko 2017-04-07 1797
6976e74b5f Michal Wajdeczko 2017-04-10 1798 /* Catch any overuse of this function */
84d84cb7e2 Chris Wilson 2017-04-11 1799 might_sleep_if(slow_timeout_ms);
84d84cb7e2 Chris Wilson 2017-04-11 1800 GEM_BUG_ON(fast_timeout_us > 20000);
6976e74b5f Michal Wajdeczko 2017-04-10 1801
84d84cb7e2 Chris Wilson 2017-04-11 1802 ret = -ETIMEDOUT;
84d84cb7e2 Chris Wilson 2017-04-11 1803 if (fast_timeout_us && fast_timeout_us <= 20000)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1804 ret = _wait_for_atomic(done, fast_timeout_us, 0);
ff26ffa8ee Daniel Vetter 2017-05-10 1805 if (ret && slow_timeout_ms)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1806 ret = wait_for(done, slow_timeout_ms);
84d84cb7e2 Chris Wilson 2017-04-11 1807
1d1a9774e4 Michal Wajdeczko 2017-04-07 1808 if (out_value)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1809 *out_value = reg_value;
84d84cb7e2 Chris Wilson 2017-04-11 1810
1758b90e38 Chris Wilson 2016-06-30 1811 return ret;
1758b90e38 Chris Wilson 2016-06-30 1812 #undef done
1758b90e38 Chris Wilson 2016-06-30 1813 }
1758b90e38 Chris Wilson 2016-06-30 1814
:::::: The code at line 1794 was first introduced by commit
:::::: ff26ffa8ee267dcbd27a5d81cb21d1c41bfdb44a drm/i915: Fix __intel_wait_for_register_fw to not sleep in atomic
:::::: TO: Daniel Vetter <daniel.vetter@ffwll.ch>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 6597 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 8/9] drm/i915: switch intel_wait_for_register to uncore
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 7/9] drm/i915: intel_wait_for_register_fw to uncore Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-26 19:17 ` kbuild test robot
2019-03-25 21:49 ` [PATCH 9/9] drm/i915: take a reference to uncore in the engine and use it Daniele Ceraolo Spurio
` (4 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
The intel_uncore structure is the owner of register access, so
subclass the function to it.
While at it, use a local uncore var and switch to the new read/write
functions where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 12 +++++------
drivers/gpu/drm/i915/icl_dsi.c | 6 ++++--
drivers/gpu/drm/i915/intel_cdclk.c | 8 +++----
drivers/gpu/drm/i915/intel_crt.c | 6 +++---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/intel_dpio_phy.c | 2 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 +++++++++++-----------
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_guc.c | 2 +-
drivers/gpu/drm/i915/intel_hdcp.c | 16 +++++++-------
drivers/gpu/drm/i915/intel_huc.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 6 ++++--
drivers/gpu/drm/i915/intel_psr.c | 8 +++----
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +++----
drivers/gpu/drm/i915/intel_sideband.c | 12 +++++------
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
drivers/gpu/drm/i915/intel_uncore.h | 6 +++---
drivers/gpu/drm/i915/vlv_dsi.c | 28 ++++++++++++-------------
drivers/gpu/drm/i915/vlv_dsi_pll.c | 4 ++--
24 files changed, 102 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 85e80701a4c6..f1334f5d4ead 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2654,7 +2654,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
if (!force_on)
return 0;
- err = intel_wait_for_register(dev_priv,
+ err = intel_wait_for_register(&dev_priv->uncore,
VLV_GTLC_SURVIVABILITY_REG,
VLV_GFX_CLK_STATUS_BIT,
VLV_GFX_CLK_STATUS_BIT,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 85c5cb779297..39a4804091d7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1920,10 +1920,10 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream)
static void gen7_oa_disable(struct i915_perf_stream *stream)
{
- struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct intel_uncore *uncore = &stream->dev_priv->uncore;
- I915_WRITE(GEN7_OACONTROL, 0);
- if (intel_wait_for_register(dev_priv,
+ intel_uncore_write(uncore, GEN7_OACONTROL, 0);
+ if (intel_wait_for_register(uncore,
GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
50))
DRM_ERROR("wait for OA to be disabled timed out\n");
@@ -1931,10 +1931,10 @@ static void gen7_oa_disable(struct i915_perf_stream *stream)
static void gen8_oa_disable(struct i915_perf_stream *stream)
{
- struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct intel_uncore *uncore = &stream->dev_priv->uncore;
- I915_WRITE(GEN8_OACONTROL, 0);
- if (intel_wait_for_register(dev_priv,
+ intel_uncore_write(uncore, GEN8_OACONTROL, 0);
+ if (intel_wait_for_register(uncore,
GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
50))
DRM_ERROR("wait for OA to be disabled timed out\n");
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 92440ff48f93..fb068219903e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -861,7 +861,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
I915_WRITE(PIPECONF(dsi_trans), tmp);
/* wait for transcoder to be enabled */
- if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ if (intel_wait_for_register(&dev_priv->uncore,
+ PIPECONF(dsi_trans),
I965_PIPECONF_ACTIVE,
I965_PIPECONF_ACTIVE, 10))
DRM_ERROR("DSI transcoder not enabled\n");
@@ -1039,7 +1040,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
I915_WRITE(PIPECONF(dsi_trans), tmp);
/* wait for transcoder to be disabled */
- if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ if (intel_wait_for_register(&dev_priv->uncore,
+ PIPECONF(dsi_trans),
I965_PIPECONF_ACTIVE, 0, 50))
DRM_ERROR("DSI trancoder not disabled\n");
}
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index d27ccd23d753..d9b09d3a22f0 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -965,7 +965,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5))
DRM_ERROR("DPLL0 not locked\n");
@@ -979,7 +979,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
{
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
1))
DRM_ERROR("Couldn't disable DPLL0\n");
@@ -1324,7 +1324,7 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
I915_WRITE(BXT_DE_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1))
DRM_ERROR("timeout waiting for DE PLL unlock\n");
@@ -1345,7 +1345,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
/* Timeout 200us */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_DE_PLL_ENABLE,
BXT_DE_PLL_LOCK,
BXT_DE_PLL_LOCK,
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 3716b2ee362f..50530e49982c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -435,7 +435,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
I915_WRITE(crt->adpa_reg, adpa);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
1000))
@@ -489,7 +489,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
I915_WRITE(crt->adpa_reg, adpa);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
1000)) {
@@ -542,7 +542,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
+ if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,
CRT_HOTPLUG_FORCE_DETECT, 0,
1000))
DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 933df3a57a8a..80763d7b4223 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3074,7 +3074,7 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
val |= DP_TP_CTL_FEC_ENABLE;
I915_WRITE(DP_TP_CTL(port), val);
- if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
DP_TP_STATUS_FEC_ENABLE_LIVE,
DP_TP_STATUS_FEC_ENABLE_LIVE,
1))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9a9b78c120b1..8576a7f799f2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1040,7 +1040,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
i915_reg_t reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
reg, I965_PIPECONF_ACTIVE, 0,
100))
WARN(1, "pipe_off wait timed out\n");
@@ -1346,7 +1346,7 @@ static void _vlv_enable_pll(struct intel_crtc *crtc,
POSTING_READ(DPLL(pipe));
udelay(150);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DPLL(pipe),
DPLL_LOCK_VLV,
DPLL_LOCK_VLV,
@@ -1399,7 +1399,7 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
/* Check PLL is locked */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1))
DRM_ERROR("PLL %d failed to lock\n", pipe);
@@ -1580,7 +1580,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
BUG();
}
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
dpll_reg, port_mask, expected_mask,
1000))
WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
@@ -1641,7 +1641,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
}
I915_WRITE(reg, val | TRANS_ENABLE);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
100))
DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
@@ -1671,7 +1671,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
val |= TRANS_PROGRESSIVE;
I915_WRITE(LPT_TRANSCONF, val);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
LPT_TRANSCONF,
TRANS_STATE_ENABLE,
TRANS_STATE_ENABLE,
@@ -1697,7 +1697,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
val &= ~TRANS_ENABLE;
I915_WRITE(reg, val);
/* wait for PCH transcoder off, transcoder state */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
reg, TRANS_STATE_ENABLE, 0,
50))
DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
@@ -1719,7 +1719,7 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
val &= ~TRANS_ENABLE;
I915_WRITE(LPT_TRANSCONF, val);
/* wait for PCH transcoder off, transcoder state */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
50))
DRM_ERROR("Failed to disable PCH transcoder\n");
@@ -5299,7 +5299,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
* and don't wait for vblanks until the end of crtc_enable, then
* the HW state readout code will complain that the expected
* IPS_CTL value is not the one we read. */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
IPS_CTL, IPS_ENABLE, IPS_ENABLE,
50))
DRM_ERROR("Timed out waiting for IPS enable\n");
@@ -5324,7 +5324,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
* 42ms timeout value leads to occasional timeouts so use 100ms
* instead.
*/
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
IPS_CTL, IPS_ENABLE, 0,
100))
DRM_ERROR("Timed out waiting for IPS disable\n");
@@ -9481,7 +9481,8 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
I915_WRITE(LCPLL_CTL, val);
POSTING_READ(LCPLL_CTL);
- if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
DRM_ERROR("LCPLL still locked\n");
val = hsw_read_dcomp(dev_priv);
@@ -9536,7 +9537,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
val &= ~LCPLL_PLL_DISABLE;
I915_WRITE(LCPLL_CTL, val);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
5))
DRM_ERROR("LCPLL not locked yet\n");
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 326de12c3f44..74fe14103459 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2348,7 +2348,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
I915_READ(pp_stat_reg),
I915_READ(pp_ctrl_reg));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
pp_stat_reg, mask, value,
5000))
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
@@ -3937,7 +3937,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (port == PORT_A)
return;
- if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
DP_TP_STATUS_IDLE_DONE,
DP_TP_STATUS_IDLE_DONE,
1))
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index fb67cd931117..ecad1f58ebf8 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -289,7 +289,7 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DP_TP_STATUS(port),
DP_TP_STATUS_ACT_SENT,
DP_TP_STATUS_ACT_SENT,
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index a0591b64070b..db295c77ff0d 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -341,7 +341,7 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_PORT_REF_DW3(phy),
GRC_DONE, GRC_DONE,
10))
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index eeb659946203..e01c057ce50b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -960,7 +960,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(regs[id].ctl,
I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DPLL_STATUS,
DPLL_LOCK(id),
DPLL_LOCK(id),
@@ -1977,7 +1977,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
CNL_DPLL_ENABLE(id),
PLL_POWER_STATE,
PLL_POWER_STATE,
@@ -2018,7 +2018,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 7. Wait for PLL lock status in DPLL_ENABLE. */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
CNL_DPLL_ENABLE(id),
PLL_LOCK,
PLL_LOCK,
@@ -2066,7 +2066,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
CNL_DPLL_ENABLE(id),
PLL_LOCK,
0,
@@ -2088,7 +2088,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
CNL_DPLL_ENABLE(id),
PLL_POWER_STATE,
0,
@@ -3050,8 +3050,8 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
- PLL_POWER_STATE, 1))
+ if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
+ PLL_POWER_STATE, PLL_POWER_STATE, 1))
DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
}
@@ -3066,8 +3066,8 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(enable_reg, val);
/* Timeout is actually 600us. */
- if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
- 1))
+ if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
+ PLL_LOCK, PLL_LOCK, 1))
DRM_ERROR("PLL %d not locked\n", pll->info->id);
}
@@ -3149,7 +3149,8 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(enable_reg, val);
/* Timeout is actually 1us. */
- if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ enable_reg, PLL_LOCK, 0, 1))
DRM_ERROR("PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
@@ -3162,8 +3163,8 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
- 1))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ enable_reg, PLL_POWER_STATE, 0, 1))
DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
}
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 656e684e7c9a..43fe08be3b7d 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -108,7 +108,7 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
I915_WRITE(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
FBC_STATUS, FBC_STAT_COMPRESSING, 0,
10)) {
DRM_DEBUG_KMS("FBC idle timed out\n");
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index fb9af193dbfc..3aabfa2d9198 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -565,7 +565,7 @@ static int guc_sleep_state_action(struct intel_guc *guc,
if (ret)
return ret;
- ret = __intel_wait_for_register(dev_priv, SOFT_SCRATCH(14),
+ ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
INTEL_GUC_SLEEP_STATE_INVALID_MASK,
0, 0, 10, &status);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 9ce09f67776d..111ff2044f2e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -225,7 +225,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
}
/* Wait for the keys to load (500us) */
- ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
+ ret = __intel_wait_for_register(&dev_priv->uncore, HDCP_KEY_STATUS,
HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
10, 1, &val);
if (ret)
@@ -243,7 +243,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
{
I915_WRITE(HDCP_SHA_TEXT, sha_text);
- if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
+ if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
DRM_ERROR("Timed out waiting for SHA1 ready\n");
return -ETIMEDOUT;
@@ -474,7 +474,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
/* Tell the HW we're done with the hash and wait for it to ACK */
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
- if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
+ if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
HDCP_SHA1_COMPLETE,
HDCP_SHA1_COMPLETE, 1)) {
DRM_ERROR("Timed out waiting for SHA1 complete\n");
@@ -604,7 +604,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
/* Wait for An to be acquired */
- if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
HDCP_STATUS_AN_READY,
HDCP_STATUS_AN_READY, 1)) {
DRM_ERROR("Timed out waiting for An\n");
@@ -685,7 +685,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
}
/* Wait for encryption confirmation */
- if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
+ if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
HDCP_STATUS_ENC, HDCP_STATUS_ENC,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Timed out waiting for encryption\n");
@@ -717,7 +717,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
hdcp->hdcp_encrypted = false;
I915_WRITE(PORT_HDCP_CONF(port), 0);
- if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
+ if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port), ~0, 0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1477,7 +1477,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
CTL_LINK_ENCRYPTION_REQ);
}
- ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
LINK_ENCRYPTION_STATUS,
LINK_ENCRYPTION_STATUS,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
@@ -1498,7 +1498,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
I915_WRITE(HDCP2_CTL_DDI(port),
I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
- ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
LINK_ENCRYPTION_STATUS, 0x0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 9bd1c9002c2a..94c04f16a2ad 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -79,7 +79,7 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(i915,
+ ret = __intel_wait_for_register(&i915->uncore,
HUC_STATUS2,
HUC_FW_VERIFIED,
HUC_FW_VERIFIED,
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index ccd5ac6d3fcd..34dd2d71814b 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -311,7 +311,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
POSTING_READ(lvds_encoder->reg);
- if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ PP_STATUS(0), PP_ON, PP_ON, 5000))
DRM_ERROR("timed out waiting for panel to power on\n");
intel_panel_enable_backlight(pipe_config, conn_state);
@@ -325,7 +326,8 @@ static void intel_disable_lvds(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
- if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ PP_STATUS(0), PP_ON, 0, 1000))
DRM_ERROR("timed out waiting for panel to power off\n");
I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 605fe8fc85cc..ec874d802d48 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -834,8 +834,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
}
/* Wait till PSR is idle */
- if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
- 2000))
+ if (intel_wait_for_register(&dev_priv->uncore,
+ psr_status, psr_status_mask, 0, 2000))
DRM_ERROR("Timed out waiting PSR idle state\n");
/* Disable PSR on Sink */
@@ -956,7 +956,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
* defensive enough to cover everything.
*/
- return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
+ return __intel_wait_for_register(&dev_priv->uncore, EDP_PSR_STATUS,
EDP_PSR_STATUS_STATE_MASK,
EDP_PSR_STATUS_STATE_IDLE, 2, 50,
out_value);
@@ -981,7 +981,7 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->psr.lock);
- err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
+ err = intel_wait_for_register(&dev_priv->uncore, reg, mask, 0, 50);
if (err)
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5103bada8900..a5b4a2d9a492 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -586,7 +586,7 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
I915_WRITE(instpm,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
INSTPM_SYNC_FLUSH));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
instpm, INSTPM_SYNC_FLUSH, 0,
1000))
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
@@ -607,7 +607,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
if (INTEL_GEN(dev_priv) > 2) {
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
RING_MI_MODE(engine->mmio_base),
MODE_IDLE,
MODE_IDLE,
@@ -699,7 +699,8 @@ static int init_ring_common(struct intel_engine_cs *engine)
I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
/* If the head is still not zero, the ring is dead */
- if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
+ if (intel_wait_for_register(&dev_priv->uncore,
+ RING_CTL(engine->mmio_base),
RING_VALID, RING_VALID,
50)) {
DRM_ERROR("%s initialization failed "
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 676a89bb8194..40ddfbb97acb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -565,7 +565,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
int pw_idx = power_well->desc->hsw.idx;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
- WARN_ON(intel_wait_for_register(dev_priv,
+ WARN_ON(intel_wait_for_register(&dev_priv->uncore,
regs->driver,
HSW_PWR_WELL_CTL_STATE(pw_idx),
HSW_PWR_WELL_CTL_STATE(pw_idx),
@@ -620,7 +620,7 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
enum skl_power_gate pg)
{
/* Timeout 5us for PG#0, for other PGs 1us */
- WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS,
+ WARN_ON(intel_wait_for_register(&dev_priv->uncore, SKL_FUSE_STATUS,
SKL_FUSE_PG_DIST_STATUS(pg),
SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
@@ -1521,7 +1521,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change.
*/
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DISPLAY_PHY_STATUS,
phy_status_mask,
phy_status,
@@ -1556,7 +1556,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, true);
/* Poll for phypwrgood signal */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
DISPLAY_PHY_STATUS,
PHY_POWERGOOD(phy),
PHY_POWERGOOD(phy),
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 75c872bb8cc9..57de41b1f989 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -51,7 +51,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
5)) {
DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
@@ -63,7 +63,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
5)) {
DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
@@ -208,7 +208,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
u32 value = 0;
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT, SBI_BUSY, 0,
100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
@@ -224,7 +224,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT,
SBI_BUSY,
0,
@@ -248,7 +248,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT, SBI_BUSY, 0,
100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
@@ -264,7 +264,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT,
SBI_BUSY,
0,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 3f38b344f58b..fd3aa4448920 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1831,7 +1831,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
*
* Returns 0 if the register matches the desired condition, or -ETIMEOUT.
*/
-int __intel_wait_for_register(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
@@ -1839,7 +1839,6 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
unsigned int slow_timeout_ms,
u32 *out_value)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
unsigned fw =
intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
u32 reg_value;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index b0a2bc772c79..1a32e576b376 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -189,7 +189,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
-int __intel_wait_for_register(struct drm_i915_private *dev_priv,
+int __intel_wait_for_register(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
@@ -197,13 +197,13 @@ int __intel_wait_for_register(struct drm_i915_private *dev_priv,
unsigned int slow_timeout_ms,
u32 *out_value);
static inline
-int intel_wait_for_register(struct drm_i915_private *dev_priv,
+int intel_wait_for_register(struct intel_uncore *uncore,
i915_reg_t reg,
u32 mask,
u32 value,
unsigned int timeout_ms)
{
- return __intel_wait_for_register(dev_priv, reg, mask, value, 2,
+ return __intel_wait_for_register(uncore, reg, mask, value, 2,
timeout_ms, NULL);
}
int __intel_wait_for_register_fw(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index 01278b2e257c..d34085e738e7 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -78,7 +78,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_GEN_FIFO_STAT(port), mask, mask,
100))
DRM_ERROR("DPI FIFOs are not empty\n");
@@ -148,7 +148,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* note: this is never true for reads */
if (packet.payload_length) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_GEN_FIFO_STAT(port),
data_mask, 0,
50))
@@ -162,7 +162,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
}
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_GEN_FIFO_STAT(port),
ctrl_mask, 0,
50)) {
@@ -174,7 +174,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* ->rx_len is set only for reads */
if (msg->rx_len) {
data_mask = GEN_READ_DATA_AVAIL;
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_INTR_STAT(port),
data_mask, data_mask,
50))
@@ -234,7 +234,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
mask = SPL_PKT_SENT_INTERRUPT;
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_INTR_STAT(port), mask, mask,
100))
DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
@@ -353,7 +353,7 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
/* Wait for Pwr ACK */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPIO port is powergated\n");
@@ -377,7 +377,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
GLK_PHY_STATUS_PORT_READY, 20))
DRM_ERROR("PHY is not ON\n");
@@ -403,7 +403,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
I915_WRITE(MIPI_DEVICE_READY(port), val);
/* Wait for ULPS active */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
DRM_ERROR("ULPS not active\n");
@@ -427,7 +427,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for Stop state */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
GLK_DATA_LANE_STOP_STATE, 20))
DRM_ERROR("Date lane not in STOP state\n");
@@ -435,7 +435,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for AFE LATCH */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
AFE_LATCHOUT, 20))
DRM_ERROR("D-PHY not entering LP-11 state\n");
@@ -537,7 +537,7 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port),
GLK_PHY_STATUS_PORT_READY, 0, 20))
DRM_ERROR("PHY is not turning OFF\n");
@@ -545,7 +545,7 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
/* Wait for Pwr ACK bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port),
GLK_MIPIIO_PORT_POWERED, 0, 20))
DRM_ERROR("MIPI IO Port is not powergated\n");
@@ -566,7 +566,7 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port),
GLK_PHY_STATUS_PORT_READY, 0, 20))
DRM_ERROR("PHY is not turning OFF\n");
@@ -616,7 +616,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
* Port A only. MIPI Port C has no similar bit for checking.
*/
if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
- intel_wait_for_register(dev_priv,
+ intel_wait_for_register(&dev_priv->uncore,
port_ctrl, AFE_LATCHOUT, 0,
30))
DRM_ERROR("DSI LP not going Low\n");
diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
index 954d5a8c4fa7..5e7b1fb2db5d 100644
--- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
@@ -244,7 +244,7 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder)
* PLL lock should deassert within 200us.
* Wait up to 1ms before timing out.
*/
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_DSI_PLL_ENABLE,
BXT_DSI_PLL_LOCKED,
0,
@@ -528,7 +528,7 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
I915_WRITE(BXT_DSI_PLL_ENABLE, val);
/* Timeout and fail if PLL not locked */
- if (intel_wait_for_register(dev_priv,
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_DSI_PLL_ENABLE,
BXT_DSI_PLL_LOCKED,
BXT_DSI_PLL_LOCKED,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 8/9] drm/i915: switch intel_wait_for_register to uncore
2019-03-25 21:49 ` [PATCH 8/9] drm/i915: switch intel_wait_for_register " Daniele Ceraolo Spurio
@ 2019-03-26 19:17 ` kbuild test robot
0 siblings, 0 replies; 27+ messages in thread
From: kbuild test robot @ 2019-03-26 19:17 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all, Paulo Zanoni
[-- Attachment #1: Type: text/plain, Size: 35136 bytes --]
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190326]
[cannot apply to v5.1-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/more-uncore-rework/20190326-110805
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf'
include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf'
include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found
include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip'
include/linux/iio/hw-consumer.h:1: warning: no structured comments found
include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry'
include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints'
include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb'
arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb'
drivers/slimbus/stream.c:1: warning: no structured comments found
include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device'
drivers/target/target_core_device.c:1: warning: no structured comments found
drivers/usb/typec/bus.c:1: warning: no structured comments found
drivers/usb/typec/class.c:1: warning: no structured comments found
include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family'
fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete'
fs/file_table.c:1: warning: no structured comments found
fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end'
fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode'
fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:183: warning: Function parameter or member 'blockable' not described in 'amdgpu_mn_read_lock'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:295: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Function parameter or member 'range' not described in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:344: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_end'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:374: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:375: warning: cannot understand function prototype: 'struct amdgpu_vm_pt_cursor '
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'start' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'end' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:547: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_leaf'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'adev' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'vm' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'cursor' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:595: warning: Function parameter or member 'entry' not described in 'for_each_amdgpu_vm_pt_dfs_safe'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:866: warning: Function parameter or member 'level' not described in 'amdgpu_vm_bo_param'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1346: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_func'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'params' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'bo' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'level' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'pe' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'addr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'count' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'incr' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1514: warning: Function parameter or member 'flags' not described in 'amdgpu_vm_update_flags'
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:3104: warning: Function parameter or member 'pasid' not described in 'amdgpu_vm_make_compute'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:375: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Function parameter or member 'ih' not described in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c:376: warning: Excess function parameter 'entry' description in 'amdgpu_irq_dispatch'
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1: warning: no structured comments found
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:128: warning: Incorrect use of kernel-doc format: Documentation Makefile include scripts source @atomic_obj
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'atomic_obj_lock' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_link' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'backlight_caps' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'freesync_module' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'fw_dmcu' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:203: warning: Function parameter or member 'dmcu_fw_version' not described in 'amdgpu_display_manager'
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:1: warning: no structured comments found
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_pin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_unpin' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_res_obj' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_get_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_import_sg_table' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_vunmap' not described in 'drm_driver'
include/drm/drm_drv.h:715: warning: Function parameter or member 'gem_prime_mmap' not described in 'drm_driver'
include/drm/drm_atomic_state_helper.h:1: warning: no structured comments found
drivers/gpu/drm/scheduler/sched_main.c:376: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:377: warning: Excess function parameter 'bad' description in 'drm_sched_stop'
drivers/gpu/drm/scheduler/sched_main.c:420: warning: Function parameter or member 'full_recovery' not described in 'drm_sched_start'
drivers/gpu/drm/i915/intel_uncore.c:1794: warning: Function parameter or member 'uncore' not described in '__intel_wait_for_register_fw'
drivers/gpu/drm/i915/intel_uncore.c:1794: warning: Excess function parameter 'dev_priv' description in '__intel_wait_for_register_fw'
>> drivers/gpu/drm/i915/intel_uncore.c:1842: warning: Function parameter or member 'uncore' not described in '__intel_wait_for_register'
drivers/gpu/drm/i915/intel_uncore.c:1842: warning: Excess function parameter 'dev_priv' description in '__intel_wait_for_register'
drivers/gpu/drm/i915/intel_uncore.c:1979: warning: Function parameter or member 'uncore' not described in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/intel_uncore.c:1979: warning: Excess function parameter 'dev_priv' description in 'intel_uncore_forcewake_for_reg'
drivers/gpu/drm/i915/i915_vma.h:50: warning: cannot understand function prototype: 'struct i915_vma '
drivers/gpu/drm/i915/i915_vma.h:1: warning: no structured comments found
drivers/gpu/drm/i915/intel_guc_fwif.h:536: warning: cannot understand function prototype: 'struct guc_log_buffer_state '
drivers/gpu/drm/i915/i915_trace.h:1: warning: no structured comments found
drivers/gpu/drm/i915/i915_reg.h:156: warning: bad line:
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'hw_id' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'max_active_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:126: warning: Function parameter or member 'supported_outputs' not described in 'komeda_component'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:142: warning: Function parameter or member 'output_port' not described in 'komeda_component_output'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'component' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'crtc' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'plane' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'wb_conn' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'changed_active_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:196: warning: Function parameter or member 'affected_inputs' not described in 'komeda_component_state'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'layers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'n_scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'scalers' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'compiz' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'wb_layer' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'improc' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'ctrlr' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:300: warning: Function parameter or member 'funcs' not described in 'komeda_pipeline'
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h:321: warning: Function parameter or member 'pipe' not described in 'komeda_pipeline_state'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'dev' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'reg_base' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'chip' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'mclk' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'n_pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_dev.h:97: warning: Function parameter or member 'pipelines' not described in 'komeda_dev'
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c:1: warning: no structured comments found
drivers/gpu/drm/arm/display/komeda/komeda_plane.c:1: warning: no structured comments found
include/linux/skbuff.h:876: warning: Function parameter or member 'dev_scratch' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'list' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'ip_defrag_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'skb_mstamp_ns' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__cloned_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'head_frag' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_type_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encapsulation' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'encap_hdr_csum' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_valid' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member '__pkt_vlan_present_offset' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'vlan_present' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_complete_sw' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'csum_level' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_protocol_type' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'remcsum_offload' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'sender_cpu' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'reserved_tailroom' not described in 'sk_buff'
include/linux/skbuff.h:876: warning: Function parameter or member 'inner_ipproto' not described in 'sk_buff'
include/net/sock.h:238: warning: Function parameter or member 'skc_addrpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_portpair' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_ipv6only' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_net_refcnt' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_daddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_v6_rcv_saddr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_cookie' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_listener' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_dr' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_rcv_wnd' not described in 'sock_common'
include/net/sock.h:238: warning: Function parameter or member 'skc_tw_rcv_nxt' not described in 'sock_common'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.rmem_alloc' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.len' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.head' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_backlog.tail' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_wq_raw' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'tcp_rtx_queue' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_route_forced_caps' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_txtime_report_errors' not described in 'sock'
include/net/sock.h:513: warning: Function parameter or member 'sk_validate_xmit_skb' not described in 'sock'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.upper' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'adj_list.lower' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gso_partial_features' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'switchdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'l3mdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xfrmdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'tlsdev_ops' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'name_assign_type' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'ieee802154_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'mpls_ptr' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xdp_prog' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'gro_flush_timeout' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'nf_hooks_ingress' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member '____cacheline_aligned_in_smp' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'qdisc_hash' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_cpus_map' not described in 'net_device'
include/linux/netdevice.h:2051: warning: Function parameter or member 'xps_rxqs_map' not described in 'net_device'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising' not described in 'phylink_link_state'
include/linux/phylink.h:56: warning: Function parameter or member '__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising' not described in 'phylink_link_state'
Documentation/admin-guide/cgroup-v2.rst:1509: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1511: WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/admin-guide/cgroup-v2.rst:1512: WARNING: Block quote ends without a blank line; unexpected unindent.
include/linux/interrupt.h:252: WARNING: Inline emphasis start-string without end-string.
include/net/mac80211.h:1214: ERROR: Unexpected indentation.
vim +1842 drivers/gpu/drm/i915/intel_uncore.c
907b28c56e Chris Wilson 2013-07-19 1759
e34b0345e6 Michel Thierry 2018-04-05 1760 /**
1d1a9774e4 Michal Wajdeczko 2017-04-07 1761 * __intel_wait_for_register_fw - wait until register matches expected state
1758b90e38 Chris Wilson 2016-06-30 1762 * @dev_priv: the i915 device
1758b90e38 Chris Wilson 2016-06-30 1763 * @reg: the register to read
1758b90e38 Chris Wilson 2016-06-30 1764 * @mask: mask to apply to register value
1758b90e38 Chris Wilson 2016-06-30 1765 * @value: expected value
1d1a9774e4 Michal Wajdeczko 2017-04-07 1766 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1d1a9774e4 Michal Wajdeczko 2017-04-07 1767 * @slow_timeout_ms: slow timeout in millisecond
1d1a9774e4 Michal Wajdeczko 2017-04-07 1768 * @out_value: optional placeholder to hold registry value
1758b90e38 Chris Wilson 2016-06-30 1769 *
1758b90e38 Chris Wilson 2016-06-30 1770 * This routine waits until the target register @reg contains the expected
3d466cd67e Daniel Vetter 2016-07-15 1771 * @value after applying the @mask, i.e. it waits until ::
3d466cd67e Daniel Vetter 2016-07-15 1772 *
3d466cd67e Daniel Vetter 2016-07-15 1773 * (I915_READ_FW(reg) & mask) == value
3d466cd67e Daniel Vetter 2016-07-15 1774 *
1d1a9774e4 Michal Wajdeczko 2017-04-07 1775 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
6976e74b5f Michal Wajdeczko 2017-04-10 1776 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
84d84cb7e2 Chris Wilson 2017-04-11 1777 * must be not larger than 20,0000 microseconds.
1758b90e38 Chris Wilson 2016-06-30 1778 *
1758b90e38 Chris Wilson 2016-06-30 1779 * Note that this routine assumes the caller holds forcewake asserted, it is
1758b90e38 Chris Wilson 2016-06-30 1780 * not suitable for very long waits. See intel_wait_for_register() if you
1758b90e38 Chris Wilson 2016-06-30 1781 * wish to wait without holding forcewake for the duration (i.e. you expect
1758b90e38 Chris Wilson 2016-06-30 1782 * the wait to be slow).
1758b90e38 Chris Wilson 2016-06-30 1783 *
1758b90e38 Chris Wilson 2016-06-30 1784 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1758b90e38 Chris Wilson 2016-06-30 1785 */
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1786 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
1758b90e38 Chris Wilson 2016-06-30 1787 i915_reg_t reg,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1788 u32 mask,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1789 u32 value,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1790 unsigned int fast_timeout_us,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1791 unsigned int slow_timeout_ms,
1d1a9774e4 Michal Wajdeczko 2017-04-07 1792 u32 *out_value)
1758b90e38 Chris Wilson 2016-06-30 1793 {
ff26ffa8ee Daniel Vetter 2017-05-10 @1794 u32 uninitialized_var(reg_value);
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1795 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1796 int ret;
1d1a9774e4 Michal Wajdeczko 2017-04-07 1797
6976e74b5f Michal Wajdeczko 2017-04-10 1798 /* Catch any overuse of this function */
84d84cb7e2 Chris Wilson 2017-04-11 1799 might_sleep_if(slow_timeout_ms);
84d84cb7e2 Chris Wilson 2017-04-11 1800 GEM_BUG_ON(fast_timeout_us > 20000);
6976e74b5f Michal Wajdeczko 2017-04-10 1801
84d84cb7e2 Chris Wilson 2017-04-11 1802 ret = -ETIMEDOUT;
84d84cb7e2 Chris Wilson 2017-04-11 1803 if (fast_timeout_us && fast_timeout_us <= 20000)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1804 ret = _wait_for_atomic(done, fast_timeout_us, 0);
ff26ffa8ee Daniel Vetter 2017-05-10 1805 if (ret && slow_timeout_ms)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1806 ret = wait_for(done, slow_timeout_ms);
84d84cb7e2 Chris Wilson 2017-04-11 1807
1d1a9774e4 Michal Wajdeczko 2017-04-07 1808 if (out_value)
1d1a9774e4 Michal Wajdeczko 2017-04-07 1809 *out_value = reg_value;
84d84cb7e2 Chris Wilson 2017-04-11 1810
1758b90e38 Chris Wilson 2016-06-30 1811 return ret;
1758b90e38 Chris Wilson 2016-06-30 1812 #undef done
1758b90e38 Chris Wilson 2016-06-30 1813 }
1758b90e38 Chris Wilson 2016-06-30 1814
1758b90e38 Chris Wilson 2016-06-30 1815 /**
23fdbdd7ed Sean Paul 2018-01-08 1816 * __intel_wait_for_register - wait until register matches expected state
1758b90e38 Chris Wilson 2016-06-30 1817 * @dev_priv: the i915 device
1758b90e38 Chris Wilson 2016-06-30 1818 * @reg: the register to read
1758b90e38 Chris Wilson 2016-06-30 1819 * @mask: mask to apply to register value
1758b90e38 Chris Wilson 2016-06-30 1820 * @value: expected value
23fdbdd7ed Sean Paul 2018-01-08 1821 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
23fdbdd7ed Sean Paul 2018-01-08 1822 * @slow_timeout_ms: slow timeout in millisecond
23fdbdd7ed Sean Paul 2018-01-08 1823 * @out_value: optional placeholder to hold registry value
1758b90e38 Chris Wilson 2016-06-30 1824 *
1758b90e38 Chris Wilson 2016-06-30 1825 * This routine waits until the target register @reg contains the expected
3d466cd67e Daniel Vetter 2016-07-15 1826 * @value after applying the @mask, i.e. it waits until ::
3d466cd67e Daniel Vetter 2016-07-15 1827 *
3d466cd67e Daniel Vetter 2016-07-15 1828 * (I915_READ(reg) & mask) == value
3d466cd67e Daniel Vetter 2016-07-15 1829 *
1758b90e38 Chris Wilson 2016-06-30 1830 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1758b90e38 Chris Wilson 2016-06-30 1831 *
1758b90e38 Chris Wilson 2016-06-30 1832 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1758b90e38 Chris Wilson 2016-06-30 1833 */
ede29af9b0 Daniele Ceraolo Spurio 2019-03-25 1834 int __intel_wait_for_register(struct intel_uncore *uncore,
f0f59a00a1 Ville Syrjälä 2015-11-18 1835 i915_reg_t reg,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1836 u32 mask,
3fc7d86b32 Michal Wajdeczko 2017-04-10 1837 u32 value,
23fdbdd7ed Sean Paul 2018-01-08 1838 unsigned int fast_timeout_us,
23fdbdd7ed Sean Paul 2018-01-08 1839 unsigned int slow_timeout_ms,
23fdbdd7ed Sean Paul 2018-01-08 1840 u32 *out_value)
7fd2d26921 Mika Kuoppala 2015-06-18 1841 {
1758b90e38 Chris Wilson 2016-06-30 @1842 unsigned fw =
1388c063e1 Daniele Ceraolo Spurio 2019-03-25 1843 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
23fdbdd7ed Sean Paul 2018-01-08 1844 u32 reg_value;
1758b90e38 Chris Wilson 2016-06-30 1845 int ret;
1758b90e38 Chris Wilson 2016-06-30 1846
3df82dd43b Chris Wilson 2018-03-29 1847 might_sleep_if(slow_timeout_ms);
0564654340 Chris Wilson 2017-04-11 1848
272c7e5230 Daniele Ceraolo Spurio 2019-03-19 1849 spin_lock_irq(&uncore->lock);
272c7e5230 Daniele Ceraolo Spurio 2019-03-19 1850 intel_uncore_forcewake_get__locked(uncore, fw);
0564654340 Chris Wilson 2017-04-11 1851
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1852 ret = __intel_wait_for_register_fw(uncore,
0564654340 Chris Wilson 2017-04-11 1853 reg, mask, value,
23fdbdd7ed Sean Paul 2018-01-08 1854 fast_timeout_us, 0, ®_value);
0564654340 Chris Wilson 2017-04-11 1855
272c7e5230 Daniele Ceraolo Spurio 2019-03-19 1856 intel_uncore_forcewake_put__locked(uncore, fw);
272c7e5230 Daniele Ceraolo Spurio 2019-03-19 1857 spin_unlock_irq(&uncore->lock);
0564654340 Chris Wilson 2017-04-11 1858
3df82dd43b Chris Wilson 2018-03-29 1859 if (ret && slow_timeout_ms)
db32ed6fea Daniele Ceraolo Spurio 2019-03-25 1860 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, reg),
23fdbdd7ed Sean Paul 2018-01-08 1861 (reg_value & mask) == value,
23fdbdd7ed Sean Paul 2018-01-08 1862 slow_timeout_ms * 1000, 10, 1000);
23fdbdd7ed Sean Paul 2018-01-08 1863
39806c3f11 Ville Syrjälä 2019-02-04 1864 /* just trace the final value */
39806c3f11 Ville Syrjälä 2019-02-04 1865 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
39806c3f11 Ville Syrjälä 2019-02-04 1866
23fdbdd7ed Sean Paul 2018-01-08 1867 if (out_value)
23fdbdd7ed Sean Paul 2018-01-08 1868 *out_value = reg_value;
1758b90e38 Chris Wilson 2016-06-30 1869
1758b90e38 Chris Wilson 2016-06-30 1870 return ret;
7fd2d26921 Mika Kuoppala 2015-06-18 1871 }
7fd2d26921 Mika Kuoppala 2015-06-18 1872
:::::: The code at line 1842 was first introduced by commit
:::::: 1758b90e38f53b93821c908201826e825a37cb65 drm/i915: Use a hybrid scheme for fast register waits
:::::: TO: Chris Wilson <chris@chris-wilson.co.uk>
:::::: CC: Chris Wilson <chris@chris-wilson.co.uk>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 6597 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 9/9] drm/i915: take a reference to uncore in the engine and use it
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 8/9] drm/i915: switch intel_wait_for_register " Daniele Ceraolo Spurio
@ 2019-03-25 21:49 ` Daniele Ceraolo Spurio
2019-03-25 22:21 ` Chris Wilson
2019-03-26 12:01 ` ✗ Fi.CI.CHECKPATCH: warning for more uncore rework Patchwork
` (3 subsequent siblings)
12 siblings, 1 reply; 27+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-03-25 21:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
A few advantages:
- Prepares us for the planned split of display uncore from GT uncore
- Improves our engine-centric view of the world in the engine code
and allows us to avoid jumping back to dev_priv.
- Allows us to wrap accesses to engine register in nice macros that
automatically pick the right mmio base.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 42 +++---
drivers/gpu/drm/i915/i915_reg.h | 16 +--
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 119 ++++++++---------
drivers/gpu/drm/i915/intel_engine_types.h | 2 +
drivers/gpu/drm/i915/intel_hangcheck.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 19 ++-
drivers/gpu/drm/i915/intel_lrc.h | 22 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 149 ++++++++++------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 45 +++++--
12 files changed, 213 insertions(+), 211 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b596cb42e24e..dbc749617922 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1848,7 +1848,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
- MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
+ MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
MMIO_D(GEN7_CXT_SIZE, D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 47bf07a59b5e..bb2c16c439ea 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -880,7 +880,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
for_each_engine(engine, dev_priv, id) {
seq_printf(m,
"Graphics Interrupt mask (%s): %08x\n",
- engine->name, I915_READ_IMR(engine));
+ engine->name, ENGINE_READ(engine, RING_IMR));
}
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a9557f92756f..b88021a87626 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1136,7 +1136,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
struct drm_i915_private *dev_priv = engine->i915;
if (INTEL_GEN(dev_priv) >= 6) {
- ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
+ ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else
@@ -1144,32 +1144,32 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
}
if (INTEL_GEN(dev_priv) >= 4) {
- ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
- ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
- ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
- ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
- ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
+ ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
+ ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
+ ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
+ ee->instps = ENGINE_READ(engine, RING_INSTPS);
+ ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
if (INTEL_GEN(dev_priv) >= 8) {
- ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
- ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
+ ee->faddr |= (u64) ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
+ ee->bbaddr |= (u64) ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
}
- ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
+ ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
} else {
- ee->faddr = I915_READ(DMA_FADD_I8XX);
- ee->ipeir = I915_READ(IPEIR);
- ee->ipehr = I915_READ(IPEHR);
+ ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
+ ee->ipeir = ENGINE_READ(engine, IPEIR);
+ ee->ipehr = ENGINE_READ(engine, IPEHR);
}
intel_engine_get_instdone(engine, &ee->instdone);
- ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
+ ee->instpm = ENGINE_READ(engine, RING_INSTPM);
ee->acthd = intel_engine_get_active_head(engine);
- ee->start = I915_READ_START(engine);
- ee->head = I915_READ_HEAD(engine);
- ee->tail = I915_READ_TAIL(engine);
- ee->ctl = I915_READ_CTL(engine);
+ ee->start = ENGINE_READ(engine, RING_START);
+ ee->head = ENGINE_READ(engine, RING_HEAD);
+ ee->tail = ENGINE_READ(engine, RING_TAIL);
+ ee->ctl = ENGINE_READ(engine, RING_CTL);
if (INTEL_GEN(dev_priv) > 2)
- ee->mode = I915_READ_MODE(engine);
+ ee->mode = ENGINE_READ(engine, RING_MI_MODE);
if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
i915_reg_t mmio;
@@ -1214,10 +1214,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (IS_GEN(dev_priv, 6))
ee->vm_info.pp_dir_base =
- I915_READ(RING_PP_DIR_BASE_READ(engine));
+ ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
else if (IS_GEN(dev_priv, 7))
ee->vm_info.pp_dir_base =
- I915_READ(RING_PP_DIR_BASE(engine));
+ ENGINE_READ(engine, RING_PP_DIR_BASE);
else if (INTEL_GEN(dev_priv) >= 8)
for (i = 0; i < 4; i++) {
ee->vm_info.pdp[i] =
@@ -1601,7 +1601,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
}
if (INTEL_GEN(dev_priv) >= 5)
- error->ccid = I915_READ(CCID);
+ error->ccid = I915_READ(CCID(RENDER_RING_BASE));
/* 3: Feature specific registers */
if (IS_GEN_RANGE(dev_priv, 6, 7)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b46910453e61..362f483f8ab2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -434,9 +434,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
-#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
-#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
-#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
+#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
+#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
+#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
#define PP_DIR_DCLV_2G 0xffffffff
#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
@@ -2568,12 +2568,12 @@ enum i915_power_well_id {
#define HWS_START_ADDRESS_SHIFT 4
#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
#define PWRCTX_EN (1 << 0)
-#define IPEIR _MMIO(0x2088)
-#define IPEHR _MMIO(0x208c)
+#define IPEIR(base) _MMIO((base) + 0x88)
+#define IPEHR(base) _MMIO((base) + 0x8c)
#define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098)
-#define DMA_FADD_I8XX _MMIO(0x20d0)
+#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
#define RING_BBSTATE(base) _MMIO((base) + 0x110)
#define RING_BB_PPGTT (1 << 5)
#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
@@ -2747,7 +2747,7 @@ enum i915_power_well_id {
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5)
-#define ACTHD _MMIO(0x20c8)
+#define ACTHD(base) _MMIO((base) + 0xc8)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
@@ -3947,7 +3947,7 @@ enum i915_power_well_id {
/*
* Logical Context regs
*/
-#define CCID _MMIO(0x2180)
+#define CCID(base) _MMIO((base) + 0x180)
#define CCID_EN BIT(0)
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3)
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index 17f802a8f8f0..2ef28dd7a4c5 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -1181,7 +1181,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv)
I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
if (INTEL_GEN(dev_priv) < 4)
- I915_WRITE(IPEIR, I915_READ(IPEIR));
+ I915_WRITE(IPEIR(RENDER_RING_BASE), I915_READ(IPEIR(RENDER_RING_BASE)));
else
I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index c936c6df34e4..74b6334c5ee0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -255,21 +255,17 @@ static void __sprint_engine_name(char *name, const struct engine_info *info)
void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
{
- struct drm_i915_private *dev_priv = engine->i915;
- i915_reg_t hwstam;
-
/*
* Though they added more rings on g4x/ilk, they did not add
* per-engine HWSTAM until gen6.
*/
- if (INTEL_GEN(dev_priv) < 6 && engine->class != RENDER_CLASS)
+ if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
return;
- hwstam = RING_HWSTAM(engine->mmio_base);
- if (INTEL_GEN(dev_priv) >= 3)
- I915_WRITE(hwstam, mask);
+ if (INTEL_GEN(engine->i915) >= 3)
+ ENGINE_WRITE(engine, RING_HWSTAM, mask);
else
- I915_WRITE16(hwstam, mask);
+ ENGINE_WRITE16(engine, RING_HWSTAM, mask);
}
static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
@@ -309,6 +305,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->id = id;
engine->mask = BIT(id);
engine->i915 = dev_priv;
+ engine->uncore = &dev_priv->uncore;
__sprint_engine_name(engine->name, info);
engine->hw_id = engine->guc_id = info->hw_id;
engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);
@@ -787,37 +784,35 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct drm_i915_private *i915 = engine->i915;
+
u64 acthd;
- if (INTEL_GEN(dev_priv) >= 8)
- acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
- RING_ACTHD_UDW(engine->mmio_base));
- else if (INTEL_GEN(dev_priv) >= 4)
- acthd = I915_READ(RING_ACTHD(engine->mmio_base));
+ if (INTEL_GEN(i915) >= 8)
+ acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
+ else if (INTEL_GEN(i915) >= 4)
+ acthd = ENGINE_READ(engine, RING_ACTHD);
else
- acthd = I915_READ(ACTHD);
+ acthd = ENGINE_READ(engine, ACTHD);
return acthd;
}
u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
u64 bbaddr;
- if (INTEL_GEN(dev_priv) >= 8)
- bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
- RING_BBADDR_UDW(engine->mmio_base));
+ if (INTEL_GEN(engine->i915) >= 8)
+ bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
else
- bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
+ bbaddr = ENGINE_READ(engine, RING_BBADDR);
return bbaddr;
}
int intel_engine_stop_cs(struct intel_engine_cs *engine)
{
- struct intel_uncore *uncore = &engine->i915->uncore;
+ struct intel_uncore *uncore = engine->uncore;
const u32 base = engine->mmio_base;
const i915_reg_t mode = RING_MI_MODE(base);
int err;
@@ -846,12 +841,9 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
GEM_TRACE("%s\n", engine->name);
- I915_WRITE_FW(RING_MI_MODE(engine->mmio_base),
- _MASKED_BIT_DISABLE(STOP_RING));
+ ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
@@ -946,6 +938,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
int subslice;
@@ -954,12 +947,12 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
switch (INTEL_GEN(dev_priv)) {
default:
- instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
+ instdone->instdone = intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id != RCS0)
break;
- instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
+ instdone->slice_common = intel_uncore_read(uncore, GEN7_SC_INSTDONE);
for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
@@ -970,28 +963,28 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
}
break;
case 7:
- instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
+ instdone->instdone = intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id != RCS0)
break;
- instdone->slice_common = I915_READ(GEN7_SC_INSTDONE);
- instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE);
- instdone->row[0][0] = I915_READ(GEN7_ROW_INSTDONE);
+ instdone->slice_common = intel_uncore_read(uncore, GEN7_SC_INSTDONE);
+ instdone->sampler[0][0] = intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
+ instdone->row[0][0] = intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
break;
case 6:
case 5:
case 4:
- instdone->instdone = I915_READ(RING_INSTDONE(mmio_base));
+ instdone->instdone = intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
if (engine->id == RCS0)
/* HACK: Using the wrong struct member */
- instdone->slice_common = I915_READ(GEN4_INSTDONE1);
+ instdone->slice_common = intel_uncore_read(uncore, GEN4_INSTDONE1);
break;
case 3:
case 2:
- instdone->instdone = I915_READ(GEN2_INSTDONE);
+ instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
break;
}
}
@@ -1011,12 +1004,12 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
return true;
/* First check that no commands are left in the ring */
- if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
- (I915_READ_TAIL(engine) & TAIL_ADDR))
+ if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
+ (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
idle = false;
/* No bit for gen2, so assume the CS parser is idle */
- if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
+ if (INTEL_GEN(dev_priv) > 2 && !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
idle = false;
intel_runtime_pm_put(dev_priv, wakeref);
@@ -1332,24 +1325,24 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
u64 addr;
if (engine->id == RCS0 && IS_GEN_RANGE(dev_priv, 4, 7))
- drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
+ drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
drm_printf(m, "\tRING_START: 0x%08x\n",
- I915_READ(RING_START(engine->mmio_base)));
+ ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
- I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR);
+ ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
drm_printf(m, "\tRING_TAIL: 0x%08x\n",
- I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR);
+ ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
- I915_READ(RING_CTL(engine->mmio_base)),
- I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
if (INTEL_GEN(engine->i915) > 2) {
drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
- I915_READ(RING_MI_MODE(engine->mmio_base)),
- I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
+ ENGINE_READ(engine, RING_MI_MODE),
+ ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
}
if (INTEL_GEN(dev_priv) >= 6) {
- drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
+ drm_printf(m, "\tRING_IMR: %08x\n", ENGINE_READ(engine, RING_IMR));
}
addr = intel_engine_get_active_head(engine);
@@ -1359,22 +1352,21 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
if (INTEL_GEN(dev_priv) >= 8)
- addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
- RING_DMA_FADD_UDW(engine->mmio_base));
+ addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
else if (INTEL_GEN(dev_priv) >= 4)
- addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+ addr = ENGINE_READ(engine, RING_DMA_FADD);
else
- addr = I915_READ(DMA_FADD_I8XX);
+ addr = ENGINE_READ(engine, DMA_FADD_I8XX);
drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
if (INTEL_GEN(dev_priv) >= 4) {
drm_printf(m, "\tIPEIR: 0x%08x\n",
- I915_READ(RING_IPEIR(engine->mmio_base)));
+ ENGINE_READ(engine, RING_IPEIR));
drm_printf(m, "\tIPEHR: 0x%08x\n",
- I915_READ(RING_IPEHR(engine->mmio_base)));
+ ENGINE_READ(engine, RING_IPEHR));
} else {
- drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
- drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+ drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
+ drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
if (HAS_EXECLISTS(dev_priv)) {
@@ -1384,15 +1376,15 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
u8 read, write;
drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
- I915_READ(RING_EXECLIST_STATUS_LO(engine)),
- I915_READ(RING_EXECLIST_STATUS_HI(engine)));
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
read = execlists->csb_head;
write = READ_ONCE(*execlists->csb_write);
drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
read, write,
- GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
+ GEN8_CSB_WRITE_PTR(ENGINE_READ(engine, RING_CONTEXT_STATUS_PTR)),
yesno(test_bit(TASKLET_STATE_SCHED,
&engine->execlists.tasklet.state)),
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
@@ -1407,9 +1399,9 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
idx,
hws[idx * 2],
- I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
+ ENGINE_READ_IDX(engine, RING_CONTEXT_STATUS_BUF_LO, idx),
hws[idx * 2 + 1],
- I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
+ ENGINE_READ_IDX(engine, RING_CONTEXT_STATUS_BUF_HI, idx));
}
rcu_read_lock();
@@ -1436,11 +1428,11 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
rcu_read_unlock();
} else if (INTEL_GEN(dev_priv) > 6) {
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE(engine)));
+ ENGINE_READ(engine, RING_PP_DIR_BASE));
drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
- I915_READ(RING_PP_DIR_BASE_READ(engine)));
+ ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
- I915_READ(RING_PP_DIR_DCLV(engine)));
+ ENGINE_READ(engine, RING_PP_DIR_DCLV));
}
}
@@ -1687,8 +1679,7 @@ void intel_disable_engine_stats(struct intel_engine_cs *engine)
static bool match_ring(struct i915_request *rq)
{
- struct drm_i915_private *dev_priv = rq->i915;
- u32 ring = I915_READ(RING_START(rq->engine->mmio_base));
+ u32 ring = ENGINE_READ(rq->engine, RING_START);
return ring == i915_ggtt_offset(rq->ring->vma);
}
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h
index 88ed7ba8886f..b3249bf6a65f 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -29,6 +29,7 @@ struct drm_i915_reg_table;
struct i915_gem_context;
struct i915_request;
struct i915_sched_attr;
+struct intel_uncore;
struct intel_hw_status_page {
struct i915_vma *vma;
@@ -250,6 +251,7 @@ struct intel_engine_execlists {
struct intel_engine_cs {
struct drm_i915_private *i915;
+ struct intel_uncore *uncore;
char name[INTEL_ENGINE_CS_MAX_NAME];
enum intel_engine_id id;
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index 125662c64934..59232df11ada 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -118,11 +118,11 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
* and break the hang. This should work on
* all but the second generation chipsets.
*/
- tmp = I915_READ_CTL(engine);
+ tmp = ENGINE_READ(engine, RING_CTL);
if (tmp & RING_WAIT) {
i915_handle_error(dev_priv, engine->mask, 0,
"stuck wait on %s", engine->name);
- I915_WRITE_CTL(engine, tmp);
+ ENGINE_WRITE(engine, RING_CTL, tmp);
return ENGINE_WAIT_KICK;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 66bc3cd4e166..6edbe5cbdb94 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2074,16 +2074,14 @@ static int gen8_emit_bb_start(struct i915_request *rq,
static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
- I915_WRITE_IMR(engine,
+ ENGINE_WRITE(engine, RING_IMR,
~(engine->irq_enable_mask | engine->irq_keep_mask));
- POSTING_READ_FW(RING_IMR(engine->mmio_base));
+ ENGINE_POSTING_READ(engine, RING_IMR);
}
static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
- I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
+ ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
}
static int gen8_emit_flush(struct i915_request *request, u32 mode)
@@ -2288,7 +2286,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
dev_priv = engine->i915;
if (engine->buffer) {
- WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+ WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
}
if (engine->cleanup)
@@ -2400,6 +2398,7 @@ static int logical_ring_init(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
struct intel_engine_execlists * const execlists = &engine->execlists;
+ u32 base = engine->mmio_base;
int ret;
ret = intel_engine_init_common(engine);
@@ -2410,12 +2409,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
if (HAS_LOGICAL_RING_ELSQ(i915)) {
execlists->submit_reg = i915->uncore.regs +
- i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
+ i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
execlists->ctrl_reg = i915->uncore.regs +
- i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
+ i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
} else {
execlists->submit_reg = i915->uncore.regs +
- i915_mmio_reg_offset(RING_ELSP(engine));
+ i915_mmio_reg_offset(RING_ELSP(base));
}
execlists->preempt_complete_status = ~0u;
@@ -2658,7 +2657,7 @@ static void execlists_init_reg_state(u32 *regs,
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
MI_LRI_FORCE_POSTED;
- CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
+ CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
if (INTEL_GEN(engine->i915) < 11) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index f1aec8a6986f..92642ab91472 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -28,20 +28,20 @@
#include "i915_gem_context.h"
/* Execlists regs */
-#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
-#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
-#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
-#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
+#define RING_ELSP(base) _MMIO((base) + 0x230)
+#define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
+#define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
+#define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
-#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
+#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
-#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
-#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
-#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
+#define RING_CONTEXT_STATUS_BUF_BASE(base) _MMIO((base) + 0x370)
+#define RING_CONTEXT_STATUS_BUF_LO(base, i) _MMIO((base) + 0x370 + (i) * 8)
+#define RING_CONTEXT_STATUS_BUF_HI(base, i) _MMIO((base) + 0x370 + (i) * 8 + 4)
+#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
+#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
+#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
#define EL_CTRL_LOAD (1 << 0)
/* The docs specify that the write pointer wraps around after 5h, "After status
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a5b4a2d9a492..67f103fbb91e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -575,19 +575,19 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
static void flush_cs_tlb(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- i915_reg_t instpm = RING_INSTPM(engine->mmio_base);
if (!IS_GEN_RANGE(dev_priv, 6, 7))
return;
/* ring should be idle before issuing a sync flush*/
- WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
-
- I915_WRITE(instpm,
- _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
- INSTPM_SYNC_FLUSH));
- if (intel_wait_for_register(&dev_priv->uncore,
- instpm, INSTPM_SYNC_FLUSH, 0,
+ WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+
+ ENGINE_WRITE(engine, RING_INSTPM,
+ _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+ INSTPM_SYNC_FLUSH));
+ if (intel_wait_for_register(engine->uncore,
+ RING_INSTPM(engine->mmio_base),
+ INSTPM_SYNC_FLUSH, 0,
1000))
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
engine->name);
@@ -606,8 +606,8 @@ static bool stop_ring(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
if (INTEL_GEN(dev_priv) > 2) {
- I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
- if (intel_wait_for_register(&dev_priv->uncore,
+ ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
+ if (intel_wait_for_register(engine->uncore,
RING_MI_MODE(engine->mmio_base),
MODE_IDLE,
MODE_IDLE,
@@ -618,20 +618,20 @@ static bool stop_ring(struct intel_engine_cs *engine)
* set even though the ring is empty. So double
* check before giving up.
*/
- if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
+ if (ENGINE_READ(engine, RING_HEAD) != ENGINE_READ(engine, RING_TAIL))
return false;
}
}
- I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
+ ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
- I915_WRITE_HEAD(engine, 0);
- I915_WRITE_TAIL(engine, 0);
+ ENGINE_WRITE(engine, RING_HEAD, 0);
+ ENGINE_WRITE(engine, RING_TAIL, 0);
/* The ring must be empty before it is disabled */
- I915_WRITE_CTL(engine, 0);
+ ENGINE_WRITE(engine, RING_CTL, 0);
- return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
+ return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
}
static int init_ring_common(struct intel_engine_cs *engine)
@@ -640,26 +640,26 @@ static int init_ring_common(struct intel_engine_cs *engine)
struct intel_ring *ring = engine->buffer;
int ret = 0;
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
if (!stop_ring(engine)) {
/* G45 ring initialization often fails to reset head to zero */
DRM_DEBUG_DRIVER("%s head not reset to zero "
"ctl %08x head %08x tail %08x start %08x\n",
engine->name,
- I915_READ_CTL(engine),
- I915_READ_HEAD(engine),
- I915_READ_TAIL(engine),
- I915_READ_START(engine));
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_HEAD),
+ ENGINE_READ(engine, RING_TAIL),
+ ENGINE_READ(engine, RING_START));
if (!stop_ring(engine)) {
DRM_ERROR("failed to set %s head to zero "
"ctl %08x head %08x tail %08x start %08x\n",
engine->name,
- I915_READ_CTL(engine),
- I915_READ_HEAD(engine),
- I915_READ_TAIL(engine),
- I915_READ_START(engine));
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_HEAD),
+ ENGINE_READ(engine, RING_TAIL),
+ ENGINE_READ(engine, RING_START));
ret = -EIO;
goto out;
}
@@ -673,18 +673,18 @@ static int init_ring_common(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
/* Enforce ordering by reading HEAD register back */
- I915_READ_HEAD(engine);
+ ENGINE_READ(engine, RING_HEAD);
/* Initialize the ring. This must happen _after_ we've cleared the ring
* registers with the above sequence (the readback of the HEAD registers
* also enforces ordering), otherwise the hw might lose the new ring
* register values. */
- I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
+ ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
/* WaClearRingBufHeadRegAtInit:ctg,elk */
- if (I915_READ_HEAD(engine))
+ if (ENGINE_READ(engine, RING_HEAD))
DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
- engine->name, I915_READ_HEAD(engine));
+ engine->name, ENGINE_READ(engine, RING_HEAD));
/* Check that the ring offsets point within the ring! */
GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
@@ -692,43 +692,43 @@ static int init_ring_common(struct intel_engine_cs *engine)
intel_ring_update_space(ring);
/* First wake the ring up to an empty/idle ring */
- I915_WRITE_HEAD(engine, ring->head);
- I915_WRITE_TAIL(engine, ring->head);
- (void)I915_READ_TAIL(engine);
+ ENGINE_WRITE(engine, RING_HEAD, ring->head);
+ ENGINE_WRITE(engine, RING_TAIL, ring->head);
+ ENGINE_POSTING_READ(engine, RING_TAIL);
- I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
+ ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
/* If the head is still not zero, the ring is dead */
- if (intel_wait_for_register(&dev_priv->uncore,
+ if (intel_wait_for_register(engine->uncore,
RING_CTL(engine->mmio_base),
RING_VALID, RING_VALID,
50)) {
DRM_ERROR("%s initialization failed "
"ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
engine->name,
- I915_READ_CTL(engine),
- I915_READ_CTL(engine) & RING_VALID,
- I915_READ_HEAD(engine), ring->head,
- I915_READ_TAIL(engine), ring->tail,
- I915_READ_START(engine),
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_CTL) & RING_VALID,
+ ENGINE_READ(engine, RING_HEAD), ring->head,
+ ENGINE_READ(engine, RING_TAIL), ring->tail,
+ ENGINE_READ(engine, RING_START),
i915_ggtt_offset(ring->vma));
ret = -EIO;
goto out;
}
if (INTEL_GEN(dev_priv) > 2)
- I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
+ ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
/* Now awake, let it get started */
if (ring->tail != ring->head) {
- I915_WRITE_TAIL(engine, ring->tail);
- (void)I915_READ_TAIL(engine);
+ ENGINE_WRITE(engine, RING_TAIL, ring->tail);
+ ENGINE_POSTING_READ(engine, RING_TAIL);
}
/* Papering over lost _interrupts_ immediately following the restart */
intel_engine_queue_breadcrumbs(engine);
out:
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
return ret;
}
@@ -869,7 +869,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (INTEL_GEN(dev_priv) >= 6)
- I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
+ ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
return 0;
}
@@ -896,12 +896,10 @@ static void cancel_requests(struct intel_engine_cs *engine)
static void i9xx_submit_request(struct i915_request *request)
{
- struct drm_i915_private *dev_priv = request->i915;
-
i915_request_submit(request);
- I915_WRITE_TAIL(request->engine,
- intel_ring_set_tail(request->ring, request->tail));
+ ENGINE_WRITE(request->engine, RING_TAIL,
+ intel_ring_set_tail(request->ring, request->tail));
}
static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
@@ -973,20 +971,20 @@ gen5_irq_disable(struct intel_engine_cs *engine)
static void
i9xx_irq_enable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ GEM_BUG_ON(engine->id != RCS0);
- dev_priv->irq_mask &= ~engine->irq_enable_mask;
- I915_WRITE(IMR, dev_priv->irq_mask);
- POSTING_READ_FW(RING_IMR(engine->mmio_base));
+ engine->i915->irq_mask &= ~engine->irq_enable_mask;
+ ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
+ ENGINE_POSTING_READ(engine, RING_IMR);
}
static void
i9xx_irq_disable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ GEM_BUG_ON(engine->id != RCS0);
- dev_priv->irq_mask |= engine->irq_enable_mask;
- I915_WRITE(IMR, dev_priv->irq_mask);
+ engine->i915->irq_mask |= engine->irq_enable_mask;
+ ENGINE_WRITE(engine, RING_IMR, engine->i915->irq_mask);
}
static void
@@ -1026,47 +1024,38 @@ bsd_ring_flush(struct i915_request *rq, u32 mode)
static void
gen6_irq_enable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- I915_WRITE_IMR(engine,
- ~(engine->irq_enable_mask |
- engine->irq_keep_mask));
+ ENGINE_WRITE(engine, RING_IMR,
+ ~(engine->irq_enable_mask | engine->irq_keep_mask));
/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
- POSTING_READ_FW(RING_IMR(engine->mmio_base));
+ ENGINE_POSTING_READ(engine, RING_IMR);
- gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
+ gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
}
static void
gen6_irq_disable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
- gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
+ ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
+ gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
}
static void
hsw_vebox_irq_enable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+ ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
- POSTING_READ_FW(RING_IMR(engine->mmio_base));
+ ENGINE_POSTING_READ(engine, RING_IMR);
- gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
+ gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask);
}
static void
hsw_vebox_irq_disable(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- I915_WRITE_IMR(engine, ~0);
- gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
+ ENGINE_WRITE(engine, RING_IMR, ~0);
+ gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask);
}
static int
@@ -1577,7 +1566,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
WARN_ON(INTEL_GEN(dev_priv) > 2 &&
- (I915_READ_MODE(engine) & MODE_IDLE) == 0);
+ (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
intel_ring_unpin(engine->buffer);
intel_ring_put(engine->buffer);
@@ -1612,11 +1601,11 @@ static int load_pd_dir(struct i915_request *rq,
return PTR_ERR(cs);
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
+ *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
*cs++ = PP_DIR_DCLV_2G;
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
+ *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
*cs++ = ppgtt->pd.base.ggtt_offset << 10;
intel_ring_advance(rq, cs);
@@ -1635,7 +1624,7 @@ static int flush_pd_dir(struct i915_request *rq)
/* Stall until the page table load is complete */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
+ *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
*cs++ = i915_scratch_offset(rq->i915);
*cs++ = MI_NOOP;
@@ -2052,7 +2041,7 @@ int intel_ring_cacheline_align(struct i915_request *rq)
static void gen6_bsd_submit_request(struct i915_request *request)
{
- struct intel_uncore *uncore = &request->i915->uncore;
+ struct intel_uncore *uncore = request->engine->uncore;
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a02c92dac5da..e58d6f04177b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -29,23 +29,44 @@ struct drm_printer;
#define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
-#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
-#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
+/*
+ * The register defines to be used with the following macros need to accept a
+ * base param, e.g:
+ *
+ * REG_FOO(base) _MMIO((base) + <relative offset>)
+ * ENGINE_READ(engine, REG_FOO);
+ *
+ * register arrays are to be defined and accessed as follows:
+ *
+ * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
+ * ENGINE_READ_IDX(engine, REG_BAR, i)
+ */
+
+#define __ENGINE_REG_OP(op__, engine__, ...) \
+ intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
+
+#define __ENGINE_READ_OP(op__, engine__, reg__) \
+ __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
-#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
-#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
+#define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
+#define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
+#define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
+#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
-#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
-#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
+#define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
+ __ENGINE_REG_OP(read64_2x32, (engine__), \
+ lower_reg__((engine__)->mmio_base), \
+ upper_reg__((engine__)->mmio_base))
-#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
-#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
+#define ENGINE_READ_IDX(engine__, reg__, idx__) \
+ __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
-#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
-#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
+#define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
+ __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
-#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
-#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
+#define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
+#define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
+#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 9/9] drm/i915: take a reference to uncore in the engine and use it
2019-03-25 21:49 ` [PATCH 9/9] drm/i915: take a reference to uncore in the engine and use it Daniele Ceraolo Spurio
@ 2019-03-25 22:21 ` Chris Wilson
0 siblings, 0 replies; 27+ messages in thread
From: Chris Wilson @ 2019-03-25 22:21 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-03-25 21:49:40)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index a02c92dac5da..e58d6f04177b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -29,23 +29,44 @@ struct drm_printer;
> #define CACHELINE_BYTES 64
> #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
>
> -#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
> -#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
> +/*
> + * The register defines to be used with the following macros need to accept a
> + * base param, e.g:
> + *
> + * REG_FOO(base) _MMIO((base) + <relative offset>)
> + * ENGINE_READ(engine, REG_FOO);
> + *
> + * register arrays are to be defined and accessed as follows:
> + *
> + * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
> + * ENGINE_READ_IDX(engine, REG_BAR, i)
> + */
> +
> +#define __ENGINE_REG_OP(op__, engine__, ...) \
> + intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
> +
> +#define __ENGINE_READ_OP(op__, engine__, reg__) \
> + __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
I'm warming to ENGINE_READ/WRITE. I must admit I was hoping to lose the
macros and all the shouting.
I was just stopping by here to say, now would be the perfect opportunity
to split this out into intel_engine_reg.h ?
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for more uncore rework
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2019-03-25 21:49 ` [PATCH 9/9] drm/i915: take a reference to uncore in the engine and use it Daniele Ceraolo Spurio
@ 2019-03-26 12:01 ` Patchwork
2019-03-26 12:06 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-03-26 12:01 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: more uncore rework
URL : https://patchwork.freedesktop.org/series/58550/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6e25d35e2cc9 drm/i915: rename raw reg access functions
-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/intel_uncore.c:455:
+ dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
HSW_EDRAM_CAP);
-:298: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#298: FILE: drivers/gpu/drm/i915/intel_uncore.h:232:
+}
+__raw_read(8, b)
total: 0 errors, 0 warnings, 2 checks, 262 lines checked
166116555629 drm/i915: add HAS_FORCEWAKE flag to uncore
77645a276eb5 drm/i915: add uncore flags for unclaimed mmio
2cf0b14f6229 drm/i915: take a ref to the rpm in the uncore structure
-:45: CHECK:LINE_SPACING: Please don't use multiple blank lines
#45: FILE: drivers/gpu/drm/i915/intel_drv.h:2293:
+
+
total: 0 errors, 0 warnings, 1 checks, 111 lines checked
b1d91e233942 drm/i915: switch uncore mmio funcs to use intel_uncore
-:44: WARNING:LONG_LINE: line over 100 characters
#44: FILE: drivers/gpu/drm/i915/i915_drv.h:3477:
+#define I915_WRITE16_NOTRACE(reg__, val__) __I915_REG_OP(write16_notrace, dev_priv, (reg__), (val__))
-:229: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#229: FILE: drivers/gpu/drm/i915/intel_uncore.h:254:
+#define __uncore_read(name__, x__, s__, trace__) \
+static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
+ i915_reg_t reg) \
+{ \
+ return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
+}
-:275: WARNING:LINE_SPACING: Missing a blank line after declarations
#275: FILE: drivers/gpu/drm/i915/intel_uncore.h:300:
+ u32 upper, lower, old_upper, loop = 0;
+ upper = intel_uncore_read(uncore, upper_reg);
total: 1 errors, 2 warnings, 0 checks, 295 lines checked
443cb3ccc31f drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore
fc9304b17a6a drm/i915: intel_wait_for_register_fw to uncore
-:415: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#415: FILE: drivers/gpu/drm/i915/intel_uncore.h:209:
}
+int __intel_wait_for_register_fw(struct intel_uncore *uncore,
total: 0 errors, 0 warnings, 1 checks, 364 lines checked
7c8747a40025 drm/i915: switch intel_wait_for_register to uncore
-:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#104: FILE: drivers/gpu/drm/i915/intel_cdclk.c:983:
+ if (intel_wait_for_register(&dev_priv->uncore,
LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
-:734: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#734: FILE: drivers/gpu/drm/i915/intel_uncore.c:1835:
+int __intel_wait_for_register(struct intel_uncore *uncore,
i915_reg_t reg,
-:829: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#829: FILE: drivers/gpu/drm/i915/vlv_dsi.c:357:
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
-:838: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#838: FILE: drivers/gpu/drm/i915/vlv_dsi.c:381:
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
-:847: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#847: FILE: drivers/gpu/drm/i915/vlv_dsi.c:407:
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
-:856: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#856: FILE: drivers/gpu/drm/i915/vlv_dsi.c:431:
+ if (intel_wait_for_register(&dev_priv->uncore,
MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
-:865: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#865: FILE: drivers/gpu/drm/i915/vlv_dsi.c:439:
+ if (intel_wait_for_register(&dev_priv->uncore,
BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
total: 0 errors, 0 warnings, 7 checks, 727 lines checked
65409c86a0d0 drm/i915: take a reference to uncore in the engine and use it
-:76: CHECK:SPACING: No space is necessary after a cast
#76: FILE: drivers/gpu/drm/i915/i915_gpu_error.c:1153:
+ ee->faddr |= (u64) ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
-:77: CHECK:SPACING: No space is necessary after a cast
#77: FILE: drivers/gpu/drm/i915/i915_gpu_error.c:1154:
+ ee->bbaddr |= (u64) ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
-:390: WARNING:LONG_LINE: line over 100 characters
#390: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:1337:
+ ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
-:540: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#540: FILE: drivers/gpu/drm/i915/intel_lrc.c:2078:
+ ENGINE_WRITE(engine, RING_IMR,
~(engine->irq_enable_mask | engine->irq_keep_mask));
-:996: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#996: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:48:
+#define __ENGINE_READ_OP(op__, engine__, reg__) \
+ __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
-:1008: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#1008: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:56:
+#define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
+ __ENGINE_REG_OP(read64_2x32, (engine__), \
+ lower_reg__((engine__)->mmio_base), \
+ upper_reg__((engine__)->mmio_base))
-:1015: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#1015: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:61:
+#define ENGINE_READ_IDX(engine__, reg__, idx__) \
+ __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
-:1020: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects?
#1020: FILE: drivers/gpu/drm/i915/intel_ringbuffer.h:64:
+#define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
+ __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
total: 0 errors, 1 warnings, 7 checks, 914 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✗ Fi.CI.SPARSE: warning for more uncore rework
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2019-03-26 12:01 ` ✗ Fi.CI.CHECKPATCH: warning for more uncore rework Patchwork
@ 2019-03-26 12:06 ` Patchwork
2019-03-26 12:29 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-26 16:46 ` ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-03-26 12:06 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: more uncore rework
URL : https://patchwork.freedesktop.org/series/58550/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: rename raw reg access functions
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3586:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void)
Commit: drm/i915: add HAS_FORCEWAKE flag to uncore
Okay!
Commit: drm/i915: add uncore flags for unclaimed mmio
Okay!
Commit: drm/i915: take a ref to the rpm in the uncore structure
Okay!
Commit: drm/i915: switch uncore mmio funcs to use intel_uncore
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3555:16: warning: expression using sizeof(void)
Commit: drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore
Okay!
Commit: drm/i915: intel_wait_for_register_fw to uncore
Okay!
Commit: drm/i915: switch intel_wait_for_register to uncore
Okay!
Commit: drm/i915: take a reference to uncore in the engine and use it
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.BAT: success for more uncore rework
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2019-03-26 12:06 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-03-26 12:29 ` Patchwork
2019-03-26 16:46 ` ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-03-26 12:29 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: more uncore rework
URL : https://patchwork.freedesktop.org/series/58550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5814 -> Patchwork_12596
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58550/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12596 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_contexts:
- fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569]
- fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: NOTRUN -> INCOMPLETE [fdo#108569]
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bwr-2160: PASS -> FAIL [fdo#100368]
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: NOTRUN -> DMESG-FAIL [fdo#103182]
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709]
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@i915_selftest@live_uncore:
- fi-skl-gvtdvm: DMESG-FAIL [fdo#110210] -> PASS
- fi-ivb-3770: DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (43 -> 39)
------------------------------
Additional (4): fi-byt-j1900 fi-byt-n2820 fi-gdg-551 fi-icl-u3
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-elk-e7500 fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5814 -> Patchwork_12596
CI_DRM_5814: a0a0cf2e35724447ba6cdda8fc3c451df742028e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4903: a4dc3d0f9ac6abf2a0ca6a4771255cb5dcb3b07b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12596: 65409c86a0d0b0c87e82f2498fe61aed2d4b55ac @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12596/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_uc.o
In file included from drivers/gpu/drm/i915/intel_guc.h:28:0,
from drivers/gpu/drm/i915/intel_uc.h:27,
from drivers/gpu/drm/i915/intel_uc.c:25:
drivers/gpu/drm/i915/intel_uncore.h: In function ‘__raw_uncore_read64’:
drivers/gpu/drm/i915/intel_uncore.h:232:9: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration]
return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:244:1: note: in expansion of macro ‘__raw_read’
__raw_read(64, q)
^~~~~~~~~~
drivers/gpu/drm/i915/intel_uncore.h: In function ‘__raw_uncore_write64’:
drivers/gpu/drm/i915/intel_uncore.h:239:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration]
write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
^
drivers/gpu/drm/i915/intel_uncore.h:249:1: note: in expansion of macro ‘__raw_write’
__raw_write(64, q)
^~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/intel_uc.o' failed
make[5]: *** [drivers/gpu/drm/i915/intel_uc.o] Error 1
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed
make[4]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed
make[3]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed
make[2]: *** [drivers/gpu] Error 2
/home/cidrm/kernel/Makefile:1046: recipe for target 'drivers' failed
make[1]: *** [drivers] Error 2
Makefile:170: recipe for target 'sub-make' failed
make: *** [sub-make] Error 2
== Linux commits ==
65409c86a0d0 drm/i915: take a reference to uncore in the engine and use it
7c8747a40025 drm/i915: switch intel_wait_for_register to uncore
fc9304b17a6a drm/i915: intel_wait_for_register_fw to uncore
443cb3ccc31f drm/i915: switch intel_uncore_forcewake_for_reg to intel_uncore
b1d91e233942 drm/i915: switch uncore mmio funcs to use intel_uncore
2cf0b14f6229 drm/i915: take a ref to the rpm in the uncore structure
77645a276eb5 drm/i915: add uncore flags for unclaimed mmio
166116555629 drm/i915: add HAS_FORCEWAKE flag to uncore
6e25d35e2cc9 drm/i915: rename raw reg access functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12596/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.IGT: success for more uncore rework
2019-03-25 21:49 [PATCH 0/9] more uncore rework Daniele Ceraolo Spurio
` (11 preceding siblings ...)
2019-03-26 12:29 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-26 16:46 ` Patchwork
12 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-03-26 16:46 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: more uncore rework
URL : https://patchwork.freedesktop.org/series/58550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5814_full -> Patchwork_12596_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12596_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@gem-mmap-gtt:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@i2c:
- shard-iclb: PASS -> DMESG-WARN [fdo#109982]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-pageflip-hang-newfb-render-e:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +1
* igt@kms_chamelium@hdmi-crc-argb1555:
- shard-iclb: NOTRUN -> SKIP [fdo#109284]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232] +2
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: PASS -> DMESG-WARN [fdo#109593]
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: PASS -> FAIL [fdo#105363] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#103167] +10
* igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#109247] +12
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] / [fdo#109278]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: PASS -> SKIP [fdo#109642]
* igt@kms_psr@psr2_basic:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: PASS -> FAIL [fdo#104894] +1
* igt@perf@blocking:
- shard-iclb: PASS -> FAIL [fdo#108587] +1
* igt@perf@short-reads:
- shard-kbl: PASS -> FAIL [fdo#103183]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +46
* igt@runner@aborted:
- shard-iclb: NOTRUN -> FAIL [fdo#109593]
#### Possible fixes ####
* igt@gem_mmap_gtt@forked-big-copy-odd:
- shard-iclb: TIMEOUT [fdo#109673] -> PASS
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-iclb: INCOMPLETE -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-iclb: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
- shard-snb: SKIP [fdo#109271] -> PASS +1
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: FAIL [fdo#109247] -> PASS +1
* {igt@kms_plane@pixel-format-pipe-b-planes}:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr2_su@page_flip:
- shard-iclb: SKIP [fdo#109642] -> PASS
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: SKIP [fdo#109441] -> PASS +3
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-iclb: FAIL [fdo#104894] -> PASS
#### Warnings ####
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> DMESG-FAIL [fdo#103232]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108587]: https://bugs.freedesktop.org/show_bug.cgi?id=108587
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5814 -> Patchwork_12596
CI_DRM_5814: a0a0cf2e35724447ba6cdda8fc3c451df742028e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4903: a4dc3d0f9ac6abf2a0ca6a4771255cb5dcb3b07b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12596: 65409c86a0d0b0c87e82f2498fe61aed2d4b55ac @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12596/
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