* [U-Boot] [PATCH 0/6] ARM: meson: Add support for G12A based U200 board
@ 2019-03-26 15:02 ` Neil Armstrong
0 siblings, 0 replies; 16+ messages in thread
From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw)
To: u-boot
This patchset adds basic support for the recent Amlogic G12A SoC family.
This SoC family embeds 4xCortex A53 CPUs, and is very similar to
the AXG SoC Family with the multimedia features of previous families.
This patchset adds :
- pinctrl support
- clk driver atfer a rework of the drivers files
- import Linux 5.1-rc1 G12A & U200 DT files
- add board/amlogic/u200 to support the U200 reference design
Jerome Brunet (5):
pinctrl: meson: add g12a support
clk: create meson directory and move related drivers
clk: meson: add g12a support
ARM: meson: add G12a support
boards: meson: add g12a u200
Neil Armstrong (1):
ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1
MAINTAINERS | 2 +-
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/meson-g12a-u200.dts | 29 +
arch/arm/dts/meson-g12a.dtsi | 192 +++
arch/arm/include/asm/arch-meson/clock-g12a.h | 104 ++
arch/arm/include/asm/arch-meson/g12a.h | 66 +
arch/arm/mach-meson/Kconfig | 9 +-
arch/arm/mach-meson/Makefile | 1 +
arch/arm/mach-meson/board-g12a.c | 150 ++
board/amlogic/u200/MAINTAINERS | 5 +
board/amlogic/u200/Makefile | 6 +
board/amlogic/u200/README | 128 ++
board/amlogic/u200/u200.c | 22 +
configs/u200_defconfig | 40 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 2 +-
drivers/clk/meson/Kconfig | 23 +
drivers/clk/meson/Makefile | 9 +
drivers/clk/{clk_meson_axg.c => meson/axg.c} | 0
drivers/clk/{ => meson}/clk_meson.h | 0
drivers/clk/meson/g12a.c | 315 ++++
drivers/clk/{clk_meson.c => meson/gxbb.c} | 0
drivers/pinctrl/meson/Kconfig | 4 +
drivers/pinctrl/meson/Makefile | 1 +
drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 +++++++++++++++++
drivers/pinctrl/meson/pinctrl-meson.c | 17 +-
drivers/pinctrl/meson/pinctrl-meson.h | 1 +
include/dt-bindings/clock/g12a-aoclkc.h | 34 +
include/dt-bindings/clock/g12a-clkc.h | 135 ++
include/dt-bindings/gpio/meson-g12a-gpio.h | 114 ++
.../reset/amlogic,meson-g12a-reset.h | 134 ++
include/dt-bindings/reset/g12a-aoclkc.h | 18 +
32 files changed, 2850 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/dts/meson-g12a-u200.dts
create mode 100644 arch/arm/dts/meson-g12a.dtsi
create mode 100644 arch/arm/include/asm/arch-meson/clock-g12a.h
create mode 100644 arch/arm/include/asm/arch-meson/g12a.h
create mode 100644 arch/arm/mach-meson/board-g12a.c
create mode 100644 board/amlogic/u200/MAINTAINERS
create mode 100644 board/amlogic/u200/Makefile
create mode 100644 board/amlogic/u200/README
create mode 100644 board/amlogic/u200/u200.c
create mode 100644 configs/u200_defconfig
create mode 100644 drivers/clk/meson/Kconfig
create mode 100644 drivers/clk/meson/Makefile
rename drivers/clk/{clk_meson_axg.c => meson/axg.c} (100%)
rename drivers/clk/{ => meson}/clk_meson.h (100%)
create mode 100644 drivers/clk/meson/g12a.c
rename drivers/clk/{clk_meson.c => meson/gxbb.c} (100%)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c
create mode 100644 include/dt-bindings/clock/g12a-aoclkc.h
create mode 100644 include/dt-bindings/clock/g12a-clkc.h
create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h
create mode 100644 include/dt-bindings/reset/amlogic,meson-g12a-reset.h
create mode 100644 include/dt-bindings/reset/g12a-aoclkc.h
--
2.21.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 0/6] ARM: meson: Add support for G12A based U200 board @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Neil Armstrong, u-boot This patchset adds basic support for the recent Amlogic G12A SoC family. This SoC family embeds 4xCortex A53 CPUs, and is very similar to the AXG SoC Family with the multimedia features of previous families. This patchset adds : - pinctrl support - clk driver atfer a rework of the drivers files - import Linux 5.1-rc1 G12A & U200 DT files - add board/amlogic/u200 to support the U200 reference design Jerome Brunet (5): pinctrl: meson: add g12a support clk: create meson directory and move related drivers clk: meson: add g12a support ARM: meson: add G12a support boards: meson: add g12a u200 Neil Armstrong (1): ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1 MAINTAINERS | 2 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/meson-g12a-u200.dts | 29 + arch/arm/dts/meson-g12a.dtsi | 192 +++ arch/arm/include/asm/arch-meson/clock-g12a.h | 104 ++ arch/arm/include/asm/arch-meson/g12a.h | 66 + arch/arm/mach-meson/Kconfig | 9 +- arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/board-g12a.c | 150 ++ board/amlogic/u200/MAINTAINERS | 5 + board/amlogic/u200/Makefile | 6 + board/amlogic/u200/README | 128 ++ board/amlogic/u200/u200.c | 22 + configs/u200_defconfig | 40 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 +- drivers/clk/meson/Kconfig | 23 + drivers/clk/meson/Makefile | 9 + drivers/clk/{clk_meson_axg.c => meson/axg.c} | 0 drivers/clk/{ => meson}/clk_meson.h | 0 drivers/clk/meson/g12a.c | 315 ++++ drivers/clk/{clk_meson.c => meson/gxbb.c} | 0 drivers/pinctrl/meson/Kconfig | 4 + drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 +++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson.c | 17 +- drivers/pinctrl/meson/pinctrl-meson.h | 1 + include/dt-bindings/clock/g12a-aoclkc.h | 34 + include/dt-bindings/clock/g12a-clkc.h | 135 ++ include/dt-bindings/gpio/meson-g12a-gpio.h | 114 ++ .../reset/amlogic,meson-g12a-reset.h | 134 ++ include/dt-bindings/reset/g12a-aoclkc.h | 18 + 32 files changed, 2850 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/meson-g12a-u200.dts create mode 100644 arch/arm/dts/meson-g12a.dtsi create mode 100644 arch/arm/include/asm/arch-meson/clock-g12a.h create mode 100644 arch/arm/include/asm/arch-meson/g12a.h create mode 100644 arch/arm/mach-meson/board-g12a.c create mode 100644 board/amlogic/u200/MAINTAINERS create mode 100644 board/amlogic/u200/Makefile create mode 100644 board/amlogic/u200/README create mode 100644 board/amlogic/u200/u200.c create mode 100644 configs/u200_defconfig create mode 100644 drivers/clk/meson/Kconfig create mode 100644 drivers/clk/meson/Makefile rename drivers/clk/{clk_meson_axg.c => meson/axg.c} (100%) rename drivers/clk/{ => meson}/clk_meson.h (100%) create mode 100644 drivers/clk/meson/g12a.c rename drivers/clk/{clk_meson.c => meson/gxbb.c} (100%) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c create mode 100644 include/dt-bindings/clock/g12a-aoclkc.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h create mode 100644 include/dt-bindings/reset/amlogic,meson-g12a-reset.h create mode 100644 include/dt-bindings/reset/g12a-aoclkc.h -- 2.21.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 1/6] pinctrl: meson: add g12a support 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot From: Jerome Brunet <jbrunet@baylibre.com> Add pinctrl support for the Amlogic G12A SoC, which is very similar to the Amlogic AXG support but with an additionnal drive-strength register bank. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/pinctrl/meson/Kconfig | 4 + drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 ++++++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson.c | 17 +- drivers/pinctrl/meson/pinctrl-meson.h | 1 + 5 files changed, 1312 insertions(+), 5 deletions(-) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 162642d728..ef02087ed2 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -25,4 +25,8 @@ config PINCTRL_MESON_AXG bool "Amlogic Meson AXG SoC pinctrl driver" select PINCTRL_MESON_AXG_PMX +config PINCTRL_MESON_G12A + bool "Amlogic Meson G12a SoC pinctrl driver" + select PINCTRL_MESON_AXG_PMX + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 707287cd1d..80dba65e1b 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c new file mode 100644 index 0000000000..86f1290385 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -0,0 +1,1294 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * (C) Copyright (C) 2019 Jerome Brunet <jbrunet@baylibre.com> + * + * Based on code from Linux kernel: + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + * Author: Yixun Lan <yixun.lan@amlogic.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> + +#include "pinctrl-meson-axg.h" + +#define EE_OFF 15 + +/* emmc */ +static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 }; +static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 }; +static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 }; +static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 }; +static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 }; +static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 }; +static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 }; +static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 }; +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; +static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 }; + +/* nand */ +static const unsigned int nand_wen_clk_pins[] = { BOOT_8 }; +static const unsigned int nand_ale_pins[] = { BOOT_9 }; +static const unsigned int nand_cle_pins[] = { BOOT_10 }; +static const unsigned int nand_ce0_pins[] = { BOOT_11 }; +static const unsigned int nand_ren_wr_pins[] = { BOOT_12 }; +static const unsigned int nand_rb0_pins[] = { BOOT_14 }; +static const unsigned int nand_ce1_pins[] = { BOOT_15 }; + +/* nor */ +static const unsigned int nor_hold_pins[] = { BOOT_3 }; +static const unsigned int nor_d_pins[] = { BOOT_4 }; +static const unsigned int nor_q_pins[] = { BOOT_5 }; +static const unsigned int nor_c_pins[] = { BOOT_6 }; +static const unsigned int nor_wp_pins[] = { BOOT_7 }; +static const unsigned int nor_cs_pins[] = { BOOT_14 }; + +/* sdio */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; + +/* sdcard */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; + +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; + +/* spi0 */ +static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 }; +static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 }; + +static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 }; + +/* spi1 */ +static const unsigned int spi1_mosi_pins[] = { GPIOH_4 }; +static const unsigned int spi1_miso_pins[] = { GPIOH_5 }; +static const unsigned int spi1_ss0_pins[] = { GPIOH_6 }; +static const unsigned int spi1_clk_pins[] = { GPIOH_7 }; + +/* i2c0 */ +static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 }; +static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 }; +static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 }; +static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 }; +static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 }; +static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 }; + +/* i2c1 */ +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 }; +static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 }; +static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 }; +static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 }; +static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 }; + +/* i2c2 */ +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; +static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 }; +static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 }; + +/* i2c3 */ +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 }; +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 }; +static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 }; +static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 }; + +/* uart_a */ +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; + +/* uart_b */ +static const unsigned int uart_b_tx_pins[] = { GPIOX_6 }; +static const unsigned int uart_b_rx_pins[] = { GPIOX_7 }; + +/* uart_c */ +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; + +/* uart_ao_a_c */ +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; + +/* iso7816 */ +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; + +/* eth */ +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; + +/* pwm_a */ +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; + +/* pwm_b */ +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; + +/* pwm_c */ +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; +static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 }; +static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 }; + +/* pwm_d */ +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; + +/* pwm_e */ +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; + +/* pwm_f */ +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; + +/* cec_ao */ +static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 }; +static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 }; + +/* jtag_b */ +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; + +/* bt565_a */ +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 }; +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 }; +static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 }; +static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 }; +static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 }; +static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 }; +static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 }; +static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 }; +static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 }; +static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 }; +static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 }; + +/* tsin_a */ +static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 }; +static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 }; +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 }; + +/* tsin_b */ +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 }; +static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 }; +static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 }; +static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 }; + +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 }; +static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 }; +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 }; + +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; + +/* hdmitx */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; + +/* pdm */ +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 }; +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; + +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; + +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; + +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; +static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 }; +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; +static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 }; +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 }; + +/* spdif_in */ +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; +static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 }; +static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 }; + +/* spdif_out */ +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 }; +static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 }; + +/* mclk0 */ +static const unsigned int mclk0_a_pins[] = { GPIOA_0 }; + +/* mclk1 */ +static const unsigned int mclk1_x_pins[] = { GPIOX_5 }; +static const unsigned int mclk1_z_pins[] = { GPIOZ_8 }; +static const unsigned int mclk1_a_pins[] = { GPIOA_11 }; + +/* tdm */ +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; + +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 }; +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 }; + +static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 }; +static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 }; +static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 }; +static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 }; +static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 }; +static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 }; +static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 }; +static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 }; +static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 }; +static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 }; +static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 }; +static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 }; +static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 }; +static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 }; +static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 }; +static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 }; + +static struct meson_pmx_group meson_g12a_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + GPIO_GROUP(GPIOZ_11, EE_OFF), + GPIO_GROUP(GPIOZ_12, EE_OFF), + GPIO_GROUP(GPIOZ_13, EE_OFF), + GPIO_GROUP(GPIOZ_14, EE_OFF), + GPIO_GROUP(GPIOZ_15, EE_OFF), + GPIO_GROUP(GPIOH_0, EE_OFF), + GPIO_GROUP(GPIOH_1, EE_OFF), + GPIO_GROUP(GPIOH_2, EE_OFF), + GPIO_GROUP(GPIOH_3, EE_OFF), + GPIO_GROUP(GPIOH_4, EE_OFF), + GPIO_GROUP(GPIOH_5, EE_OFF), + GPIO_GROUP(GPIOH_6, EE_OFF), + GPIO_GROUP(GPIOH_7, EE_OFF), + GPIO_GROUP(GPIOH_8, EE_OFF), + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + GPIO_GROUP(BOOT_15, EE_OFF), + GPIO_GROUP(GPIOC_0, EE_OFF), + GPIO_GROUP(GPIOC_1, EE_OFF), + GPIO_GROUP(GPIOC_2, EE_OFF), + GPIO_GROUP(GPIOC_3, EE_OFF), + GPIO_GROUP(GPIOC_4, EE_OFF), + GPIO_GROUP(GPIOC_5, EE_OFF), + GPIO_GROUP(GPIOC_6, EE_OFF), + GPIO_GROUP(GPIOC_7, EE_OFF), + GPIO_GROUP(GPIOA_0, EE_OFF), + GPIO_GROUP(GPIOA_1, EE_OFF), + GPIO_GROUP(GPIOA_2, EE_OFF), + GPIO_GROUP(GPIOA_3, EE_OFF), + GPIO_GROUP(GPIOA_4, EE_OFF), + GPIO_GROUP(GPIOA_5, EE_OFF), + GPIO_GROUP(GPIOA_6, EE_OFF), + GPIO_GROUP(GPIOA_7, EE_OFF), + GPIO_GROUP(GPIOA_8, EE_OFF), + GPIO_GROUP(GPIOA_9, EE_OFF), + GPIO_GROUP(GPIOA_10, EE_OFF), + GPIO_GROUP(GPIOA_11, EE_OFF), + GPIO_GROUP(GPIOA_12, EE_OFF), + GPIO_GROUP(GPIOA_13, EE_OFF), + GPIO_GROUP(GPIOA_14, EE_OFF), + GPIO_GROUP(GPIOA_15, EE_OFF), + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + GPIO_GROUP(GPIOX_19, EE_OFF), + + /* bank BOOT */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + GROUP(nand_ce0, 2), + GROUP(nand_ale, 2), + GROUP(nand_cle, 2), + GROUP(nand_wen_clk, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_rb0, 2), + GROUP(nand_ce1, 2), + GROUP(nor_hold, 3), + GROUP(nor_d, 3), + GROUP(nor_q, 3), + GROUP(nor_c, 3), + GROUP(nor_wp, 3), + GROUP(nor_cs, 3), + + /* bank GPIOZ */ + GROUP(sdcard_d0_z, 5), + GROUP(sdcard_d1_z, 5), + GROUP(sdcard_d2_z, 5), + GROUP(sdcard_d3_z, 5), + GROUP(sdcard_clk_z, 5), + GROUP(sdcard_cmd_z, 5), + GROUP(i2c0_sda_z0, 4), + GROUP(i2c0_sck_z1, 4), + GROUP(i2c0_sda_z7, 7), + GROUP(i2c0_sck_z8, 7), + GROUP(i2c2_sda_z, 3), + GROUP(i2c2_sck_z, 3), + GROUP(iso7816_clk_z, 3), + GROUP(iso7816_data_z, 3), + GROUP(eth_mdio, 1), + GROUP(eth_mdc, 1), + GROUP(eth_rgmii_rx_clk, 1), + GROUP(eth_rx_dv, 1), + GROUP(eth_rxd0, 1), + GROUP(eth_rxd1, 1), + GROUP(eth_rxd2_rgmii, 1), + GROUP(eth_rxd3_rgmii, 1), + GROUP(eth_rgmii_tx_clk, 1), + GROUP(eth_txen, 1), + GROUP(eth_txd0, 1), + GROUP(eth_txd1, 1), + GROUP(eth_txd2_rgmii, 1), + GROUP(eth_txd3_rgmii, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + GROUP(bt565_a_vs, 2), + GROUP(bt565_a_hs, 2), + GROUP(bt565_a_clk, 2), + GROUP(bt565_a_din0, 2), + GROUP(bt565_a_din1, 2), + GROUP(bt565_a_din2, 2), + GROUP(bt565_a_din3, 2), + GROUP(bt565_a_din4, 2), + GROUP(bt565_a_din5, 2), + GROUP(bt565_a_din6, 2), + GROUP(bt565_a_din7, 2), + GROUP(tsin_b_valid_z, 3), + GROUP(tsin_b_sop_z, 3), + GROUP(tsin_b_din0_z, 3), + GROUP(tsin_b_clk_z, 3), + GROUP(tsin_b_fail, 3), + GROUP(tsin_b_din1, 3), + GROUP(tsin_b_din2, 3), + GROUP(tsin_b_din3, 3), + GROUP(tsin_b_din4, 3), + GROUP(tsin_b_din5, 3), + GROUP(tsin_b_din6, 3), + GROUP(tsin_b_din7, 3), + GROUP(pdm_din0_z, 7), + GROUP(pdm_din1_z, 7), + GROUP(pdm_din2_z, 7), + GROUP(pdm_din3_z, 7), + GROUP(pdm_dclk_z, 7), + GROUP(tdm_c_slv_sclk_z, 6), + GROUP(tdm_c_slv_fs_z, 6), + GROUP(tdm_c_din0_z, 6), + GROUP(tdm_c_din1_z, 6), + GROUP(tdm_c_din2_z, 6), + GROUP(tdm_c_din3_z, 6), + GROUP(tdm_c_sclk_z, 4), + GROUP(tdm_c_fs_z, 4), + GROUP(tdm_c_dout0_z, 4), + GROUP(tdm_c_dout1_z, 4), + GROUP(tdm_c_dout2_z, 4), + GROUP(tdm_c_dout3_z, 4), + GROUP(mclk1_z, 4), + + /* bank GPIOX */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(spi0_mosi_x, 4), + GROUP(spi0_miso_x, 4), + GROUP(spi0_ss0_x, 4), + GROUP(spi0_clk_x, 4), + GROUP(i2c1_sda_x, 5), + GROUP(i2c1_sck_x, 5), + GROUP(i2c2_sda_x, 1), + GROUP(i2c2_sck_x, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(uart_b_tx, 2), + GROUP(uart_b_rx, 2), + GROUP(iso7816_clk_x, 6), + GROUP(iso7816_data_x, 6), + GROUP(pwm_a, 1), + GROUP(pwm_b_x7, 4), + GROUP(pwm_b_x19, 1), + GROUP(pwm_c_x5, 4), + GROUP(pwm_c_x8, 5), + GROUP(pwm_d_x3, 4), + GROUP(pwm_d_x6, 4), + GROUP(pwm_e, 1), + GROUP(pwm_f_x, 1), + GROUP(tsin_a_valid, 3), + GROUP(tsin_a_sop, 3), + GROUP(tsin_a_din0, 3), + GROUP(tsin_a_clk, 3), + GROUP(tsin_b_valid_x, 3), + GROUP(tsin_b_sop_x, 3), + GROUP(tsin_b_din0_x, 3), + GROUP(tsin_b_clk_x, 3), + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_din2_x, 2), + GROUP(pdm_din3_x, 2), + GROUP(pdm_dclk_x, 2), + GROUP(tdm_a_slv_sclk, 2), + GROUP(tdm_a_slv_fs, 2), + GROUP(tdm_a_din0, 2), + GROUP(tdm_a_din1, 2), + GROUP(tdm_a_sclk, 1), + GROUP(tdm_a_fs, 1), + GROUP(tdm_a_dout0, 1), + GROUP(tdm_a_dout1, 1), + GROUP(mclk1_x, 2), + + /* bank GPIOC */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(spi0_mosi_c, 5), + GROUP(spi0_miso_c, 5), + GROUP(spi0_ss0_c, 5), + GROUP(spi0_clk_c, 5), + GROUP(i2c0_sda_c, 3), + GROUP(i2c0_sck_c, 3), + GROUP(uart_ao_a_rx_c, 2), + GROUP(uart_ao_a_tx_c, 2), + GROUP(iso7816_clk_c, 5), + GROUP(iso7816_data_c, 5), + GROUP(pwm_c_c, 5), + GROUP(jtag_b_tdo, 2), + GROUP(jtag_b_tdi, 2), + GROUP(jtag_b_clk, 2), + GROUP(jtag_b_tms, 2), + GROUP(pdm_din0_c, 4), + GROUP(pdm_din1_c, 4), + GROUP(pdm_din2_c, 4), + GROUP(pdm_din3_c, 4), + GROUP(pdm_dclk_c, 4), + + /* bank GPIOH */ + GROUP(spi1_mosi, 3), + GROUP(spi1_miso, 3), + GROUP(spi1_ss0, 3), + GROUP(spi1_clk, 3), + GROUP(i2c1_sda_h2, 2), + GROUP(i2c1_sck_h3, 2), + GROUP(i2c1_sda_h6, 4), + GROUP(i2c1_sck_h7, 4), + GROUP(i2c3_sda_h, 2), + GROUP(i2c3_sck_h, 2), + GROUP(uart_c_tx, 2), + GROUP(uart_c_rx, 2), + GROUP(uart_c_cts, 2), + GROUP(uart_c_rts, 2), + GROUP(iso7816_clk_h, 1), + GROUP(iso7816_data_h, 1), + GROUP(pwm_f_h, 4), + GROUP(cec_ao_a_h, 4), + GROUP(cec_ao_b_h, 5), + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_sck, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in_h, 1), + GROUP(tdm_b_din3_h, 6), + GROUP(tdm_b_dout3_h, 5), + + /* bank GPIOA */ + GROUP(i2c3_sda_a, 2), + GROUP(i2c3_sck_a, 2), + GROUP(pdm_din0_a, 1), + GROUP(pdm_din1_a, 1), + GROUP(pdm_din2_a, 1), + GROUP(pdm_din3_a, 1), + GROUP(pdm_dclk_a, 1), + GROUP(spdif_in_a10, 1), + GROUP(spdif_in_a12, 1), + GROUP(spdif_out_a11, 1), + GROUP(spdif_out_a13, 1), + GROUP(tdm_b_slv_sclk, 2), + GROUP(tdm_b_slv_fs, 2), + GROUP(tdm_b_din0, 2), + GROUP(tdm_b_din1, 2), + GROUP(tdm_b_din2, 2), + GROUP(tdm_b_din3_a, 2), + GROUP(tdm_b_sclk, 1), + GROUP(tdm_b_fs, 1), + GROUP(tdm_b_dout0, 1), + GROUP(tdm_b_dout1, 1), + GROUP(tdm_b_dout2, 3), + GROUP(tdm_b_dout3_a, 3), + GROUP(tdm_c_slv_sclk_a, 3), + GROUP(tdm_c_slv_fs_a, 3), + GROUP(tdm_c_din0_a, 3), + GROUP(tdm_c_din1_a, 3), + GROUP(tdm_c_din2_a, 3), + GROUP(tdm_c_din3_a, 3), + GROUP(tdm_c_sclk_a, 2), + GROUP(tdm_c_fs_a, 2), + GROUP(tdm_c_dout0_a, 2), + GROUP(tdm_c_dout1_a, 2), + GROUP(tdm_c_dout2_a, 2), + GROUP(tdm_c_dout3_a, 2), + GROUP(mclk0_a, 1), + GROUP(mclk1_a, 2), +}; + +/* uart_ao_a */ +static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 }; +static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 }; +static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 }; + +/* uart_ao_b */ +static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 }; +static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 }; +static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 }; +static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 }; +static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 }; + +/* i2c_ao */ +static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 }; +static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 }; + +static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 }; + +/* i2c_ao_slave */ +static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 }; +static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 }; + +/* ir_in */ +static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; + +/* ir_out */ +static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; + +/* pwm_ao_a */ +static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; +static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; + +/* pwm_ao_b */ +static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 }; + +/* pwm_ao_c */ +static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 }; +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 }; +static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 }; + +/* pwm_ao_d */ +static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 }; +static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 }; +static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 }; + +/* jtag_a */ +static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 }; +static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 }; + +/* cec_ao */ +static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 }; +static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 }; + +/* tsin_ao_a */ +static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 }; +static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 }; +static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 }; +static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 }; + +/* spdif_ao_out */ +static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 }; + +/* tdm_ao_b */ +static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 }; +static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 }; +static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 }; +static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 }; +static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 }; +static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 }; +static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 }; +static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 }; +static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 }; +static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 }; + +/* mclk0_ao */ +static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 }; + +static struct meson_pmx_group meson_g12a_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_10, 0), + GPIO_GROUP(GPIOAO_11, 0), + GPIO_GROUP(GPIOE_0, 0), + GPIO_GROUP(GPIOE_1, 0), + GPIO_GROUP(GPIOE_2, 0), + + /* bank AO */ + GROUP(uart_ao_a_tx, 1), + GROUP(uart_ao_a_rx, 1), + GROUP(uart_ao_a_cts, 1), + GROUP(uart_ao_a_rts, 1), + GROUP(uart_ao_b_tx_2, 2), + GROUP(uart_ao_b_rx_3, 2), + GROUP(uart_ao_b_tx_8, 3), + GROUP(uart_ao_b_rx_9, 3), + GROUP(uart_ao_b_cts, 2), + GROUP(uart_ao_b_rts, 2), + GROUP(i2c_ao_sck, 1), + GROUP(i2c_ao_sda, 1), + GROUP(i2c_ao_sck_e, 4), + GROUP(i2c_ao_sda_e, 4), + GROUP(i2c_ao_slave_sck, 3), + GROUP(i2c_ao_slave_sda, 3), + GROUP(remote_ao_input, 1), + GROUP(remote_ao_out, 1), + GROUP(pwm_ao_a, 3), + GROUP(pwm_ao_a_hiz, 2), + GROUP(pwm_ao_b, 3), + GROUP(pwm_ao_c_4, 3), + GROUP(pwm_ao_c_hiz, 4), + GROUP(pwm_ao_c_6, 3), + GROUP(pwm_ao_d_5, 3), + GROUP(pwm_ao_d_10, 3), + GROUP(pwm_ao_d_e, 3), + GROUP(jtag_a_tdi, 1), + GROUP(jtag_a_tdo, 1), + GROUP(jtag_a_clk, 1), + GROUP(jtag_a_tms, 1), + GROUP(cec_ao_a, 1), + GROUP(cec_ao_b, 2), + GROUP(tsin_ao_asop, 4), + GROUP(tsin_ao_adin0, 4), + GROUP(tsin_ao_aclk, 4), + GROUP(tsin_ao_a_valid, 4), + GROUP(spdif_ao_out, 4), + GROUP(tdm_ao_b_dout0, 5), + GROUP(tdm_ao_b_dout1, 5), + GROUP(tdm_ao_b_dout2, 5), + GROUP(tdm_ao_b_fs, 5), + GROUP(tdm_ao_b_sclk, 5), + GROUP(tdm_ao_b_din0, 6), + GROUP(tdm_ao_b_din1, 6), + GROUP(tdm_ao_b_din2, 6), + GROUP(tdm_ao_b_slv_fs, 6), + GROUP(tdm_ao_b_slv_sclk, 6), + GROUP(mclk0_ao, 5), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", + "GPIOZ_15", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", "GPIOC_7", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", + "GPIOA_15", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "nand_ce0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_rb0", + "emmc_nand_ds", "nand_ce1", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", + "nor_hold", "nor_wp", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", "sdio_dummy", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcard_clk_c", "sdcard_cmd_c", + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const spi0_groups[] = { + "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c", + "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x", +}; + +static const char * const spi1_groups[] = { + "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda_c", "i2c0_sck_c", + "i2c0_sda_z0", "i2c0_sck_z1", + "i2c0_sda_z7", "i2c0_sck_z8", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_x", "i2c1_sck_x", + "i2c1_sda_h2", "i2c1_sck_h3", + "i2c1_sda_h6", "i2c1_sck_h7", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda_x", "i2c2_sck_x", + "i2c2_sda_z", "i2c2_sck_z", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_h", "i2c3_sck_h", + "i2c3_sda_a", "i2c3_sck_a", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx", "uart_b_rx", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", +}; + +static const char * const uart_ao_a_c_groups[] = { + "uart_ao_a_rx_c", "uart_ao_a_tx_c", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_data_c", + "iso7816_clk_x", "iso7816_data_x", + "iso7816_clk_h", "iso7816_data_h", + "iso7816_clk_z", "iso7816_data_z", +}; + +static const char * const eth_groups[] = { + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", + "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc", + "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio", + "eth_link_led", "eth_act_led", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_x7", "pwm_b_x19", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_c", "pwm_c_x5", "pwm_c_x8", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_x3", "pwm_d_x6", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_h", +}; + +static const char * const cec_ao_a_h_groups[] = { + "cec_ao_a_h", +}; + +static const char * const cec_ao_b_h_groups[] = { + "cec_ao_b_h", +}; + +static const char * const jtag_b_groups[] = { + "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", +}; + +static const char * const bt565_a_groups[] = { + "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", + "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", + "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", + "bt565_a_din6", "bt565_a_din7", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_valid", "tsin_a_sop", "tsin_a_din0", + "tsin_a_clk", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x", + "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z", + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", +}; + +static const char * const pdm_groups[] = { + "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c", + "pdm_dclk_c", + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", + "pdm_dclk_x", + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", + "pdm_dclk_z", + "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a", + "pdm_dclk_a", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_h", "spdif_in_a10", "spdif_in_a12", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", "spdif_out_a11", "spdif_out_a13", +}; + +static const char * const mclk0_groups[] = { + "mclk0_a", +}; + +static const char * const mclk1_groups[] = { + "mclk1_x", "mclk1_z", "mclk1_a", +}; + +static const char * const tdm_a_groups[] = { + "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs", + "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1", +}; + +static const char * const tdm_b_groups[] = { + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs", + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", + "tdm_b_din3_a", "tdm_b_din3_h", + "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2", + "tdm_b_dout3_a", "tdm_b_dout3_h", +}; + +static const char * const tdm_c_groups[] = { + "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a", + "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z", + "tdm_c_sclk_a", "tdm_c_fs_a", + "tdm_c_sclk_z", "tdm_c_fs_z", + "tdm_c_din0_a", "tdm_c_din1_a", + "tdm_c_din2_a", "tdm_c_din3_a", + "tdm_c_din0_z", "tdm_c_din1_z", + "tdm_c_din2_z", "tdm_c_din3_z", + "tdm_c_dout0_a", "tdm_c_dout1_a", + "tdm_c_dout2_a", "tdm_c_dout3_a", + "tdm_c_dout0_z", "tdm_c_dout1_z", + "tdm_c_dout2_z", "tdm_c_dout3_z", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2", +}; + +static const char * const uart_ao_a_groups[] = { + "uart_ao_a_tx", "uart_ao_a_rx", + "uart_ao_a_cts", "uart_ao_a_rts", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_ao_b_tx_2", "uart_ao_b_rx_3", + "uart_ao_b_tx_8", "uart_ao_b_rx_9", + "uart_ao_b_cts", "uart_ao_b_rts", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_ao_sck", "i2c_ao_sda", + "i2c_ao_sck_e", "i2c_ao_sda_e", +}; + +static const char * const i2c_ao_slave_groups[] = { + "i2c_ao_slave_sck", "i2c_ao_slave_sda", +}; + +static const char * const remote_ao_input_groups[] = { + "remote_ao_input", +}; + +static const char * const remote_ao_out_groups[] = { + "remote_ao_out", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a", "pwm_ao_a_hiz", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", +}; + +static const char * const pwm_ao_c_groups[] = { + "pwm_ao_c_4", "pwm_ao_c_hiz", + "pwm_ao_c_6", +}; + +static const char * const pwm_ao_d_groups[] = { + "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms", +}; + +static const char * const cec_ao_a_groups[] = { + "cec_ao_a", +}; + +static const char * const cec_ao_b_groups[] = { + "cec_ao_b", +}; + +static const char * const tsin_ao_a_groups[] = { + "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid", +}; + +static const char * const spdif_ao_out_groups[] = { + "spdif_ao_out", +}; + +static const char * const tdm_ao_b_groups[] = { + "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2", + "tdm_ao_b_fs", "tdm_ao_b_sclk", + "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2", + "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk", +}; + +static const char * const mclk0_ao_groups[] = { + "mclk0_ao", +}; + +static struct meson_pmx_func meson_g12a_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi0), + FUNCTION(spi1), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(sdcard), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_ao_a_c), + FUNCTION(iso7816), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(cec_ao_a_h), + FUNCTION(cec_ao_b_h), + FUNCTION(jtag_b), + FUNCTION(bt565_a), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(hdmitx), + FUNCTION(pdm), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(mclk0), + FUNCTION(mclk1), + FUNCTION(tdm_a), + FUNCTION(tdm_b), + FUNCTION(tdm_c), +}; + +static struct meson_pmx_func meson_g12a_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao_a), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_ao_slave), + FUNCTION(remote_ao_input), + FUNCTION(remote_ao_out), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(pwm_ao_c), + FUNCTION(pwm_ao_d), + FUNCTION(jtag_a), + FUNCTION(cec_ao_a), + FUNCTION(cec_ao_b), + FUNCTION(tsin_ao_a), + FUNCTION(spdif_ao_out), + FUNCTION(tdm_ao_b), + FUNCTION(mclk0_ao), +}; + +static struct meson_bank meson_g12a_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), +}; + +static struct meson_bank meson_g12a_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_11, 0), 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), + BANK("E", PIN(GPIOE_0, 0), PIN(GPIOE_2, 0), 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), +}; + +static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { + /* name first lask reg offset */ + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), + BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), +}; + +static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = { + .pmx_banks = meson_g12a_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks), +}; + +static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = { + BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0), + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16), +}; + +static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { + .pmx_banks = meson_g12a_aobus_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks), +}; + +static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = EE_OFF, + .groups = meson_g12a_periphs_groups, + .funcs = meson_g12a_periphs_functions, + .banks = meson_g12a_periphs_banks, + .num_pins = 85, + .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), + .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_g12a_periphs_pmx_banks_data, +}; + +static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_g12a_aobus_groups, + .funcs = meson_g12a_aobus_functions, + .banks = meson_g12a_aobus_banks, + .num_pins = 15, + .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), + .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_g12a_aobus_pmx_banks_data, +}; + +static const struct udevice_id meson_g12a_pinctrl_match[] = { + { + .compatible = "amlogic,meson-g12a-periphs-pinctrl", + .data = (ulong)&meson_g12a_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-g12a-aobus-pinctrl", + .data = (ulong)&meson_g12a_aobus_pinctrl_data, + }, + { }, +}; + +U_BOOT_DRIVER(meson_axg_pinctrl) = { + .name = "meson-g12a-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_g12a_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index fa3d78858a..8735418c5b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -314,11 +314,11 @@ int meson_pinctrl_probe(struct udevice *dev) priv->reg_gpio = (void __iomem *)addr; addr = parse_address(gpio, "pull", na, ns); - if (addr == FDT_ADDR_T_NONE) { - debug("pull address not found\n"); - return -EINVAL; - } - priv->reg_pull = (void __iomem *)addr; + /* Use gpio region if pull one is not present */ + if (addr == FDT_ADDR_T_NONE) + priv->reg_pull = priv->reg_gpio; + else + priv->reg_pull = (void __iomem *)addr; addr = parse_address(gpio, "pull-enable", na, ns); /* Use pull region if pull-enable one is not present */ @@ -327,6 +327,13 @@ int meson_pinctrl_probe(struct udevice *dev) else priv->reg_pullen = (void __iomem *)addr; + addr = parse_address(gpio, "ds", na, ns); + /* Drive strength region is optional */ + if (addr == FDT_ADDR_T_NONE) + priv->reg_ds = NULL; + else + priv->reg_ds = (void __iomem *)addr; + priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev); /* Lookup GPIO driver */ diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 28085a7495..b3683e2073 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -41,6 +41,7 @@ struct meson_pinctrl { void __iomem *reg_gpio; void __iomem *reg_pull; void __iomem *reg_pullen; + void __iomem *reg_ds; }; /** -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/6] pinctrl: meson: add g12a support @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, sjg, Neil Armstrong From: Jerome Brunet <jbrunet@baylibre.com> Add pinctrl support for the Amlogic G12A SoC, which is very similar to the Amlogic AXG support but with an additionnal drive-strength register bank. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/pinctrl/meson/Kconfig | 4 + drivers/pinctrl/meson/Makefile | 1 + drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 ++++++++++++++++++++ drivers/pinctrl/meson/pinctrl-meson.c | 17 +- drivers/pinctrl/meson/pinctrl-meson.h | 1 + 5 files changed, 1312 insertions(+), 5 deletions(-) create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 162642d728..ef02087ed2 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -25,4 +25,8 @@ config PINCTRL_MESON_AXG bool "Amlogic Meson AXG SoC pinctrl driver" select PINCTRL_MESON_AXG_PMX +config PINCTRL_MESON_G12A + bool "Amlogic Meson G12a SoC pinctrl driver" + select PINCTRL_MESON_AXG_PMX + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 707287cd1d..80dba65e1b 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c new file mode 100644 index 0000000000..86f1290385 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -0,0 +1,1294 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * (C) Copyright (C) 2019 Jerome Brunet <jbrunet@baylibre.com> + * + * Based on code from Linux kernel: + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + * Author: Yixun Lan <yixun.lan@amlogic.com> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> + +#include "pinctrl-meson-axg.h" + +#define EE_OFF 15 + +/* emmc */ +static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 }; +static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 }; +static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 }; +static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 }; +static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 }; +static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 }; +static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 }; +static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 }; +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; +static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 }; + +/* nand */ +static const unsigned int nand_wen_clk_pins[] = { BOOT_8 }; +static const unsigned int nand_ale_pins[] = { BOOT_9 }; +static const unsigned int nand_cle_pins[] = { BOOT_10 }; +static const unsigned int nand_ce0_pins[] = { BOOT_11 }; +static const unsigned int nand_ren_wr_pins[] = { BOOT_12 }; +static const unsigned int nand_rb0_pins[] = { BOOT_14 }; +static const unsigned int nand_ce1_pins[] = { BOOT_15 }; + +/* nor */ +static const unsigned int nor_hold_pins[] = { BOOT_3 }; +static const unsigned int nor_d_pins[] = { BOOT_4 }; +static const unsigned int nor_q_pins[] = { BOOT_5 }; +static const unsigned int nor_c_pins[] = { BOOT_6 }; +static const unsigned int nor_wp_pins[] = { BOOT_7 }; +static const unsigned int nor_cs_pins[] = { BOOT_14 }; + +/* sdio */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; + +/* sdcard */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; + +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; + +/* spi0 */ +static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 }; +static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 }; + +static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 }; + +/* spi1 */ +static const unsigned int spi1_mosi_pins[] = { GPIOH_4 }; +static const unsigned int spi1_miso_pins[] = { GPIOH_5 }; +static const unsigned int spi1_ss0_pins[] = { GPIOH_6 }; +static const unsigned int spi1_clk_pins[] = { GPIOH_7 }; + +/* i2c0 */ +static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 }; +static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 }; +static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 }; +static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 }; +static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 }; +static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 }; + +/* i2c1 */ +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 }; +static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 }; +static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 }; +static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 }; +static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 }; + +/* i2c2 */ +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; +static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 }; +static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 }; + +/* i2c3 */ +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 }; +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 }; +static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 }; +static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 }; + +/* uart_a */ +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; + +/* uart_b */ +static const unsigned int uart_b_tx_pins[] = { GPIOX_6 }; +static const unsigned int uart_b_rx_pins[] = { GPIOX_7 }; + +/* uart_c */ +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; + +/* uart_ao_a_c */ +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; + +/* iso7816 */ +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; + +/* eth */ +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; + +/* pwm_a */ +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; + +/* pwm_b */ +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; + +/* pwm_c */ +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; +static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 }; +static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 }; + +/* pwm_d */ +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; + +/* pwm_e */ +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; + +/* pwm_f */ +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; + +/* cec_ao */ +static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 }; +static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 }; + +/* jtag_b */ +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; + +/* bt565_a */ +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 }; +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 }; +static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 }; +static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 }; +static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 }; +static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 }; +static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 }; +static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 }; +static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 }; +static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 }; +static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 }; + +/* tsin_a */ +static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 }; +static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 }; +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 }; + +/* tsin_b */ +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 }; +static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 }; +static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 }; +static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 }; + +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 }; +static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 }; +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 }; + +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; + +/* hdmitx */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; + +/* pdm */ +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 }; +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; + +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; + +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; + +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; +static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 }; +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; +static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 }; +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 }; + +/* spdif_in */ +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; +static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 }; +static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 }; + +/* spdif_out */ +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 }; +static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 }; + +/* mclk0 */ +static const unsigned int mclk0_a_pins[] = { GPIOA_0 }; + +/* mclk1 */ +static const unsigned int mclk1_x_pins[] = { GPIOX_5 }; +static const unsigned int mclk1_z_pins[] = { GPIOZ_8 }; +static const unsigned int mclk1_a_pins[] = { GPIOA_11 }; + +/* tdm */ +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; + +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 }; +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 }; + +static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 }; +static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 }; +static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 }; +static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 }; +static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 }; +static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 }; +static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 }; +static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 }; +static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 }; +static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 }; +static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 }; +static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 }; +static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 }; +static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 }; +static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 }; +static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 }; + +static struct meson_pmx_group meson_g12a_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + GPIO_GROUP(GPIOZ_11, EE_OFF), + GPIO_GROUP(GPIOZ_12, EE_OFF), + GPIO_GROUP(GPIOZ_13, EE_OFF), + GPIO_GROUP(GPIOZ_14, EE_OFF), + GPIO_GROUP(GPIOZ_15, EE_OFF), + GPIO_GROUP(GPIOH_0, EE_OFF), + GPIO_GROUP(GPIOH_1, EE_OFF), + GPIO_GROUP(GPIOH_2, EE_OFF), + GPIO_GROUP(GPIOH_3, EE_OFF), + GPIO_GROUP(GPIOH_4, EE_OFF), + GPIO_GROUP(GPIOH_5, EE_OFF), + GPIO_GROUP(GPIOH_6, EE_OFF), + GPIO_GROUP(GPIOH_7, EE_OFF), + GPIO_GROUP(GPIOH_8, EE_OFF), + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + GPIO_GROUP(BOOT_15, EE_OFF), + GPIO_GROUP(GPIOC_0, EE_OFF), + GPIO_GROUP(GPIOC_1, EE_OFF), + GPIO_GROUP(GPIOC_2, EE_OFF), + GPIO_GROUP(GPIOC_3, EE_OFF), + GPIO_GROUP(GPIOC_4, EE_OFF), + GPIO_GROUP(GPIOC_5, EE_OFF), + GPIO_GROUP(GPIOC_6, EE_OFF), + GPIO_GROUP(GPIOC_7, EE_OFF), + GPIO_GROUP(GPIOA_0, EE_OFF), + GPIO_GROUP(GPIOA_1, EE_OFF), + GPIO_GROUP(GPIOA_2, EE_OFF), + GPIO_GROUP(GPIOA_3, EE_OFF), + GPIO_GROUP(GPIOA_4, EE_OFF), + GPIO_GROUP(GPIOA_5, EE_OFF), + GPIO_GROUP(GPIOA_6, EE_OFF), + GPIO_GROUP(GPIOA_7, EE_OFF), + GPIO_GROUP(GPIOA_8, EE_OFF), + GPIO_GROUP(GPIOA_9, EE_OFF), + GPIO_GROUP(GPIOA_10, EE_OFF), + GPIO_GROUP(GPIOA_11, EE_OFF), + GPIO_GROUP(GPIOA_12, EE_OFF), + GPIO_GROUP(GPIOA_13, EE_OFF), + GPIO_GROUP(GPIOA_14, EE_OFF), + GPIO_GROUP(GPIOA_15, EE_OFF), + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + GPIO_GROUP(GPIOX_19, EE_OFF), + + /* bank BOOT */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + GROUP(nand_ce0, 2), + GROUP(nand_ale, 2), + GROUP(nand_cle, 2), + GROUP(nand_wen_clk, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_rb0, 2), + GROUP(nand_ce1, 2), + GROUP(nor_hold, 3), + GROUP(nor_d, 3), + GROUP(nor_q, 3), + GROUP(nor_c, 3), + GROUP(nor_wp, 3), + GROUP(nor_cs, 3), + + /* bank GPIOZ */ + GROUP(sdcard_d0_z, 5), + GROUP(sdcard_d1_z, 5), + GROUP(sdcard_d2_z, 5), + GROUP(sdcard_d3_z, 5), + GROUP(sdcard_clk_z, 5), + GROUP(sdcard_cmd_z, 5), + GROUP(i2c0_sda_z0, 4), + GROUP(i2c0_sck_z1, 4), + GROUP(i2c0_sda_z7, 7), + GROUP(i2c0_sck_z8, 7), + GROUP(i2c2_sda_z, 3), + GROUP(i2c2_sck_z, 3), + GROUP(iso7816_clk_z, 3), + GROUP(iso7816_data_z, 3), + GROUP(eth_mdio, 1), + GROUP(eth_mdc, 1), + GROUP(eth_rgmii_rx_clk, 1), + GROUP(eth_rx_dv, 1), + GROUP(eth_rxd0, 1), + GROUP(eth_rxd1, 1), + GROUP(eth_rxd2_rgmii, 1), + GROUP(eth_rxd3_rgmii, 1), + GROUP(eth_rgmii_tx_clk, 1), + GROUP(eth_txen, 1), + GROUP(eth_txd0, 1), + GROUP(eth_txd1, 1), + GROUP(eth_txd2_rgmii, 1), + GROUP(eth_txd3_rgmii, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + GROUP(bt565_a_vs, 2), + GROUP(bt565_a_hs, 2), + GROUP(bt565_a_clk, 2), + GROUP(bt565_a_din0, 2), + GROUP(bt565_a_din1, 2), + GROUP(bt565_a_din2, 2), + GROUP(bt565_a_din3, 2), + GROUP(bt565_a_din4, 2), + GROUP(bt565_a_din5, 2), + GROUP(bt565_a_din6, 2), + GROUP(bt565_a_din7, 2), + GROUP(tsin_b_valid_z, 3), + GROUP(tsin_b_sop_z, 3), + GROUP(tsin_b_din0_z, 3), + GROUP(tsin_b_clk_z, 3), + GROUP(tsin_b_fail, 3), + GROUP(tsin_b_din1, 3), + GROUP(tsin_b_din2, 3), + GROUP(tsin_b_din3, 3), + GROUP(tsin_b_din4, 3), + GROUP(tsin_b_din5, 3), + GROUP(tsin_b_din6, 3), + GROUP(tsin_b_din7, 3), + GROUP(pdm_din0_z, 7), + GROUP(pdm_din1_z, 7), + GROUP(pdm_din2_z, 7), + GROUP(pdm_din3_z, 7), + GROUP(pdm_dclk_z, 7), + GROUP(tdm_c_slv_sclk_z, 6), + GROUP(tdm_c_slv_fs_z, 6), + GROUP(tdm_c_din0_z, 6), + GROUP(tdm_c_din1_z, 6), + GROUP(tdm_c_din2_z, 6), + GROUP(tdm_c_din3_z, 6), + GROUP(tdm_c_sclk_z, 4), + GROUP(tdm_c_fs_z, 4), + GROUP(tdm_c_dout0_z, 4), + GROUP(tdm_c_dout1_z, 4), + GROUP(tdm_c_dout2_z, 4), + GROUP(tdm_c_dout3_z, 4), + GROUP(mclk1_z, 4), + + /* bank GPIOX */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(spi0_mosi_x, 4), + GROUP(spi0_miso_x, 4), + GROUP(spi0_ss0_x, 4), + GROUP(spi0_clk_x, 4), + GROUP(i2c1_sda_x, 5), + GROUP(i2c1_sck_x, 5), + GROUP(i2c2_sda_x, 1), + GROUP(i2c2_sck_x, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(uart_b_tx, 2), + GROUP(uart_b_rx, 2), + GROUP(iso7816_clk_x, 6), + GROUP(iso7816_data_x, 6), + GROUP(pwm_a, 1), + GROUP(pwm_b_x7, 4), + GROUP(pwm_b_x19, 1), + GROUP(pwm_c_x5, 4), + GROUP(pwm_c_x8, 5), + GROUP(pwm_d_x3, 4), + GROUP(pwm_d_x6, 4), + GROUP(pwm_e, 1), + GROUP(pwm_f_x, 1), + GROUP(tsin_a_valid, 3), + GROUP(tsin_a_sop, 3), + GROUP(tsin_a_din0, 3), + GROUP(tsin_a_clk, 3), + GROUP(tsin_b_valid_x, 3), + GROUP(tsin_b_sop_x, 3), + GROUP(tsin_b_din0_x, 3), + GROUP(tsin_b_clk_x, 3), + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_din2_x, 2), + GROUP(pdm_din3_x, 2), + GROUP(pdm_dclk_x, 2), + GROUP(tdm_a_slv_sclk, 2), + GROUP(tdm_a_slv_fs, 2), + GROUP(tdm_a_din0, 2), + GROUP(tdm_a_din1, 2), + GROUP(tdm_a_sclk, 1), + GROUP(tdm_a_fs, 1), + GROUP(tdm_a_dout0, 1), + GROUP(tdm_a_dout1, 1), + GROUP(mclk1_x, 2), + + /* bank GPIOC */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(spi0_mosi_c, 5), + GROUP(spi0_miso_c, 5), + GROUP(spi0_ss0_c, 5), + GROUP(spi0_clk_c, 5), + GROUP(i2c0_sda_c, 3), + GROUP(i2c0_sck_c, 3), + GROUP(uart_ao_a_rx_c, 2), + GROUP(uart_ao_a_tx_c, 2), + GROUP(iso7816_clk_c, 5), + GROUP(iso7816_data_c, 5), + GROUP(pwm_c_c, 5), + GROUP(jtag_b_tdo, 2), + GROUP(jtag_b_tdi, 2), + GROUP(jtag_b_clk, 2), + GROUP(jtag_b_tms, 2), + GROUP(pdm_din0_c, 4), + GROUP(pdm_din1_c, 4), + GROUP(pdm_din2_c, 4), + GROUP(pdm_din3_c, 4), + GROUP(pdm_dclk_c, 4), + + /* bank GPIOH */ + GROUP(spi1_mosi, 3), + GROUP(spi1_miso, 3), + GROUP(spi1_ss0, 3), + GROUP(spi1_clk, 3), + GROUP(i2c1_sda_h2, 2), + GROUP(i2c1_sck_h3, 2), + GROUP(i2c1_sda_h6, 4), + GROUP(i2c1_sck_h7, 4), + GROUP(i2c3_sda_h, 2), + GROUP(i2c3_sck_h, 2), + GROUP(uart_c_tx, 2), + GROUP(uart_c_rx, 2), + GROUP(uart_c_cts, 2), + GROUP(uart_c_rts, 2), + GROUP(iso7816_clk_h, 1), + GROUP(iso7816_data_h, 1), + GROUP(pwm_f_h, 4), + GROUP(cec_ao_a_h, 4), + GROUP(cec_ao_b_h, 5), + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_sck, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in_h, 1), + GROUP(tdm_b_din3_h, 6), + GROUP(tdm_b_dout3_h, 5), + + /* bank GPIOA */ + GROUP(i2c3_sda_a, 2), + GROUP(i2c3_sck_a, 2), + GROUP(pdm_din0_a, 1), + GROUP(pdm_din1_a, 1), + GROUP(pdm_din2_a, 1), + GROUP(pdm_din3_a, 1), + GROUP(pdm_dclk_a, 1), + GROUP(spdif_in_a10, 1), + GROUP(spdif_in_a12, 1), + GROUP(spdif_out_a11, 1), + GROUP(spdif_out_a13, 1), + GROUP(tdm_b_slv_sclk, 2), + GROUP(tdm_b_slv_fs, 2), + GROUP(tdm_b_din0, 2), + GROUP(tdm_b_din1, 2), + GROUP(tdm_b_din2, 2), + GROUP(tdm_b_din3_a, 2), + GROUP(tdm_b_sclk, 1), + GROUP(tdm_b_fs, 1), + GROUP(tdm_b_dout0, 1), + GROUP(tdm_b_dout1, 1), + GROUP(tdm_b_dout2, 3), + GROUP(tdm_b_dout3_a, 3), + GROUP(tdm_c_slv_sclk_a, 3), + GROUP(tdm_c_slv_fs_a, 3), + GROUP(tdm_c_din0_a, 3), + GROUP(tdm_c_din1_a, 3), + GROUP(tdm_c_din2_a, 3), + GROUP(tdm_c_din3_a, 3), + GROUP(tdm_c_sclk_a, 2), + GROUP(tdm_c_fs_a, 2), + GROUP(tdm_c_dout0_a, 2), + GROUP(tdm_c_dout1_a, 2), + GROUP(tdm_c_dout2_a, 2), + GROUP(tdm_c_dout3_a, 2), + GROUP(mclk0_a, 1), + GROUP(mclk1_a, 2), +}; + +/* uart_ao_a */ +static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 }; +static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 }; +static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 }; + +/* uart_ao_b */ +static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 }; +static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 }; +static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 }; +static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 }; +static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 }; + +/* i2c_ao */ +static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 }; +static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 }; + +static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 }; + +/* i2c_ao_slave */ +static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 }; +static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 }; + +/* ir_in */ +static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; + +/* ir_out */ +static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; + +/* pwm_ao_a */ +static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; +static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; + +/* pwm_ao_b */ +static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 }; + +/* pwm_ao_c */ +static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 }; +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 }; +static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 }; + +/* pwm_ao_d */ +static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 }; +static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 }; +static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 }; + +/* jtag_a */ +static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 }; +static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 }; + +/* cec_ao */ +static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 }; +static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 }; + +/* tsin_ao_a */ +static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 }; +static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 }; +static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 }; +static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 }; + +/* spdif_ao_out */ +static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 }; + +/* tdm_ao_b */ +static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 }; +static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 }; +static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 }; +static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 }; +static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 }; +static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 }; +static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 }; +static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 }; +static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 }; +static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 }; + +/* mclk0_ao */ +static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 }; + +static struct meson_pmx_group meson_g12a_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_10, 0), + GPIO_GROUP(GPIOAO_11, 0), + GPIO_GROUP(GPIOE_0, 0), + GPIO_GROUP(GPIOE_1, 0), + GPIO_GROUP(GPIOE_2, 0), + + /* bank AO */ + GROUP(uart_ao_a_tx, 1), + GROUP(uart_ao_a_rx, 1), + GROUP(uart_ao_a_cts, 1), + GROUP(uart_ao_a_rts, 1), + GROUP(uart_ao_b_tx_2, 2), + GROUP(uart_ao_b_rx_3, 2), + GROUP(uart_ao_b_tx_8, 3), + GROUP(uart_ao_b_rx_9, 3), + GROUP(uart_ao_b_cts, 2), + GROUP(uart_ao_b_rts, 2), + GROUP(i2c_ao_sck, 1), + GROUP(i2c_ao_sda, 1), + GROUP(i2c_ao_sck_e, 4), + GROUP(i2c_ao_sda_e, 4), + GROUP(i2c_ao_slave_sck, 3), + GROUP(i2c_ao_slave_sda, 3), + GROUP(remote_ao_input, 1), + GROUP(remote_ao_out, 1), + GROUP(pwm_ao_a, 3), + GROUP(pwm_ao_a_hiz, 2), + GROUP(pwm_ao_b, 3), + GROUP(pwm_ao_c_4, 3), + GROUP(pwm_ao_c_hiz, 4), + GROUP(pwm_ao_c_6, 3), + GROUP(pwm_ao_d_5, 3), + GROUP(pwm_ao_d_10, 3), + GROUP(pwm_ao_d_e, 3), + GROUP(jtag_a_tdi, 1), + GROUP(jtag_a_tdo, 1), + GROUP(jtag_a_clk, 1), + GROUP(jtag_a_tms, 1), + GROUP(cec_ao_a, 1), + GROUP(cec_ao_b, 2), + GROUP(tsin_ao_asop, 4), + GROUP(tsin_ao_adin0, 4), + GROUP(tsin_ao_aclk, 4), + GROUP(tsin_ao_a_valid, 4), + GROUP(spdif_ao_out, 4), + GROUP(tdm_ao_b_dout0, 5), + GROUP(tdm_ao_b_dout1, 5), + GROUP(tdm_ao_b_dout2, 5), + GROUP(tdm_ao_b_fs, 5), + GROUP(tdm_ao_b_sclk, 5), + GROUP(tdm_ao_b_din0, 6), + GROUP(tdm_ao_b_din1, 6), + GROUP(tdm_ao_b_din2, 6), + GROUP(tdm_ao_b_slv_fs, 6), + GROUP(tdm_ao_b_slv_sclk, 6), + GROUP(mclk0_ao, 5), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", + "GPIOZ_15", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", "GPIOC_7", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", + "GPIOA_15", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", + "emmc_nand_d6", "emmc_nand_d7", + "nand_ce0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_rb0", + "emmc_nand_ds", "nand_ce1", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", + "nor_hold", "nor_wp", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", "sdio_dummy", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcard_clk_c", "sdcard_cmd_c", + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const spi0_groups[] = { + "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c", + "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x", +}; + +static const char * const spi1_groups[] = { + "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda_c", "i2c0_sck_c", + "i2c0_sda_z0", "i2c0_sck_z1", + "i2c0_sda_z7", "i2c0_sck_z8", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_x", "i2c1_sck_x", + "i2c1_sda_h2", "i2c1_sck_h3", + "i2c1_sda_h6", "i2c1_sck_h7", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda_x", "i2c2_sck_x", + "i2c2_sda_z", "i2c2_sck_z", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_h", "i2c3_sck_h", + "i2c3_sda_a", "i2c3_sck_a", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx", "uart_b_rx", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", +}; + +static const char * const uart_ao_a_c_groups[] = { + "uart_ao_a_rx_c", "uart_ao_a_tx_c", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_data_c", + "iso7816_clk_x", "iso7816_data_x", + "iso7816_clk_h", "iso7816_data_h", + "iso7816_clk_z", "iso7816_data_z", +}; + +static const char * const eth_groups[] = { + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", + "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc", + "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio", + "eth_link_led", "eth_act_led", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_x7", "pwm_b_x19", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_c", "pwm_c_x5", "pwm_c_x8", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_x3", "pwm_d_x6", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_h", +}; + +static const char * const cec_ao_a_h_groups[] = { + "cec_ao_a_h", +}; + +static const char * const cec_ao_b_h_groups[] = { + "cec_ao_b_h", +}; + +static const char * const jtag_b_groups[] = { + "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", +}; + +static const char * const bt565_a_groups[] = { + "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", + "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", + "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", + "bt565_a_din6", "bt565_a_din7", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_valid", "tsin_a_sop", "tsin_a_din0", + "tsin_a_clk", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x", + "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z", + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", +}; + +static const char * const pdm_groups[] = { + "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c", + "pdm_dclk_c", + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", + "pdm_dclk_x", + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", + "pdm_dclk_z", + "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a", + "pdm_dclk_a", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_h", "spdif_in_a10", "spdif_in_a12", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", "spdif_out_a11", "spdif_out_a13", +}; + +static const char * const mclk0_groups[] = { + "mclk0_a", +}; + +static const char * const mclk1_groups[] = { + "mclk1_x", "mclk1_z", "mclk1_a", +}; + +static const char * const tdm_a_groups[] = { + "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs", + "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1", +}; + +static const char * const tdm_b_groups[] = { + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs", + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", + "tdm_b_din3_a", "tdm_b_din3_h", + "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2", + "tdm_b_dout3_a", "tdm_b_dout3_h", +}; + +static const char * const tdm_c_groups[] = { + "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a", + "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z", + "tdm_c_sclk_a", "tdm_c_fs_a", + "tdm_c_sclk_z", "tdm_c_fs_z", + "tdm_c_din0_a", "tdm_c_din1_a", + "tdm_c_din2_a", "tdm_c_din3_a", + "tdm_c_din0_z", "tdm_c_din1_z", + "tdm_c_din2_z", "tdm_c_din3_z", + "tdm_c_dout0_a", "tdm_c_dout1_a", + "tdm_c_dout2_a", "tdm_c_dout3_a", + "tdm_c_dout0_z", "tdm_c_dout1_z", + "tdm_c_dout2_z", "tdm_c_dout3_z", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2", +}; + +static const char * const uart_ao_a_groups[] = { + "uart_ao_a_tx", "uart_ao_a_rx", + "uart_ao_a_cts", "uart_ao_a_rts", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_ao_b_tx_2", "uart_ao_b_rx_3", + "uart_ao_b_tx_8", "uart_ao_b_rx_9", + "uart_ao_b_cts", "uart_ao_b_rts", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_ao_sck", "i2c_ao_sda", + "i2c_ao_sck_e", "i2c_ao_sda_e", +}; + +static const char * const i2c_ao_slave_groups[] = { + "i2c_ao_slave_sck", "i2c_ao_slave_sda", +}; + +static const char * const remote_ao_input_groups[] = { + "remote_ao_input", +}; + +static const char * const remote_ao_out_groups[] = { + "remote_ao_out", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a", "pwm_ao_a_hiz", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", +}; + +static const char * const pwm_ao_c_groups[] = { + "pwm_ao_c_4", "pwm_ao_c_hiz", + "pwm_ao_c_6", +}; + +static const char * const pwm_ao_d_groups[] = { + "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms", +}; + +static const char * const cec_ao_a_groups[] = { + "cec_ao_a", +}; + +static const char * const cec_ao_b_groups[] = { + "cec_ao_b", +}; + +static const char * const tsin_ao_a_groups[] = { + "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid", +}; + +static const char * const spdif_ao_out_groups[] = { + "spdif_ao_out", +}; + +static const char * const tdm_ao_b_groups[] = { + "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2", + "tdm_ao_b_fs", "tdm_ao_b_sclk", + "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2", + "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk", +}; + +static const char * const mclk0_ao_groups[] = { + "mclk0_ao", +}; + +static struct meson_pmx_func meson_g12a_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi0), + FUNCTION(spi1), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(sdcard), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_ao_a_c), + FUNCTION(iso7816), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(cec_ao_a_h), + FUNCTION(cec_ao_b_h), + FUNCTION(jtag_b), + FUNCTION(bt565_a), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(hdmitx), + FUNCTION(pdm), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(mclk0), + FUNCTION(mclk1), + FUNCTION(tdm_a), + FUNCTION(tdm_b), + FUNCTION(tdm_c), +}; + +static struct meson_pmx_func meson_g12a_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao_a), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_ao_slave), + FUNCTION(remote_ao_input), + FUNCTION(remote_ao_out), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(pwm_ao_c), + FUNCTION(pwm_ao_d), + FUNCTION(jtag_a), + FUNCTION(cec_ao_a), + FUNCTION(cec_ao_b), + FUNCTION(tsin_ao_a), + FUNCTION(spdif_ao_out), + FUNCTION(tdm_ao_b), + FUNCTION(mclk0_ao), +}; + +static struct meson_bank meson_g12a_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), +}; + +static struct meson_bank meson_g12a_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_11, 0), 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), + BANK("E", PIN(GPIOE_0, 0), PIN(GPIOE_2, 0), 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), +}; + +static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { + /* name first lask reg offset */ + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), + BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), +}; + +static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = { + .pmx_banks = meson_g12a_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks), +}; + +static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = { + BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0), + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16), +}; + +static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { + .pmx_banks = meson_g12a_aobus_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks), +}; + +static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = EE_OFF, + .groups = meson_g12a_periphs_groups, + .funcs = meson_g12a_periphs_functions, + .banks = meson_g12a_periphs_banks, + .num_pins = 85, + .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), + .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_g12a_periphs_pmx_banks_data, +}; + +static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_g12a_aobus_groups, + .funcs = meson_g12a_aobus_functions, + .banks = meson_g12a_aobus_banks, + .num_pins = 15, + .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), + .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), + .gpio_driver = &meson_axg_gpio_driver, + .pmx_data = &meson_g12a_aobus_pmx_banks_data, +}; + +static const struct udevice_id meson_g12a_pinctrl_match[] = { + { + .compatible = "amlogic,meson-g12a-periphs-pinctrl", + .data = (ulong)&meson_g12a_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-g12a-aobus-pinctrl", + .data = (ulong)&meson_g12a_aobus_pinctrl_data, + }, + { }, +}; + +U_BOOT_DRIVER(meson_axg_pinctrl) = { + .name = "meson-g12a-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_g12a_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index fa3d78858a..8735418c5b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -314,11 +314,11 @@ int meson_pinctrl_probe(struct udevice *dev) priv->reg_gpio = (void __iomem *)addr; addr = parse_address(gpio, "pull", na, ns); - if (addr == FDT_ADDR_T_NONE) { - debug("pull address not found\n"); - return -EINVAL; - } - priv->reg_pull = (void __iomem *)addr; + /* Use gpio region if pull one is not present */ + if (addr == FDT_ADDR_T_NONE) + priv->reg_pull = priv->reg_gpio; + else + priv->reg_pull = (void __iomem *)addr; addr = parse_address(gpio, "pull-enable", na, ns); /* Use pull region if pull-enable one is not present */ @@ -327,6 +327,13 @@ int meson_pinctrl_probe(struct udevice *dev) else priv->reg_pullen = (void __iomem *)addr; + addr = parse_address(gpio, "ds", na, ns); + /* Drive strength region is optional */ + if (addr == FDT_ADDR_T_NONE) + priv->reg_ds = NULL; + else + priv->reg_ds = (void __iomem *)addr; + priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev); /* Lookup GPIO driver */ diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 28085a7495..b3683e2073 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -41,6 +41,7 @@ struct meson_pinctrl { void __iomem *reg_gpio; void __iomem *reg_pull; void __iomem *reg_pullen; + void __iomem *reg_ds; }; /** -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 1/6] pinctrl: meson: add g12a support 2019-03-26 15:02 ` Neil Armstrong @ 2019-04-10 14:57 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-04-10 14:57 UTC (permalink / raw) To: u-boot On 26/03/2019 16:02, Neil Armstrong wrote: > From: Jerome Brunet <jbrunet@baylibre.com> > > Add pinctrl support for the Amlogic G12A SoC, which is > very similar to the Amlogic AXG support but with an additionnal > drive-strength register bank. > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/pinctrl/meson/Kconfig | 4 + > drivers/pinctrl/meson/Makefile | 1 + > drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 ++++++++++++++++++++ > drivers/pinctrl/meson/pinctrl-meson.c | 17 +- > drivers/pinctrl/meson/pinctrl-meson.h | 1 + > 5 files changed, 1312 insertions(+), 5 deletions(-) > create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c > > diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig > index 162642d728..ef02087ed2 100644 > --- a/drivers/pinctrl/meson/Kconfig > +++ b/drivers/pinctrl/meson/Kconfig > @@ -25,4 +25,8 @@ config PINCTRL_MESON_AXG > bool "Amlogic Meson AXG SoC pinctrl driver" > select PINCTRL_MESON_AXG_PMX > > +config PINCTRL_MESON_G12A > + bool "Amlogic Meson G12a SoC pinctrl driver" > + select PINCTRL_MESON_AXG_PMX > + > endif > diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile > index 707287cd1d..80dba65e1b 100644 > --- a/drivers/pinctrl/meson/Makefile > +++ b/drivers/pinctrl/meson/Makefile > @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o > obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o > obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o > obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o > +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o > diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c > new file mode 100644 > index 0000000000..86f1290385 > --- /dev/null > +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c > @@ -0,0 +1,1294 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * (C) Copyright (C) 2019 Jerome Brunet <jbrunet@baylibre.com> > + * > + * Based on code from Linux kernel: > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. > + * Author: Xingyu Chen <xingyu.chen@amlogic.com> > + * Author: Yixun Lan <yixun.lan@amlogic.com> > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <dm/pinctrl.h> > +#include <dt-bindings/gpio/meson-g12a-gpio.h> > + > +#include "pinctrl-meson-axg.h" > + > +#define EE_OFF 15 > + > +/* emmc */ > +static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 }; > +static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 }; > +static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 }; > +static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 }; > +static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 }; > +static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 }; > +static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 }; > +static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 }; > +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; > +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; > +static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 }; > + > +/* nand */ > +static const unsigned int nand_wen_clk_pins[] = { BOOT_8 }; > +static const unsigned int nand_ale_pins[] = { BOOT_9 }; > +static const unsigned int nand_cle_pins[] = { BOOT_10 }; > +static const unsigned int nand_ce0_pins[] = { BOOT_11 }; > +static const unsigned int nand_ren_wr_pins[] = { BOOT_12 }; > +static const unsigned int nand_rb0_pins[] = { BOOT_14 }; > +static const unsigned int nand_ce1_pins[] = { BOOT_15 }; > + > +/* nor */ > +static const unsigned int nor_hold_pins[] = { BOOT_3 }; > +static const unsigned int nor_d_pins[] = { BOOT_4 }; > +static const unsigned int nor_q_pins[] = { BOOT_5 }; > +static const unsigned int nor_c_pins[] = { BOOT_6 }; > +static const unsigned int nor_wp_pins[] = { BOOT_7 }; > +static const unsigned int nor_cs_pins[] = { BOOT_14 }; > + > +/* sdio */ > +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; > +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; > +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; > +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; > +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; > +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; > + > +/* sdcard */ > +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; > +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; > +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; > +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; > +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; > +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; > + > +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; > +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; > + > +/* spi0 */ > +static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 }; > +static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 }; > +static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 }; > +static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 }; > + > +static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 }; > +static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 }; > +static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 }; > +static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 }; > + > +/* spi1 */ > +static const unsigned int spi1_mosi_pins[] = { GPIOH_4 }; > +static const unsigned int spi1_miso_pins[] = { GPIOH_5 }; > +static const unsigned int spi1_ss0_pins[] = { GPIOH_6 }; > +static const unsigned int spi1_clk_pins[] = { GPIOH_7 }; > + > +/* i2c0 */ > +static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 }; > +static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 }; > +static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 }; > +static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 }; > +static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 }; > +static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 }; > + > +/* i2c1 */ > +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 }; > +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 }; > +static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 }; > +static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 }; > +static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 }; > +static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 }; > + > +/* i2c2 */ > +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; > +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; > +static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 }; > +static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 }; > + > +/* i2c3 */ > +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 }; > +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 }; > +static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 }; > +static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 }; > + > +/* uart_a */ > +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; > +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; > +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; > +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; > + > +/* uart_b */ > +static const unsigned int uart_b_tx_pins[] = { GPIOX_6 }; > +static const unsigned int uart_b_rx_pins[] = { GPIOX_7 }; > + > +/* uart_c */ > +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; > +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; > +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; > +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; > + > +/* uart_ao_a_c */ > +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; > +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; > + > +/* iso7816 */ > +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; > +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; > +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; > +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; > +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; > +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; > +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; > +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; > + > +/* eth */ > +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; > +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; > +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; > +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; > +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; > +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; > +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; > +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; > +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; > +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; > +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; > +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; > +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; > +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; > +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; > +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; > + > +/* pwm_a */ > +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; > + > +/* pwm_b */ > +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; > +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; > + > +/* pwm_c */ > +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; > +static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 }; > +static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 }; > + > +/* pwm_d */ > +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; > +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; > + > +/* pwm_e */ > +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; > + > +/* pwm_f */ > +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; > +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; > + > +/* cec_ao */ > +static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 }; > +static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 }; > + > +/* jtag_b */ > +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; > +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; > +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; > +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; > + > +/* bt565_a */ > +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 }; > +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 }; > +static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 }; > +static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 }; > +static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 }; > +static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 }; > +static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 }; > +static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 }; > +static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 }; > +static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 }; > +static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 }; > + > +/* tsin_a */ > +static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 }; > +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 }; > +static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 }; > +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 }; > + > +/* tsin_b */ > +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 }; > +static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 }; > +static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 }; > +static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 }; > + > +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 }; > + > +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; > +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; > +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; > +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; > +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; > +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; > +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; > +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; > + > +/* hdmitx */ > +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; > +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; > +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; > + > +/* pdm */ > +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; > +static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 }; > +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; > +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; > +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; > + > +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; > +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; > +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; > +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; > +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; > + > +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; > + > +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; > +static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 }; > +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; > +static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 }; > +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 }; > + > +/* spdif_in */ > +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; > +static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 }; > +static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 }; > + > +/* spdif_out */ > +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; > +static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 }; > +static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 }; > + > +/* mclk0 */ > +static const unsigned int mclk0_a_pins[] = { GPIOA_0 }; > + > +/* mclk1 */ > +static const unsigned int mclk1_x_pins[] = { GPIOX_5 }; > +static const unsigned int mclk1_z_pins[] = { GPIOZ_8 }; > +static const unsigned int mclk1_a_pins[] = { GPIOA_11 }; > + > +/* tdm */ > +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; > +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; > +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; > +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; > +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; > +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; > +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; > +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; > + > +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; > +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; > +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; > +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; > +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; > +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; > +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; > +static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 }; > +static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 }; > +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; > +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; > +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; > +static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 }; > +static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 }; > + > +static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 }; > +static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 }; > +static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 }; > +static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 }; > +static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 }; > +static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 }; > +static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 }; > +static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 }; > +static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 }; > +static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 }; > +static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 }; > +static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 }; > +static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 }; > +static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 }; > +static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 }; > +static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 }; > +static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 }; > + > +static struct meson_pmx_group meson_g12a_periphs_groups[] = { > + GPIO_GROUP(GPIOZ_0, EE_OFF), > + GPIO_GROUP(GPIOZ_1, EE_OFF), > + GPIO_GROUP(GPIOZ_2, EE_OFF), > + GPIO_GROUP(GPIOZ_3, EE_OFF), > + GPIO_GROUP(GPIOZ_4, EE_OFF), > + GPIO_GROUP(GPIOZ_5, EE_OFF), > + GPIO_GROUP(GPIOZ_6, EE_OFF), > + GPIO_GROUP(GPIOZ_7, EE_OFF), > + GPIO_GROUP(GPIOZ_8, EE_OFF), > + GPIO_GROUP(GPIOZ_9, EE_OFF), > + GPIO_GROUP(GPIOZ_10, EE_OFF), > + GPIO_GROUP(GPIOZ_11, EE_OFF), > + GPIO_GROUP(GPIOZ_12, EE_OFF), > + GPIO_GROUP(GPIOZ_13, EE_OFF), > + GPIO_GROUP(GPIOZ_14, EE_OFF), > + GPIO_GROUP(GPIOZ_15, EE_OFF), > + GPIO_GROUP(GPIOH_0, EE_OFF), > + GPIO_GROUP(GPIOH_1, EE_OFF), > + GPIO_GROUP(GPIOH_2, EE_OFF), > + GPIO_GROUP(GPIOH_3, EE_OFF), > + GPIO_GROUP(GPIOH_4, EE_OFF), > + GPIO_GROUP(GPIOH_5, EE_OFF), > + GPIO_GROUP(GPIOH_6, EE_OFF), > + GPIO_GROUP(GPIOH_7, EE_OFF), > + GPIO_GROUP(GPIOH_8, EE_OFF), > + GPIO_GROUP(BOOT_0, EE_OFF), > + GPIO_GROUP(BOOT_1, EE_OFF), > + GPIO_GROUP(BOOT_2, EE_OFF), > + GPIO_GROUP(BOOT_3, EE_OFF), > + GPIO_GROUP(BOOT_4, EE_OFF), > + GPIO_GROUP(BOOT_5, EE_OFF), > + GPIO_GROUP(BOOT_6, EE_OFF), > + GPIO_GROUP(BOOT_7, EE_OFF), > + GPIO_GROUP(BOOT_8, EE_OFF), > + GPIO_GROUP(BOOT_9, EE_OFF), > + GPIO_GROUP(BOOT_10, EE_OFF), > + GPIO_GROUP(BOOT_11, EE_OFF), > + GPIO_GROUP(BOOT_12, EE_OFF), > + GPIO_GROUP(BOOT_13, EE_OFF), > + GPIO_GROUP(BOOT_14, EE_OFF), > + GPIO_GROUP(BOOT_15, EE_OFF), > + GPIO_GROUP(GPIOC_0, EE_OFF), > + GPIO_GROUP(GPIOC_1, EE_OFF), > + GPIO_GROUP(GPIOC_2, EE_OFF), > + GPIO_GROUP(GPIOC_3, EE_OFF), > + GPIO_GROUP(GPIOC_4, EE_OFF), > + GPIO_GROUP(GPIOC_5, EE_OFF), > + GPIO_GROUP(GPIOC_6, EE_OFF), > + GPIO_GROUP(GPIOC_7, EE_OFF), > + GPIO_GROUP(GPIOA_0, EE_OFF), > + GPIO_GROUP(GPIOA_1, EE_OFF), > + GPIO_GROUP(GPIOA_2, EE_OFF), > + GPIO_GROUP(GPIOA_3, EE_OFF), > + GPIO_GROUP(GPIOA_4, EE_OFF), > + GPIO_GROUP(GPIOA_5, EE_OFF), > + GPIO_GROUP(GPIOA_6, EE_OFF), > + GPIO_GROUP(GPIOA_7, EE_OFF), > + GPIO_GROUP(GPIOA_8, EE_OFF), > + GPIO_GROUP(GPIOA_9, EE_OFF), > + GPIO_GROUP(GPIOA_10, EE_OFF), > + GPIO_GROUP(GPIOA_11, EE_OFF), > + GPIO_GROUP(GPIOA_12, EE_OFF), > + GPIO_GROUP(GPIOA_13, EE_OFF), > + GPIO_GROUP(GPIOA_14, EE_OFF), > + GPIO_GROUP(GPIOA_15, EE_OFF), > + GPIO_GROUP(GPIOX_0, EE_OFF), > + GPIO_GROUP(GPIOX_1, EE_OFF), > + GPIO_GROUP(GPIOX_2, EE_OFF), > + GPIO_GROUP(GPIOX_3, EE_OFF), > + GPIO_GROUP(GPIOX_4, EE_OFF), > + GPIO_GROUP(GPIOX_5, EE_OFF), > + GPIO_GROUP(GPIOX_6, EE_OFF), > + GPIO_GROUP(GPIOX_7, EE_OFF), > + GPIO_GROUP(GPIOX_8, EE_OFF), > + GPIO_GROUP(GPIOX_9, EE_OFF), > + GPIO_GROUP(GPIOX_10, EE_OFF), > + GPIO_GROUP(GPIOX_11, EE_OFF), > + GPIO_GROUP(GPIOX_12, EE_OFF), > + GPIO_GROUP(GPIOX_13, EE_OFF), > + GPIO_GROUP(GPIOX_14, EE_OFF), > + GPIO_GROUP(GPIOX_15, EE_OFF), > + GPIO_GROUP(GPIOX_16, EE_OFF), > + GPIO_GROUP(GPIOX_17, EE_OFF), > + GPIO_GROUP(GPIOX_18, EE_OFF), > + GPIO_GROUP(GPIOX_19, EE_OFF), > + > + /* bank BOOT */ > + GROUP(emmc_nand_d0, 1), > + GROUP(emmc_nand_d1, 1), > + GROUP(emmc_nand_d2, 1), > + GROUP(emmc_nand_d3, 1), > + GROUP(emmc_nand_d4, 1), > + GROUP(emmc_nand_d5, 1), > + GROUP(emmc_nand_d6, 1), > + GROUP(emmc_nand_d7, 1), > + GROUP(emmc_clk, 1), > + GROUP(emmc_cmd, 1), > + GROUP(emmc_nand_ds, 1), > + GROUP(nand_ce0, 2), > + GROUP(nand_ale, 2), > + GROUP(nand_cle, 2), > + GROUP(nand_wen_clk, 2), > + GROUP(nand_ren_wr, 2), > + GROUP(nand_rb0, 2), > + GROUP(nand_ce1, 2), > + GROUP(nor_hold, 3), > + GROUP(nor_d, 3), > + GROUP(nor_q, 3), > + GROUP(nor_c, 3), > + GROUP(nor_wp, 3), > + GROUP(nor_cs, 3), > + > + /* bank GPIOZ */ > + GROUP(sdcard_d0_z, 5), > + GROUP(sdcard_d1_z, 5), > + GROUP(sdcard_d2_z, 5), > + GROUP(sdcard_d3_z, 5), > + GROUP(sdcard_clk_z, 5), > + GROUP(sdcard_cmd_z, 5), > + GROUP(i2c0_sda_z0, 4), > + GROUP(i2c0_sck_z1, 4), > + GROUP(i2c0_sda_z7, 7), > + GROUP(i2c0_sck_z8, 7), > + GROUP(i2c2_sda_z, 3), > + GROUP(i2c2_sck_z, 3), > + GROUP(iso7816_clk_z, 3), > + GROUP(iso7816_data_z, 3), > + GROUP(eth_mdio, 1), > + GROUP(eth_mdc, 1), > + GROUP(eth_rgmii_rx_clk, 1), > + GROUP(eth_rx_dv, 1), > + GROUP(eth_rxd0, 1), > + GROUP(eth_rxd1, 1), > + GROUP(eth_rxd2_rgmii, 1), > + GROUP(eth_rxd3_rgmii, 1), > + GROUP(eth_rgmii_tx_clk, 1), > + GROUP(eth_txen, 1), > + GROUP(eth_txd0, 1), > + GROUP(eth_txd1, 1), > + GROUP(eth_txd2_rgmii, 1), > + GROUP(eth_txd3_rgmii, 1), > + GROUP(eth_link_led, 1), > + GROUP(eth_act_led, 1), > + GROUP(bt565_a_vs, 2), > + GROUP(bt565_a_hs, 2), > + GROUP(bt565_a_clk, 2), > + GROUP(bt565_a_din0, 2), > + GROUP(bt565_a_din1, 2), > + GROUP(bt565_a_din2, 2), > + GROUP(bt565_a_din3, 2), > + GROUP(bt565_a_din4, 2), > + GROUP(bt565_a_din5, 2), > + GROUP(bt565_a_din6, 2), > + GROUP(bt565_a_din7, 2), > + GROUP(tsin_b_valid_z, 3), > + GROUP(tsin_b_sop_z, 3), > + GROUP(tsin_b_din0_z, 3), > + GROUP(tsin_b_clk_z, 3), > + GROUP(tsin_b_fail, 3), > + GROUP(tsin_b_din1, 3), > + GROUP(tsin_b_din2, 3), > + GROUP(tsin_b_din3, 3), > + GROUP(tsin_b_din4, 3), > + GROUP(tsin_b_din5, 3), > + GROUP(tsin_b_din6, 3), > + GROUP(tsin_b_din7, 3), > + GROUP(pdm_din0_z, 7), > + GROUP(pdm_din1_z, 7), > + GROUP(pdm_din2_z, 7), > + GROUP(pdm_din3_z, 7), > + GROUP(pdm_dclk_z, 7), > + GROUP(tdm_c_slv_sclk_z, 6), > + GROUP(tdm_c_slv_fs_z, 6), > + GROUP(tdm_c_din0_z, 6), > + GROUP(tdm_c_din1_z, 6), > + GROUP(tdm_c_din2_z, 6), > + GROUP(tdm_c_din3_z, 6), > + GROUP(tdm_c_sclk_z, 4), > + GROUP(tdm_c_fs_z, 4), > + GROUP(tdm_c_dout0_z, 4), > + GROUP(tdm_c_dout1_z, 4), > + GROUP(tdm_c_dout2_z, 4), > + GROUP(tdm_c_dout3_z, 4), > + GROUP(mclk1_z, 4), > + > + /* bank GPIOX */ > + GROUP(sdio_d0, 1), > + GROUP(sdio_d1, 1), > + GROUP(sdio_d2, 1), > + GROUP(sdio_d3, 1), > + GROUP(sdio_clk, 1), > + GROUP(sdio_cmd, 1), > + GROUP(spi0_mosi_x, 4), > + GROUP(spi0_miso_x, 4), > + GROUP(spi0_ss0_x, 4), > + GROUP(spi0_clk_x, 4), > + GROUP(i2c1_sda_x, 5), > + GROUP(i2c1_sck_x, 5), > + GROUP(i2c2_sda_x, 1), > + GROUP(i2c2_sck_x, 1), > + GROUP(uart_a_tx, 1), > + GROUP(uart_a_rx, 1), > + GROUP(uart_a_cts, 1), > + GROUP(uart_a_rts, 1), > + GROUP(uart_b_tx, 2), > + GROUP(uart_b_rx, 2), > + GROUP(iso7816_clk_x, 6), > + GROUP(iso7816_data_x, 6), > + GROUP(pwm_a, 1), > + GROUP(pwm_b_x7, 4), > + GROUP(pwm_b_x19, 1), > + GROUP(pwm_c_x5, 4), > + GROUP(pwm_c_x8, 5), > + GROUP(pwm_d_x3, 4), > + GROUP(pwm_d_x6, 4), > + GROUP(pwm_e, 1), > + GROUP(pwm_f_x, 1), > + GROUP(tsin_a_valid, 3), > + GROUP(tsin_a_sop, 3), > + GROUP(tsin_a_din0, 3), > + GROUP(tsin_a_clk, 3), > + GROUP(tsin_b_valid_x, 3), > + GROUP(tsin_b_sop_x, 3), > + GROUP(tsin_b_din0_x, 3), > + GROUP(tsin_b_clk_x, 3), > + GROUP(pdm_din0_x, 2), > + GROUP(pdm_din1_x, 2), > + GROUP(pdm_din2_x, 2), > + GROUP(pdm_din3_x, 2), > + GROUP(pdm_dclk_x, 2), > + GROUP(tdm_a_slv_sclk, 2), > + GROUP(tdm_a_slv_fs, 2), > + GROUP(tdm_a_din0, 2), > + GROUP(tdm_a_din1, 2), > + GROUP(tdm_a_sclk, 1), > + GROUP(tdm_a_fs, 1), > + GROUP(tdm_a_dout0, 1), > + GROUP(tdm_a_dout1, 1), > + GROUP(mclk1_x, 2), > + > + /* bank GPIOC */ > + GROUP(sdcard_d0_c, 1), > + GROUP(sdcard_d1_c, 1), > + GROUP(sdcard_d2_c, 1), > + GROUP(sdcard_d3_c, 1), > + GROUP(sdcard_clk_c, 1), > + GROUP(sdcard_cmd_c, 1), > + GROUP(spi0_mosi_c, 5), > + GROUP(spi0_miso_c, 5), > + GROUP(spi0_ss0_c, 5), > + GROUP(spi0_clk_c, 5), > + GROUP(i2c0_sda_c, 3), > + GROUP(i2c0_sck_c, 3), > + GROUP(uart_ao_a_rx_c, 2), > + GROUP(uart_ao_a_tx_c, 2), > + GROUP(iso7816_clk_c, 5), > + GROUP(iso7816_data_c, 5), > + GROUP(pwm_c_c, 5), > + GROUP(jtag_b_tdo, 2), > + GROUP(jtag_b_tdi, 2), > + GROUP(jtag_b_clk, 2), > + GROUP(jtag_b_tms, 2), > + GROUP(pdm_din0_c, 4), > + GROUP(pdm_din1_c, 4), > + GROUP(pdm_din2_c, 4), > + GROUP(pdm_din3_c, 4), > + GROUP(pdm_dclk_c, 4), > + > + /* bank GPIOH */ > + GROUP(spi1_mosi, 3), > + GROUP(spi1_miso, 3), > + GROUP(spi1_ss0, 3), > + GROUP(spi1_clk, 3), > + GROUP(i2c1_sda_h2, 2), > + GROUP(i2c1_sck_h3, 2), > + GROUP(i2c1_sda_h6, 4), > + GROUP(i2c1_sck_h7, 4), > + GROUP(i2c3_sda_h, 2), > + GROUP(i2c3_sck_h, 2), > + GROUP(uart_c_tx, 2), > + GROUP(uart_c_rx, 2), > + GROUP(uart_c_cts, 2), > + GROUP(uart_c_rts, 2), > + GROUP(iso7816_clk_h, 1), > + GROUP(iso7816_data_h, 1), > + GROUP(pwm_f_h, 4), > + GROUP(cec_ao_a_h, 4), > + GROUP(cec_ao_b_h, 5), > + GROUP(hdmitx_sda, 1), > + GROUP(hdmitx_sck, 1), > + GROUP(hdmitx_hpd_in, 1), > + GROUP(spdif_out_h, 1), > + GROUP(spdif_in_h, 1), > + GROUP(tdm_b_din3_h, 6), > + GROUP(tdm_b_dout3_h, 5), > + > + /* bank GPIOA */ > + GROUP(i2c3_sda_a, 2), > + GROUP(i2c3_sck_a, 2), > + GROUP(pdm_din0_a, 1), > + GROUP(pdm_din1_a, 1), > + GROUP(pdm_din2_a, 1), > + GROUP(pdm_din3_a, 1), > + GROUP(pdm_dclk_a, 1), > + GROUP(spdif_in_a10, 1), > + GROUP(spdif_in_a12, 1), > + GROUP(spdif_out_a11, 1), > + GROUP(spdif_out_a13, 1), > + GROUP(tdm_b_slv_sclk, 2), > + GROUP(tdm_b_slv_fs, 2), > + GROUP(tdm_b_din0, 2), > + GROUP(tdm_b_din1, 2), > + GROUP(tdm_b_din2, 2), > + GROUP(tdm_b_din3_a, 2), > + GROUP(tdm_b_sclk, 1), > + GROUP(tdm_b_fs, 1), > + GROUP(tdm_b_dout0, 1), > + GROUP(tdm_b_dout1, 1), > + GROUP(tdm_b_dout2, 3), > + GROUP(tdm_b_dout3_a, 3), > + GROUP(tdm_c_slv_sclk_a, 3), > + GROUP(tdm_c_slv_fs_a, 3), > + GROUP(tdm_c_din0_a, 3), > + GROUP(tdm_c_din1_a, 3), > + GROUP(tdm_c_din2_a, 3), > + GROUP(tdm_c_din3_a, 3), > + GROUP(tdm_c_sclk_a, 2), > + GROUP(tdm_c_fs_a, 2), > + GROUP(tdm_c_dout0_a, 2), > + GROUP(tdm_c_dout1_a, 2), > + GROUP(tdm_c_dout2_a, 2), > + GROUP(tdm_c_dout3_a, 2), > + GROUP(mclk0_a, 1), > + GROUP(mclk1_a, 2), > +}; > + > +/* uart_ao_a */ > +static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 }; > +static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 }; > +static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 }; > +static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 }; > + > +/* uart_ao_b */ > +static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 }; > +static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 }; > +static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 }; > +static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 }; > +static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 }; > +static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 }; > + > +/* i2c_ao */ > +static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 }; > +static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 }; > + > +static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 }; > +static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 }; > + > +/* i2c_ao_slave */ > +static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 }; > +static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 }; > + > +/* ir_in */ > +static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; > + > +/* ir_out */ > +static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; > + > +/* pwm_ao_a */ > +static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; > +static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; > + > +/* pwm_ao_b */ > +static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 }; > + > +/* pwm_ao_c */ > +static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 }; > +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 }; > +static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 }; > + > +/* pwm_ao_d */ > +static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 }; > +static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 }; > +static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 }; > + > +/* jtag_a */ > +static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 }; > +static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 }; > +static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 }; > +static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 }; > + > +/* cec_ao */ > +static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 }; > +static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 }; > + > +/* tsin_ao_a */ > +static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 }; > +static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 }; > +static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 }; > + > +/* spdif_ao_out */ > +static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 }; > + > +/* tdm_ao_b */ > +static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 }; > +static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 }; > +static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 }; > +static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 }; > +static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 }; > +static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 }; > +static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 }; > +static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 }; > + > +/* mclk0_ao */ > +static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 }; > + > +static struct meson_pmx_group meson_g12a_aobus_groups[] = { > + GPIO_GROUP(GPIOAO_0, 0), > + GPIO_GROUP(GPIOAO_1, 0), > + GPIO_GROUP(GPIOAO_2, 0), > + GPIO_GROUP(GPIOAO_3, 0), > + GPIO_GROUP(GPIOAO_4, 0), > + GPIO_GROUP(GPIOAO_5, 0), > + GPIO_GROUP(GPIOAO_6, 0), > + GPIO_GROUP(GPIOAO_7, 0), > + GPIO_GROUP(GPIOAO_8, 0), > + GPIO_GROUP(GPIOAO_9, 0), > + GPIO_GROUP(GPIOAO_10, 0), > + GPIO_GROUP(GPIOAO_11, 0), > + GPIO_GROUP(GPIOE_0, 0), > + GPIO_GROUP(GPIOE_1, 0), > + GPIO_GROUP(GPIOE_2, 0), > + > + /* bank AO */ > + GROUP(uart_ao_a_tx, 1), > + GROUP(uart_ao_a_rx, 1), > + GROUP(uart_ao_a_cts, 1), > + GROUP(uart_ao_a_rts, 1), > + GROUP(uart_ao_b_tx_2, 2), > + GROUP(uart_ao_b_rx_3, 2), > + GROUP(uart_ao_b_tx_8, 3), > + GROUP(uart_ao_b_rx_9, 3), > + GROUP(uart_ao_b_cts, 2), > + GROUP(uart_ao_b_rts, 2), > + GROUP(i2c_ao_sck, 1), > + GROUP(i2c_ao_sda, 1), > + GROUP(i2c_ao_sck_e, 4), > + GROUP(i2c_ao_sda_e, 4), > + GROUP(i2c_ao_slave_sck, 3), > + GROUP(i2c_ao_slave_sda, 3), > + GROUP(remote_ao_input, 1), > + GROUP(remote_ao_out, 1), > + GROUP(pwm_ao_a, 3), > + GROUP(pwm_ao_a_hiz, 2), > + GROUP(pwm_ao_b, 3), > + GROUP(pwm_ao_c_4, 3), > + GROUP(pwm_ao_c_hiz, 4), > + GROUP(pwm_ao_c_6, 3), > + GROUP(pwm_ao_d_5, 3), > + GROUP(pwm_ao_d_10, 3), > + GROUP(pwm_ao_d_e, 3), > + GROUP(jtag_a_tdi, 1), > + GROUP(jtag_a_tdo, 1), > + GROUP(jtag_a_clk, 1), > + GROUP(jtag_a_tms, 1), > + GROUP(cec_ao_a, 1), > + GROUP(cec_ao_b, 2), > + GROUP(tsin_ao_asop, 4), > + GROUP(tsin_ao_adin0, 4), > + GROUP(tsin_ao_aclk, 4), > + GROUP(tsin_ao_a_valid, 4), > + GROUP(spdif_ao_out, 4), > + GROUP(tdm_ao_b_dout0, 5), > + GROUP(tdm_ao_b_dout1, 5), > + GROUP(tdm_ao_b_dout2, 5), > + GROUP(tdm_ao_b_fs, 5), > + GROUP(tdm_ao_b_sclk, 5), > + GROUP(tdm_ao_b_din0, 6), > + GROUP(tdm_ao_b_din1, 6), > + GROUP(tdm_ao_b_din2, 6), > + GROUP(tdm_ao_b_slv_fs, 6), > + GROUP(tdm_ao_b_slv_sclk, 6), > + GROUP(mclk0_ao, 5), > +}; > + > +static const char * const gpio_periphs_groups[] = { > + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", > + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", > + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", > + "GPIOZ_15", > + > + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", > + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", > + > + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", > + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", > + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", > + "BOOT_15", > + > + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", > + "GPIOC_5", "GPIOC_6", "GPIOC_7", > + > + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", > + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", > + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", > + "GPIOA_15", > + > + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", > + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", > + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", > + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", > +}; > + > +static const char * const emmc_groups[] = { > + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", > + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", > + "emmc_nand_d6", "emmc_nand_d7", > + "emmc_clk", "emmc_cmd", "emmc_nand_ds", > +}; > + > +static const char * const nand_groups[] = { > + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", > + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", > + "emmc_nand_d6", "emmc_nand_d7", > + "nand_ce0", "nand_ale", "nand_cle", > + "nand_wen_clk", "nand_ren_wr", "nand_rb0", > + "emmc_nand_ds", "nand_ce1", > +}; > + > +static const char * const nor_groups[] = { > + "nor_d", "nor_q", "nor_c", "nor_cs", > + "nor_hold", "nor_wp", > +}; > + > +static const char * const sdio_groups[] = { > + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", > + "sdio_cmd", "sdio_clk", "sdio_dummy", > +}; > + > +static const char * const sdcard_groups[] = { > + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", > + "sdcard_clk_c", "sdcard_cmd_c", > + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", > + "sdcard_clk_z", "sdcard_cmd_z", > +}; > + > +static const char * const spi0_groups[] = { > + "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c", > + "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x", > +}; > + > +static const char * const spi1_groups[] = { > + "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk", > +}; > + > +static const char * const i2c0_groups[] = { > + "i2c0_sda_c", "i2c0_sck_c", > + "i2c0_sda_z0", "i2c0_sck_z1", > + "i2c0_sda_z7", "i2c0_sck_z8", > +}; > + > +static const char * const i2c1_groups[] = { > + "i2c1_sda_x", "i2c1_sck_x", > + "i2c1_sda_h2", "i2c1_sck_h3", > + "i2c1_sda_h6", "i2c1_sck_h7", > +}; > + > +static const char * const i2c2_groups[] = { > + "i2c2_sda_x", "i2c2_sck_x", > + "i2c2_sda_z", "i2c2_sck_z", > +}; > + > +static const char * const i2c3_groups[] = { > + "i2c3_sda_h", "i2c3_sck_h", > + "i2c3_sda_a", "i2c3_sck_a", > +}; > + > +static const char * const uart_a_groups[] = { > + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", > +}; > + > +static const char * const uart_b_groups[] = { > + "uart_b_tx", "uart_b_rx", > +}; > + > +static const char * const uart_c_groups[] = { > + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", > +}; > + > +static const char * const uart_ao_a_c_groups[] = { > + "uart_ao_a_rx_c", "uart_ao_a_tx_c", > +}; > + > +static const char * const iso7816_groups[] = { > + "iso7816_clk_c", "iso7816_data_c", > + "iso7816_clk_x", "iso7816_data_x", > + "iso7816_clk_h", "iso7816_data_h", > + "iso7816_clk_z", "iso7816_data_z", > +}; > + > +static const char * const eth_groups[] = { > + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", > + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", > + "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc", > + "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio", > + "eth_link_led", "eth_act_led", > +}; > + > +static const char * const pwm_a_groups[] = { > + "pwm_a", > +}; > + > +static const char * const pwm_b_groups[] = { > + "pwm_b_x7", "pwm_b_x19", > +}; > + > +static const char * const pwm_c_groups[] = { > + "pwm_c_c", "pwm_c_x5", "pwm_c_x8", > +}; > + > +static const char * const pwm_d_groups[] = { > + "pwm_d_x3", "pwm_d_x6", > +}; > + > +static const char * const pwm_e_groups[] = { > + "pwm_e", > +}; > + > +static const char * const pwm_f_groups[] = { > + "pwm_f_x", "pwm_f_h", > +}; > + > +static const char * const cec_ao_a_h_groups[] = { > + "cec_ao_a_h", > +}; > + > +static const char * const cec_ao_b_h_groups[] = { > + "cec_ao_b_h", > +}; > + > +static const char * const jtag_b_groups[] = { > + "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", > +}; > + > +static const char * const bt565_a_groups[] = { > + "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", > + "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", > + "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", > + "bt565_a_din6", "bt565_a_din7", > +}; > + > +static const char * const tsin_a_groups[] = { > + "tsin_a_valid", "tsin_a_sop", "tsin_a_din0", > + "tsin_a_clk", > +}; > + > +static const char * const tsin_b_groups[] = { > + "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x", > + "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z", > + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", > + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", > +}; > + > +static const char * const hdmitx_groups[] = { > + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", > +}; > + > +static const char * const pdm_groups[] = { > + "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c", > + "pdm_dclk_c", > + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", > + "pdm_dclk_x", > + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", > + "pdm_dclk_z", > + "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a", > + "pdm_dclk_a", > +}; > + > +static const char * const spdif_in_groups[] = { > + "spdif_in_h", "spdif_in_a10", "spdif_in_a12", > +}; > + > +static const char * const spdif_out_groups[] = { > + "spdif_out_h", "spdif_out_a11", "spdif_out_a13", > +}; > + > +static const char * const mclk0_groups[] = { > + "mclk0_a", > +}; > + > +static const char * const mclk1_groups[] = { > + "mclk1_x", "mclk1_z", "mclk1_a", > +}; > + > +static const char * const tdm_a_groups[] = { > + "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs", > + "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1", > +}; > + > +static const char * const tdm_b_groups[] = { > + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs", > + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", > + "tdm_b_din3_a", "tdm_b_din3_h", > + "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2", > + "tdm_b_dout3_a", "tdm_b_dout3_h", > +}; > + > +static const char * const tdm_c_groups[] = { > + "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a", > + "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z", > + "tdm_c_sclk_a", "tdm_c_fs_a", > + "tdm_c_sclk_z", "tdm_c_fs_z", > + "tdm_c_din0_a", "tdm_c_din1_a", > + "tdm_c_din2_a", "tdm_c_din3_a", > + "tdm_c_din0_z", "tdm_c_din1_z", > + "tdm_c_din2_z", "tdm_c_din3_z", > + "tdm_c_dout0_a", "tdm_c_dout1_a", > + "tdm_c_dout2_a", "tdm_c_dout3_a", > + "tdm_c_dout0_z", "tdm_c_dout1_z", > + "tdm_c_dout2_z", "tdm_c_dout3_z", > +}; > + > +static const char * const gpio_aobus_groups[] = { > + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", > + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", > + "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2", > +}; > + > +static const char * const uart_ao_a_groups[] = { > + "uart_ao_a_tx", "uart_ao_a_rx", > + "uart_ao_a_cts", "uart_ao_a_rts", > +}; > + > +static const char * const uart_ao_b_groups[] = { > + "uart_ao_b_tx_2", "uart_ao_b_rx_3", > + "uart_ao_b_tx_8", "uart_ao_b_rx_9", > + "uart_ao_b_cts", "uart_ao_b_rts", > +}; > + > +static const char * const i2c_ao_groups[] = { > + "i2c_ao_sck", "i2c_ao_sda", > + "i2c_ao_sck_e", "i2c_ao_sda_e", > +}; > + > +static const char * const i2c_ao_slave_groups[] = { > + "i2c_ao_slave_sck", "i2c_ao_slave_sda", > +}; > + > +static const char * const remote_ao_input_groups[] = { > + "remote_ao_input", > +}; > + > +static const char * const remote_ao_out_groups[] = { > + "remote_ao_out", > +}; > + > +static const char * const pwm_ao_a_groups[] = { > + "pwm_ao_a", "pwm_ao_a_hiz", > +}; > + > +static const char * const pwm_ao_b_groups[] = { > + "pwm_ao_b", > +}; > + > +static const char * const pwm_ao_c_groups[] = { > + "pwm_ao_c_4", "pwm_ao_c_hiz", > + "pwm_ao_c_6", > +}; > + > +static const char * const pwm_ao_d_groups[] = { > + "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e", > +}; > + > +static const char * const jtag_a_groups[] = { > + "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms", > +}; > + > +static const char * const cec_ao_a_groups[] = { > + "cec_ao_a", > +}; > + > +static const char * const cec_ao_b_groups[] = { > + "cec_ao_b", > +}; > + > +static const char * const tsin_ao_a_groups[] = { > + "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid", > +}; > + > +static const char * const spdif_ao_out_groups[] = { > + "spdif_ao_out", > +}; > + > +static const char * const tdm_ao_b_groups[] = { > + "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2", > + "tdm_ao_b_fs", "tdm_ao_b_sclk", > + "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2", > + "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk", > +}; > + > +static const char * const mclk0_ao_groups[] = { > + "mclk0_ao", > +}; > + > +static struct meson_pmx_func meson_g12a_periphs_functions[] = { > + FUNCTION(gpio_periphs), > + FUNCTION(emmc), > + FUNCTION(nor), > + FUNCTION(spi0), > + FUNCTION(spi1), > + FUNCTION(sdio), > + FUNCTION(nand), > + FUNCTION(sdcard), > + FUNCTION(i2c0), > + FUNCTION(i2c1), > + FUNCTION(i2c2), > + FUNCTION(i2c3), > + FUNCTION(uart_a), > + FUNCTION(uart_b), > + FUNCTION(uart_c), > + FUNCTION(uart_ao_a_c), > + FUNCTION(iso7816), > + FUNCTION(eth), > + FUNCTION(pwm_a), > + FUNCTION(pwm_b), > + FUNCTION(pwm_c), > + FUNCTION(pwm_d), > + FUNCTION(pwm_e), > + FUNCTION(pwm_f), > + FUNCTION(cec_ao_a_h), > + FUNCTION(cec_ao_b_h), > + FUNCTION(jtag_b), > + FUNCTION(bt565_a), > + FUNCTION(tsin_a), > + FUNCTION(tsin_b), > + FUNCTION(hdmitx), > + FUNCTION(pdm), > + FUNCTION(spdif_out), > + FUNCTION(spdif_in), > + FUNCTION(mclk0), > + FUNCTION(mclk1), > + FUNCTION(tdm_a), > + FUNCTION(tdm_b), > + FUNCTION(tdm_c), > +}; > + > +static struct meson_pmx_func meson_g12a_aobus_functions[] = { > + FUNCTION(gpio_aobus), > + FUNCTION(uart_ao_a), > + FUNCTION(uart_ao_b), > + FUNCTION(i2c_ao), > + FUNCTION(i2c_ao_slave), > + FUNCTION(remote_ao_input), > + FUNCTION(remote_ao_out), > + FUNCTION(pwm_ao_a), > + FUNCTION(pwm_ao_b), > + FUNCTION(pwm_ao_c), > + FUNCTION(pwm_ao_d), > + FUNCTION(jtag_a), > + FUNCTION(cec_ao_a), > + FUNCTION(cec_ao_b), > + FUNCTION(tsin_ao_a), > + FUNCTION(spdif_ao_out), > + FUNCTION(tdm_ao_b), > + FUNCTION(mclk0_ao), > +}; > + > +static struct meson_bank meson_g12a_periphs_banks[] = { > + /* name first last pullen pull dir out in */ > + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), > + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), > + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), > + BANK("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), > + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), > + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), > +}; > + > +static struct meson_bank meson_g12a_aobus_banks[] = { > + /* name first last pullen pull dir out in */ > + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_11, 0), 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), > + BANK("E", PIN(GPIOE_0, 0), PIN(GPIOE_2, 0), 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), > +}; > + > +static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { > + /* name first lask reg offset */ > + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), > + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), > + BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), > + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), > + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0), > + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), > +}; > + > +static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = { > + .pmx_banks = meson_g12a_periphs_pmx_banks, > + .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks), > +}; > + > +static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = { > + BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0), > + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16), > +}; > + > +static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { > + .pmx_banks = meson_g12a_aobus_pmx_banks, > + .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks), > +}; > + > +static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { > + .name = "periphs-banks", > + .pin_base = EE_OFF, > + .groups = meson_g12a_periphs_groups, > + .funcs = meson_g12a_periphs_functions, > + .banks = meson_g12a_periphs_banks, > + .num_pins = 85, > + .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), > + .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), > + .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), > + .gpio_driver = &meson_axg_gpio_driver, > + .pmx_data = &meson_g12a_periphs_pmx_banks_data, > +}; > + > +static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { > + .name = "aobus-banks", > + .pin_base = 0, > + .groups = meson_g12a_aobus_groups, > + .funcs = meson_g12a_aobus_functions, > + .banks = meson_g12a_aobus_banks, > + .num_pins = 15, > + .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), > + .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), > + .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), > + .gpio_driver = &meson_axg_gpio_driver, > + .pmx_data = &meson_g12a_aobus_pmx_banks_data, > +}; > + > +static const struct udevice_id meson_g12a_pinctrl_match[] = { > + { > + .compatible = "amlogic,meson-g12a-periphs-pinctrl", > + .data = (ulong)&meson_g12a_periphs_pinctrl_data, > + }, > + { > + .compatible = "amlogic,meson-g12a-aobus-pinctrl", > + .data = (ulong)&meson_g12a_aobus_pinctrl_data, > + }, > + { }, > +}; > + > +U_BOOT_DRIVER(meson_axg_pinctrl) = { > + .name = "meson-g12a-pinctrl", > + .id = UCLASS_PINCTRL, > + .of_match = of_match_ptr(meson_g12a_pinctrl_match), > + .probe = meson_pinctrl_probe, > + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), > + .ops = &meson_axg_pinctrl_ops, > +}; > diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c > index fa3d78858a..8735418c5b 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson.c > +++ b/drivers/pinctrl/meson/pinctrl-meson.c > @@ -314,11 +314,11 @@ int meson_pinctrl_probe(struct udevice *dev) > priv->reg_gpio = (void __iomem *)addr; > > addr = parse_address(gpio, "pull", na, ns); > - if (addr == FDT_ADDR_T_NONE) { > - debug("pull address not found\n"); > - return -EINVAL; > - } > - priv->reg_pull = (void __iomem *)addr; > + /* Use gpio region if pull one is not present */ > + if (addr == FDT_ADDR_T_NONE) > + priv->reg_pull = priv->reg_gpio; > + else > + priv->reg_pull = (void __iomem *)addr; > > addr = parse_address(gpio, "pull-enable", na, ns); > /* Use pull region if pull-enable one is not present */ > @@ -327,6 +327,13 @@ int meson_pinctrl_probe(struct udevice *dev) > else > priv->reg_pullen = (void __iomem *)addr; > > + addr = parse_address(gpio, "ds", na, ns); > + /* Drive strength region is optional */ > + if (addr == FDT_ADDR_T_NONE) > + priv->reg_ds = NULL; > + else > + priv->reg_ds = (void __iomem *)addr; > + > priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev); > > /* Lookup GPIO driver */ > diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h > index 28085a7495..b3683e2073 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson.h > +++ b/drivers/pinctrl/meson/pinctrl-meson.h > @@ -41,6 +41,7 @@ struct meson_pinctrl { > void __iomem *reg_gpio; > void __iomem *reg_pull; > void __iomem *reg_pullen; > + void __iomem *reg_ds; > }; > > /** > This also need fixing like AXG, I will resend with the same fix. Neil ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] pinctrl: meson: add g12a support @ 2019-04-10 14:57 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-04-10 14:57 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, sjg On 26/03/2019 16:02, Neil Armstrong wrote: > From: Jerome Brunet <jbrunet@baylibre.com> > > Add pinctrl support for the Amlogic G12A SoC, which is > very similar to the Amlogic AXG support but with an additionnal > drive-strength register bank. > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/pinctrl/meson/Kconfig | 4 + > drivers/pinctrl/meson/Makefile | 1 + > drivers/pinctrl/meson/pinctrl-meson-g12a.c | 1294 ++++++++++++++++++++ > drivers/pinctrl/meson/pinctrl-meson.c | 17 +- > drivers/pinctrl/meson/pinctrl-meson.h | 1 + > 5 files changed, 1312 insertions(+), 5 deletions(-) > create mode 100644 drivers/pinctrl/meson/pinctrl-meson-g12a.c > > diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig > index 162642d728..ef02087ed2 100644 > --- a/drivers/pinctrl/meson/Kconfig > +++ b/drivers/pinctrl/meson/Kconfig > @@ -25,4 +25,8 @@ config PINCTRL_MESON_AXG > bool "Amlogic Meson AXG SoC pinctrl driver" > select PINCTRL_MESON_AXG_PMX > > +config PINCTRL_MESON_G12A > + bool "Amlogic Meson G12a SoC pinctrl driver" > + select PINCTRL_MESON_AXG_PMX > + > endif > diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile > index 707287cd1d..80dba65e1b 100644 > --- a/drivers/pinctrl/meson/Makefile > +++ b/drivers/pinctrl/meson/Makefile > @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o > obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o > obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o > obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o > +obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o > diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c > new file mode 100644 > index 0000000000..86f1290385 > --- /dev/null > +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c > @@ -0,0 +1,1294 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * (C) Copyright (C) 2019 Jerome Brunet <jbrunet@baylibre.com> > + * > + * Based on code from Linux kernel: > + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. > + * Author: Xingyu Chen <xingyu.chen@amlogic.com> > + * Author: Yixun Lan <yixun.lan@amlogic.com> > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <dm/pinctrl.h> > +#include <dt-bindings/gpio/meson-g12a-gpio.h> > + > +#include "pinctrl-meson-axg.h" > + > +#define EE_OFF 15 > + > +/* emmc */ > +static const unsigned int emmc_nand_d0_pins[] = { BOOT_0 }; > +static const unsigned int emmc_nand_d1_pins[] = { BOOT_1 }; > +static const unsigned int emmc_nand_d2_pins[] = { BOOT_2 }; > +static const unsigned int emmc_nand_d3_pins[] = { BOOT_3 }; > +static const unsigned int emmc_nand_d4_pins[] = { BOOT_4 }; > +static const unsigned int emmc_nand_d5_pins[] = { BOOT_5 }; > +static const unsigned int emmc_nand_d6_pins[] = { BOOT_6 }; > +static const unsigned int emmc_nand_d7_pins[] = { BOOT_7 }; > +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; > +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; > +static const unsigned int emmc_nand_ds_pins[] = { BOOT_13 }; > + > +/* nand */ > +static const unsigned int nand_wen_clk_pins[] = { BOOT_8 }; > +static const unsigned int nand_ale_pins[] = { BOOT_9 }; > +static const unsigned int nand_cle_pins[] = { BOOT_10 }; > +static const unsigned int nand_ce0_pins[] = { BOOT_11 }; > +static const unsigned int nand_ren_wr_pins[] = { BOOT_12 }; > +static const unsigned int nand_rb0_pins[] = { BOOT_14 }; > +static const unsigned int nand_ce1_pins[] = { BOOT_15 }; > + > +/* nor */ > +static const unsigned int nor_hold_pins[] = { BOOT_3 }; > +static const unsigned int nor_d_pins[] = { BOOT_4 }; > +static const unsigned int nor_q_pins[] = { BOOT_5 }; > +static const unsigned int nor_c_pins[] = { BOOT_6 }; > +static const unsigned int nor_wp_pins[] = { BOOT_7 }; > +static const unsigned int nor_cs_pins[] = { BOOT_14 }; > + > +/* sdio */ > +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; > +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; > +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; > +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; > +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; > +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; > + > +/* sdcard */ > +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; > +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; > +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; > +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; > +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; > +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; > + > +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; > +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; > + > +/* spi0 */ > +static const unsigned int spi0_mosi_c_pins[] = { GPIOC_0 }; > +static const unsigned int spi0_miso_c_pins[] = { GPIOC_1 }; > +static const unsigned int spi0_ss0_c_pins[] = { GPIOC_2 }; > +static const unsigned int spi0_clk_c_pins[] = { GPIOC_3 }; > + > +static const unsigned int spi0_mosi_x_pins[] = { GPIOX_8 }; > +static const unsigned int spi0_miso_x_pins[] = { GPIOX_9 }; > +static const unsigned int spi0_ss0_x_pins[] = { GPIOX_10 }; > +static const unsigned int spi0_clk_x_pins[] = { GPIOX_11 }; > + > +/* spi1 */ > +static const unsigned int spi1_mosi_pins[] = { GPIOH_4 }; > +static const unsigned int spi1_miso_pins[] = { GPIOH_5 }; > +static const unsigned int spi1_ss0_pins[] = { GPIOH_6 }; > +static const unsigned int spi1_clk_pins[] = { GPIOH_7 }; > + > +/* i2c0 */ > +static const unsigned int i2c0_sda_c_pins[] = { GPIOC_5 }; > +static const unsigned int i2c0_sck_c_pins[] = { GPIOC_6 }; > +static const unsigned int i2c0_sda_z0_pins[] = { GPIOZ_0 }; > +static const unsigned int i2c0_sck_z1_pins[] = { GPIOZ_1 }; > +static const unsigned int i2c0_sda_z7_pins[] = { GPIOZ_7 }; > +static const unsigned int i2c0_sck_z8_pins[] = { GPIOZ_8 }; > + > +/* i2c1 */ > +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_10 }; > +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_11 }; > +static const unsigned int i2c1_sda_h2_pins[] = { GPIOH_2 }; > +static const unsigned int i2c1_sck_h3_pins[] = { GPIOH_3 }; > +static const unsigned int i2c1_sda_h6_pins[] = { GPIOH_6 }; > +static const unsigned int i2c1_sck_h7_pins[] = { GPIOH_7 }; > + > +/* i2c2 */ > +static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; > +static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; > +static const unsigned int i2c2_sda_z_pins[] = { GPIOZ_14 }; > +static const unsigned int i2c2_sck_z_pins[] = { GPIOZ_15 }; > + > +/* i2c3 */ > +static const unsigned int i2c3_sda_h_pins[] = { GPIOH_0 }; > +static const unsigned int i2c3_sck_h_pins[] = { GPIOH_1 }; > +static const unsigned int i2c3_sda_a_pins[] = { GPIOA_14 }; > +static const unsigned int i2c3_sck_a_pins[] = { GPIOA_15 }; > + > +/* uart_a */ > +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; > +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; > +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; > +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; > + > +/* uart_b */ > +static const unsigned int uart_b_tx_pins[] = { GPIOX_6 }; > +static const unsigned int uart_b_rx_pins[] = { GPIOX_7 }; > + > +/* uart_c */ > +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; > +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; > +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; > +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; > + > +/* uart_ao_a_c */ > +static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; > +static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; > + > +/* iso7816 */ > +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; > +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; > +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; > +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; > +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; > +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; > +static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; > +static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; > + > +/* eth */ > +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; > +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; > +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; > +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; > +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; > +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; > +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; > +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; > +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; > +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; > +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; > +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; > +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; > +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; > +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; > +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; > + > +/* pwm_a */ > +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; > + > +/* pwm_b */ > +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; > +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; > + > +/* pwm_c */ > +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; > +static const unsigned int pwm_c_x5_pins[] = { GPIOX_5 }; > +static const unsigned int pwm_c_x8_pins[] = { GPIOX_8 }; > + > +/* pwm_d */ > +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; > +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; > + > +/* pwm_e */ > +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; > + > +/* pwm_f */ > +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; > +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; > + > +/* cec_ao */ > +static const unsigned int cec_ao_a_h_pins[] = { GPIOH_3 }; > +static const unsigned int cec_ao_b_h_pins[] = { GPIOH_3 }; > + > +/* jtag_b */ > +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; > +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; > +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; > +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; > + > +/* bt565_a */ > +static const unsigned int bt565_a_vs_pins[] = { GPIOZ_0 }; > +static const unsigned int bt565_a_hs_pins[] = { GPIOZ_1 }; > +static const unsigned int bt565_a_clk_pins[] = { GPIOZ_3 }; > +static const unsigned int bt565_a_din0_pins[] = { GPIOZ_4 }; > +static const unsigned int bt565_a_din1_pins[] = { GPIOZ_5 }; > +static const unsigned int bt565_a_din2_pins[] = { GPIOZ_6 }; > +static const unsigned int bt565_a_din3_pins[] = { GPIOZ_7 }; > +static const unsigned int bt565_a_din4_pins[] = { GPIOZ_8 }; > +static const unsigned int bt565_a_din5_pins[] = { GPIOZ_9 }; > +static const unsigned int bt565_a_din6_pins[] = { GPIOZ_10 }; > +static const unsigned int bt565_a_din7_pins[] = { GPIOZ_11 }; > + > +/* tsin_a */ > +static const unsigned int tsin_a_valid_pins[] = { GPIOX_2 }; > +static const unsigned int tsin_a_sop_pins[] = { GPIOX_1 }; > +static const unsigned int tsin_a_din0_pins[] = { GPIOX_0 }; > +static const unsigned int tsin_a_clk_pins[] = { GPIOX_3 }; > + > +/* tsin_b */ > +static const unsigned int tsin_b_valid_x_pins[] = { GPIOX_9 }; > +static const unsigned int tsin_b_sop_x_pins[] = { GPIOX_8 }; > +static const unsigned int tsin_b_din0_x_pins[] = { GPIOX_10 }; > +static const unsigned int tsin_b_clk_x_pins[] = { GPIOX_11 }; > + > +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tsin_b_din0_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_5 }; > + > +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; > +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; > +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; > +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; > +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; > +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; > +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; > +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; > + > +/* hdmitx */ > +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; > +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; > +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; > + > +/* pdm */ > +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; > +static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 }; > +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; > +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; > +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; > + > +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; > +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; > +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; > +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; > +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; > + > +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; > + > +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; > +static const unsigned int pdm_din1_a_pins[] = { GPIOA_9 }; > +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; > +static const unsigned int pdm_din3_a_pins[] = { GPIOA_5 }; > +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_7 }; > + > +/* spdif_in */ > +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; > +static const unsigned int spdif_in_a10_pins[] = { GPIOA_10 }; > +static const unsigned int spdif_in_a12_pins[] = { GPIOA_12 }; > + > +/* spdif_out */ > +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; > +static const unsigned int spdif_out_a11_pins[] = { GPIOA_11 }; > +static const unsigned int spdif_out_a13_pins[] = { GPIOA_13 }; > + > +/* mclk0 */ > +static const unsigned int mclk0_a_pins[] = { GPIOA_0 }; > + > +/* mclk1 */ > +static const unsigned int mclk1_x_pins[] = { GPIOX_5 }; > +static const unsigned int mclk1_z_pins[] = { GPIOZ_8 }; > +static const unsigned int mclk1_a_pins[] = { GPIOA_11 }; > + > +/* tdm */ > +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; > +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; > +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; > +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; > +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; > +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; > +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; > +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; > + > +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; > +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; > +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; > +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; > +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; > +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; > +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; > +static const unsigned int tdm_b_din3_a_pins[] = { GPIOA_6 }; > +static const unsigned int tdm_b_din3_h_pins[] = { GPIOH_5 }; > +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; > +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; > +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; > +static const unsigned int tdm_b_dout3_a_pins[] = { GPIOA_6 }; > +static const unsigned int tdm_b_dout3_h_pins[] = { GPIOH_5 }; > + > +static const unsigned int tdm_c_slv_sclk_a_pins[] = { GPIOA_12 }; > +static const unsigned int tdm_c_slv_fs_a_pins[] = { GPIOA_13 }; > +static const unsigned int tdm_c_slv_sclk_z_pins[] = { GPIOZ_7 }; > +static const unsigned int tdm_c_slv_fs_z_pins[] = { GPIOZ_6 }; > +static const unsigned int tdm_c_sclk_a_pins[] = { GPIOA_12 }; > +static const unsigned int tdm_c_fs_a_pins[] = { GPIOA_13 }; > +static const unsigned int tdm_c_sclk_z_pins[] = { GPIOZ_7 }; > +static const unsigned int tdm_c_fs_z_pins[] = { GPIOZ_6 }; > +static const unsigned int tdm_c_din0_a_pins[] = { GPIOA_10 }; > +static const unsigned int tdm_c_din1_a_pins[] = { GPIOA_9 }; > +static const unsigned int tdm_c_din2_a_pins[] = { GPIOA_8 }; > +static const unsigned int tdm_c_din3_a_pins[] = { GPIOA_7 }; > +static const unsigned int tdm_c_din0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tdm_c_din1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tdm_c_din2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tdm_c_din3_z_pins[] = { GPIOZ_5 }; > +static const unsigned int tdm_c_dout0_a_pins[] = { GPIOA_10 }; > +static const unsigned int tdm_c_dout1_a_pins[] = { GPIOA_9 }; > +static const unsigned int tdm_c_dout2_a_pins[] = { GPIOA_8 }; > +static const unsigned int tdm_c_dout3_a_pins[] = { GPIOA_7 }; > +static const unsigned int tdm_c_dout0_z_pins[] = { GPIOZ_2 }; > +static const unsigned int tdm_c_dout1_z_pins[] = { GPIOZ_3 }; > +static const unsigned int tdm_c_dout2_z_pins[] = { GPIOZ_4 }; > +static const unsigned int tdm_c_dout3_z_pins[] = { GPIOZ_5 }; > + > +static struct meson_pmx_group meson_g12a_periphs_groups[] = { > + GPIO_GROUP(GPIOZ_0, EE_OFF), > + GPIO_GROUP(GPIOZ_1, EE_OFF), > + GPIO_GROUP(GPIOZ_2, EE_OFF), > + GPIO_GROUP(GPIOZ_3, EE_OFF), > + GPIO_GROUP(GPIOZ_4, EE_OFF), > + GPIO_GROUP(GPIOZ_5, EE_OFF), > + GPIO_GROUP(GPIOZ_6, EE_OFF), > + GPIO_GROUP(GPIOZ_7, EE_OFF), > + GPIO_GROUP(GPIOZ_8, EE_OFF), > + GPIO_GROUP(GPIOZ_9, EE_OFF), > + GPIO_GROUP(GPIOZ_10, EE_OFF), > + GPIO_GROUP(GPIOZ_11, EE_OFF), > + GPIO_GROUP(GPIOZ_12, EE_OFF), > + GPIO_GROUP(GPIOZ_13, EE_OFF), > + GPIO_GROUP(GPIOZ_14, EE_OFF), > + GPIO_GROUP(GPIOZ_15, EE_OFF), > + GPIO_GROUP(GPIOH_0, EE_OFF), > + GPIO_GROUP(GPIOH_1, EE_OFF), > + GPIO_GROUP(GPIOH_2, EE_OFF), > + GPIO_GROUP(GPIOH_3, EE_OFF), > + GPIO_GROUP(GPIOH_4, EE_OFF), > + GPIO_GROUP(GPIOH_5, EE_OFF), > + GPIO_GROUP(GPIOH_6, EE_OFF), > + GPIO_GROUP(GPIOH_7, EE_OFF), > + GPIO_GROUP(GPIOH_8, EE_OFF), > + GPIO_GROUP(BOOT_0, EE_OFF), > + GPIO_GROUP(BOOT_1, EE_OFF), > + GPIO_GROUP(BOOT_2, EE_OFF), > + GPIO_GROUP(BOOT_3, EE_OFF), > + GPIO_GROUP(BOOT_4, EE_OFF), > + GPIO_GROUP(BOOT_5, EE_OFF), > + GPIO_GROUP(BOOT_6, EE_OFF), > + GPIO_GROUP(BOOT_7, EE_OFF), > + GPIO_GROUP(BOOT_8, EE_OFF), > + GPIO_GROUP(BOOT_9, EE_OFF), > + GPIO_GROUP(BOOT_10, EE_OFF), > + GPIO_GROUP(BOOT_11, EE_OFF), > + GPIO_GROUP(BOOT_12, EE_OFF), > + GPIO_GROUP(BOOT_13, EE_OFF), > + GPIO_GROUP(BOOT_14, EE_OFF), > + GPIO_GROUP(BOOT_15, EE_OFF), > + GPIO_GROUP(GPIOC_0, EE_OFF), > + GPIO_GROUP(GPIOC_1, EE_OFF), > + GPIO_GROUP(GPIOC_2, EE_OFF), > + GPIO_GROUP(GPIOC_3, EE_OFF), > + GPIO_GROUP(GPIOC_4, EE_OFF), > + GPIO_GROUP(GPIOC_5, EE_OFF), > + GPIO_GROUP(GPIOC_6, EE_OFF), > + GPIO_GROUP(GPIOC_7, EE_OFF), > + GPIO_GROUP(GPIOA_0, EE_OFF), > + GPIO_GROUP(GPIOA_1, EE_OFF), > + GPIO_GROUP(GPIOA_2, EE_OFF), > + GPIO_GROUP(GPIOA_3, EE_OFF), > + GPIO_GROUP(GPIOA_4, EE_OFF), > + GPIO_GROUP(GPIOA_5, EE_OFF), > + GPIO_GROUP(GPIOA_6, EE_OFF), > + GPIO_GROUP(GPIOA_7, EE_OFF), > + GPIO_GROUP(GPIOA_8, EE_OFF), > + GPIO_GROUP(GPIOA_9, EE_OFF), > + GPIO_GROUP(GPIOA_10, EE_OFF), > + GPIO_GROUP(GPIOA_11, EE_OFF), > + GPIO_GROUP(GPIOA_12, EE_OFF), > + GPIO_GROUP(GPIOA_13, EE_OFF), > + GPIO_GROUP(GPIOA_14, EE_OFF), > + GPIO_GROUP(GPIOA_15, EE_OFF), > + GPIO_GROUP(GPIOX_0, EE_OFF), > + GPIO_GROUP(GPIOX_1, EE_OFF), > + GPIO_GROUP(GPIOX_2, EE_OFF), > + GPIO_GROUP(GPIOX_3, EE_OFF), > + GPIO_GROUP(GPIOX_4, EE_OFF), > + GPIO_GROUP(GPIOX_5, EE_OFF), > + GPIO_GROUP(GPIOX_6, EE_OFF), > + GPIO_GROUP(GPIOX_7, EE_OFF), > + GPIO_GROUP(GPIOX_8, EE_OFF), > + GPIO_GROUP(GPIOX_9, EE_OFF), > + GPIO_GROUP(GPIOX_10, EE_OFF), > + GPIO_GROUP(GPIOX_11, EE_OFF), > + GPIO_GROUP(GPIOX_12, EE_OFF), > + GPIO_GROUP(GPIOX_13, EE_OFF), > + GPIO_GROUP(GPIOX_14, EE_OFF), > + GPIO_GROUP(GPIOX_15, EE_OFF), > + GPIO_GROUP(GPIOX_16, EE_OFF), > + GPIO_GROUP(GPIOX_17, EE_OFF), > + GPIO_GROUP(GPIOX_18, EE_OFF), > + GPIO_GROUP(GPIOX_19, EE_OFF), > + > + /* bank BOOT */ > + GROUP(emmc_nand_d0, 1), > + GROUP(emmc_nand_d1, 1), > + GROUP(emmc_nand_d2, 1), > + GROUP(emmc_nand_d3, 1), > + GROUP(emmc_nand_d4, 1), > + GROUP(emmc_nand_d5, 1), > + GROUP(emmc_nand_d6, 1), > + GROUP(emmc_nand_d7, 1), > + GROUP(emmc_clk, 1), > + GROUP(emmc_cmd, 1), > + GROUP(emmc_nand_ds, 1), > + GROUP(nand_ce0, 2), > + GROUP(nand_ale, 2), > + GROUP(nand_cle, 2), > + GROUP(nand_wen_clk, 2), > + GROUP(nand_ren_wr, 2), > + GROUP(nand_rb0, 2), > + GROUP(nand_ce1, 2), > + GROUP(nor_hold, 3), > + GROUP(nor_d, 3), > + GROUP(nor_q, 3), > + GROUP(nor_c, 3), > + GROUP(nor_wp, 3), > + GROUP(nor_cs, 3), > + > + /* bank GPIOZ */ > + GROUP(sdcard_d0_z, 5), > + GROUP(sdcard_d1_z, 5), > + GROUP(sdcard_d2_z, 5), > + GROUP(sdcard_d3_z, 5), > + GROUP(sdcard_clk_z, 5), > + GROUP(sdcard_cmd_z, 5), > + GROUP(i2c0_sda_z0, 4), > + GROUP(i2c0_sck_z1, 4), > + GROUP(i2c0_sda_z7, 7), > + GROUP(i2c0_sck_z8, 7), > + GROUP(i2c2_sda_z, 3), > + GROUP(i2c2_sck_z, 3), > + GROUP(iso7816_clk_z, 3), > + GROUP(iso7816_data_z, 3), > + GROUP(eth_mdio, 1), > + GROUP(eth_mdc, 1), > + GROUP(eth_rgmii_rx_clk, 1), > + GROUP(eth_rx_dv, 1), > + GROUP(eth_rxd0, 1), > + GROUP(eth_rxd1, 1), > + GROUP(eth_rxd2_rgmii, 1), > + GROUP(eth_rxd3_rgmii, 1), > + GROUP(eth_rgmii_tx_clk, 1), > + GROUP(eth_txen, 1), > + GROUP(eth_txd0, 1), > + GROUP(eth_txd1, 1), > + GROUP(eth_txd2_rgmii, 1), > + GROUP(eth_txd3_rgmii, 1), > + GROUP(eth_link_led, 1), > + GROUP(eth_act_led, 1), > + GROUP(bt565_a_vs, 2), > + GROUP(bt565_a_hs, 2), > + GROUP(bt565_a_clk, 2), > + GROUP(bt565_a_din0, 2), > + GROUP(bt565_a_din1, 2), > + GROUP(bt565_a_din2, 2), > + GROUP(bt565_a_din3, 2), > + GROUP(bt565_a_din4, 2), > + GROUP(bt565_a_din5, 2), > + GROUP(bt565_a_din6, 2), > + GROUP(bt565_a_din7, 2), > + GROUP(tsin_b_valid_z, 3), > + GROUP(tsin_b_sop_z, 3), > + GROUP(tsin_b_din0_z, 3), > + GROUP(tsin_b_clk_z, 3), > + GROUP(tsin_b_fail, 3), > + GROUP(tsin_b_din1, 3), > + GROUP(tsin_b_din2, 3), > + GROUP(tsin_b_din3, 3), > + GROUP(tsin_b_din4, 3), > + GROUP(tsin_b_din5, 3), > + GROUP(tsin_b_din6, 3), > + GROUP(tsin_b_din7, 3), > + GROUP(pdm_din0_z, 7), > + GROUP(pdm_din1_z, 7), > + GROUP(pdm_din2_z, 7), > + GROUP(pdm_din3_z, 7), > + GROUP(pdm_dclk_z, 7), > + GROUP(tdm_c_slv_sclk_z, 6), > + GROUP(tdm_c_slv_fs_z, 6), > + GROUP(tdm_c_din0_z, 6), > + GROUP(tdm_c_din1_z, 6), > + GROUP(tdm_c_din2_z, 6), > + GROUP(tdm_c_din3_z, 6), > + GROUP(tdm_c_sclk_z, 4), > + GROUP(tdm_c_fs_z, 4), > + GROUP(tdm_c_dout0_z, 4), > + GROUP(tdm_c_dout1_z, 4), > + GROUP(tdm_c_dout2_z, 4), > + GROUP(tdm_c_dout3_z, 4), > + GROUP(mclk1_z, 4), > + > + /* bank GPIOX */ > + GROUP(sdio_d0, 1), > + GROUP(sdio_d1, 1), > + GROUP(sdio_d2, 1), > + GROUP(sdio_d3, 1), > + GROUP(sdio_clk, 1), > + GROUP(sdio_cmd, 1), > + GROUP(spi0_mosi_x, 4), > + GROUP(spi0_miso_x, 4), > + GROUP(spi0_ss0_x, 4), > + GROUP(spi0_clk_x, 4), > + GROUP(i2c1_sda_x, 5), > + GROUP(i2c1_sck_x, 5), > + GROUP(i2c2_sda_x, 1), > + GROUP(i2c2_sck_x, 1), > + GROUP(uart_a_tx, 1), > + GROUP(uart_a_rx, 1), > + GROUP(uart_a_cts, 1), > + GROUP(uart_a_rts, 1), > + GROUP(uart_b_tx, 2), > + GROUP(uart_b_rx, 2), > + GROUP(iso7816_clk_x, 6), > + GROUP(iso7816_data_x, 6), > + GROUP(pwm_a, 1), > + GROUP(pwm_b_x7, 4), > + GROUP(pwm_b_x19, 1), > + GROUP(pwm_c_x5, 4), > + GROUP(pwm_c_x8, 5), > + GROUP(pwm_d_x3, 4), > + GROUP(pwm_d_x6, 4), > + GROUP(pwm_e, 1), > + GROUP(pwm_f_x, 1), > + GROUP(tsin_a_valid, 3), > + GROUP(tsin_a_sop, 3), > + GROUP(tsin_a_din0, 3), > + GROUP(tsin_a_clk, 3), > + GROUP(tsin_b_valid_x, 3), > + GROUP(tsin_b_sop_x, 3), > + GROUP(tsin_b_din0_x, 3), > + GROUP(tsin_b_clk_x, 3), > + GROUP(pdm_din0_x, 2), > + GROUP(pdm_din1_x, 2), > + GROUP(pdm_din2_x, 2), > + GROUP(pdm_din3_x, 2), > + GROUP(pdm_dclk_x, 2), > + GROUP(tdm_a_slv_sclk, 2), > + GROUP(tdm_a_slv_fs, 2), > + GROUP(tdm_a_din0, 2), > + GROUP(tdm_a_din1, 2), > + GROUP(tdm_a_sclk, 1), > + GROUP(tdm_a_fs, 1), > + GROUP(tdm_a_dout0, 1), > + GROUP(tdm_a_dout1, 1), > + GROUP(mclk1_x, 2), > + > + /* bank GPIOC */ > + GROUP(sdcard_d0_c, 1), > + GROUP(sdcard_d1_c, 1), > + GROUP(sdcard_d2_c, 1), > + GROUP(sdcard_d3_c, 1), > + GROUP(sdcard_clk_c, 1), > + GROUP(sdcard_cmd_c, 1), > + GROUP(spi0_mosi_c, 5), > + GROUP(spi0_miso_c, 5), > + GROUP(spi0_ss0_c, 5), > + GROUP(spi0_clk_c, 5), > + GROUP(i2c0_sda_c, 3), > + GROUP(i2c0_sck_c, 3), > + GROUP(uart_ao_a_rx_c, 2), > + GROUP(uart_ao_a_tx_c, 2), > + GROUP(iso7816_clk_c, 5), > + GROUP(iso7816_data_c, 5), > + GROUP(pwm_c_c, 5), > + GROUP(jtag_b_tdo, 2), > + GROUP(jtag_b_tdi, 2), > + GROUP(jtag_b_clk, 2), > + GROUP(jtag_b_tms, 2), > + GROUP(pdm_din0_c, 4), > + GROUP(pdm_din1_c, 4), > + GROUP(pdm_din2_c, 4), > + GROUP(pdm_din3_c, 4), > + GROUP(pdm_dclk_c, 4), > + > + /* bank GPIOH */ > + GROUP(spi1_mosi, 3), > + GROUP(spi1_miso, 3), > + GROUP(spi1_ss0, 3), > + GROUP(spi1_clk, 3), > + GROUP(i2c1_sda_h2, 2), > + GROUP(i2c1_sck_h3, 2), > + GROUP(i2c1_sda_h6, 4), > + GROUP(i2c1_sck_h7, 4), > + GROUP(i2c3_sda_h, 2), > + GROUP(i2c3_sck_h, 2), > + GROUP(uart_c_tx, 2), > + GROUP(uart_c_rx, 2), > + GROUP(uart_c_cts, 2), > + GROUP(uart_c_rts, 2), > + GROUP(iso7816_clk_h, 1), > + GROUP(iso7816_data_h, 1), > + GROUP(pwm_f_h, 4), > + GROUP(cec_ao_a_h, 4), > + GROUP(cec_ao_b_h, 5), > + GROUP(hdmitx_sda, 1), > + GROUP(hdmitx_sck, 1), > + GROUP(hdmitx_hpd_in, 1), > + GROUP(spdif_out_h, 1), > + GROUP(spdif_in_h, 1), > + GROUP(tdm_b_din3_h, 6), > + GROUP(tdm_b_dout3_h, 5), > + > + /* bank GPIOA */ > + GROUP(i2c3_sda_a, 2), > + GROUP(i2c3_sck_a, 2), > + GROUP(pdm_din0_a, 1), > + GROUP(pdm_din1_a, 1), > + GROUP(pdm_din2_a, 1), > + GROUP(pdm_din3_a, 1), > + GROUP(pdm_dclk_a, 1), > + GROUP(spdif_in_a10, 1), > + GROUP(spdif_in_a12, 1), > + GROUP(spdif_out_a11, 1), > + GROUP(spdif_out_a13, 1), > + GROUP(tdm_b_slv_sclk, 2), > + GROUP(tdm_b_slv_fs, 2), > + GROUP(tdm_b_din0, 2), > + GROUP(tdm_b_din1, 2), > + GROUP(tdm_b_din2, 2), > + GROUP(tdm_b_din3_a, 2), > + GROUP(tdm_b_sclk, 1), > + GROUP(tdm_b_fs, 1), > + GROUP(tdm_b_dout0, 1), > + GROUP(tdm_b_dout1, 1), > + GROUP(tdm_b_dout2, 3), > + GROUP(tdm_b_dout3_a, 3), > + GROUP(tdm_c_slv_sclk_a, 3), > + GROUP(tdm_c_slv_fs_a, 3), > + GROUP(tdm_c_din0_a, 3), > + GROUP(tdm_c_din1_a, 3), > + GROUP(tdm_c_din2_a, 3), > + GROUP(tdm_c_din3_a, 3), > + GROUP(tdm_c_sclk_a, 2), > + GROUP(tdm_c_fs_a, 2), > + GROUP(tdm_c_dout0_a, 2), > + GROUP(tdm_c_dout1_a, 2), > + GROUP(tdm_c_dout2_a, 2), > + GROUP(tdm_c_dout3_a, 2), > + GROUP(mclk0_a, 1), > + GROUP(mclk1_a, 2), > +}; > + > +/* uart_ao_a */ > +static const unsigned int uart_ao_a_tx_pins[] = { GPIOAO_0 }; > +static const unsigned int uart_ao_a_rx_pins[] = { GPIOAO_1 }; > +static const unsigned int uart_ao_a_cts_pins[] = { GPIOE_0 }; > +static const unsigned int uart_ao_a_rts_pins[] = { GPIOE_1 }; > + > +/* uart_ao_b */ > +static const unsigned int uart_ao_b_tx_2_pins[] = { GPIOAO_2 }; > +static const unsigned int uart_ao_b_rx_3_pins[] = { GPIOAO_3 }; > +static const unsigned int uart_ao_b_tx_8_pins[] = { GPIOAO_8 }; > +static const unsigned int uart_ao_b_rx_9_pins[] = { GPIOAO_9 }; > +static const unsigned int uart_ao_b_cts_pins[] = { GPIOE_0 }; > +static const unsigned int uart_ao_b_rts_pins[] = { GPIOE_1 }; > + > +/* i2c_ao */ > +static const unsigned int i2c_ao_sck_pins[] = { GPIOAO_2 }; > +static const unsigned int i2c_ao_sda_pins[] = { GPIOAO_3 }; > + > +static const unsigned int i2c_ao_sck_e_pins[] = { GPIOE_0 }; > +static const unsigned int i2c_ao_sda_e_pins[] = { GPIOE_1 }; > + > +/* i2c_ao_slave */ > +static const unsigned int i2c_ao_slave_sck_pins[] = { GPIOAO_2 }; > +static const unsigned int i2c_ao_slave_sda_pins[] = { GPIOAO_3 }; > + > +/* ir_in */ > +static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; > + > +/* ir_out */ > +static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; > + > +/* pwm_ao_a */ > +static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; > +static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; > + > +/* pwm_ao_b */ > +static const unsigned int pwm_ao_b_pins[] = { GPIOE_0 }; > + > +/* pwm_ao_c */ > +static const unsigned int pwm_ao_c_4_pins[] = { GPIOAO_4 }; > +static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOAO_4 }; > +static const unsigned int pwm_ao_c_6_pins[] = { GPIOAO_6 }; > + > +/* pwm_ao_d */ > +static const unsigned int pwm_ao_d_5_pins[] = { GPIOAO_5 }; > +static const unsigned int pwm_ao_d_10_pins[] = { GPIOAO_10 }; > +static const unsigned int pwm_ao_d_e_pins[] = { GPIOE_1 }; > + > +/* jtag_a */ > +static const unsigned int jtag_a_tdi_pins[] = { GPIOAO_8 }; > +static const unsigned int jtag_a_tdo_pins[] = { GPIOAO_9 }; > +static const unsigned int jtag_a_clk_pins[] = { GPIOAO_6 }; > +static const unsigned int jtag_a_tms_pins[] = { GPIOAO_7 }; > + > +/* cec_ao */ > +static const unsigned int cec_ao_a_pins[] = { GPIOAO_10 }; > +static const unsigned int cec_ao_b_pins[] = { GPIOAO_10 }; > + > +/* tsin_ao_a */ > +static const unsigned int tsin_ao_asop_pins[] = { GPIOAO_6 }; > +static const unsigned int tsin_ao_adin0_pins[] = { GPIOAO_7 }; > +static const unsigned int tsin_ao_aclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tsin_ao_a_valid_pins[] = { GPIOAO_9 }; > + > +/* spdif_ao_out */ > +static const unsigned int spdif_ao_out_pins[] = { GPIOAO_10 }; > + > +/* tdm_ao_b */ > +static const unsigned int tdm_ao_b_slv_fs_pins[] = { GPIOAO_7 }; > +static const unsigned int tdm_ao_b_slv_sclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tdm_ao_b_fs_pins[] = { GPIOAO_7 }; > +static const unsigned int tdm_ao_b_sclk_pins[] = { GPIOAO_8 }; > +static const unsigned int tdm_ao_b_din0_pins[] = { GPIOAO_4 }; > +static const unsigned int tdm_ao_b_din1_pins[] = { GPIOAO_10 }; > +static const unsigned int tdm_ao_b_din2_pins[] = { GPIOAO_6 }; > +static const unsigned int tdm_ao_b_dout0_pins[] = { GPIOAO_4 }; > +static const unsigned int tdm_ao_b_dout1_pins[] = { GPIOAO_10 }; > +static const unsigned int tdm_ao_b_dout2_pins[] = { GPIOAO_6 }; > + > +/* mclk0_ao */ > +static const unsigned int mclk0_ao_pins[] = { GPIOAO_9 }; > + > +static struct meson_pmx_group meson_g12a_aobus_groups[] = { > + GPIO_GROUP(GPIOAO_0, 0), > + GPIO_GROUP(GPIOAO_1, 0), > + GPIO_GROUP(GPIOAO_2, 0), > + GPIO_GROUP(GPIOAO_3, 0), > + GPIO_GROUP(GPIOAO_4, 0), > + GPIO_GROUP(GPIOAO_5, 0), > + GPIO_GROUP(GPIOAO_6, 0), > + GPIO_GROUP(GPIOAO_7, 0), > + GPIO_GROUP(GPIOAO_8, 0), > + GPIO_GROUP(GPIOAO_9, 0), > + GPIO_GROUP(GPIOAO_10, 0), > + GPIO_GROUP(GPIOAO_11, 0), > + GPIO_GROUP(GPIOE_0, 0), > + GPIO_GROUP(GPIOE_1, 0), > + GPIO_GROUP(GPIOE_2, 0), > + > + /* bank AO */ > + GROUP(uart_ao_a_tx, 1), > + GROUP(uart_ao_a_rx, 1), > + GROUP(uart_ao_a_cts, 1), > + GROUP(uart_ao_a_rts, 1), > + GROUP(uart_ao_b_tx_2, 2), > + GROUP(uart_ao_b_rx_3, 2), > + GROUP(uart_ao_b_tx_8, 3), > + GROUP(uart_ao_b_rx_9, 3), > + GROUP(uart_ao_b_cts, 2), > + GROUP(uart_ao_b_rts, 2), > + GROUP(i2c_ao_sck, 1), > + GROUP(i2c_ao_sda, 1), > + GROUP(i2c_ao_sck_e, 4), > + GROUP(i2c_ao_sda_e, 4), > + GROUP(i2c_ao_slave_sck, 3), > + GROUP(i2c_ao_slave_sda, 3), > + GROUP(remote_ao_input, 1), > + GROUP(remote_ao_out, 1), > + GROUP(pwm_ao_a, 3), > + GROUP(pwm_ao_a_hiz, 2), > + GROUP(pwm_ao_b, 3), > + GROUP(pwm_ao_c_4, 3), > + GROUP(pwm_ao_c_hiz, 4), > + GROUP(pwm_ao_c_6, 3), > + GROUP(pwm_ao_d_5, 3), > + GROUP(pwm_ao_d_10, 3), > + GROUP(pwm_ao_d_e, 3), > + GROUP(jtag_a_tdi, 1), > + GROUP(jtag_a_tdo, 1), > + GROUP(jtag_a_clk, 1), > + GROUP(jtag_a_tms, 1), > + GROUP(cec_ao_a, 1), > + GROUP(cec_ao_b, 2), > + GROUP(tsin_ao_asop, 4), > + GROUP(tsin_ao_adin0, 4), > + GROUP(tsin_ao_aclk, 4), > + GROUP(tsin_ao_a_valid, 4), > + GROUP(spdif_ao_out, 4), > + GROUP(tdm_ao_b_dout0, 5), > + GROUP(tdm_ao_b_dout1, 5), > + GROUP(tdm_ao_b_dout2, 5), > + GROUP(tdm_ao_b_fs, 5), > + GROUP(tdm_ao_b_sclk, 5), > + GROUP(tdm_ao_b_din0, 6), > + GROUP(tdm_ao_b_din1, 6), > + GROUP(tdm_ao_b_din2, 6), > + GROUP(tdm_ao_b_slv_fs, 6), > + GROUP(tdm_ao_b_slv_sclk, 6), > + GROUP(mclk0_ao, 5), > +}; > + > +static const char * const gpio_periphs_groups[] = { > + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", > + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", > + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", > + "GPIOZ_15", > + > + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", > + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", > + > + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", > + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", > + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", > + "BOOT_15", > + > + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", > + "GPIOC_5", "GPIOC_6", "GPIOC_7", > + > + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", > + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", > + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", > + "GPIOA_15", > + > + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", > + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", > + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", > + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", > +}; > + > +static const char * const emmc_groups[] = { > + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", > + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", > + "emmc_nand_d6", "emmc_nand_d7", > + "emmc_clk", "emmc_cmd", "emmc_nand_ds", > +}; > + > +static const char * const nand_groups[] = { > + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", > + "emmc_nand_d3", "emmc_nand_d4", "emmc_nand_d5", > + "emmc_nand_d6", "emmc_nand_d7", > + "nand_ce0", "nand_ale", "nand_cle", > + "nand_wen_clk", "nand_ren_wr", "nand_rb0", > + "emmc_nand_ds", "nand_ce1", > +}; > + > +static const char * const nor_groups[] = { > + "nor_d", "nor_q", "nor_c", "nor_cs", > + "nor_hold", "nor_wp", > +}; > + > +static const char * const sdio_groups[] = { > + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", > + "sdio_cmd", "sdio_clk", "sdio_dummy", > +}; > + > +static const char * const sdcard_groups[] = { > + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", > + "sdcard_clk_c", "sdcard_cmd_c", > + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", > + "sdcard_clk_z", "sdcard_cmd_z", > +}; > + > +static const char * const spi0_groups[] = { > + "spi0_mosi_c", "spi0_miso_c", "spi0_ss0_c", "spi0_clk_c", > + "spi0_mosi_x", "spi0_miso_x", "spi0_ss0_x", "spi0_clk_x", > +}; > + > +static const char * const spi1_groups[] = { > + "spi1_mosi", "spi1_miso", "spi1_ss0", "spi1_clk", > +}; > + > +static const char * const i2c0_groups[] = { > + "i2c0_sda_c", "i2c0_sck_c", > + "i2c0_sda_z0", "i2c0_sck_z1", > + "i2c0_sda_z7", "i2c0_sck_z8", > +}; > + > +static const char * const i2c1_groups[] = { > + "i2c1_sda_x", "i2c1_sck_x", > + "i2c1_sda_h2", "i2c1_sck_h3", > + "i2c1_sda_h6", "i2c1_sck_h7", > +}; > + > +static const char * const i2c2_groups[] = { > + "i2c2_sda_x", "i2c2_sck_x", > + "i2c2_sda_z", "i2c2_sck_z", > +}; > + > +static const char * const i2c3_groups[] = { > + "i2c3_sda_h", "i2c3_sck_h", > + "i2c3_sda_a", "i2c3_sck_a", > +}; > + > +static const char * const uart_a_groups[] = { > + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", > +}; > + > +static const char * const uart_b_groups[] = { > + "uart_b_tx", "uart_b_rx", > +}; > + > +static const char * const uart_c_groups[] = { > + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", > +}; > + > +static const char * const uart_ao_a_c_groups[] = { > + "uart_ao_a_rx_c", "uart_ao_a_tx_c", > +}; > + > +static const char * const iso7816_groups[] = { > + "iso7816_clk_c", "iso7816_data_c", > + "iso7816_clk_x", "iso7816_data_x", > + "iso7816_clk_h", "iso7816_data_h", > + "iso7816_clk_z", "iso7816_data_z", > +}; > + > +static const char * const eth_groups[] = { > + "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", > + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", > + "eth_txd0", "eth_txd1", "eth_txen", "eth_mdc", > + "eth_rxd0", "eth_rxd1", "eth_rx_dv", "eth_mdio", > + "eth_link_led", "eth_act_led", > +}; > + > +static const char * const pwm_a_groups[] = { > + "pwm_a", > +}; > + > +static const char * const pwm_b_groups[] = { > + "pwm_b_x7", "pwm_b_x19", > +}; > + > +static const char * const pwm_c_groups[] = { > + "pwm_c_c", "pwm_c_x5", "pwm_c_x8", > +}; > + > +static const char * const pwm_d_groups[] = { > + "pwm_d_x3", "pwm_d_x6", > +}; > + > +static const char * const pwm_e_groups[] = { > + "pwm_e", > +}; > + > +static const char * const pwm_f_groups[] = { > + "pwm_f_x", "pwm_f_h", > +}; > + > +static const char * const cec_ao_a_h_groups[] = { > + "cec_ao_a_h", > +}; > + > +static const char * const cec_ao_b_h_groups[] = { > + "cec_ao_b_h", > +}; > + > +static const char * const jtag_b_groups[] = { > + "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", > +}; > + > +static const char * const bt565_a_groups[] = { > + "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", > + "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", > + "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", > + "bt565_a_din6", "bt565_a_din7", > +}; > + > +static const char * const tsin_a_groups[] = { > + "tsin_a_valid", "tsin_a_sop", "tsin_a_din0", > + "tsin_a_clk", > +}; > + > +static const char * const tsin_b_groups[] = { > + "tsin_b_valid_x", "tsin_b_sop_x", "tsin_b_din0_x", "tsin_b_clk_x", > + "tsin_b_valid_z", "tsin_b_sop_z", "tsin_b_din0_z", "tsin_b_clk_z", > + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", > + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", > +}; > + > +static const char * const hdmitx_groups[] = { > + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", > +}; > + > +static const char * const pdm_groups[] = { > + "pdm_din0_c", "pdm_din1_c", "pdm_din2_c", "pdm_din3_c", > + "pdm_dclk_c", > + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", > + "pdm_dclk_x", > + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", > + "pdm_dclk_z", > + "pdm_din0_a", "pdm_din1_a", "pdm_din2_a", "pdm_din3_a", > + "pdm_dclk_a", > +}; > + > +static const char * const spdif_in_groups[] = { > + "spdif_in_h", "spdif_in_a10", "spdif_in_a12", > +}; > + > +static const char * const spdif_out_groups[] = { > + "spdif_out_h", "spdif_out_a11", "spdif_out_a13", > +}; > + > +static const char * const mclk0_groups[] = { > + "mclk0_a", > +}; > + > +static const char * const mclk1_groups[] = { > + "mclk1_x", "mclk1_z", "mclk1_a", > +}; > + > +static const char * const tdm_a_groups[] = { > + "tdm_a_slv_sclk", "tdm_a_slv_fs", "tdm_a_sclk", "tdm_a_fs", > + "tdm_a_din0", "tdm_a_din1", "tdm_a_dout0", "tdm_a_dout1", > +}; > + > +static const char * const tdm_b_groups[] = { > + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_sclk", "tdm_b_fs", > + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", > + "tdm_b_din3_a", "tdm_b_din3_h", > + "tdm_b_dout0", "tdm_b_dout1", "tdm_b_dout2", > + "tdm_b_dout3_a", "tdm_b_dout3_h", > +}; > + > +static const char * const tdm_c_groups[] = { > + "tdm_c_slv_sclk_a", "tdm_c_slv_fs_a", > + "tdm_c_slv_sclk_z", "tdm_c_slv_fs_z", > + "tdm_c_sclk_a", "tdm_c_fs_a", > + "tdm_c_sclk_z", "tdm_c_fs_z", > + "tdm_c_din0_a", "tdm_c_din1_a", > + "tdm_c_din2_a", "tdm_c_din3_a", > + "tdm_c_din0_z", "tdm_c_din1_z", > + "tdm_c_din2_z", "tdm_c_din3_z", > + "tdm_c_dout0_a", "tdm_c_dout1_a", > + "tdm_c_dout2_a", "tdm_c_dout3_a", > + "tdm_c_dout0_z", "tdm_c_dout1_z", > + "tdm_c_dout2_z", "tdm_c_dout3_z", > +}; > + > +static const char * const gpio_aobus_groups[] = { > + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", > + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", > + "GPIOAO_10", "GPIOAO_11", "GPIOE_0", "GPIOE_1", "GPIOE_2", > +}; > + > +static const char * const uart_ao_a_groups[] = { > + "uart_ao_a_tx", "uart_ao_a_rx", > + "uart_ao_a_cts", "uart_ao_a_rts", > +}; > + > +static const char * const uart_ao_b_groups[] = { > + "uart_ao_b_tx_2", "uart_ao_b_rx_3", > + "uart_ao_b_tx_8", "uart_ao_b_rx_9", > + "uart_ao_b_cts", "uart_ao_b_rts", > +}; > + > +static const char * const i2c_ao_groups[] = { > + "i2c_ao_sck", "i2c_ao_sda", > + "i2c_ao_sck_e", "i2c_ao_sda_e", > +}; > + > +static const char * const i2c_ao_slave_groups[] = { > + "i2c_ao_slave_sck", "i2c_ao_slave_sda", > +}; > + > +static const char * const remote_ao_input_groups[] = { > + "remote_ao_input", > +}; > + > +static const char * const remote_ao_out_groups[] = { > + "remote_ao_out", > +}; > + > +static const char * const pwm_ao_a_groups[] = { > + "pwm_ao_a", "pwm_ao_a_hiz", > +}; > + > +static const char * const pwm_ao_b_groups[] = { > + "pwm_ao_b", > +}; > + > +static const char * const pwm_ao_c_groups[] = { > + "pwm_ao_c_4", "pwm_ao_c_hiz", > + "pwm_ao_c_6", > +}; > + > +static const char * const pwm_ao_d_groups[] = { > + "pwm_ao_d_5", "pwm_ao_d_10", "pwm_ao_d_e", > +}; > + > +static const char * const jtag_a_groups[] = { > + "jtag_a_tdi", "jtag_a_tdo", "jtag_a_clk", "jtag_a_tms", > +}; > + > +static const char * const cec_ao_a_groups[] = { > + "cec_ao_a", > +}; > + > +static const char * const cec_ao_b_groups[] = { > + "cec_ao_b", > +}; > + > +static const char * const tsin_ao_a_groups[] = { > + "tsin_ao_asop", "tsin_ao_adin0", "tsin_ao_aclk", "tsin_ao_a_valid", > +}; > + > +static const char * const spdif_ao_out_groups[] = { > + "spdif_ao_out", > +}; > + > +static const char * const tdm_ao_b_groups[] = { > + "tdm_ao_b_dout0", "tdm_ao_b_dout1", "tdm_ao_b_dout2", > + "tdm_ao_b_fs", "tdm_ao_b_sclk", > + "tdm_ao_b_din0", "tdm_ao_b_din1", "tdm_ao_b_din2", > + "tdm_ao_b_slv_fs", "tdm_ao_b_slv_sclk", > +}; > + > +static const char * const mclk0_ao_groups[] = { > + "mclk0_ao", > +}; > + > +static struct meson_pmx_func meson_g12a_periphs_functions[] = { > + FUNCTION(gpio_periphs), > + FUNCTION(emmc), > + FUNCTION(nor), > + FUNCTION(spi0), > + FUNCTION(spi1), > + FUNCTION(sdio), > + FUNCTION(nand), > + FUNCTION(sdcard), > + FUNCTION(i2c0), > + FUNCTION(i2c1), > + FUNCTION(i2c2), > + FUNCTION(i2c3), > + FUNCTION(uart_a), > + FUNCTION(uart_b), > + FUNCTION(uart_c), > + FUNCTION(uart_ao_a_c), > + FUNCTION(iso7816), > + FUNCTION(eth), > + FUNCTION(pwm_a), > + FUNCTION(pwm_b), > + FUNCTION(pwm_c), > + FUNCTION(pwm_d), > + FUNCTION(pwm_e), > + FUNCTION(pwm_f), > + FUNCTION(cec_ao_a_h), > + FUNCTION(cec_ao_b_h), > + FUNCTION(jtag_b), > + FUNCTION(bt565_a), > + FUNCTION(tsin_a), > + FUNCTION(tsin_b), > + FUNCTION(hdmitx), > + FUNCTION(pdm), > + FUNCTION(spdif_out), > + FUNCTION(spdif_in), > + FUNCTION(mclk0), > + FUNCTION(mclk1), > + FUNCTION(tdm_a), > + FUNCTION(tdm_b), > + FUNCTION(tdm_c), > +}; > + > +static struct meson_pmx_func meson_g12a_aobus_functions[] = { > + FUNCTION(gpio_aobus), > + FUNCTION(uart_ao_a), > + FUNCTION(uart_ao_b), > + FUNCTION(i2c_ao), > + FUNCTION(i2c_ao_slave), > + FUNCTION(remote_ao_input), > + FUNCTION(remote_ao_out), > + FUNCTION(pwm_ao_a), > + FUNCTION(pwm_ao_b), > + FUNCTION(pwm_ao_c), > + FUNCTION(pwm_ao_d), > + FUNCTION(jtag_a), > + FUNCTION(cec_ao_a), > + FUNCTION(cec_ao_b), > + FUNCTION(tsin_ao_a), > + FUNCTION(spdif_ao_out), > + FUNCTION(tdm_ao_b), > + FUNCTION(mclk0_ao), > +}; > + > +static struct meson_bank meson_g12a_periphs_banks[] = { > + /* name first last pullen pull dir out in */ > + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), > + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_8, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), > + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), > + BANK("C", PIN(GPIOC_0, EE_OFF), PIN(GPIOC_7, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), > + BANK("A", PIN(GPIOA_0, EE_OFF), PIN(GPIOA_15, EE_OFF), 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), > + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_19, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), > +}; > + > +static struct meson_bank meson_g12a_aobus_banks[] = { > + /* name first last pullen pull dir out in */ > + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_11, 0), 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), > + BANK("E", PIN(GPIOE_0, 0), PIN(GPIOE_2, 0), 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), > +}; > + > +static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { > + /* name first lask reg offset */ > + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), > + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), > + BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0), > + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), > + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xd, 0), > + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), > +}; > + > +static struct meson_axg_pmx_data meson_g12a_periphs_pmx_banks_data = { > + .pmx_banks = meson_g12a_periphs_pmx_banks, > + .num_pmx_banks = ARRAY_SIZE(meson_g12a_periphs_pmx_banks), > +}; > + > +static struct meson_pmx_bank meson_g12a_aobus_pmx_banks[] = { > + BANK_PMX("AO", GPIOAO_0, GPIOAO_11, 0x0, 0), > + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x1, 16), > +}; > + > +static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { > + .pmx_banks = meson_g12a_aobus_pmx_banks, > + .num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks), > +}; > + > +static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = { > + .name = "periphs-banks", > + .pin_base = EE_OFF, > + .groups = meson_g12a_periphs_groups, > + .funcs = meson_g12a_periphs_functions, > + .banks = meson_g12a_periphs_banks, > + .num_pins = 85, > + .num_groups = ARRAY_SIZE(meson_g12a_periphs_groups), > + .num_funcs = ARRAY_SIZE(meson_g12a_periphs_functions), > + .num_banks = ARRAY_SIZE(meson_g12a_periphs_banks), > + .gpio_driver = &meson_axg_gpio_driver, > + .pmx_data = &meson_g12a_periphs_pmx_banks_data, > +}; > + > +static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { > + .name = "aobus-banks", > + .pin_base = 0, > + .groups = meson_g12a_aobus_groups, > + .funcs = meson_g12a_aobus_functions, > + .banks = meson_g12a_aobus_banks, > + .num_pins = 15, > + .num_groups = ARRAY_SIZE(meson_g12a_aobus_groups), > + .num_funcs = ARRAY_SIZE(meson_g12a_aobus_functions), > + .num_banks = ARRAY_SIZE(meson_g12a_aobus_banks), > + .gpio_driver = &meson_axg_gpio_driver, > + .pmx_data = &meson_g12a_aobus_pmx_banks_data, > +}; > + > +static const struct udevice_id meson_g12a_pinctrl_match[] = { > + { > + .compatible = "amlogic,meson-g12a-periphs-pinctrl", > + .data = (ulong)&meson_g12a_periphs_pinctrl_data, > + }, > + { > + .compatible = "amlogic,meson-g12a-aobus-pinctrl", > + .data = (ulong)&meson_g12a_aobus_pinctrl_data, > + }, > + { }, > +}; > + > +U_BOOT_DRIVER(meson_axg_pinctrl) = { > + .name = "meson-g12a-pinctrl", > + .id = UCLASS_PINCTRL, > + .of_match = of_match_ptr(meson_g12a_pinctrl_match), > + .probe = meson_pinctrl_probe, > + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), > + .ops = &meson_axg_pinctrl_ops, > +}; > diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c > index fa3d78858a..8735418c5b 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson.c > +++ b/drivers/pinctrl/meson/pinctrl-meson.c > @@ -314,11 +314,11 @@ int meson_pinctrl_probe(struct udevice *dev) > priv->reg_gpio = (void __iomem *)addr; > > addr = parse_address(gpio, "pull", na, ns); > - if (addr == FDT_ADDR_T_NONE) { > - debug("pull address not found\n"); > - return -EINVAL; > - } > - priv->reg_pull = (void __iomem *)addr; > + /* Use gpio region if pull one is not present */ > + if (addr == FDT_ADDR_T_NONE) > + priv->reg_pull = priv->reg_gpio; > + else > + priv->reg_pull = (void __iomem *)addr; > > addr = parse_address(gpio, "pull-enable", na, ns); > /* Use pull region if pull-enable one is not present */ > @@ -327,6 +327,13 @@ int meson_pinctrl_probe(struct udevice *dev) > else > priv->reg_pullen = (void __iomem *)addr; > > + addr = parse_address(gpio, "ds", na, ns); > + /* Drive strength region is optional */ > + if (addr == FDT_ADDR_T_NONE) > + priv->reg_ds = NULL; > + else > + priv->reg_ds = (void __iomem *)addr; > + > priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev); > > /* Lookup GPIO driver */ > diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h > index 28085a7495..b3683e2073 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson.h > +++ b/drivers/pinctrl/meson/pinctrl-meson.h > @@ -41,6 +41,7 @@ struct meson_pinctrl { > void __iomem *reg_gpio; > void __iomem *reg_pull; > void __iomem *reg_pullen; > + void __iomem *reg_ds; > }; > > /** > This also need fixing like AXG, I will resend with the same fix. Neil ^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 2/6] clk: create meson directory and move related drivers 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot From: Jerome Brunet <jbrunet@baylibre.com> In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- MAINTAINERS | 2 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 +- drivers/clk/meson/Kconfig | 15 +++++++++++++++ drivers/clk/meson/Makefile | 8 ++++++++ drivers/clk/{clk_meson_axg.c => meson/axg.c} | 0 drivers/clk/{ => meson}/clk_meson.h | 0 drivers/clk/{clk_meson.c => meson/gxbb.c} | 0 8 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/meson/Kconfig create mode 100644 drivers/clk/meson/Makefile rename drivers/clk/{clk_meson_axg.c => meson/axg.c} (100%) rename drivers/clk/{ => meson}/clk_meson.h (100%) rename drivers/clk/{clk_meson.c => meson/gxbb.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 8a4c5d4eab..845ecca758 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -93,7 +93,7 @@ L: u-boot-amlogic at groups.io T: git git://git.denx.de/u-boot-amlogic.git F: arch/arm/mach-meson/ F: arch/arm/include/asm/arch-meson/ -F: drivers/clk/clk_meson* +F: drivers/clk/meson/ F: drivers/serial/serial_meson.c F: drivers/reset/reset-meson.c F: drivers/i2c/meson_i2c.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ff60fc5c45..96969b9e30 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -101,6 +101,7 @@ config CLK_STM32MP1 source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" +source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 1d9d725cae..719b9b8e02 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,7 +12,7 @@ obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ -obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o +obj-$(CONFIG_ARCH_MESON) += meson/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig new file mode 100644 index 0000000000..2419a30dcb --- /dev/null +++ b/drivers/clk/meson/Kconfig @@ -0,0 +1,15 @@ +config CLK_MESON_GX + bool "Enable clock support for Amlogic GX" + depends on CLK && ARCH_MESON + default MESON_GX + help + Enable clock support for the Amlogic GX SoC family, such as + the S905, S905X/D and S912. + +config CLK_MESON_AXG + bool "Enable clock support for Amlogic AXG" + depends on CLK && ARCH_MESON + default MESON_AXG + help + Enable clock support for the Amlogic AXG SoC family, such as + the A113X/D diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile new file mode 100644 index 0000000000..47a5ad588e --- /dev/null +++ b/drivers/clk/meson/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2019 Baylibre, SAS +# Jerome Brunet <jbrunet@baylibre.com> + +obj-$(CONFIG_CLK_MESON_GX) += gxbb.o +obj-$(CONFIG_CLK_MESON_AXG) += axg.o + diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/meson/axg.c similarity index 100% rename from drivers/clk/clk_meson_axg.c rename to drivers/clk/meson/axg.c diff --git a/drivers/clk/clk_meson.h b/drivers/clk/meson/clk_meson.h similarity index 100% rename from drivers/clk/clk_meson.h rename to drivers/clk/meson/clk_meson.h diff --git a/drivers/clk/clk_meson.c b/drivers/clk/meson/gxbb.c similarity index 100% rename from drivers/clk/clk_meson.c rename to drivers/clk/meson/gxbb.c -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/6] clk: create meson directory and move related drivers @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, sjg, Neil Armstrong From: Jerome Brunet <jbrunet@baylibre.com> In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- MAINTAINERS | 2 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 +- drivers/clk/meson/Kconfig | 15 +++++++++++++++ drivers/clk/meson/Makefile | 8 ++++++++ drivers/clk/{clk_meson_axg.c => meson/axg.c} | 0 drivers/clk/{ => meson}/clk_meson.h | 0 drivers/clk/{clk_meson.c => meson/gxbb.c} | 0 8 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/meson/Kconfig create mode 100644 drivers/clk/meson/Makefile rename drivers/clk/{clk_meson_axg.c => meson/axg.c} (100%) rename drivers/clk/{ => meson}/clk_meson.h (100%) rename drivers/clk/{clk_meson.c => meson/gxbb.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 8a4c5d4eab..845ecca758 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -93,7 +93,7 @@ L: u-boot-amlogic@groups.io T: git git://git.denx.de/u-boot-amlogic.git F: arch/arm/mach-meson/ F: arch/arm/include/asm/arch-meson/ -F: drivers/clk/clk_meson* +F: drivers/clk/meson/ F: drivers/serial/serial_meson.c F: drivers/reset/reset-meson.c F: drivers/i2c/meson_i2c.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ff60fc5c45..96969b9e30 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -101,6 +101,7 @@ config CLK_STM32MP1 source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" +source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 1d9d725cae..719b9b8e02 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,7 +12,7 @@ obj-y += imx/ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ -obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o +obj-$(CONFIG_ARCH_MESON) += meson/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig new file mode 100644 index 0000000000..2419a30dcb --- /dev/null +++ b/drivers/clk/meson/Kconfig @@ -0,0 +1,15 @@ +config CLK_MESON_GX + bool "Enable clock support for Amlogic GX" + depends on CLK && ARCH_MESON + default MESON_GX + help + Enable clock support for the Amlogic GX SoC family, such as + the S905, S905X/D and S912. + +config CLK_MESON_AXG + bool "Enable clock support for Amlogic AXG" + depends on CLK && ARCH_MESON + default MESON_AXG + help + Enable clock support for the Amlogic AXG SoC family, such as + the A113X/D diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile new file mode 100644 index 0000000000..47a5ad588e --- /dev/null +++ b/drivers/clk/meson/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2019 Baylibre, SAS +# Jerome Brunet <jbrunet@baylibre.com> + +obj-$(CONFIG_CLK_MESON_GX) += gxbb.o +obj-$(CONFIG_CLK_MESON_AXG) += axg.o + diff --git a/drivers/clk/clk_meson_axg.c b/drivers/clk/meson/axg.c similarity index 100% rename from drivers/clk/clk_meson_axg.c rename to drivers/clk/meson/axg.c diff --git a/drivers/clk/clk_meson.h b/drivers/clk/meson/clk_meson.h similarity index 100% rename from drivers/clk/clk_meson.h rename to drivers/clk/meson/clk_meson.h diff --git a/drivers/clk/clk_meson.c b/drivers/clk/meson/gxbb.c similarity index 100% rename from drivers/clk/clk_meson.c rename to drivers/clk/meson/gxbb.c -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 3/6] clk: meson: add g12a support 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot From: Jerome Brunet <jbrunet@baylibre.com> Add basic support for the Amlogic G12A clock controller based on the AXG driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/include/asm/arch-meson/clock-g12a.h | 104 ++++++ drivers/clk/meson/Kconfig | 8 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/g12a.c | 315 +++++++++++++++++++ 4 files changed, 428 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/clock-g12a.h create mode 100644 drivers/clk/meson/g12a.c diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h new file mode 100644 index 0000000000..d52e27e008 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-g12a.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#ifndef _ARCH_MESON_CLOCK_G12A_H_ +#define _ARCH_MESON_CLOCK_G12A_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00C +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04C +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05C +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09C +#define HHI_PCIE_PLL_CNTL2 0x0A0 +#define HHI_PCIE_PLL_CNTL3 0x0A4 +#define HHI_PCIE_PLL_CNTL4 0x0A8 +#define HHI_PCIE_PLL_CNTL5 0x0AC +#define HHI_PCIE_PLL_STS 0x0B8 +#define HHI_HIFI_PLL_CNTL0 0x0D8 +#define HHI_HIFI_PLL_CNTL1 0x0DC +#define HHI_HIFI_PLL_CNTL2 0x0E0 +#define HHI_HIFI_PLL_CNTL3 0x0E4 +#define HHI_HIFI_PLL_CNTL4 0x0E8 +#define HHI_HIFI_PLL_CNTL5 0x0EC +#define HHI_HIFI_PLL_CNTL6 0x0F0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12C +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1A0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_HDMI_CLK_CNTL 0x1CC +#define HHI_VDEC_CLK_CNTL 0x1E0 +#define HHI_VDEC2_CLK_CNTL 0x1E4 +#define HHI_VDEC3_CLK_CNTL 0x1E8 +#define HHI_VDEC4_CLK_CNTL 0x1EC +#define HHI_HDCP22_CLK_CNTL 0x1F0 +#define HHI_VAPBCLK_CNTL 0x1F4 +#define HHI_VPU_CLKB_CNTL 0x20C +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27C +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2A0 +#define HHI_FIX_PLL_CNTL1 0x2A4 +#define HHI_FIX_PLL_CNTL3 0x2AC +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc + +#endif diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 2419a30dcb..994b44ad7a 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -13,3 +13,11 @@ config CLK_MESON_AXG help Enable clock support for the Amlogic AXG SoC family, such as the A113X/D + +config CLK_MESON_G12A + bool "Enable clock support for Amlogic G12A" + depends on CLK && ARCH_MESON + default MESON_G12A + help + Enable clock support for the Amlogic G12A SoC family, such as + the S905X/D2 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 47a5ad588e..c873d6976f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_CLK_MESON_GX) += gxbb.o obj-$(CONFIG_CLK_MESON_AXG) += axg.o +obj-$(CONFIG_CLK_MESON_G12A) += g12a.o diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c new file mode 100644 index 0000000000..fedc9eb7dd --- /dev/null +++ b/drivers/clk/meson/g12a.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/clock-g12a.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <div64.h> +#include <dt-bindings/clock/g12a-clkc.h> +#include "clk_meson.h" + +#define XTAL_RATE 24000000 + +struct meson_clk { + struct regmap *map; +}; + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); + +#define NUM_CLKS 178 + +static struct meson_gate gates[NUM_CLKS] = { + /* Everything Else (EE) domain gates */ + MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8), + MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9), + MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13), + MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14), + MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25), + MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26), + MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3), + MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16), + + /* Peripheral Gates */ + MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23), + MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7), +}; + +static int meson_set_gate(struct clk *clk, bool on) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct meson_gate *gate; + + if (clk->id >= ARRAY_SIZE(gates)) + return -ENOENT; + + gate = &gates[clk->id]; + + if (gate->reg == 0) + return 0; + + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); + + return 0; +} + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate(clk, true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate(clk, false); +} + +static unsigned long meson_clk81_get_rate(struct clk *clk) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned long parent_rate; + uint reg; + int parents[] = { + -1, + -1, + CLKID_FCLK_DIV7, + CLKID_MPLL1, + CLKID_MPLL2, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5 + }; + + /* mux */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = (reg >> 12) & 7; + + switch (reg) { + case 0: + parent_rate = XTAL_RATE; + break; + case 1: + return -ENOENT; + default: + parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]); + } + + /* divider */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = reg & ((1 << 7) - 1); + + return parent_rate / reg; +} + +static long mpll_rate_from_params(unsigned long parent_rate, + unsigned long sdm, + unsigned long n2) +{ + unsigned long divisor = (SDM_DEN * n2) + sdm; + + if (n2 < N2_MIN) + return -EINVAL; + + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); +} + +static struct parm meson_mpll0_parm[2] = { + {HHI_MPLL_CNTL1, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */ +}; + +static struct parm meson_mpll1_parm[2] = { + {HHI_MPLL_CNTL3, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */ +}; + +static struct parm meson_mpll2_parm[2] = { + {HHI_MPLL_CNTL5, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */ +}; + +/* + * MultiPhase Locked Loops are outputs from a PLL with additional frequency + * scaling capabilities. MPLL rates are calculated as: + * + * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) + */ +static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *psdm, *pn2; + unsigned long sdm, n2; + unsigned long parent_rate; + uint reg; + + switch (id) { + case CLKID_MPLL0: + psdm = &meson_mpll0_parm[0]; + pn2 = &meson_mpll0_parm[1]; + break; + case CLKID_MPLL1: + psdm = &meson_mpll1_parm[0]; + pn2 = &meson_mpll1_parm[1]; + break; + case CLKID_MPLL2: + psdm = &meson_mpll2_parm[0]; + pn2 = &meson_mpll2_parm[1]; + break; + default: + return -ENOENT; + } + + parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; + + regmap_read(priv->map, psdm->reg_off, ®); + sdm = PARM_GET(psdm->width, psdm->shift, reg); + + regmap_read(priv->map, pn2->reg_off, ®); + n2 = PARM_GET(pn2->width, pn2->shift, reg); + + return mpll_rate_from_params(parent_rate, sdm, n2); +} + +static struct parm meson_fixed_pll_parm[3] = { + {HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */ + {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */ + {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */ + {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */ + {HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */ +}; + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = XTAL_RATE / 1000000; + u16 n, m, od; + uint reg; + + /* + * FIXME: Between the unit conversion and the missing frac, we know + * rate will be slightly off ... + */ + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + regmap_read(priv->map, pn->reg_off, ®); + n = PARM_GET(pn->width, pn->shift, reg); + + regmap_read(priv->map, pm->reg_off, ®); + m = PARM_GET(pm->width, pm->shift, reg); + + regmap_read(priv->map, pod->reg_off, ®); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) +{ + ulong rate; + + switch (id) { + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_MPLL0: + case CLKID_MPLL1: + case CLKID_MPLL2: + rate = meson_mpll_get_rate(clk, id); + break; + case CLKID_CLK81: + rate = meson_clk81_get_rate(clk); + break; + default: + if (gates[id].reg != 0) { + /* a clock gate */ + rate = meson_clk81_get_rate(clk); + break; + } + return -ENOENT; + } + + debug("clock %lu has rate %lu\n", id, rate); + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + debug("meson-clk-g12a: probed\n"); + + return 0; +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, +}; + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,g12a-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk_g12a) = { + .name = "meson_clk_g12a", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/6] clk: meson: add g12a support @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, sjg, Neil Armstrong From: Jerome Brunet <jbrunet@baylibre.com> Add basic support for the Amlogic G12A clock controller based on the AXG driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/include/asm/arch-meson/clock-g12a.h | 104 ++++++ drivers/clk/meson/Kconfig | 8 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/g12a.c | 315 +++++++++++++++++++ 4 files changed, 428 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/clock-g12a.h create mode 100644 drivers/clk/meson/g12a.c diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h new file mode 100644 index 0000000000..d52e27e008 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/clock-g12a.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - AmLogic, Inc. + * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ +#ifndef _ARCH_MESON_CLOCK_G12A_H_ +#define _ARCH_MESON_CLOCK_G12A_H_ + +/* + * Clock controller register offsets + * + * Register offsets from the data sheet are listed in comment blocks below. + * Those offsets must be multiplied by 4 before adding them to the base address + * to get the right value + */ + +#define HHI_MIPI_CNTL0 0x000 +#define HHI_MIPI_CNTL1 0x004 +#define HHI_MIPI_CNTL2 0x008 +#define HHI_MIPI_STS 0x00C +#define HHI_GP0_PLL_CNTL0 0x040 +#define HHI_GP0_PLL_CNTL1 0x044 +#define HHI_GP0_PLL_CNTL2 0x048 +#define HHI_GP0_PLL_CNTL3 0x04C +#define HHI_GP0_PLL_CNTL4 0x050 +#define HHI_GP0_PLL_CNTL5 0x054 +#define HHI_GP0_PLL_CNTL6 0x058 +#define HHI_GP0_PLL_STS 0x05C +#define HHI_PCIE_PLL_CNTL0 0x098 +#define HHI_PCIE_PLL_CNTL1 0x09C +#define HHI_PCIE_PLL_CNTL2 0x0A0 +#define HHI_PCIE_PLL_CNTL3 0x0A4 +#define HHI_PCIE_PLL_CNTL4 0x0A8 +#define HHI_PCIE_PLL_CNTL5 0x0AC +#define HHI_PCIE_PLL_STS 0x0B8 +#define HHI_HIFI_PLL_CNTL0 0x0D8 +#define HHI_HIFI_PLL_CNTL1 0x0DC +#define HHI_HIFI_PLL_CNTL2 0x0E0 +#define HHI_HIFI_PLL_CNTL3 0x0E4 +#define HHI_HIFI_PLL_CNTL4 0x0E8 +#define HHI_HIFI_PLL_CNTL5 0x0EC +#define HHI_HIFI_PLL_CNTL6 0x0F0 +#define HHI_VIID_CLK_DIV 0x128 +#define HHI_VIID_CLK_CNTL 0x12C +#define HHI_GCLK_MPEG0 0x140 +#define HHI_GCLK_MPEG1 0x144 +#define HHI_GCLK_MPEG2 0x148 +#define HHI_GCLK_OTHER 0x150 +#define HHI_GCLK_OTHER2 0x154 +#define HHI_VID_CLK_DIV 0x164 +#define HHI_MPEG_CLK_CNTL 0x174 +#define HHI_AUD_CLK_CNTL 0x178 +#define HHI_VID_CLK_CNTL 0x17c +#define HHI_TS_CLK_CNTL 0x190 +#define HHI_VID_CLK_CNTL2 0x194 +#define HHI_SYS_CPU_CLK_CNTL0 0x19c +#define HHI_VID_PLL_CLK_DIV 0x1A0 +#define HHI_MALI_CLK_CNTL 0x1b0 +#define HHI_VPU_CLKC_CNTL 0x1b4 +#define HHI_VPU_CLK_CNTL 0x1bC +#define HHI_HDMI_CLK_CNTL 0x1CC +#define HHI_VDEC_CLK_CNTL 0x1E0 +#define HHI_VDEC2_CLK_CNTL 0x1E4 +#define HHI_VDEC3_CLK_CNTL 0x1E8 +#define HHI_VDEC4_CLK_CNTL 0x1EC +#define HHI_HDCP22_CLK_CNTL 0x1F0 +#define HHI_VAPBCLK_CNTL 0x1F4 +#define HHI_VPU_CLKB_CNTL 0x20C +#define HHI_GEN_CLK_CNTL 0x228 +#define HHI_VDIN_MEAS_CLK_CNTL 0x250 +#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 +#define HHI_NAND_CLK_CNTL 0x25C +#define HHI_SD_EMMC_CLK_CNTL 0x264 +#define HHI_MPLL_CNTL0 0x278 +#define HHI_MPLL_CNTL1 0x27C +#define HHI_MPLL_CNTL2 0x280 +#define HHI_MPLL_CNTL3 0x284 +#define HHI_MPLL_CNTL4 0x288 +#define HHI_MPLL_CNTL5 0x28c +#define HHI_MPLL_CNTL6 0x290 +#define HHI_MPLL_CNTL7 0x294 +#define HHI_MPLL_CNTL8 0x298 +#define HHI_FIX_PLL_CNTL0 0x2A0 +#define HHI_FIX_PLL_CNTL1 0x2A4 +#define HHI_FIX_PLL_CNTL3 0x2AC +#define HHI_SYS_PLL_CNTL0 0x2f4 +#define HHI_SYS_PLL_CNTL1 0x2f8 +#define HHI_SYS_PLL_CNTL2 0x2fc +#define HHI_SYS_PLL_CNTL3 0x300 +#define HHI_SYS_PLL_CNTL4 0x304 +#define HHI_SYS_PLL_CNTL5 0x308 +#define HHI_SYS_PLL_CNTL6 0x30c +#define HHI_HDMI_PLL_CNTL0 0x320 +#define HHI_HDMI_PLL_CNTL1 0x324 +#define HHI_HDMI_PLL_CNTL2 0x328 +#define HHI_HDMI_PLL_CNTL3 0x32c +#define HHI_HDMI_PLL_CNTL4 0x330 +#define HHI_HDMI_PLL_CNTL5 0x334 +#define HHI_HDMI_PLL_CNTL6 0x338 +#define HHI_SPICC_CLK_CNTL 0x3dc + +#endif diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 2419a30dcb..994b44ad7a 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -13,3 +13,11 @@ config CLK_MESON_AXG help Enable clock support for the Amlogic AXG SoC family, such as the A113X/D + +config CLK_MESON_G12A + bool "Enable clock support for Amlogic G12A" + depends on CLK && ARCH_MESON + default MESON_G12A + help + Enable clock support for the Amlogic G12A SoC family, such as + the S905X/D2 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 47a5ad588e..c873d6976f 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_CLK_MESON_GX) += gxbb.o obj-$(CONFIG_CLK_MESON_AXG) += axg.o +obj-$(CONFIG_CLK_MESON_G12A) += g12a.o diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c new file mode 100644 index 0000000000..fedc9eb7dd --- /dev/null +++ b/drivers/clk/meson/g12a.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/clock-g12a.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <div64.h> +#include <dt-bindings/clock/g12a-clkc.h> +#include "clk_meson.h" + +#define XTAL_RATE 24000000 + +struct meson_clk { + struct regmap *map; +}; + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); + +#define NUM_CLKS 178 + +static struct meson_gate gates[NUM_CLKS] = { + /* Everything Else (EE) domain gates */ + MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8), + MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9), + MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13), + MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 14), + MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25), + MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26), + MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3), + MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16), + + /* Peripheral Gates */ + MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23), + MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7), +}; + +static int meson_set_gate(struct clk *clk, bool on) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct meson_gate *gate; + + if (clk->id >= ARRAY_SIZE(gates)) + return -ENOENT; + + gate = &gates[clk->id]; + + if (gate->reg == 0) + return 0; + + regmap_update_bits(priv->map, gate->reg, + BIT(gate->bit), on ? BIT(gate->bit) : 0); + + return 0; +} + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate(clk, true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate(clk, false); +} + +static unsigned long meson_clk81_get_rate(struct clk *clk) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned long parent_rate; + uint reg; + int parents[] = { + -1, + -1, + CLKID_FCLK_DIV7, + CLKID_MPLL1, + CLKID_MPLL2, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5 + }; + + /* mux */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = (reg >> 12) & 7; + + switch (reg) { + case 0: + parent_rate = XTAL_RATE; + break; + case 1: + return -ENOENT; + default: + parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]); + } + + /* divider */ + regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®); + reg = reg & ((1 << 7) - 1); + + return parent_rate / reg; +} + +static long mpll_rate_from_params(unsigned long parent_rate, + unsigned long sdm, + unsigned long n2) +{ + unsigned long divisor = (SDM_DEN * n2) + sdm; + + if (n2 < N2_MIN) + return -EINVAL; + + return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); +} + +static struct parm meson_mpll0_parm[2] = { + {HHI_MPLL_CNTL1, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL1, 20, 9}, /* pn2 */ +}; + +static struct parm meson_mpll1_parm[2] = { + {HHI_MPLL_CNTL3, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL3, 20, 9}, /* pn2 */ +}; + +static struct parm meson_mpll2_parm[2] = { + {HHI_MPLL_CNTL5, 0, 14}, /* psdm */ + {HHI_MPLL_CNTL5, 20, 9}, /* pn2 */ +}; + +/* + * MultiPhase Locked Loops are outputs from a PLL with additional frequency + * scaling capabilities. MPLL rates are calculated as: + * + * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) + */ +static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *psdm, *pn2; + unsigned long sdm, n2; + unsigned long parent_rate; + uint reg; + + switch (id) { + case CLKID_MPLL0: + psdm = &meson_mpll0_parm[0]; + pn2 = &meson_mpll0_parm[1]; + break; + case CLKID_MPLL1: + psdm = &meson_mpll1_parm[0]; + pn2 = &meson_mpll1_parm[1]; + break; + case CLKID_MPLL2: + psdm = &meson_mpll2_parm[0]; + pn2 = &meson_mpll2_parm[1]; + break; + default: + return -ENOENT; + } + + parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; + + regmap_read(priv->map, psdm->reg_off, ®); + sdm = PARM_GET(psdm->width, psdm->shift, reg); + + regmap_read(priv->map, pn2->reg_off, ®); + n2 = PARM_GET(pn2->width, pn2->shift, reg); + + return mpll_rate_from_params(parent_rate, sdm, n2); +} + +static struct parm meson_fixed_pll_parm[3] = { + {HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */ + {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */ + {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */ + {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */ + {HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */ +}; + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = XTAL_RATE / 1000000; + u16 n, m, od; + uint reg; + + /* + * FIXME: Between the unit conversion and the missing frac, we know + * rate will be slightly off ... + */ + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + regmap_read(priv->map, pn->reg_off, ®); + n = PARM_GET(pn->width, pn->shift, reg); + + regmap_read(priv->map, pm->reg_off, ®); + m = PARM_GET(pm->width, pm->shift, reg); + + regmap_read(priv->map, pod->reg_off, ®); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) +{ + ulong rate; + + switch (id) { + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_MPLL0: + case CLKID_MPLL1: + case CLKID_MPLL2: + rate = meson_mpll_get_rate(clk, id); + break; + case CLKID_CLK81: + rate = meson_clk81_get_rate(clk); + break; + default: + if (gates[id].reg != 0) { + /* a clock gate */ + rate = meson_clk81_get_rate(clk); + break; + } + return -ENOENT; + } + + debug("clock %lu has rate %lu\n", id, rate); + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + debug("meson-clk-g12a: probed\n"); + + return 0; +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, +}; + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,g12a-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk_g12a) = { + .name = "meson_clk_g12a", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +}; -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 4/6] ARM: meson: add G12a support 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot From: Jerome Brunet <jbrunet@baylibre.com> Add support for the Amlogic G12A SoC, which is a mix between the new physical memory mapping of AXG and the functionnalities of the previous Amlogic GXL/GXM SoCs. To handle the internal ethernet PHY, the Amlogic G12A SoCs now embeds a dedicated PLL to feed the internal PHY. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/include/asm/arch-meson/g12a.h | 66 +++++++++++ arch/arm/mach-meson/Kconfig | 9 +- arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/board-g12a.c | 150 +++++++++++++++++++++++++ 4 files changed, 225 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-meson/g12a.h create mode 100644 arch/arm/mach-meson/board-g12a.c diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h new file mode 100644 index 0000000000..b806667860 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/g12a.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __G12A_H__ +#define __G12A_H__ + +#define G12A_AOBUS_BASE 0xff800000 +#define G12A_PERIPHS_BASE 0xff634400 +#define G12A_HIU_BASE 0xff63c000 +#define G12A_ETH_PHY_BASE 0xff64c000 +#define G12A_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) + +#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) +#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) +#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) +#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) + +#define G12A_AO_BOOT_DEVICE 0xF +#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_MEM_SIZE_SHIFT 16 +#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) + +#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) +#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) + +#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) +#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define G12A_ETH_REG_0_CLK_EN BIT(12) + +#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) +#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) +#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) +#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) +#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) +#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) +#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) +#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) +#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) +#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) +#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) +#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) + +/* HIU registers */ +#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) + +#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __G12A_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 1b1d0aef0d..e29e4c0acc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -41,7 +41,13 @@ config MESON_AXG bool "AXG" select MESON64_COMMON help - Select this if your SoC is an A113X/D + Select this if your SoC is an A113X/D + +config MESON_G12A + bool "G12A" + select MESON64_COMMON + help + Select this if your SoC is an S905X/D2 endchoice @@ -65,6 +71,7 @@ config SYS_BOARD default "p212" if MESON_GXL default "q200" if MESON_GXM default "s400" if MESON_AXG + default "u200" if MESON_G12A default "" help This option contains information about board name. diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 6ddfba606b..a9e4046f80 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -5,3 +5,4 @@ obj-y += board-common.o sm.o board-info.o obj-$(CONFIG_MESON_GX) += board-gx.o obj-$(CONFIG_MESON_AXG) += board-axg.o +obj-$(CONFIG_MESON_G12A) += board-g12a.o diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c new file mode 100644 index 0000000000..fc3764b960 --- /dev/null +++ b/arch/arm/mach-meson/board-g12a.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/boot.h> +#include <asm/arch/eth.h> +#include <asm/arch/g12a.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +int meson_get_boot_device(void) +{ + return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; +} + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(G12A_AO_SEC_GP_CFG3); + + bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK) + >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(G12A_AO_SEC_GP_CFG5); + bl32_start = readl(G12A_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) + >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region g12a_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = g12a_mem_map; + +static void g12a_enable_external_mdio(void) +{ + writel(0x0, ETH_PHY_CNTL2); +} + +static void g12a_enable_internal_mdio(void) +{ + /* Fire up the PHY PLL */ + writel(0x29c0040a, ETH_PLL_CNTL0); + writel(0x927e0000, ETH_PLL_CNTL1); + writel(0xac5f49e5, ETH_PLL_CNTL2); + writel(0x00000000, ETH_PLL_CNTL3); + writel(0x00000000, ETH_PLL_CNTL4); + writel(0x20200000, ETH_PLL_CNTL5); + writel(0x0000c002, ETH_PLL_CNTL6); + writel(0x00000023, ETH_PLL_CNTL7); + writel(0x39c0040a, ETH_PLL_CNTL0); + writel(0x19c0040a, ETH_PLL_CNTL0); + + /* Select the internal MDIO */ + writel(0x33000180, ETH_PHY_CNTL0); + writel(0x00074043, ETH_PHY_CNTL1); + writel(0x00000260, ETH_PHY_CNTL2); +} + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII | + G12A_ETH_REG_0_TX_PHASE(1) | + G12A_ETH_REG_0_TX_RATIO(4) | + G12A_ETH_REG_0_PHY_CLK_EN | + G12A_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII | + G12A_ETH_REG_0_INVERT_RMII_CLK | + G12A_ETH_REG_0_CLK_EN); + + /* Use G12A RMII Internal PHY */ + if (flags & MESON_USE_INTERNAL_RMII_PHY) + g12a_enable_internal_mdio(); + else + g12a_enable_external_mdio(); + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK); +} -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/6] ARM: meson: add G12a support @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, Neil Armstrong From: Jerome Brunet <jbrunet@baylibre.com> Add support for the Amlogic G12A SoC, which is a mix between the new physical memory mapping of AXG and the functionnalities of the previous Amlogic GXL/GXM SoCs. To handle the internal ethernet PHY, the Amlogic G12A SoCs now embeds a dedicated PLL to feed the internal PHY. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/include/asm/arch-meson/g12a.h | 66 +++++++++++ arch/arm/mach-meson/Kconfig | 9 +- arch/arm/mach-meson/Makefile | 1 + arch/arm/mach-meson/board-g12a.c | 150 +++++++++++++++++++++++++ 4 files changed, 225 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-meson/g12a.h create mode 100644 arch/arm/mach-meson/board-g12a.c diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h new file mode 100644 index 0000000000..b806667860 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/g12a.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef __G12A_H__ +#define __G12A_H__ + +#define G12A_AOBUS_BASE 0xff800000 +#define G12A_PERIPHS_BASE 0xff634400 +#define G12A_HIU_BASE 0xff63c000 +#define G12A_ETH_PHY_BASE 0xff64c000 +#define G12A_ETH_BASE 0xff3f0000 + +/* Always-On Peripherals registers */ +#define G12A_AO_ADDR(off) (G12A_AOBUS_BASE + ((off) << 2)) + +#define G12A_AO_SEC_GP_CFG0 G12A_AO_ADDR(0x90) +#define G12A_AO_SEC_GP_CFG3 G12A_AO_ADDR(0x93) +#define G12A_AO_SEC_GP_CFG4 G12A_AO_ADDR(0x94) +#define G12A_AO_SEC_GP_CFG5 G12A_AO_ADDR(0x95) + +#define G12A_AO_BOOT_DEVICE 0xF +#define G12A_AO_MEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_MEM_SIZE_SHIFT 16 +#define G12A_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 +#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16 +#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF + +/* Peripherals registers */ +#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2)) + +#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50) +#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51) + +#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0) +#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2) +#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) +#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) +#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10) +#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11) +#define G12A_ETH_REG_0_CLK_EN BIT(12) + +#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2)) +#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11) +#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12) +#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13) +#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14) +#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15) +#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16) +#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17) +#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18) +#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20) +#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21) +#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22) + +/* HIU registers */ +#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2)) + +#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40) + +/* Ethernet memory power domain */ +#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) + +#endif /* __G12A_H__ */ diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 1b1d0aef0d..e29e4c0acc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -41,7 +41,13 @@ config MESON_AXG bool "AXG" select MESON64_COMMON help - Select this if your SoC is an A113X/D + Select this if your SoC is an A113X/D + +config MESON_G12A + bool "G12A" + select MESON64_COMMON + help + Select this if your SoC is an S905X/D2 endchoice @@ -65,6 +71,7 @@ config SYS_BOARD default "p212" if MESON_GXL default "q200" if MESON_GXM default "s400" if MESON_AXG + default "u200" if MESON_G12A default "" help This option contains information about board name. diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 6ddfba606b..a9e4046f80 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -5,3 +5,4 @@ obj-y += board-common.o sm.o board-info.o obj-$(CONFIG_MESON_GX) += board-gx.o obj-$(CONFIG_MESON_AXG) += board-axg.o +obj-$(CONFIG_MESON_G12A) += board-g12a.o diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c new file mode 100644 index 0000000000..fc3764b960 --- /dev/null +++ b/arch/arm/mach-meson/board-g12a.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <asm/arch/boot.h> +#include <asm/arch/eth.h> +#include <asm/arch/g12a.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +int meson_get_boot_device(void) +{ + return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; +} + +/* Configure the reserved memory zones exported by the secure registers + * into EFI and DTB reserved memory entries. + */ +void meson_init_reserved_memory(void *fdt) +{ + u64 bl31_size, bl31_start; + u64 bl32_size, bl32_start; + u32 reg; + + /* + * Get ARM Trusted Firmware reserved memory zones in : + * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 + * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL + * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL + */ + reg = readl(G12A_AO_SEC_GP_CFG3); + + bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK) + >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; + bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; + + bl31_start = readl(G12A_AO_SEC_GP_CFG5); + bl32_start = readl(G12A_AO_SEC_GP_CFG4); + + /* Add BL31 reserved zone */ + if (bl31_start && bl31_size) + meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); + + /* Add BL32 reserved zone */ + if (bl32_start && bl32_size) + meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); +} + +phys_size_t get_effective_memsize(void) +{ + /* Size is reported in MiB, convert it in bytes */ + return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK) + >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M; +} + +static struct mm_region g12a_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = g12a_mem_map; + +static void g12a_enable_external_mdio(void) +{ + writel(0x0, ETH_PHY_CNTL2); +} + +static void g12a_enable_internal_mdio(void) +{ + /* Fire up the PHY PLL */ + writel(0x29c0040a, ETH_PLL_CNTL0); + writel(0x927e0000, ETH_PLL_CNTL1); + writel(0xac5f49e5, ETH_PLL_CNTL2); + writel(0x00000000, ETH_PLL_CNTL3); + writel(0x00000000, ETH_PLL_CNTL4); + writel(0x20200000, ETH_PLL_CNTL5); + writel(0x0000c002, ETH_PLL_CNTL6); + writel(0x00000023, ETH_PLL_CNTL7); + writel(0x39c0040a, ETH_PLL_CNTL0); + writel(0x19c0040a, ETH_PLL_CNTL0); + + /* Select the internal MDIO */ + writel(0x33000180, ETH_PHY_CNTL0); + writel(0x00074043, ETH_PHY_CNTL1); + writel(0x00000260, ETH_PHY_CNTL2); +} + +/* Configure the Ethernet MAC with the requested interface mode + * with some optional flags. + */ +void meson_eth_init(phy_interface_t mode, unsigned int flags) +{ + switch (mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Set RGMII mode */ + setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII | + G12A_ETH_REG_0_TX_PHASE(1) | + G12A_ETH_REG_0_TX_RATIO(4) | + G12A_ETH_REG_0_PHY_CLK_EN | + G12A_ETH_REG_0_CLK_EN); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Set RMII mode */ + out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII | + G12A_ETH_REG_0_INVERT_RMII_CLK | + G12A_ETH_REG_0_CLK_EN); + + /* Use G12A RMII Internal PHY */ + if (flags & MESON_USE_INTERNAL_RMII_PHY) + g12a_enable_internal_mdio(); + else + g12a_enable_external_mdio(); + + break; + + default: + printf("Invalid Ethernet interface mode\n"); + return; + } + + /* Enable power gate */ + clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK); +} -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 5/6] ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot Import Linux 5.1-rc1 DT from 9e98c678c2d6 ("Linux 5.1-rc1") for the meson-g12a-u200 board, the meson-g12a.dtsi and the corresponding bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/meson-g12a-u200.dts | 29 +++ arch/arm/dts/meson-g12a.dtsi | 192 ++++++++++++++++++ include/dt-bindings/clock/g12a-aoclkc.h | 34 ++++ include/dt-bindings/clock/g12a-clkc.h | 135 ++++++++++++ include/dt-bindings/gpio/meson-g12a-gpio.h | 114 +++++++++++ .../reset/amlogic,meson-g12a-reset.h | 134 ++++++++++++ include/dt-bindings/reset/g12a-aoclkc.h | 18 ++ 8 files changed, 658 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/meson-g12a-u200.dts create mode 100644 arch/arm/dts/meson-g12a.dtsi create mode 100644 include/dt-bindings/clock/g12a-aoclkc.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h create mode 100644 include/dt-bindings/reset/amlogic,meson-g12a-reset.h create mode 100644 include/dt-bindings/reset/g12a-aoclkc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ab2fc795c0..dbf81d1f04 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -104,7 +104,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxm-khadas-vim2.dtb \ - meson-axg-s400.dtb + meson-axg-s400.dtb \ + meson-g12a-u200.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts new file mode 100644 index 0000000000..c44dbdddf2 --- /dev/null +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" + +/ { + compatible = "amlogic,u200", "amlogic,g12a"; + model = "Amlogic Meson G12A U200 Development Board"; + + aliases { + serial0 = &uart_AO; + }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory at 0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; + diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi new file mode 100644 index 0000000000..17c6217f8a --- /dev/null +++ b/arch/arm/dts/meson-g12a.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "amlogic,g12a"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon at 5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb: bus at ff600000 { + compatible = "simple-bus"; + reg = <0x0 0xff600000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; + + periphs: bus at 34400 { + compatible = "simple-bus"; + reg = <0x0 0x34400 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; + }; + + hiu: bus at 3c000 { + compatible = "simple-bus"; + reg = <0x0 0x3c000 0x0 0x1400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller at 0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; + }; + }; + + aobus: bus at ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + uart_AO: serial at 3000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial at 4000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + gic: interrupt-controller at ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus at ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + + clk_msr: clock-measure at 18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + +}; diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100644 index 0000000000..8db01ffbeb --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai <qiufang.dai@amlogic.com> + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB 0 +#define CLKID_AO_IR_IN 1 +#define CLKID_AO_I2C_M0 2 +#define CLKID_AO_I2C_S0 3 +#define CLKID_AO_UART 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_OUT 7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_MAILBOX 9 +#define CLKID_AO_M3 10 +#define CLKID_AO_AHB_SRAM 11 +#define CLKID_AO_RTI 12 +#define CLKID_AO_M4_FCLK 13 +#define CLKID_AO_M4_HCLK 14 +#define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_CLK 18 +#define CLKID_AO_32K 23 +#define CLKID_AO_CEC 27 +#define CLKID_AO_CTS_RTC_OSCIN 28 + +#endif diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 0000000000..83b657038d --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST 18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL301 21 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART0 28 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE 30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A 33 +#define CLKID_SD_EMMC_B 34 +#define CLKID_SD_EMMC_C 35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO 37 +#define CLKID_ETH 38 +#define CLKID_DEMUX 39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART1 42 +#define CLKID_G2D 43 +#define CLKID_RESET 44 +#define CLKID_PCIE_COMB 45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT656 54 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART2 57 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_A_CLK0 60 +#define CLKID_SD_EMMC_B_CLK0 61 +#define CLKID_SD_EMMC_C_CLK0 62 +#define CLKID_HIFI_PLL 74 +#define CLKID_VCLK2_VENCI0 80 +#define CLKID_VCLK2_VENCI1 81 +#define CLKID_VCLK2_VENCP0 82 +#define CLKID_VCLK2_VENCP1 83 +#define CLKID_VCLK2_VENCT0 84 +#define CLKID_VCLK2_VENCT1 85 +#define CLKID_VCLK2_OTHER 86 +#define CLKID_VCLK2_ENCI 87 +#define CLKID_VCLK2_ENCP 88 +#define CLKID_DAC_CLK 89 +#define CLKID_AOCLK 90 +#define CLKID_IEC958 91 +#define CLKID_ENC480P 92 +#define CLKID_RNG1 93 +#define CLKID_VCLK2_ENCT 94 +#define CLKID_VCLK2_ENCL 95 +#define CLKID_VCLK2_VENCLMMC 96 +#define CLKID_VCLK2_VENCL 97 +#define CLKID_VCLK2_OTHER1 98 +#define CLKID_FCLK_DIV2P5 99 +#define CLKID_DMA 105 +#define CLKID_EFUSE 106 +#define CLKID_ROM_BOOT 107 +#define CLKID_RESET_SEC 108 +#define CLKID_SEC_AHB_APB3 109 +#define CLKID_VPU_0_SEL 110 +#define CLKID_VPU_0 112 +#define CLKID_VPU_1_SEL 113 +#define CLKID_VPU_1 115 +#define CLKID_VPU 116 +#define CLKID_VAPB_0_SEL 117 +#define CLKID_VAPB_0 119 +#define CLKID_VAPB_1_SEL 120 +#define CLKID_VAPB_1 122 +#define CLKID_VAPB_SEL 123 +#define CLKID_VAPB 124 +#define CLKID_HDMI_PLL 128 +#define CLKID_VID_PLL 129 +#define CLKID_VCLK 138 +#define CLKID_VCLK2 139 +#define CLKID_VCLK_DIV1 148 +#define CLKID_VCLK_DIV2 149 +#define CLKID_VCLK_DIV4 150 +#define CLKID_VCLK_DIV6 151 +#define CLKID_VCLK_DIV12 152 +#define CLKID_VCLK2_DIV1 153 +#define CLKID_VCLK2_DIV2 154 +#define CLKID_VCLK2_DIV4 155 +#define CLKID_VCLK2_DIV6 156 +#define CLKID_VCLK2_DIV12 157 +#define CLKID_CTS_ENCI 162 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_VDAC 164 +#define CLKID_HDMI_TX 165 +#define CLKID_HDMI 168 +#define CLKID_MALI_0_SEL 169 +#define CLKID_MALI_0 171 +#define CLKID_MALI_1_SEL 172 +#define CLKID_MALI_1 174 +#define CLKID_MALI 175 +#define CLKID_MPLL_5OM 177 + +#endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h new file mode 100644 index 0000000000..f7bd69350d --- /dev/null +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +#define _DT_BINDINGS_MESON_G12A_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define BOOT_0 25 +#define BOOT_1 26 +#define BOOT_2 27 +#define BOOT_3 28 +#define BOOT_4 29 +#define BOOT_5 30 +#define BOOT_6 31 +#define BOOT_7 32 +#define BOOT_8 33 +#define BOOT_9 34 +#define BOOT_10 35 +#define BOOT_11 36 +#define BOOT_12 37 +#define BOOT_13 38 +#define BOOT_14 39 +#define BOOT_15 40 +#define GPIOC_0 41 +#define GPIOC_1 42 +#define GPIOC_2 43 +#define GPIOC_3 44 +#define GPIOC_4 45 +#define GPIOC_5 46 +#define GPIOC_6 47 +#define GPIOC_7 48 +#define GPIOA_0 49 +#define GPIOA_1 50 +#define GPIOA_2 51 +#define GPIOA_3 52 +#define GPIOA_4 53 +#define GPIOA_5 54 +#define GPIOA_6 55 +#define GPIOA_7 56 +#define GPIOA_8 57 +#define GPIOA_9 58 +#define GPIOA_10 59 +#define GPIOA_11 60 +#define GPIOA_12 61 +#define GPIOA_13 62 +#define GPIOA_14 63 +#define GPIOA_15 64 +#define GPIOX_0 65 +#define GPIOX_1 66 +#define GPIOX_2 67 +#define GPIOX_3 68 +#define GPIOX_4 69 +#define GPIOX_5 70 +#define GPIOX_6 71 +#define GPIOX_7 72 +#define GPIOX_8 73 +#define GPIOX_9 74 +#define GPIOX_10 75 +#define GPIOX_11 76 +#define GPIOX_12 77 +#define GPIOX_13 78 +#define GPIOX_14 79 +#define GPIOX_15 80 +#define GPIOX_16 81 +#define GPIOX_17 82 +#define GPIOX_18 83 +#define GPIOX_19 84 + +#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h new file mode 100644 index 0000000000..8063e8314e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS 2 +/* 3-4 */ +#define RESET_VIU 5 +#define RESET_AFIFO 6 +#define RESET_VID_PLL_DIV 7 +/* 8-9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_PCIE_CTRL_A 12 +#define RESET_VCBUS 13 +#define RESET_PCIE_PHY 14 +#define RESET_PCIE_APB 15 +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18 */ +#define RESET_HDMITX_CAPB3 19 +#define RESET_DVALIN_CAPB3 20 +#define RESET_DOS_CAPB3 21 +/* 22 */ +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +/* 27-31 */ +/* RESET1 */ +/* 32 */ +#define RESET_DEMUX 33 +#define RESET_USB 34 +#define RESET_DDR 35 +/* 36 */ +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +/* 41 */ +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +/* 47-60 */ +#define RESET_AUDIO_CODEC 61 +/* 62-63 */ +/* RESET2 */ +/* 64 */ +#define RESET_AUDIO 65 +#define RESET_HDMITX_PHY 66 +/* 67 */ +#define RESET_MIPI_DSI_HOST 68 +#define RESET_ALOCKER 69 +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75-77 */ +#define RESET_DVALIN 78 +#define RESET_HDMITX 79 +/* 80-95 */ +/* RESET3 */ +/* 96-95 */ +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES_PL 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_0 109 +#define RESET_DEMUX_1 110 +#define RESET_DEMUX_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128-129 */ +#define RESET_MIPI_DSI_PHY 130 +/* 131-132 */ +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +/* 138-139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_M1 142 +#define RESET_I2C_M2 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_GEN 192 +#define RESET_SPICC0 193 +#define RESET_SC 194 +#define RESET_SANA_3 195 +#define RESET_I2C_M0 196 +#define RESET_TS_PLL 197 +#define RESET_SPICC1 198 +#define RESET_STREAM 199 +#define RESET_TS_CPU 200 +#define RESET_UART0 201 +#define RESET_UART1_2 202 +#define RESET_ASYNC0 203 +#define RESET_ASYNC1 204 +#define RESET_SPIFC0 205 +#define RESET_I2C_M3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +#define RESET_TS_GPU 228 +#define RESET_DEVICE_MMC_ARB 229 +#define RESET_DVALIN_DMC_PIPL 230 +#define RESET_VID_LOCK 231 +#define RESET_NIC_DMC_PIPL 232 +#define RESET_DMC_VPU_PIPL 233 +#define RESET_GE2D_DMC_PIPL 234 +#define RESET_HCODEC_DMC_PIPL 235 +#define RESET_WAVE420_DMC_PIPL 236 +#define RESET_HEVCF_DMC_PIPL 237 +/* 238-255 */ + +#endif diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h new file mode 100644 index 0000000000..bd2e233713 --- /dev/null +++ b/include/dt-bindings/reset/g12a-aoclkc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK + +#define RESET_AO_IR_IN 0 +#define RESET_AO_UART 1 +#define RESET_AO_I2C_M 2 +#define RESET_AO_I2C_S 3 +#define RESET_AO_SAR_ADC 4 +#define RESET_AO_UART2 5 +#define RESET_AO_IR_OUT 6 + +#endif -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/6] ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1 @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Neil Armstrong, u-boot Import Linux 5.1-rc1 DT from 9e98c678c2d6 ("Linux 5.1-rc1") for the meson-g12a-u200 board, the meson-g12a.dtsi and the corresponding bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/meson-g12a-u200.dts | 29 +++ arch/arm/dts/meson-g12a.dtsi | 192 ++++++++++++++++++ include/dt-bindings/clock/g12a-aoclkc.h | 34 ++++ include/dt-bindings/clock/g12a-clkc.h | 135 ++++++++++++ include/dt-bindings/gpio/meson-g12a-gpio.h | 114 +++++++++++ .../reset/amlogic,meson-g12a-reset.h | 134 ++++++++++++ include/dt-bindings/reset/g12a-aoclkc.h | 18 ++ 8 files changed, 658 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/meson-g12a-u200.dts create mode 100644 arch/arm/dts/meson-g12a.dtsi create mode 100644 include/dt-bindings/clock/g12a-aoclkc.h create mode 100644 include/dt-bindings/clock/g12a-clkc.h create mode 100644 include/dt-bindings/gpio/meson-g12a-gpio.h create mode 100644 include/dt-bindings/reset/amlogic,meson-g12a-reset.h create mode 100644 include/dt-bindings/reset/g12a-aoclkc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ab2fc795c0..dbf81d1f04 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -104,7 +104,8 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxm-khadas-vim2.dtb \ - meson-axg-s400.dtb + meson-axg-s400.dtb \ + meson-g12a-u200.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts new file mode 100644 index 0000000000..c44dbdddf2 --- /dev/null +++ b/arch/arm/dts/meson-g12a-u200.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-g12a.dtsi" + +/ { + compatible = "amlogic,u200", "amlogic,g12a"; + model = "Amlogic Meson G12A U200 Development Board"; + + aliases { + serial0 = &uart_AO; + }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; + diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi new file mode 100644 index 0000000000..17c6217f8a --- /dev/null +++ b/arch/arm/dts/meson-g12a.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "amlogic,g12a"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb: bus@ff600000 { + compatible = "simple-bus"; + reg = <0x0 0xff600000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; + + periphs: bus@34400 { + compatible = "simple-bus"; + reg = <0x0 0x34400 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; + }; + + hiu: bus@3c000 { + compatible = "simple-bus"; + reg = <0x0 0x3c000 0x0 0x1400>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; + + hhi: system-controller@0 { + compatible = "amlogic,meson-gx-hhi-sysctrl", + "simple-mfd", "syscon"; + reg = <0 0 0 0x400>; + + clkc: clock-controller { + compatible = "amlogic,g12a-clkc"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + }; + }; + }; + + aobus: bus@ff800000 { + compatible = "simple-bus"; + reg = <0x0 0xff800000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; + + uart_AO: serial@3000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x3000 0x0 0x18>; + interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x4000 0x0 0x18>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ffc01000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + cbus: bus@ffd00000 { + compatible = "simple-bus"; + reg = <0x0 0xffd00000 0x0 0x100000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + + clk_msr: clock-measure@18000 { + compatible = "amlogic,meson-g12a-clk-measure"; + reg = <0x0 0x18000 0x0 0x10>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + +}; diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h new file mode 100644 index 0000000000..8db01ffbeb --- /dev/null +++ b/include/dt-bindings/clock/g12a-aoclkc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai <qiufang.dai@amlogic.com> + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK + +#define CLKID_AO_AHB 0 +#define CLKID_AO_IR_IN 1 +#define CLKID_AO_I2C_M0 2 +#define CLKID_AO_I2C_S0 3 +#define CLKID_AO_UART 4 +#define CLKID_AO_PROD_I2C 5 +#define CLKID_AO_UART2 6 +#define CLKID_AO_IR_OUT 7 +#define CLKID_AO_SAR_ADC 8 +#define CLKID_AO_MAILBOX 9 +#define CLKID_AO_M3 10 +#define CLKID_AO_AHB_SRAM 11 +#define CLKID_AO_RTI 12 +#define CLKID_AO_M4_FCLK 13 +#define CLKID_AO_M4_HCLK 14 +#define CLKID_AO_CLK81 15 +#define CLKID_AO_SAR_ADC_CLK 18 +#define CLKID_AO_32K 23 +#define CLKID_AO_CEC 27 +#define CLKID_AO_CTS_RTC_OSCIN 28 + +#endif diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h new file mode 100644 index 0000000000..83b657038d --- /dev/null +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * Meson-G12A clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + */ + +#ifndef __G12A_CLKC_H +#define __G12A_CLKC_H + +#define CLKID_SYS_PLL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV4 4 +#define CLKID_FCLK_DIV5 5 +#define CLKID_FCLK_DIV7 6 +#define CLKID_GP0_PLL 7 +#define CLKID_CLK81 10 +#define CLKID_MPLL0 11 +#define CLKID_MPLL1 12 +#define CLKID_MPLL2 13 +#define CLKID_MPLL3 14 +#define CLKID_DDR 15 +#define CLKID_DOS 16 +#define CLKID_AUDIO_LOCKER 17 +#define CLKID_MIPI_DSI_HOST 18 +#define CLKID_ETH_PHY 19 +#define CLKID_ISA 20 +#define CLKID_PL301 21 +#define CLKID_PERIPHS 22 +#define CLKID_SPICC0 23 +#define CLKID_I2C 24 +#define CLKID_SANA 25 +#define CLKID_SD 26 +#define CLKID_RNG0 27 +#define CLKID_UART0 28 +#define CLKID_SPICC1 29 +#define CLKID_HIU_IFACE 30 +#define CLKID_MIPI_DSI_PHY 31 +#define CLKID_ASSIST_MISC 32 +#define CLKID_SD_EMMC_A 33 +#define CLKID_SD_EMMC_B 34 +#define CLKID_SD_EMMC_C 35 +#define CLKID_AUDIO_CODEC 36 +#define CLKID_AUDIO 37 +#define CLKID_ETH 38 +#define CLKID_DEMUX 39 +#define CLKID_AUDIO_IFIFO 40 +#define CLKID_ADC 41 +#define CLKID_UART1 42 +#define CLKID_G2D 43 +#define CLKID_RESET 44 +#define CLKID_PCIE_COMB 45 +#define CLKID_PARSER 46 +#define CLKID_USB 47 +#define CLKID_PCIE_PHY 48 +#define CLKID_AHB_ARB0 49 +#define CLKID_AHB_DATA_BUS 50 +#define CLKID_AHB_CTRL_BUS 51 +#define CLKID_HTX_HDCP22 52 +#define CLKID_HTX_PCLK 53 +#define CLKID_BT656 54 +#define CLKID_USB1_DDR_BRIDGE 55 +#define CLKID_MMC_PCLK 56 +#define CLKID_UART2 57 +#define CLKID_VPU_INTR 58 +#define CLKID_GIC 59 +#define CLKID_SD_EMMC_A_CLK0 60 +#define CLKID_SD_EMMC_B_CLK0 61 +#define CLKID_SD_EMMC_C_CLK0 62 +#define CLKID_HIFI_PLL 74 +#define CLKID_VCLK2_VENCI0 80 +#define CLKID_VCLK2_VENCI1 81 +#define CLKID_VCLK2_VENCP0 82 +#define CLKID_VCLK2_VENCP1 83 +#define CLKID_VCLK2_VENCT0 84 +#define CLKID_VCLK2_VENCT1 85 +#define CLKID_VCLK2_OTHER 86 +#define CLKID_VCLK2_ENCI 87 +#define CLKID_VCLK2_ENCP 88 +#define CLKID_DAC_CLK 89 +#define CLKID_AOCLK 90 +#define CLKID_IEC958 91 +#define CLKID_ENC480P 92 +#define CLKID_RNG1 93 +#define CLKID_VCLK2_ENCT 94 +#define CLKID_VCLK2_ENCL 95 +#define CLKID_VCLK2_VENCLMMC 96 +#define CLKID_VCLK2_VENCL 97 +#define CLKID_VCLK2_OTHER1 98 +#define CLKID_FCLK_DIV2P5 99 +#define CLKID_DMA 105 +#define CLKID_EFUSE 106 +#define CLKID_ROM_BOOT 107 +#define CLKID_RESET_SEC 108 +#define CLKID_SEC_AHB_APB3 109 +#define CLKID_VPU_0_SEL 110 +#define CLKID_VPU_0 112 +#define CLKID_VPU_1_SEL 113 +#define CLKID_VPU_1 115 +#define CLKID_VPU 116 +#define CLKID_VAPB_0_SEL 117 +#define CLKID_VAPB_0 119 +#define CLKID_VAPB_1_SEL 120 +#define CLKID_VAPB_1 122 +#define CLKID_VAPB_SEL 123 +#define CLKID_VAPB 124 +#define CLKID_HDMI_PLL 128 +#define CLKID_VID_PLL 129 +#define CLKID_VCLK 138 +#define CLKID_VCLK2 139 +#define CLKID_VCLK_DIV1 148 +#define CLKID_VCLK_DIV2 149 +#define CLKID_VCLK_DIV4 150 +#define CLKID_VCLK_DIV6 151 +#define CLKID_VCLK_DIV12 152 +#define CLKID_VCLK2_DIV1 153 +#define CLKID_VCLK2_DIV2 154 +#define CLKID_VCLK2_DIV4 155 +#define CLKID_VCLK2_DIV6 156 +#define CLKID_VCLK2_DIV12 157 +#define CLKID_CTS_ENCI 162 +#define CLKID_CTS_ENCP 163 +#define CLKID_CTS_VDAC 164 +#define CLKID_HDMI_TX 165 +#define CLKID_HDMI 168 +#define CLKID_MALI_0_SEL 169 +#define CLKID_MALI_0 171 +#define CLKID_MALI_1_SEL 172 +#define CLKID_MALI_1 174 +#define CLKID_MALI 175 +#define CLKID_MPLL_5OM 177 + +#endif /* __G12A_CLKC_H */ diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h new file mode 100644 index 0000000000..f7bd69350d --- /dev/null +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +#define _DT_BINDINGS_MESON_G12A_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define BOOT_0 25 +#define BOOT_1 26 +#define BOOT_2 27 +#define BOOT_3 28 +#define BOOT_4 29 +#define BOOT_5 30 +#define BOOT_6 31 +#define BOOT_7 32 +#define BOOT_8 33 +#define BOOT_9 34 +#define BOOT_10 35 +#define BOOT_11 36 +#define BOOT_12 37 +#define BOOT_13 38 +#define BOOT_14 39 +#define BOOT_15 40 +#define GPIOC_0 41 +#define GPIOC_1 42 +#define GPIOC_2 43 +#define GPIOC_3 44 +#define GPIOC_4 45 +#define GPIOC_5 46 +#define GPIOC_6 47 +#define GPIOC_7 48 +#define GPIOA_0 49 +#define GPIOA_1 50 +#define GPIOA_2 51 +#define GPIOA_3 52 +#define GPIOA_4 53 +#define GPIOA_5 54 +#define GPIOA_6 55 +#define GPIOA_7 56 +#define GPIOA_8 57 +#define GPIOA_9 58 +#define GPIOA_10 59 +#define GPIOA_11 60 +#define GPIOA_12 61 +#define GPIOA_13 62 +#define GPIOA_14 63 +#define GPIOA_15 64 +#define GPIOX_0 65 +#define GPIOX_1 66 +#define GPIOX_2 67 +#define GPIOX_3 68 +#define GPIOX_4 69 +#define GPIOX_5 70 +#define GPIOX_6 71 +#define GPIOX_7 72 +#define GPIOX_8 73 +#define GPIOX_9 74 +#define GPIOX_10 75 +#define GPIOX_11 76 +#define GPIOX_12 77 +#define GPIOX_13 78 +#define GPIOX_14 79 +#define GPIOX_15 80 +#define GPIOX_16 81 +#define GPIOX_17 82 +#define GPIOX_18 83 +#define GPIOX_19 84 + +#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h new file mode 100644 index 0000000000..8063e8314e --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H + +/* RESET0 */ +#define RESET_HIU 0 +/* 1 */ +#define RESET_DOS 2 +/* 3-4 */ +#define RESET_VIU 5 +#define RESET_AFIFO 6 +#define RESET_VID_PLL_DIV 7 +/* 8-9 */ +#define RESET_VENC 10 +#define RESET_ASSIST 11 +#define RESET_PCIE_CTRL_A 12 +#define RESET_VCBUS 13 +#define RESET_PCIE_PHY 14 +#define RESET_PCIE_APB 15 +#define RESET_GIC 16 +#define RESET_CAPB3_DECODE 17 +/* 18 */ +#define RESET_HDMITX_CAPB3 19 +#define RESET_DVALIN_CAPB3 20 +#define RESET_DOS_CAPB3 21 +/* 22 */ +#define RESET_CBUS_CAPB3 23 +#define RESET_AHB_CNTL 24 +#define RESET_AHB_DATA 25 +#define RESET_VCBUS_CLK81 26 +/* 27-31 */ +/* RESET1 */ +/* 32 */ +#define RESET_DEMUX 33 +#define RESET_USB 34 +#define RESET_DDR 35 +/* 36 */ +#define RESET_BT656 37 +#define RESET_AHB_SRAM 38 +/* 39 */ +#define RESET_PARSER 40 +/* 41 */ +#define RESET_ISA 42 +#define RESET_ETHERNET 43 +#define RESET_SD_EMMC_A 44 +#define RESET_SD_EMMC_B 45 +#define RESET_SD_EMMC_C 46 +/* 47-60 */ +#define RESET_AUDIO_CODEC 61 +/* 62-63 */ +/* RESET2 */ +/* 64 */ +#define RESET_AUDIO 65 +#define RESET_HDMITX_PHY 66 +/* 67 */ +#define RESET_MIPI_DSI_HOST 68 +#define RESET_ALOCKER 69 +#define RESET_GE2D 70 +#define RESET_PARSER_REG 71 +#define RESET_PARSER_FETCH 72 +#define RESET_CTL 73 +#define RESET_PARSER_TOP 74 +/* 75-77 */ +#define RESET_DVALIN 78 +#define RESET_HDMITX 79 +/* 80-95 */ +/* RESET3 */ +/* 96-95 */ +#define RESET_DEMUX_TOP 105 +#define RESET_DEMUX_DES_PL 106 +#define RESET_DEMUX_S2P_0 107 +#define RESET_DEMUX_S2P_1 108 +#define RESET_DEMUX_0 109 +#define RESET_DEMUX_1 110 +#define RESET_DEMUX_2 111 +/* 112-127 */ +/* RESET4 */ +/* 128-129 */ +#define RESET_MIPI_DSI_PHY 130 +/* 131-132 */ +#define RESET_RDMA 133 +#define RESET_VENCI 134 +#define RESET_VENCP 135 +/* 136 */ +#define RESET_VDAC 137 +/* 138-139 */ +#define RESET_VDI6 140 +#define RESET_VENCL 141 +#define RESET_I2C_M1 142 +#define RESET_I2C_M2 143 +/* 144-159 */ +/* RESET5 */ +/* 160-191 */ +/* RESET6 */ +#define RESET_GEN 192 +#define RESET_SPICC0 193 +#define RESET_SC 194 +#define RESET_SANA_3 195 +#define RESET_I2C_M0 196 +#define RESET_TS_PLL 197 +#define RESET_SPICC1 198 +#define RESET_STREAM 199 +#define RESET_TS_CPU 200 +#define RESET_UART0 201 +#define RESET_UART1_2 202 +#define RESET_ASYNC0 203 +#define RESET_ASYNC1 204 +#define RESET_SPIFC0 205 +#define RESET_I2C_M3 206 +/* 207-223 */ +/* RESET7 */ +#define RESET_USB_DDR_0 224 +#define RESET_USB_DDR_1 225 +#define RESET_USB_DDR_2 226 +#define RESET_USB_DDR_3 227 +#define RESET_TS_GPU 228 +#define RESET_DEVICE_MMC_ARB 229 +#define RESET_DVALIN_DMC_PIPL 230 +#define RESET_VID_LOCK 231 +#define RESET_NIC_DMC_PIPL 232 +#define RESET_DMC_VPU_PIPL 233 +#define RESET_GE2D_DMC_PIPL 234 +#define RESET_HCODEC_DMC_PIPL 235 +#define RESET_WAVE420_DMC_PIPL 236 +#define RESET_HEVCF_DMC_PIPL 237 +/* 238-255 */ + +#endif diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h new file mode 100644 index 0000000000..bd2e233713 --- /dev/null +++ b/include/dt-bindings/reset/g12a-aoclkc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK + +#define RESET_AO_IR_IN 0 +#define RESET_AO_UART 1 +#define RESET_AO_I2C_M 2 +#define RESET_AO_I2C_S 3 +#define RESET_AO_SAR_ADC 4 +#define RESET_AO_UART2 5 +#define RESET_AO_IR_OUT 6 + +#endif -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 6/6] boards: meson: add g12a u200 2019-03-26 15:02 ` Neil Armstrong @ 2019-03-26 15:02 ` Neil Armstrong -1 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot From: Jerome Brunet <jbrunet@baylibre.com> The Amlogic U200 board is based on the Amlogic S905D2 SoC from the Amlogic G12A SoC family. The board has the following specifications : - Amlogic S905D2 ARM Cortex-A53 quad-core SoC - XGB DDR4 SDRAM - 10/100 Ethernet (Internal PHY) - 1 x USB 3.0 Host - eMMC - SDcard - Infrared receiver - SDIO WiFi Module - MIPI DSI Connector - Audio HAT Connector - PCI-E M.2 Connector Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- board/amlogic/u200/MAINTAINERS | 5 ++ board/amlogic/u200/Makefile | 6 ++ board/amlogic/u200/README | 128 +++++++++++++++++++++++++++++++++ board/amlogic/u200/u200.c | 22 ++++++ configs/u200_defconfig | 40 +++++++++++ 5 files changed, 201 insertions(+) create mode 100644 board/amlogic/u200/MAINTAINERS create mode 100644 board/amlogic/u200/Makefile create mode 100644 board/amlogic/u200/README create mode 100644 board/amlogic/u200/u200.c create mode 100644 configs/u200_defconfig diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS new file mode 100644 index 0000000000..baf3813fd0 --- /dev/null +++ b/board/amlogic/u200/MAINTAINERS @@ -0,0 +1,5 @@ +U200 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/u200/ +F: configs/u200_defconfig diff --git a/board/amlogic/u200/Makefile b/board/amlogic/u200/Makefile new file mode 100644 index 0000000000..485791bbb2 --- /dev/null +++ b/board/amlogic/u200/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := u200.o diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README new file mode 100644 index 0000000000..bffac5e7ae --- /dev/null +++ b/board/amlogic/u200/README @@ -0,0 +1,128 @@ +U-Boot for Amlogic U200 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905D2 ARM Cortex-A53 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + - Regulators + - Clock controller + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make u200_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + > cd amlogic-u-boot + > make g12a_u200_v1_defconfig + > make + > export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + > cp $FIPDIR/g12a/ddr3_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_2d.fw fip/ + > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + > cp $FIPDIR/g12a/piei.fw fip/ + > cp u-boot.bin fip/bl33.bin + + > sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c new file mode 100644 index 0000000000..94ee3ce6e4 --- /dev/null +++ b/board/amlogic/u200/u200.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/axg.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +int misc_init_r(void) +{ + meson_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_USE_INTERNAL_RMII_PHY); + + return 0; +} diff --git a/configs/u200_defconfig b/configs/u200_defconfig new file mode 100644 index 0000000000..c351913f0e --- /dev/null +++ b/configs/u200_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" u200" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/6] boards: meson: add g12a u200 @ 2019-03-26 15:02 ` Neil Armstrong 0 siblings, 0 replies; 16+ messages in thread From: Neil Armstrong @ 2019-03-26 15:02 UTC (permalink / raw) To: u-boot-amlogic; +Cc: Jerome Brunet, u-boot, Neil Armstrong From: Jerome Brunet <jbrunet@baylibre.com> The Amlogic U200 board is based on the Amlogic S905D2 SoC from the Amlogic G12A SoC family. The board has the following specifications : - Amlogic S905D2 ARM Cortex-A53 quad-core SoC - XGB DDR4 SDRAM - 10/100 Ethernet (Internal PHY) - 1 x USB 3.0 Host - eMMC - SDcard - Infrared receiver - SDIO WiFi Module - MIPI DSI Connector - Audio HAT Connector - PCI-E M.2 Connector Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- board/amlogic/u200/MAINTAINERS | 5 ++ board/amlogic/u200/Makefile | 6 ++ board/amlogic/u200/README | 128 +++++++++++++++++++++++++++++++++ board/amlogic/u200/u200.c | 22 ++++++ configs/u200_defconfig | 40 +++++++++++ 5 files changed, 201 insertions(+) create mode 100644 board/amlogic/u200/MAINTAINERS create mode 100644 board/amlogic/u200/Makefile create mode 100644 board/amlogic/u200/README create mode 100644 board/amlogic/u200/u200.c create mode 100644 configs/u200_defconfig diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS new file mode 100644 index 0000000000..baf3813fd0 --- /dev/null +++ b/board/amlogic/u200/MAINTAINERS @@ -0,0 +1,5 @@ +U200 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/u200/ +F: configs/u200_defconfig diff --git a/board/amlogic/u200/Makefile b/board/amlogic/u200/Makefile new file mode 100644 index 0000000000..485791bbb2 --- /dev/null +++ b/board/amlogic/u200/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := u200.o diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README new file mode 100644 index 0000000000..bffac5e7ae --- /dev/null +++ b/board/amlogic/u200/README @@ -0,0 +1,128 @@ +U-Boot for Amlogic U200 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905D2 ARM Cortex-A53 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + - Regulators + - Clock controller + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make u200_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + > cd amlogic-u-boot + > make g12a_u200_v1_defconfig + > make + > export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + > cp $FIPDIR/g12a/ddr3_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_2d.fw fip/ + > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + > cp $FIPDIR/g12a/piei.fw fip/ + > cp u-boot.bin fip/bl33.bin + + > sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c new file mode 100644 index 0000000000..94ee3ce6e4 --- /dev/null +++ b/board/amlogic/u200/u200.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/axg.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +int misc_init_r(void) +{ + meson_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_USE_INTERNAL_RMII_PHY); + + return 0; +} diff --git a/configs/u200_defconfig b/configs/u200_defconfig new file mode 100644 index 0000000000..c351913f0e --- /dev/null +++ b/configs/u200_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_MESON_G12A=y +CONFIG_DEBUG_UART_BASE=0xff803000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" u200" +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_BOARD_SETUP=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_G12A=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.21.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-04-10 14:57 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-03-26 15:02 [U-Boot] [PATCH 0/6] ARM: meson: Add support for G12A based U200 board Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 1/6] pinctrl: meson: add g12a support Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-04-10 14:57 ` [U-Boot] " Neil Armstrong 2019-04-10 14:57 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 2/6] clk: create meson directory and move related drivers Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 3/6] clk: meson: add g12a support Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 4/6] ARM: meson: add G12a support Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 5/6] ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1 Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong 2019-03-26 15:02 ` [U-Boot] [PATCH 6/6] boards: meson: add g12a u200 Neil Armstrong 2019-03-26 15:02 ` Neil Armstrong
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