[PATCH 0/4] Device id consolidation

[PATCH 0/4] Device id consolidation

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Series removes device id checks from i915_drv.h macros and consolidates them to
i915_pciids.h as the main "database", while making intel_device_info.c reference
the former, expanding the existing concept of a platform mask by a few low bits
reserved for sub-platform mask.

This has a two-fold positive effect of firstly consolidating the list of device
ids to one location, and secondly removing the if-ladders from every
IS_<platfrom>_<subplatform> call site.

Maintenance burden is not completely removed but should be improved. One case in
point is that I have found some disagreements between device id listed in
i915_pciids.h and i915_drv.h.

At the same time platform mask code is generalized to an array of u32 to
accomodate the addition of EHL and avoid spilling into u64 which would cause a
small code size increase. Downside is that any platforms on the u32 boundary,
like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE ||
IS_ELKHARTLAKE" checks into a single conditional, although at the moment there
aren't any such call-sites.

Before vs after for the whole series:

   text    data     bss     dec     hex filename
1891093   43903    7424 1942420  1da394 i915.ko.0
1890434   43903    7424 1941761  1da101 i915.ko.1

add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205)
...
Total: Before=1286293, After=1286498, chg +0.02%

Tvrtko Ursulin (4):
  drm/i915: Split Pineview device info into desktop and mobile
  drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
  drm/i915: Split some PCI ids into separate groups
  drm/i915: Introduce concept of a sub-platform

 arch/x86/kernel/early-quirks.c           |   3 +-
 drivers/gpu/drm/i915/i915_drv.c          |   8 +-
 drivers/gpu/drm/i915/i915_drv.h          | 133 +++++++++++------
 drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
 drivers/gpu/drm/i915/i915_pci.c          |  14 +-
 drivers/gpu/drm/i915/intel_device_info.c | 145 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  27 +++-
 drivers/gpu/drm/i915/intel_pm.c          |   4 +-
 include/drm/i915_pciids.h                | 179 ++++++++++++++++-------
 9 files changed, 414 insertions(+), 102 deletions(-)

-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/4] drm/i915: Split Pineview device info into desktop and mobile

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This allows the IS_PINEVIEW_<G|M> macros to be removed and avoid
duplication of device ids already defined in i915_pciids.h.

!IS_MOBILE check can be used in place of existing IS_PINEVIEW_G call
sites.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 arch/x86/kernel/early-quirks.c  |  3 ++-
 drivers/gpu/drm/i915/i915_drv.h |  2 --
 drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++--
 drivers/gpu/drm/i915/intel_pm.c |  4 ++--
 include/drm/i915_pciids.h       |  6 ++++--
 5 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 50d5848bf22e..f91d3ed2df62 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -525,7 +525,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_I945G_IDS(&gen3_early_ops),
 	INTEL_I945GM_IDS(&gen3_early_ops),
 	INTEL_VLV_IDS(&gen6_early_ops),
-	INTEL_PINEVIEW_IDS(&gen3_early_ops),
+	INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
+	INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
 	INTEL_I965G_IDS(&gen3_early_ops),
 	INTEL_G33_IDS(&gen3_early_ops),
 	INTEL_I965GM_IDS(&gen3_early_ops),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e30f7b19b51..084a36120d5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2313,8 +2313,6 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
 #define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
 #define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 #define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7e1611af26d..716f2f95c57d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -257,7 +257,14 @@ static const struct intel_device_info intel_g33_info = {
 	.display.has_overlay = 1,
 };
 
-static const struct intel_device_info intel_pineview_info = {
+static const struct intel_device_info intel_pineview_g_info = {
+	GEN3_FEATURES,
+	PLATFORM(INTEL_PINEVIEW),
+	.display.has_hotplug = 1,
+	.display.has_overlay = 1,
+};
+
+static const struct intel_device_info intel_pineview_m_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
 	.is_mobile = 1,
@@ -761,7 +768,8 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_I965GM_IDS(&intel_i965gm_info),
 	INTEL_GM45_IDS(&intel_gm45_info),
 	INTEL_G45_IDS(&intel_g45_info),
-	INTEL_PINEVIEW_IDS(&intel_pineview_info),
+	INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
+	INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a9fff971129e..6dbc30395d3c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -850,7 +850,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
 	u32 reg;
 	unsigned int wm;
 
-	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
+	latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 					 dev_priv->is_ddr3,
 					 dev_priv->fsb_freq,
 					 dev_priv->mem_freq);
@@ -9589,7 +9589,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		dev_priv->display.initial_watermarks = g4x_initial_watermarks;
 		dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
 	} else if (IS_PINEVIEW(dev_priv)) {
-		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
+		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 					    dev_priv->is_ddr3,
 					    dev_priv->fsb_freq,
 					    dev_priv->mem_freq)) {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index c7cdbfc4d033..cb9b5b35aa2c 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -108,8 +108,10 @@
 	INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
 	INTEL_VGA_DEVICE(0x2e92, info)	/* B43_G.1 */
 
-#define INTEL_PINEVIEW_IDS(info)			\
-	INTEL_VGA_DEVICE(0xa001, info),			\
+#define INTEL_PINEVIEW_G_IDS(info) \
+	INTEL_VGA_DEVICE(0xa001, info)
+
+#define INTEL_PINEVIEW_M_IDS(info) \
 	INTEL_VGA_DEVICE(0xa011, info)
 
 #define INTEL_IRONLAKE_D_IDS(info) \
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/4] drm/i915: Remove redundant device id from IS_IRONLAKE_M macro

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

IS_IRONLAKE_M can use the already defined intel_device_info.is_mobile for
this platform, so remove the instance of Ironlake's mobile device id from
the header file and replace it with an IS_MOBILE check.

v2:
 * Improved commit text. (Chris)

v3:
 * Rebased for EHL.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 084a36120d5a..48c3b139f36f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2300,6 +2300,8 @@ static inline unsigned int i915_sg_segment_size(void)
 
 #define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
 
+#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
+
 #define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
 #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
@@ -2315,7 +2317,9 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
 #define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
 #define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
+#define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
+#define IS_IRONLAKE_M(dev_priv) \
+	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 1)
@@ -2331,7 +2335,6 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
-#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/4] drm/i915: Split some PCI ids into separate groups

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This will enable the following patch to consolidate most device ids into
i915_pciids.h.

While cross-referencing the ids listed in i915_drv.h, with the ones listed
in i915_pciids.h, and also the comments in the latter, a bug for bug
approach was used. This means two things:

1.
Some ids are only present in i915_drv.h - obviously this means those parts
would not have been probed at all so they were not added to i915_pciids.h

2.
Some part type comments in i915_pciids.h were in disagreement with
i915_drv.h. For instance parts labeled as ULT or ULX were not considered
as such in i915_drv.h. The existing behaviour takes precedence here.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Jani Nikula <jani.nikula@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/i915_pciids.h | 173 +++++++++++++++++++++++++++-----------
 1 file changed, 124 insertions(+), 49 deletions(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index cb9b5b35aa2c..6477da22af28 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -168,7 +168,18 @@
 #define INTEL_IVB_Q_IDS(info) \
 	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
+
+#define INTEL_HSW_ULX_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
+
 #define INTEL_HSW_GT1_IDS(info) \
+	INTEL_HSW_ULT_GT1_IDS(info), \
+	INTEL_HSW_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 	INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
 	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
@@ -177,20 +188,26 @@
 	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
-	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
-	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
 	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
 
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
+
+#define INTEL_HSW_ULX_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
+
 #define INTEL_HSW_GT2_IDS(info) \
+	INTEL_HSW_ULT_GT2_IDS(info), \
+	INTEL_HSW_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 	INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
 	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
@@ -199,9 +216,6 @@
 	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
-	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
-	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
 	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
@@ -209,11 +223,17 @@
 	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
 
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */
+
 #define INTEL_HSW_GT3_IDS(info) \
+	INTEL_HSW_ULT_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
 	INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
 	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
@@ -222,16 +242,11 @@
 	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
-	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
-	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
 	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 
 #define INTEL_HSW_IDS(info) \
@@ -247,35 +262,59 @@
 	INTEL_VGA_DEVICE(0x0157, info), \
 	INTEL_VGA_DEVICE(0x0155, info)
 
-#define INTEL_BDW_GT1_IDS(info)  \
-	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+#define INTEL_BDW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
-	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
-	INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+	INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */
+
+#define INTEL_BDW_ULX_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */
+
+#define INTEL_BDW_GT1_IDS(info) \
+	INTEL_BDW_ULT_GT1_IDS(info), \
+	INTEL_BDW_ULX_GT1_IDS(info), \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */
 
-#define INTEL_BDW_GT2_IDS(info)  \
-	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
+#define INTEL_BDW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
-	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
-	INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
+	INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */
+
+#define INTEL_BDW_ULX_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
+
+#define INTEL_BDW_GT2_IDS(info) \
+	INTEL_BDW_ULT_GT2_IDS(info), \
+	INTEL_BDW_ULX_GT2_IDS(info), \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
+
+#define INTEL_BDW_ULX_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
+
 #define INTEL_BDW_GT3_IDS(info) \
+	INTEL_BDW_ULT_GT3_IDS(info), \
+	INTEL_BDW_ULX_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
-	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
-	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
-	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info)  /* Iris */
+
+#define INTEL_BDW_ULX_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x163E, info) /* ULX */
+
 #define INTEL_BDW_RSVD_IDS(info) \
+	INTEL_BDW_ULT_RSVD_IDS(info), \
+	INTEL_BDW_ULX_RSVD_IDS(info), \
 	INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
-	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
-	INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
-	INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
 	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 
@@ -291,25 +330,40 @@
 	INTEL_VGA_DEVICE(0x22b2, info), \
 	INTEL_VGA_DEVICE(0x22b3, info)
 
+#define INTEL_SKL_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
+
+#define INTEL_SKL_ULX_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
+
 #define INTEL_SKL_GT1_IDS(info)	\
-	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
-	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+	INTEL_SKL_ULT_GT1_IDS(info), \
+	INTEL_SKL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
 
-#define INTEL_SKL_GT2_IDS(info)	\
+#define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
-	INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
-	INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */
+
+#define INTEL_SKL_ULX_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */
+
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_SKL_ULT_GT2_IDS(info), \
+	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 
+#define INTEL_SKL_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
+
 #define INTEL_SKL_GT3_IDS(info) \
+	INTEL_SKL_ULT_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
 	INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
 	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
 	INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
@@ -338,29 +392,44 @@
 	INTEL_VGA_DEVICE(0x3184, info), \
 	INTEL_VGA_DEVICE(0x3185, info)
 
-#define INTEL_KBL_GT1_IDS(info)	\
-	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
-	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+#define INTEL_KBL_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */
+
+#define INTEL_KBL_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */
+
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_KBL_ULT_GT1_IDS(info), \
+	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
 
-#define INTEL_KBL_GT2_IDS(info)	\
+#define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */
+
+#define INTEL_KBL_ULX_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x591E, info)  /* ULX GT2 */
+
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_KBL_ULT_GT2_IDS(info), \
+	INTEL_KBL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
-	INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
-	INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 
+#define INTEL_KBL_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */
+
 #define INTEL_KBL_GT3_IDS(info) \
+	INTEL_KBL_ULT_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
 	INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
 
 #define INTEL_KBL_GT4_IDS(info) \
@@ -467,7 +536,14 @@
 	INTEL_CML_GT2_IDS(info)
 
 /* CNL */
+#define INTEL_CNL_PORT_F_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info), \
+	INTEL_VGA_DEVICE(0x5A44, info), \
+	INTEL_VGA_DEVICE(0x5A4C, info)
+
 #define INTEL_CNL_IDS(info) \
+	INTEL_CNL_PORT_F_IDS(info), \
 	INTEL_VGA_DEVICE(0x5A51, info), \
 	INTEL_VGA_DEVICE(0x5A59, info), \
 	INTEL_VGA_DEVICE(0x5A41, info), \
@@ -477,16 +553,11 @@
 	INTEL_VGA_DEVICE(0x5A42, info), \
 	INTEL_VGA_DEVICE(0x5A4A, info), \
 	INTEL_VGA_DEVICE(0x5A50, info), \
-	INTEL_VGA_DEVICE(0x5A40, info), \
-	INTEL_VGA_DEVICE(0x5A54, info), \
-	INTEL_VGA_DEVICE(0x5A5C, info), \
-	INTEL_VGA_DEVICE(0x5A44, info), \
-	INTEL_VGA_DEVICE(0x5A4C, info)
+	INTEL_VGA_DEVICE(0x5A40, info)
 
 /* ICL */
-#define INTEL_ICL_11_IDS(info) \
+#define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
-	INTEL_VGA_DEVICE(0x8A51, info), \
 	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info), \
 	INTEL_VGA_DEVICE(0x8A59, info),	\
@@ -500,6 +571,10 @@
 	INTEL_VGA_DEVICE(0x8A70, info), \
 	INTEL_VGA_DEVICE(0x8A53, info)
 
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_ICL_PORT_F_IDS(info), \
+	INTEL_VGA_DEVICE(0x8A51, info)
+
 /* EHL */
 #define INTEL_EHL_IDS(info) \
 	INTEL_VGA_DEVICE(0x4500, info),	\
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Concept of a sub-platform already exist in our code (like ULX and ULT
platform variants and similar),implemented via the macros which check a
list of device ids to determine a match.

With this patch we consolidate device ids checking into a single function
called during early driver load.

A few low bits in the platform mask are reserved for sub-platform
identification and defined as a per-platform namespace.

At the same time it future proofs the platform_mask handling by preparing
the code for easy extending, and tidies the very verbose WARN strings
generated when IS_PLATFORM macros are embedded into a WARN type
statements.

v2: Fixed IS_SUBPLATFORM. Updated commit msg.
v3: Chris was right, there is an ordering problem.

v4:
 * Catch-up with new sub-platforms.
 * Rebase for RUNTIME_INFO.
 * Drop subplatform mask union tricks and convert platform_mask to an
   array for extensibility.

v5:
 * Fix subplatform check.
 * Protect against forgetting to expand subplatform bits.
 * Remove platform enum tallying.
 * Add subplatform to error state. (Chris)
 * Drop macros and just use static inlines.
 * Remove redundant IRONLAKE_M. (Ville)

v6:
 * Split out Ironlake change.
 * Optimize subplatform check.
 * Use __always_inline. (Lucas)
 * Add platform_mask comment. (Paulo)
 * Pass stored runtime info in error capture. (Chris)

v7:
 * Rebased for new AML ULX device id.
 * Bump platform mask array size for EHL.
 * Stop mentioning device ids in intel_device_subplatform_init by using
   the trick of splitting macros i915_pciids.h. (Jani)
 * AML seems to be either a subplatform of KBL or CFL so express it like
   that.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
---
 drivers/gpu/drm/i915/i915_drv.c          |   8 +-
 drivers/gpu/drm/i915/i915_drv.h          | 124 +++++++++++++------
 drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
 drivers/gpu/drm/i915/i915_pci.c          |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 145 +++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
 6 files changed, 267 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5465b99b4392..74255374cc6b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 	if (i915_inject_load_failure())
 		return -ENODEV;
 
+	intel_device_info_subplatform_init(dev_priv);
+
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
 	mutex_init(&dev_priv->backlight_lock);
@@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 	if (drm_debug & DRM_UT_DRIVER) {
 		struct drm_printer p = drm_debug_printer("i915 device info:");
 
-		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
+		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 			   INTEL_DEVID(dev_priv),
 			   INTEL_REVID(dev_priv),
 			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
+			   intel_subplatform(RUNTIME_INFO(dev_priv),
+					     INTEL_INFO(dev_priv)->platform),
 			   INTEL_GEN(dev_priv));
 
 		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
@@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 	memcpy(device_info, match_info, sizeof(*device_info));
 	RUNTIME_INFO(i915)->device_id = pdev->device;
 
-	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-		     BITS_PER_TYPE(device_info->platform_mask));
 	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 
 	return i915;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48c3b139f36f..c29ebfd94065 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2298,7 +2298,68 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_REVID(p, since, until) \
 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
+static __always_inline unsigned int
+__platform_mask_index(const struct intel_runtime_info *info,
+		      enum intel_platform p)
+{
+	const unsigned int pbits =
+		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+	/* Expand the platform_mask array if this fails. */
+	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+		     pbits * ARRAY_SIZE(info->platform_mask));
+
+	return p / pbits;
+}
+
+static __always_inline unsigned int
+__platform_mask_bit(const struct intel_runtime_info *info,
+		    enum intel_platform p)
+{
+	const unsigned int pbits =
+		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+	return p % pbits + INTEL_SUBPLATFORM_BITS;
+}
+
+static inline u32
+intel_subplatform(const struct intel_runtime_info *info,
+		      enum intel_platform p)
+{
+	const unsigned int pi = __platform_mask_index(info, p);
+
+	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
+}
+
+static __always_inline bool
+IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
+{
+	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(info, p);
+	const unsigned int pb = __platform_mask_bit(info, p);
+
+	BUILD_BUG_ON(!__builtin_constant_p(p));
+
+	return info->platform_mask[pi] & BIT(pb);
+}
+
+static __always_inline bool
+IS_SUBPLATFORM(const struct drm_i915_private *i915,
+	       enum intel_platform p, unsigned int s)
+{
+	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(info, p);
+	const unsigned int pb = __platform_mask_bit(info, p);
+	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
+	const u32 mask = info->platform_mask[pi];
+
+	BUILD_BUG_ON(!__builtin_constant_p(p));
+	BUILD_BUG_ON(!__builtin_constant_p(s));
+	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
+
+	/* Shift and test on the MSB position so sign flag can be used. */
+	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
+}
 
 #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
 
@@ -2337,43 +2398,32 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
-/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
+#define IS_BDW_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 1)
 /* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
-				 INTEL_DEVID(dev_priv) == 0x0A1E)
-#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
-				 INTEL_DEVID(dev_priv) == 0x1913 || \
-				 INTEL_DEVID(dev_priv) == 0x1916 || \
-				 INTEL_DEVID(dev_priv) == 0x1921 || \
-				 INTEL_DEVID(dev_priv) == 0x1926)
-#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
-				 INTEL_DEVID(dev_priv) == 0x1915 || \
-				 INTEL_DEVID(dev_priv) == 0x191E)
-#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
-				 INTEL_DEVID(dev_priv) == 0x5913 || \
-				 INTEL_DEVID(dev_priv) == 0x5916 || \
-				 INTEL_DEVID(dev_priv) == 0x5921 || \
-				 INTEL_DEVID(dev_priv) == 0x5926)
-#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
-				 INTEL_DEVID(dev_priv) == 0x5915 || \
-				 INTEL_DEVID(dev_priv) == 0x591E)
-#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
-				 INTEL_DEVID(dev_priv) == 0x87C0 || \
-				 INTEL_DEVID(dev_priv) == 0x87CA)
+#define IS_HSW_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
+#define IS_SKL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_SKL_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_KBL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_KBL_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_AML_ULX(dev_priv) \
+	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
+	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
@@ -2384,16 +2434,16 @@ static inline unsigned int i915_sg_segment_size(void)
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
-					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
-#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
-					INTEL_DEVID(dev_priv) != 0x8A51)
+#define IS_CNL_WITH_PORT_F(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
+#define IS_ICL_WITH_PORT_F(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a9557f92756f..0c980b899056 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Reset count: %u\n", error->reset_count);
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
+	err_printf(m, "Subplatform: 0x%x\n",
+		   intel_subplatform(&error->runtime_info,
+				     error->device_info.platform));
 	err_print_pciid(m, m->i915);
 
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 716f2f95c57d..39251586349a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -32,7 +32,7 @@
 #include "i915_globals.h"
 #include "i915_selftest.h"
 
-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
+#define PLATFORM(x) .platform = (x)
 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
 
 #define I845_PIPE_OFFSETS \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0ac908bb4e9..85da87e14c02 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -714,6 +714,151 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+#undef INTEL_VGA_DEVICE
+#define INTEL_VGA_DEVICE(id, info) (id)
+
+static const u16 hsw_ult_ids[] = {
+	INTEL_HSW_ULT_GT1_IDS(0),
+	INTEL_HSW_ULT_GT2_IDS(0),
+	INTEL_HSW_ULT_GT3_IDS(0)
+};
+
+static const u16 hsw_ulx_ids[] = {
+	INTEL_HSW_ULX_GT1_IDS(0),
+	INTEL_HSW_ULX_GT2_IDS(0)
+};
+
+static const u16 bdw_ult_ids[] = {
+	INTEL_BDW_ULT_GT1_IDS(0),
+	INTEL_BDW_ULT_GT2_IDS(0),
+	INTEL_BDW_ULT_GT3_IDS(0),
+	INTEL_BDW_ULT_RSVD_IDS(0)
+};
+
+static const u16 bdw_ulx_ids[] = {
+	INTEL_BDW_ULX_GT1_IDS(0),
+	INTEL_BDW_ULX_GT2_IDS(0),
+	INTEL_BDW_ULX_GT3_IDS(0),
+	INTEL_BDW_ULX_RSVD_IDS(0)
+};
+
+static const u16 skl_ult_ids[] = {
+	INTEL_SKL_ULT_GT1_IDS(0),
+	INTEL_SKL_ULT_GT2_IDS(0),
+	INTEL_SKL_ULT_GT3_IDS(0)
+};
+
+static const u16 skl_ulx_ids[] = {
+	INTEL_SKL_ULX_GT1_IDS(0),
+	INTEL_SKL_ULX_GT2_IDS(0)
+};
+
+static const u16 kbl_ult_ids[] = {
+	INTEL_KBL_ULT_GT1_IDS(0),
+	INTEL_KBL_ULT_GT2_IDS(0),
+	INTEL_KBL_ULT_GT3_IDS(0)
+};
+
+static const u16 kbl_ulx_ids[] = {
+	INTEL_KBL_ULX_GT1_IDS(0),
+	INTEL_KBL_ULX_GT2_IDS(0)
+};
+
+static const u16 kbl_aml_ids[] = {
+	INTEL_AML_KBL_GT2_IDS(0)
+};
+
+static const u16 cfl_ult_ids[] = {
+	INTEL_CFL_U_GT2_IDS(0),
+	INTEL_CFL_U_GT3_IDS(0),
+	INTEL_WHL_U_GT1_IDS(0),
+	INTEL_WHL_U_GT2_IDS(0),
+	INTEL_WHL_U_GT3_IDS(0)
+};
+
+static const u16 cfl_aml_ids[] = {
+	INTEL_AML_CFL_GT2_IDS(0)
+};
+
+static const u16 cnl_portf_ids[] = {
+	INTEL_CNL_PORT_F_IDS(0)
+};
+
+static const u16 icl_portf_ids[] = {
+	INTEL_ICL_PORT_F_IDS(0)
+};
+
+static bool find_devid(u16 id, const u16 *p, unsigned int num)
+{
+	for (; num; num--, p++) {
+		if (*p == id)
+			return true;
+	}
+
+	return false;
+}
+
+void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+{
+	const struct intel_device_info *info = INTEL_INFO(i915);
+	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
+	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
+	u16 devid = INTEL_DEVID(i915);
+	u32 mask = 0;
+
+	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
+
+	if (IS_HASWELL(i915)) {
+		if (find_devid(devid, hsw_ult_ids, ARRAY_SIZE(hsw_ult_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULT);
+		else if (find_devid(devid, hsw_ulx_ids,
+				    ARRAY_SIZE(hsw_ulx_ids)))
+			/* ULX machines are also considered ULT. */
+			mask = BIT(INTEL_SUBPLATFORM_ULT) |
+			       BIT(INTEL_SUBPLATFORM_ULX);
+	} else if (IS_BROADWELL(i915)) {
+		if (find_devid(devid, bdw_ult_ids, ARRAY_SIZE(bdw_ult_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULT);
+		else if (find_devid(devid, bdw_ulx_ids,
+				    ARRAY_SIZE(bdw_ulx_ids)))
+			/* ULX machines are also considered ULT. */
+			mask = BIT(INTEL_SUBPLATFORM_ULT) |
+			       BIT(INTEL_SUBPLATFORM_ULX);
+	} else if (IS_SKYLAKE(i915)) {
+		if (find_devid(devid, skl_ult_ids, ARRAY_SIZE(skl_ult_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULT);
+		else if (find_devid(devid, skl_ulx_ids,
+				    ARRAY_SIZE(skl_ulx_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULX);
+	} else if (IS_KABYLAKE(i915)) {
+		if (find_devid(devid, kbl_ult_ids, ARRAY_SIZE(kbl_ult_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULT);
+		else if (find_devid(devid, kbl_ulx_ids,
+				    ARRAY_SIZE(kbl_ulx_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULX);
+		else if (find_devid(devid, kbl_aml_ids,
+				    ARRAY_SIZE(kbl_aml_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_AML);
+	} else if (IS_COFFEELAKE(i915)) {
+		if (find_devid(devid, cfl_ult_ids, ARRAY_SIZE(cfl_ult_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_ULT);
+		else if (find_devid(devid, cfl_aml_ids,
+				    ARRAY_SIZE(cfl_aml_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_AML);
+	} else if (IS_CANNONLAKE(i915)) {
+		if (find_devid(devid, cnl_portf_ids, ARRAY_SIZE(cnl_portf_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_PORTF);
+	} else if (IS_ICELAKE(i915)) {
+		if (find_devid(devid, icl_portf_ids, ARRAY_SIZE(icl_portf_ids)))
+			mask = BIT(INTEL_SUBPLATFORM_PORTF);
+	}
+
+	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
+
+	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 98acefaacec9..da1152eef46b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -77,6 +77,21 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
+/*
+ * Subplatform bits share the same namespace per parent platform. In other words
+ * it is fine for the same bit to be used on multiple parent platforms.
+ */
+
+#define INTEL_SUBPLATFORM_BITS (3)
+
+/* HSW/BDW/SKL/KBL/CFL */
+#define INTEL_SUBPLATFORM_ULT	(0)
+#define INTEL_SUBPLATFORM_ULX	(1)
+#define INTEL_SUBPLATFORM_AML	(2)
+
+/* CNL/ICL */
+#define INTEL_SUBPLATFORM_PORTF	(0)
+
 enum intel_ppgtt_type {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@@ -160,7 +175,6 @@ struct intel_device_info {
 	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
 
 	enum intel_platform platform;
-	u32 platform_mask;
 
 	enum intel_ppgtt_type ppgtt_type;
 	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
@@ -197,6 +211,16 @@ struct intel_device_info {
 };
 
 struct intel_runtime_info {
+	/*
+	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
+	 * into single runtime conditionals, and also to provide groundwork
+	 * for future per platform, or per SKU build optimizations.
+	 *
+	 * Array can be extended when necessary if the corresponding
+	 * BUILD_BUG_ON is hit.
+	 */
+	u32 platform_mask[2];
+
 	u16 device_id;
 
 	u8 num_sprites[I915_MAX_PIPES];
@@ -271,6 +295,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
 
 const char *intel_platform_name(enum intel_platform platform);
 
+void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Tue, 26 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Concept of a sub-platform already exist in our code (like ULX and ULT
> platform variants and similar),implemented via the macros which check a
> list of device ids to determine a match.
>
> With this patch we consolidate device ids checking into a single function
> called during early driver load.
>
> A few low bits in the platform mask are reserved for sub-platform
> identification and defined as a per-platform namespace.
>
> At the same time it future proofs the platform_mask handling by preparing
> the code for easy extending, and tidies the very verbose WARN strings
> generated when IS_PLATFORM macros are embedded into a WARN type
> statements.
>
> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
> v3: Chris was right, there is an ordering problem.
>
> v4:
>  * Catch-up with new sub-platforms.
>  * Rebase for RUNTIME_INFO.
>  * Drop subplatform mask union tricks and convert platform_mask to an
>    array for extensibility.
>
> v5:
>  * Fix subplatform check.
>  * Protect against forgetting to expand subplatform bits.
>  * Remove platform enum tallying.
>  * Add subplatform to error state. (Chris)
>  * Drop macros and just use static inlines.
>  * Remove redundant IRONLAKE_M. (Ville)
>
> v6:
>  * Split out Ironlake change.
>  * Optimize subplatform check.
>  * Use __always_inline. (Lucas)
>  * Add platform_mask comment. (Paulo)
>  * Pass stored runtime info in error capture. (Chris)
>
> v7:
>  * Rebased for new AML ULX device id.
>  * Bump platform mask array size for EHL.
>  * Stop mentioning device ids in intel_device_subplatform_init by using
>    the trick of splitting macros i915_pciids.h. (Jani)
>  * AML seems to be either a subplatform of KBL or CFL so express it like
>    that.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
> ---
>  drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>  drivers/gpu/drm/i915/i915_drv.h          | 124 +++++++++++++------
>  drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>  drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>  drivers/gpu/drm/i915/intel_device_info.c | 145 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>  6 files changed, 267 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5465b99b4392..74255374cc6b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>  	if (i915_inject_load_failure())
>  		return -ENODEV;
>  
> +	intel_device_info_subplatform_init(dev_priv);
> +
>  	spin_lock_init(&dev_priv->irq_lock);
>  	spin_lock_init(&dev_priv->gpu_error.lock);
>  	mutex_init(&dev_priv->backlight_lock);
> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>  	if (drm_debug & DRM_UT_DRIVER) {
>  		struct drm_printer p = drm_debug_printer("i915 device info:");
>  
> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>  			   INTEL_DEVID(dev_priv),
>  			   INTEL_REVID(dev_priv),
>  			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
> +					     INTEL_INFO(dev_priv)->platform),
>  			   INTEL_GEN(dev_priv));
>  
>  		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>  	memcpy(device_info, match_info, sizeof(*device_info));
>  	RUNTIME_INFO(i915)->device_id = pdev->device;
>  
> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> -		     BITS_PER_TYPE(device_info->platform_mask));
>  	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>  
>  	return i915;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48c3b139f36f..c29ebfd94065 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2298,7 +2298,68 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_REVID(p, since, until) \
>  	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>  
> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
> +static __always_inline unsigned int
> +__platform_mask_index(const struct intel_runtime_info *info,
> +		      enum intel_platform p)
> +{
> +	const unsigned int pbits =
> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
> +
> +	/* Expand the platform_mask array if this fails. */
> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> +		     pbits * ARRAY_SIZE(info->platform_mask));
> +
> +	return p / pbits;
> +}
> +
> +static __always_inline unsigned int
> +__platform_mask_bit(const struct intel_runtime_info *info,
> +		    enum intel_platform p)
> +{
> +	const unsigned int pbits =
> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
> +
> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
> +}
> +
> +static inline u32
> +intel_subplatform(const struct intel_runtime_info *info,
> +		      enum intel_platform p)
> +{
> +	const unsigned int pi = __platform_mask_index(info, p);
> +
> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
> +}
> +
> +static __always_inline bool
> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
> +{
> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(info, p);
> +	const unsigned int pb = __platform_mask_bit(info, p);
> +
> +	BUILD_BUG_ON(!__builtin_constant_p(p));
> +
> +	return info->platform_mask[pi] & BIT(pb);
> +}
> +
> +static __always_inline bool
> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
> +	       enum intel_platform p, unsigned int s)
> +{
> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(info, p);
> +	const unsigned int pb = __platform_mask_bit(info, p);
> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
> +	const u32 mask = info->platform_mask[pi];
> +
> +	BUILD_BUG_ON(!__builtin_constant_p(p));
> +	BUILD_BUG_ON(!__builtin_constant_p(s));
> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
> +
> +	/* Shift and test on the MSB position so sign flag can be used. */
> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
> +}
>  
>  #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
>  
> @@ -2337,43 +2398,32 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> -/* ULX machines are also considered ULT. */
> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> +#define IS_BDW_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
> +#define IS_BDW_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
>  #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> +#define IS_HSW_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
>  #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
>  #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 1)
>  /* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
> -				 INTEL_DEVID(dev_priv) == 0x1926)
> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
> -				 INTEL_DEVID(dev_priv) == 0x191E)
> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
> -				 INTEL_DEVID(dev_priv) == 0x5926)
> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
> -				 INTEL_DEVID(dev_priv) == 0x591E)
> -#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
> -				 INTEL_DEVID(dev_priv) == 0x87C0 || \
> -				 INTEL_DEVID(dev_priv) == 0x87CA)
> +#define IS_HSW_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
> +#define IS_SKL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_SKL_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_KBL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_KBL_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_AML_ULX(dev_priv) \
> +	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
> +	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
>  #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> @@ -2384,16 +2434,16 @@ static inline unsigned int i915_sg_segment_size(void)
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> +#define IS_CFL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
>  #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
> -#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
> -					INTEL_DEVID(dev_priv) != 0x8A51)
> +#define IS_CNL_WITH_PORT_F(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
> +#define IS_ICL_WITH_PORT_F(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>  
>  #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index a9557f92756f..0c980b899056 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "Reset count: %u\n", error->reset_count);
>  	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>  	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
> +	err_printf(m, "Subplatform: 0x%x\n",
> +		   intel_subplatform(&error->runtime_info,
> +				     error->device_info.platform));
>  	err_print_pciid(m, m->i915);
>  
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 716f2f95c57d..39251586349a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -32,7 +32,7 @@
>  #include "i915_globals.h"
>  #include "i915_selftest.h"
>  
> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
> +#define PLATFORM(x) .platform = (x)
>  #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>  
>  #define I845_PIPE_OFFSETS \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e0ac908bb4e9..85da87e14c02 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -714,6 +714,151 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +#undef INTEL_VGA_DEVICE
> +#define INTEL_VGA_DEVICE(id, info) (id)
> +
> +static const u16 hsw_ult_ids[] = {
> +	INTEL_HSW_ULT_GT1_IDS(0),
> +	INTEL_HSW_ULT_GT2_IDS(0),
> +	INTEL_HSW_ULT_GT3_IDS(0)
> +};
> +
> +static const u16 hsw_ulx_ids[] = {
> +	INTEL_HSW_ULX_GT1_IDS(0),
> +	INTEL_HSW_ULX_GT2_IDS(0)
> +};
> +
> +static const u16 bdw_ult_ids[] = {
> +	INTEL_BDW_ULT_GT1_IDS(0),
> +	INTEL_BDW_ULT_GT2_IDS(0),
> +	INTEL_BDW_ULT_GT3_IDS(0),
> +	INTEL_BDW_ULT_RSVD_IDS(0)
> +};
> +
> +static const u16 bdw_ulx_ids[] = {
> +	INTEL_BDW_ULX_GT1_IDS(0),
> +	INTEL_BDW_ULX_GT2_IDS(0),
> +	INTEL_BDW_ULX_GT3_IDS(0),
> +	INTEL_BDW_ULX_RSVD_IDS(0)
> +};
> +
> +static const u16 skl_ult_ids[] = {
> +	INTEL_SKL_ULT_GT1_IDS(0),
> +	INTEL_SKL_ULT_GT2_IDS(0),
> +	INTEL_SKL_ULT_GT3_IDS(0)
> +};
> +
> +static const u16 skl_ulx_ids[] = {
> +	INTEL_SKL_ULX_GT1_IDS(0),
> +	INTEL_SKL_ULX_GT2_IDS(0)
> +};
> +
> +static const u16 kbl_ult_ids[] = {
> +	INTEL_KBL_ULT_GT1_IDS(0),
> +	INTEL_KBL_ULT_GT2_IDS(0),
> +	INTEL_KBL_ULT_GT3_IDS(0)
> +};
> +
> +static const u16 kbl_ulx_ids[] = {
> +	INTEL_KBL_ULX_GT1_IDS(0),
> +	INTEL_KBL_ULX_GT2_IDS(0)
> +};
> +
> +static const u16 kbl_aml_ids[] = {
> +	INTEL_AML_KBL_GT2_IDS(0)
> +};
> +
> +static const u16 cfl_ult_ids[] = {
> +	INTEL_CFL_U_GT2_IDS(0),
> +	INTEL_CFL_U_GT3_IDS(0),
> +	INTEL_WHL_U_GT1_IDS(0),
> +	INTEL_WHL_U_GT2_IDS(0),
> +	INTEL_WHL_U_GT3_IDS(0)
> +};
> +
> +static const u16 cfl_aml_ids[] = {
> +	INTEL_AML_CFL_GT2_IDS(0)
> +};
> +
> +static const u16 cnl_portf_ids[] = {
> +	INTEL_CNL_PORT_F_IDS(0)
> +};
> +
> +static const u16 icl_portf_ids[] = {
> +	INTEL_ICL_PORT_F_IDS(0)
> +};

What's the benefit of having platform split in the arrays and an if
ladder in the function below?

I think I'd go with just the feature arrays.

BR,
Jani.

> +
> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
> +{
> +	for (; num; num--, p++) {
> +		if (*p == id)
> +			return true;
> +	}
> +
> +	return false;
> +}
> +
> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> +{
> +	const struct intel_device_info *info = INTEL_INFO(i915);
> +	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
> +	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
> +	u16 devid = INTEL_DEVID(i915);
> +	u32 mask = 0;
> +
> +	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
> +
> +	if (IS_HASWELL(i915)) {
> +		if (find_devid(devid, hsw_ult_ids, ARRAY_SIZE(hsw_ult_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
> +		else if (find_devid(devid, hsw_ulx_ids,
> +				    ARRAY_SIZE(hsw_ulx_ids)))
> +			/* ULX machines are also considered ULT. */
> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
> +			       BIT(INTEL_SUBPLATFORM_ULX);
> +	} else if (IS_BROADWELL(i915)) {
> +		if (find_devid(devid, bdw_ult_ids, ARRAY_SIZE(bdw_ult_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
> +		else if (find_devid(devid, bdw_ulx_ids,
> +				    ARRAY_SIZE(bdw_ulx_ids)))
> +			/* ULX machines are also considered ULT. */
> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
> +			       BIT(INTEL_SUBPLATFORM_ULX);
> +	} else if (IS_SKYLAKE(i915)) {
> +		if (find_devid(devid, skl_ult_ids, ARRAY_SIZE(skl_ult_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
> +		else if (find_devid(devid, skl_ulx_ids,
> +				    ARRAY_SIZE(skl_ulx_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
> +	} else if (IS_KABYLAKE(i915)) {
> +		if (find_devid(devid, kbl_ult_ids, ARRAY_SIZE(kbl_ult_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
> +		else if (find_devid(devid, kbl_ulx_ids,
> +				    ARRAY_SIZE(kbl_ulx_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
> +		else if (find_devid(devid, kbl_aml_ids,
> +				    ARRAY_SIZE(kbl_aml_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_AML);
> +	} else if (IS_COFFEELAKE(i915)) {
> +		if (find_devid(devid, cfl_ult_ids, ARRAY_SIZE(cfl_ult_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
> +		else if (find_devid(devid, cfl_aml_ids,
> +				    ARRAY_SIZE(cfl_aml_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_AML);
> +	} else if (IS_CANNONLAKE(i915)) {
> +		if (find_devid(devid, cnl_portf_ids, ARRAY_SIZE(cnl_portf_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
> +	} else if (IS_ICELAKE(i915)) {
> +		if (find_devid(devid, icl_portf_ids, ARRAY_SIZE(icl_portf_ids)))
> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
> +	}
> +
> +	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
> +
> +	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> +}
> +
>  /**
>   * intel_device_info_runtime_init - initialize runtime info
>   * @dev_priv: the i915 device
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 98acefaacec9..da1152eef46b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -77,6 +77,21 @@ enum intel_platform {
>  	INTEL_MAX_PLATFORMS
>  };
>  
> +/*
> + * Subplatform bits share the same namespace per parent platform. In other words
> + * it is fine for the same bit to be used on multiple parent platforms.
> + */
> +
> +#define INTEL_SUBPLATFORM_BITS (3)
> +
> +/* HSW/BDW/SKL/KBL/CFL */
> +#define INTEL_SUBPLATFORM_ULT	(0)
> +#define INTEL_SUBPLATFORM_ULX	(1)
> +#define INTEL_SUBPLATFORM_AML	(2)
> +
> +/* CNL/ICL */
> +#define INTEL_SUBPLATFORM_PORTF	(0)
> +
>  enum intel_ppgtt_type {
>  	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
>  	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> @@ -160,7 +175,6 @@ struct intel_device_info {
>  	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>  
>  	enum intel_platform platform;
> -	u32 platform_mask;
>  
>  	enum intel_ppgtt_type ppgtt_type;
>  	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
> @@ -197,6 +211,16 @@ struct intel_device_info {
>  };
>  
>  struct intel_runtime_info {
> +	/*
> +	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> +	 * into single runtime conditionals, and also to provide groundwork
> +	 * for future per platform, or per SKU build optimizations.
> +	 *
> +	 * Array can be extended when necessary if the corresponding
> +	 * BUILD_BUG_ON is hit.
> +	 */
> +	u32 platform_mask[2];
> +
>  	u16 device_id;
>  
>  	u8 num_sprites[I915_MAX_PIPES];
> @@ -271,6 +295,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>  
>  const char *intel_platform_name(enum intel_platform platform);
>  
> +void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
>  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>  void intel_device_info_dump_flags(const struct intel_device_info *info,
>  				  struct drm_printer *p);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Tue, 26 Mar 2019, Jani Nikula <jani.nikula@intel.com> wrote:
> On Tue, 26 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Concept of a sub-platform already exist in our code (like ULX and ULT
>> platform variants and similar),implemented via the macros which check a
>> list of device ids to determine a match.
>>
>> With this patch we consolidate device ids checking into a single function
>> called during early driver load.
>>
>> A few low bits in the platform mask are reserved for sub-platform
>> identification and defined as a per-platform namespace.
>>
>> At the same time it future proofs the platform_mask handling by preparing
>> the code for easy extending, and tidies the very verbose WARN strings
>> generated when IS_PLATFORM macros are embedded into a WARN type
>> statements.
>>
>> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
>> v3: Chris was right, there is an ordering problem.
>>
>> v4:
>>  * Catch-up with new sub-platforms.
>>  * Rebase for RUNTIME_INFO.
>>  * Drop subplatform mask union tricks and convert platform_mask to an
>>    array for extensibility.
>>
>> v5:
>>  * Fix subplatform check.
>>  * Protect against forgetting to expand subplatform bits.
>>  * Remove platform enum tallying.
>>  * Add subplatform to error state. (Chris)
>>  * Drop macros and just use static inlines.
>>  * Remove redundant IRONLAKE_M. (Ville)
>>
>> v6:
>>  * Split out Ironlake change.
>>  * Optimize subplatform check.
>>  * Use __always_inline. (Lucas)
>>  * Add platform_mask comment. (Paulo)
>>  * Pass stored runtime info in error capture. (Chris)
>>
>> v7:
>>  * Rebased for new AML ULX device id.
>>  * Bump platform mask array size for EHL.
>>  * Stop mentioning device ids in intel_device_subplatform_init by using
>>    the trick of splitting macros i915_pciids.h. (Jani)
>>  * AML seems to be either a subplatform of KBL or CFL so express it like
>>    that.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jose Souza <jose.souza@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>>  drivers/gpu/drm/i915/i915_drv.h          | 124 +++++++++++++------
>>  drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>>  drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>>  drivers/gpu/drm/i915/intel_device_info.c | 145 +++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>>  6 files changed, 267 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5465b99b4392..74255374cc6b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>>  	if (i915_inject_load_failure())
>>  		return -ENODEV;
>>  
>> +	intel_device_info_subplatform_init(dev_priv);
>> +
>>  	spin_lock_init(&dev_priv->irq_lock);
>>  	spin_lock_init(&dev_priv->gpu_error.lock);
>>  	mutex_init(&dev_priv->backlight_lock);
>> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>>  	if (drm_debug & DRM_UT_DRIVER) {
>>  		struct drm_printer p = drm_debug_printer("i915 device info:");
>>  
>> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>>  			   INTEL_DEVID(dev_priv),
>>  			   INTEL_REVID(dev_priv),
>>  			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
>> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
>> +					     INTEL_INFO(dev_priv)->platform),
>>  			   INTEL_GEN(dev_priv));
>>  
>>  		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
>> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>>  	memcpy(device_info, match_info, sizeof(*device_info));
>>  	RUNTIME_INFO(i915)->device_id = pdev->device;
>>  
>> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> -		     BITS_PER_TYPE(device_info->platform_mask));
>>  	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>>  
>>  	return i915;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 48c3b139f36f..c29ebfd94065 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2298,7 +2298,68 @@ static inline unsigned int i915_sg_segment_size(void)
>>  #define IS_REVID(p, since, until) \
>>  	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>>  
>> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>> +static __always_inline unsigned int
>> +__platform_mask_index(const struct intel_runtime_info *info,
>> +		      enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	/* Expand the platform_mask array if this fails. */
>> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> +		     pbits * ARRAY_SIZE(info->platform_mask));
>> +
>> +	return p / pbits;
>> +}
>> +
>> +static __always_inline unsigned int
>> +__platform_mask_bit(const struct intel_runtime_info *info,
>> +		    enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static inline u32
>> +intel_subplatform(const struct intel_runtime_info *info,
>> +		      enum intel_platform p)
>> +{
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +
>> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static __always_inline bool
>> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +
>> +	return info->platform_mask[pi] & BIT(pb);
>> +}
>> +
>> +static __always_inline bool
>> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> +	       enum intel_platform p, unsigned int s)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
>> +	const u32 mask = info->platform_mask[pi];
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +	BUILD_BUG_ON(!__builtin_constant_p(s));
>> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
>> +
>> +	/* Shift and test on the MSB position so sign flag can be used. */
>> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
>> +}
>>  
>>  #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
>>  
>> @@ -2337,43 +2398,32 @@ static inline unsigned int i915_sg_segment_size(void)
>>  #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
>> -/* ULX machines are also considered ULT. */
>> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> +#define IS_BDW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
>> +#define IS_BDW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
>>  #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> +#define IS_HSW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
>>  #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 3)
>>  #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 1)
>>  /* ULX machines are also considered ULT. */
>> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
>> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
>> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1926)
>> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
>> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x191E)
>> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5926)
>> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
>> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x591E)
>> -#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
>> -				 INTEL_DEVID(dev_priv) == 0x87C0 || \
>> -				 INTEL_DEVID(dev_priv) == 0x87CA)
>> +#define IS_HSW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
>> +#define IS_SKL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_SKL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_KBL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_KBL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_AML_ULX(dev_priv) \
>> +	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
>> +	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
>>  #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 2)
>>  #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>> @@ -2384,16 +2434,16 @@ static inline unsigned int i915_sg_segment_size(void)
>>  				 INTEL_INFO(dev_priv)->gt == 2)
>>  #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> +#define IS_CFL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
>>  #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 2)
>>  #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>  				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
>> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>> -#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
>> -					INTEL_DEVID(dev_priv) != 0x8A51)
>> +#define IS_CNL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
>> +#define IS_ICL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>>  
>>  #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>>  
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index a9557f92756f..0c980b899056 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>>  	err_printf(m, "Reset count: %u\n", error->reset_count);
>>  	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>>  	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
>> +	err_printf(m, "Subplatform: 0x%x\n",
>> +		   intel_subplatform(&error->runtime_info,
>> +				     error->device_info.platform));
>>  	err_print_pciid(m, m->i915);
>>  
>>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 716f2f95c57d..39251586349a 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -32,7 +32,7 @@
>>  #include "i915_globals.h"
>>  #include "i915_selftest.h"
>>  
>> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
>> +#define PLATFORM(x) .platform = (x)
>>  #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>>  
>>  #define I845_PIPE_OFFSETS \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index e0ac908bb4e9..85da87e14c02 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -714,6 +714,151 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>  	return 0;
>>  }
>>  
>> +#undef INTEL_VGA_DEVICE
>> +#define INTEL_VGA_DEVICE(id, info) (id)
>> +
>> +static const u16 hsw_ult_ids[] = {
>> +	INTEL_HSW_ULT_GT1_IDS(0),
>> +	INTEL_HSW_ULT_GT2_IDS(0),
>> +	INTEL_HSW_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 hsw_ulx_ids[] = {
>> +	INTEL_HSW_ULX_GT1_IDS(0),
>> +	INTEL_HSW_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 bdw_ult_ids[] = {
>> +	INTEL_BDW_ULT_GT1_IDS(0),
>> +	INTEL_BDW_ULT_GT2_IDS(0),
>> +	INTEL_BDW_ULT_GT3_IDS(0),
>> +	INTEL_BDW_ULT_RSVD_IDS(0)
>> +};
>> +
>> +static const u16 bdw_ulx_ids[] = {
>> +	INTEL_BDW_ULX_GT1_IDS(0),
>> +	INTEL_BDW_ULX_GT2_IDS(0),
>> +	INTEL_BDW_ULX_GT3_IDS(0),
>> +	INTEL_BDW_ULX_RSVD_IDS(0)
>> +};
>> +
>> +static const u16 skl_ult_ids[] = {
>> +	INTEL_SKL_ULT_GT1_IDS(0),
>> +	INTEL_SKL_ULT_GT2_IDS(0),
>> +	INTEL_SKL_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 skl_ulx_ids[] = {
>> +	INTEL_SKL_ULX_GT1_IDS(0),
>> +	INTEL_SKL_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 kbl_ult_ids[] = {
>> +	INTEL_KBL_ULT_GT1_IDS(0),
>> +	INTEL_KBL_ULT_GT2_IDS(0),
>> +	INTEL_KBL_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 kbl_ulx_ids[] = {
>> +	INTEL_KBL_ULX_GT1_IDS(0),
>> +	INTEL_KBL_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 kbl_aml_ids[] = {
>> +	INTEL_AML_KBL_GT2_IDS(0)
>> +};
>> +
>> +static const u16 cfl_ult_ids[] = {
>> +	INTEL_CFL_U_GT2_IDS(0),
>> +	INTEL_CFL_U_GT3_IDS(0),
>> +	INTEL_WHL_U_GT1_IDS(0),
>> +	INTEL_WHL_U_GT2_IDS(0),
>> +	INTEL_WHL_U_GT3_IDS(0)
>> +};
>> +
>> +static const u16 cfl_aml_ids[] = {
>> +	INTEL_AML_CFL_GT2_IDS(0)
>> +};
>> +
>> +static const u16 cnl_portf_ids[] = {
>> +	INTEL_CNL_PORT_F_IDS(0)
>> +};
>> +
>> +static const u16 icl_portf_ids[] = {
>> +	INTEL_ICL_PORT_F_IDS(0)
>> +};
>
> What's the benefit of having platform split in the arrays and an if
> ladder in the function below?
>
> I think I'd go with just the feature arrays.

Not to block this series, but looking further outside the box...

I've still got the constant vs. runtime device info split
unfinished. We've got so many things that are mostly constant, but
occasionally need changes. And we've got so many things that could be
device info flags, but would lead to proliferation of plenty of almost
identical device info structures. Like this ULX/ULT and GT number.

So I guess I'm wondering if we're doing the right thing by assigning
device info pointers to the struct pci_device_id driver_data member in
pciidlist[] table.

For one thing, that's a whole lot of bits that could be used directly
for assigning platform and subplatform, or features.

Of course, we'd then need another table besides pciidlist[] to map to
the device info, but we're sort of doing some of that with the ULX/ULT
parts.

I just overall feel that there must be a better way to do all this, and
we just haven't figured it out yet, and we're partially putting
ourselves into a box we can't break out of.

Thoughts?

BR,
Jani.



>
> BR,
> Jani.
>
>> +
>> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
>> +{
>> +	for (; num; num--, p++) {
>> +		if (*p == id)
>> +			return true;
>> +	}
>> +
>> +	return false;
>> +}
>> +
>> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> +{
>> +	const struct intel_device_info *info = INTEL_INFO(i915);
>> +	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
>> +	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
>> +	u16 devid = INTEL_DEVID(i915);
>> +	u32 mask = 0;
>> +
>> +	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
>> +
>> +	if (IS_HASWELL(i915)) {
>> +		if (find_devid(devid, hsw_ult_ids, ARRAY_SIZE(hsw_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, hsw_ulx_ids,
>> +				    ARRAY_SIZE(hsw_ulx_ids)))
>> +			/* ULX machines are also considered ULT. */
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
>> +			       BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_BROADWELL(i915)) {
>> +		if (find_devid(devid, bdw_ult_ids, ARRAY_SIZE(bdw_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, bdw_ulx_ids,
>> +				    ARRAY_SIZE(bdw_ulx_ids)))
>> +			/* ULX machines are also considered ULT. */
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
>> +			       BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_SKYLAKE(i915)) {
>> +		if (find_devid(devid, skl_ult_ids, ARRAY_SIZE(skl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, skl_ulx_ids,
>> +				    ARRAY_SIZE(skl_ulx_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_KABYLAKE(i915)) {
>> +		if (find_devid(devid, kbl_ult_ids, ARRAY_SIZE(kbl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, kbl_ulx_ids,
>> +				    ARRAY_SIZE(kbl_ulx_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
>> +		else if (find_devid(devid, kbl_aml_ids,
>> +				    ARRAY_SIZE(kbl_aml_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_AML);
>> +	} else if (IS_COFFEELAKE(i915)) {
>> +		if (find_devid(devid, cfl_ult_ids, ARRAY_SIZE(cfl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, cfl_aml_ids,
>> +				    ARRAY_SIZE(cfl_aml_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_AML);
>> +	} else if (IS_CANNONLAKE(i915)) {
>> +		if (find_devid(devid, cnl_portf_ids, ARRAY_SIZE(cnl_portf_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
>> +	} else if (IS_ICELAKE(i915)) {
>> +		if (find_devid(devid, icl_portf_ids, ARRAY_SIZE(icl_portf_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
>> +	}
>> +
>> +	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
>> +
>> +	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
>> +}
>> +
>>  /**
>>   * intel_device_info_runtime_init - initialize runtime info
>>   * @dev_priv: the i915 device
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 98acefaacec9..da1152eef46b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -77,6 +77,21 @@ enum intel_platform {
>>  	INTEL_MAX_PLATFORMS
>>  };
>>  
>> +/*
>> + * Subplatform bits share the same namespace per parent platform. In other words
>> + * it is fine for the same bit to be used on multiple parent platforms.
>> + */
>> +
>> +#define INTEL_SUBPLATFORM_BITS (3)
>> +
>> +/* HSW/BDW/SKL/KBL/CFL */
>> +#define INTEL_SUBPLATFORM_ULT	(0)
>> +#define INTEL_SUBPLATFORM_ULX	(1)
>> +#define INTEL_SUBPLATFORM_AML	(2)
>> +
>> +/* CNL/ICL */
>> +#define INTEL_SUBPLATFORM_PORTF	(0)
>> +
>>  enum intel_ppgtt_type {
>>  	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
>>  	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
>> @@ -160,7 +175,6 @@ struct intel_device_info {
>>  	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>>  
>>  	enum intel_platform platform;
>> -	u32 platform_mask;
>>  
>>  	enum intel_ppgtt_type ppgtt_type;
>>  	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
>> @@ -197,6 +211,16 @@ struct intel_device_info {
>>  };
>>  
>>  struct intel_runtime_info {
>> +	/*
>> +	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
>> +	 * into single runtime conditionals, and also to provide groundwork
>> +	 * for future per platform, or per SKU build optimizations.
>> +	 *
>> +	 * Array can be extended when necessary if the corresponding
>> +	 * BUILD_BUG_ON is hit.
>> +	 */
>> +	u32 platform_mask[2];
>> +
>>  	u16 device_id;
>>  
>>  	u8 num_sprites[I915_MAX_PIPES];
>> @@ -271,6 +295,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>>  
>>  const char *intel_platform_name(enum intel_platform platform);
>>  
>> +void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
>>  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>>  void intel_device_info_dump_flags(const struct intel_device_info *info,
>>  				  struct drm_printer *p);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Chris Wilson]

Quoting Jani Nikula (2019-03-26 09:34:45)
> Not to block this series, but looking further outside the box...
> 
> I've still got the constant vs. runtime device info split
> unfinished. We've got so many things that are mostly constant, but
> occasionally need changes. And we've got so many things that could be
> device info flags, but would lead to proliferation of plenty of almost
> identical device info structures. Like this ULX/ULT and GT number.
> 
> So I guess I'm wondering if we're doing the right thing by assigning
> device info pointers to the struct pci_device_id driver_data member in
> pciidlist[] table.
> 
> For one thing, that's a whole lot of bits that could be used directly
> for assigning platform and subplatform, or features.
> 
> Of course, we'd then need another table besides pciidlist[] to map to
> the device info, but we're sort of doing some of that with the ULX/ULT
> parts.
> 
> I just overall feel that there must be a better way to do all this, and
> we just haven't figured it out yet, and we're partially putting
> ourselves into a box we can't break out of.
> 
> Thoughts?

I think intel_device_info is still fundamentally useful. The
disadvantage of having the feature discovery separate from use is
outweighed by having consistent stanzas for those features - it makes
comparing platforms, finding feature sets much easier. (The cost being
that with the setting of the feature flag far away from the code using
it, people updating the cost are more likely to forget the flag.)

One end goal of this madness, is that we can recompile the kernel module
to only support a single sku and dce the rest. But what are the
diminishing returns here? Without measurement, I'd say a single
platform.

So that dictates what can be in the static intel_device_info, features
that are constant across a whole platform. And as you point out, we
don't need a pointer to the device_info itself, just a platform field
which is an index into the device_info block, with plenty of room for
subplatform flags.

While that says how we hook up device_info, I don't think that reflects
on the use of feature flags themselves, or our ability to statically
determine a reduced feature set.

So not a box, just a mere wet paper bag.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for Device id consolidation

[Patchwork]

== Series Details ==

Series: Device id consolidation
URL   : https://patchwork.freedesktop.org/series/58561/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
caf40a504a05 drm/i915: Split Pineview device info into desktop and mobile
1a9cbf3aa2a4 drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/i915_drv.h:2321:
+#define IS_IRONLAKE_M(dev_priv) \
+	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
40559f6a2295 drm/i915: Split some PCI ids into separate groups
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#34: FILE: include/drm/i915_pciids.h:171:
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#34: FILE: include/drm/i915_pciids.h:171:
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */

-:66: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#66: FILE: include/drm/i915_pciids.h:199:
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#66: FILE: include/drm/i915_pciids.h:199:
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */

-:99: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#99: FILE: include/drm/i915_pciids.h:228:
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */

-:99: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#99: FILE: include/drm/i915_pciids.h:228:
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */

-:134: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#134: FILE: include/drm/i915_pciids.h:265:
+#define INTEL_BDW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */

-:134: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#134: FILE: include/drm/i915_pciids.h:265:
+#define INTEL_BDW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */

-:143: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#143: FILE: include/drm/i915_pciids.h:272:
+#define INTEL_BDW_GT1_IDS(info) \
+	INTEL_BDW_ULT_GT1_IDS(info), \
+	INTEL_BDW_ULX_GT1_IDS(info), \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */

-:143: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#143: FILE: include/drm/i915_pciids.h:272:
+#define INTEL_BDW_GT1_IDS(info) \
+	INTEL_BDW_ULT_GT1_IDS(info), \
+	INTEL_BDW_ULX_GT1_IDS(info), \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */

-:152: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#152: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */

-:152: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#152: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */

-:161: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#161: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT2_IDS(info) \
+	INTEL_BDW_ULT_GT2_IDS(info), \
+	INTEL_BDW_ULX_GT2_IDS(info), \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */

-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#161: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT2_IDS(info) \
+	INTEL_BDW_ULT_GT2_IDS(info), \
+	INTEL_BDW_ULX_GT2_IDS(info), \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */

-:168: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#168: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
+

-:168: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#168: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
+

-:185: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#185: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info)  /* Iris */

-:185: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#185: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info)  /* Iris */

-:222: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#222: FILE: include/drm/i915_pciids.h:346:
+#define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */

-:222: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#222: FILE: include/drm/i915_pciids.h:346:
+#define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */

-:231: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#231: FILE: include/drm/i915_pciids.h:353:
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_SKL_ULT_GT2_IDS(info), \
+	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */

-:231: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#231: FILE: include/drm/i915_pciids.h:353:
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_SKL_ULT_GT2_IDS(info), \
+	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */

-:256: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#256: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_KBL_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */

-:256: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#256: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_KBL_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */

-:260: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#260: FILE: include/drm/i915_pciids.h:399:
+#define INTEL_KBL_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */

-:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#260: FILE: include/drm/i915_pciids.h:399:
+#define INTEL_KBL_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */

-:264: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#264: FILE: include/drm/i915_pciids.h:403:
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_KBL_ULT_GT1_IDS(info), \
+	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */

-:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#264: FILE: include/drm/i915_pciids.h:403:
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_KBL_ULT_GT1_IDS(info), \
+	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */

-:273: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#273: FILE: include/drm/i915_pciids.h:411:
+#define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */

-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#273: FILE: include/drm/i915_pciids.h:411:
+#define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */

-:280: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#280: FILE: include/drm/i915_pciids.h:418:
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_KBL_ULT_GT2_IDS(info), \
+	INTEL_KBL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */

-:280: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#280: FILE: include/drm/i915_pciids.h:418:
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_KBL_ULT_GT2_IDS(info), \
+	INTEL_KBL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */

-:305: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#305: FILE: include/drm/i915_pciids.h:539:
+#define INTEL_CNL_PORT_F_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info), \
+	INTEL_VGA_DEVICE(0x5A44, info), \
+	INTEL_VGA_DEVICE(0x5A4C, info)

-:305: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#305: FILE: include/drm/i915_pciids.h:539:
+#define INTEL_CNL_PORT_F_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info), \
+	INTEL_VGA_DEVICE(0x5A44, info), \
+	INTEL_VGA_DEVICE(0x5A4C, info)

-:329: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#329: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
 	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info), \
 	INTEL_VGA_DEVICE(0x8A59, info),	\

-:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#329: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
 	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info), \
 	INTEL_VGA_DEVICE(0x8A59, info),	\

-:339: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#339: FILE: include/drm/i915_pciids.h:574:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_ICL_PORT_F_IDS(info), \
+	INTEL_VGA_DEVICE(0x8A51, info)

-:339: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#339: FILE: include/drm/i915_pciids.h:574:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_ICL_PORT_F_IDS(info), \
+	INTEL_VGA_DEVICE(0x8A51, info)

total: 19 errors, 0 warnings, 19 checks, 305 lines checked
b5342d54426e drm/i915: Introduce concept of a sub-platform
-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/i915_drv.h:2327:
+intel_subplatform(const struct intel_runtime_info *info,
+		      enum intel_platform p)

-:233: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#233: FILE: drivers/gpu/drm/i915/i915_drv.h:2424:
+#define IS_AML_ULX(dev_priv) \
+	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
+	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))

total: 0 errors, 0 warnings, 2 checks, 401 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for Device id consolidation

[Patchwork]

== Series Details ==

Series: Device id consolidation
URL   : https://patchwork.freedesktop.org/series/58561/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Split Pineview device info into desktop and mobile
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3597:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3595:16: warning: expression using sizeof(void)

Commit: drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3595:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3598:16: warning: expression using sizeof(void)

Commit: drm/i915: Split some PCI ids into separate groups
Okay!

Commit: drm/i915: Introduce concept of a sub-platform
-drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3598:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3648:16: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for Device id consolidation

[Patchwork]

== Series Details ==

Series: Device id consolidation
URL   : https://patchwork.freedesktop.org/series/58561/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5817 -> Patchwork_12599
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58561/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12599 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_contexts:
    - fi-skl-gvtdvm:      PASS -> DMESG-FAIL [fdo#110235 ]

  * igt@kms_busy@basic-flip-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +48

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@prime_vgem@basic-fence-flip:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182] +1

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-icl-u3:          FAIL [fdo#103375] -> PASS
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
  [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 


Participating hosts (46 -> 39)
------------------------------

  Missing    (7): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5817 -> Patchwork_12599

  CI_DRM_5817: 07abdbc9d99bcd754fc906237057369fe0399f93 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4904: b9cfd64009ca2536f7a997deabf34d88f2757511 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12599: b5342d54426e4ebbb07d29e27a50fdf85dfe7351 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b5342d54426e drm/i915: Introduce concept of a sub-platform
40559f6a2295 drm/i915: Split some PCI ids into separate groups
1a9cbf3aa2a4 drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
caf40a504a05 drm/i915: Split Pineview device info into desktop and mobile

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12599/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for Device id consolidation

[Patchwork]

== Series Details ==

Series: Device id consolidation
URL   : https://patchwork.freedesktop.org/series/58561/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5817_full -> Patchwork_12599_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12599_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12599_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12599_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_gtt@forked-medium-copy:
    - shard-iclb:         NOTRUN -> INCOMPLETE

  
Known issues
------------

  Here are the changes found in Patchwork_12599_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@extended-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +3

  * igt@gem_pread@stolen-display:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277]

  * igt@gem_pwrite@big-cpu-fbr:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +180

  * igt@gem_tiled_fence_blits@normal:
    - shard-iclb:         PASS -> TIMEOUT [fdo#109673]

  * igt@gem_tiled_swapping@non-threaded:
    - shard-iclb:         PASS -> FAIL [fdo#108686]

  * igt@i915_pm_lpsp@edp-panel-fitter:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109301]

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108059]

  * igt@i915_selftest@live_workarounds:
    - shard-iclb:         PASS -> DMESG-FAIL [fdo#108954]

  * igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +8

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#110222]

  * igt@kms_busy@extended-modeset-hang-oldfb-render-d:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#110222] +1
    - shard-kbl:          NOTRUN -> DMESG-WARN [fdo#110222]

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +1

  * igt@kms_cursor_crc@cursor-512x512-offscreen:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109279]

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-iclb:         PASS -> FAIL [fdo#103355]

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#103833]

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +46

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +2

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          NOTRUN -> FAIL [fdo#105363]

  * igt@kms_force_connector_basic@force-connector-state:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109285]

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +3

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +6

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +1

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
    - shard-glk:          PASS -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         PASS -> SKIP [fdo#109642]

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +1

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_setmode@basic:
    - shard-kbl:          PASS -> FAIL [fdo#99912]

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-c:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +6

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

  * igt@kms_vblank@pipe-b-ts-continuation-modeset:
    - shard-apl:          PASS -> FAIL [fdo#104894]

  * igt@perf_pmu@rc6-runtime-pm:
    - shard-apl:          NOTRUN -> FAIL [fdo#105010]

  * igt@prime_mmap@test_correct:
    - shard-iclb:         PASS -> INCOMPLETE [fdo#110246]

  * igt@prime_nv_api@i915_nv_import_vs_close:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271] +12

  * igt@prime_nv_test@i915_blt_fill_nv_read:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291]

  * igt@prime_vgem@fence-flip-hang:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109295]

  
#### Possible fixes ####

  * igt@gem_exec_schedule@promotion-bsd:
    - shard-apl:          INCOMPLETE [fdo#103927] -> PASS

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-skl:          INCOMPLETE [fdo#107807] -> PASS +1

  * igt@kms_cursor_crc@cursor-64x64-suspend:
    - shard-skl:          FAIL [fdo#103191] / [fdo#103232] -> PASS

  * igt@kms_fbcon_fbt@fbc:
    - shard-iclb:         DMESG-WARN [fdo#109593] -> PASS

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          FAIL [fdo#105363] -> PASS

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-apl:          FAIL [fdo#102887] / [fdo#105363] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +7

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +3

  * {igt@kms_plane@pixel-format-pipe-b-planes-source-clamping}:
    - shard-glk:          SKIP [fdo#109271] -> PASS

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] -> PASS

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          FAIL [fdo#108145] -> PASS

  * igt@kms_setmode@basic:
    - shard-apl:          FAIL [fdo#99912] -> PASS

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-iclb:         FAIL [fdo#104894] -> PASS

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-apl:          FAIL -> PASS

  
#### Warnings ####

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-skl:          INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109301]: https://bugs.freedesktop.org/show_bug.cgi?id=109301
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
  [fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-hsw 


Build changes
-------------

    * Linux: CI_DRM_5817 -> Patchwork_12599

  CI_DRM_5817: 07abdbc9d99bcd754fc906237057369fe0399f93 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4904: b9cfd64009ca2536f7a997deabf34d88f2757511 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12599: b5342d54426e4ebbb07d29e27a50fdf85dfe7351 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12599/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

On 26/03/2019 09:53, Chris Wilson wrote:
> Quoting Jani Nikula (2019-03-26 09:34:45)
>> Not to block this series, but looking further outside the box...
>>
>> I've still got the constant vs. runtime device info split
>> unfinished. We've got so many things that are mostly constant, but
>> occasionally need changes. And we've got so many things that could be
>> device info flags, but would lead to proliferation of plenty of almost
>> identical device info structures. Like this ULX/ULT and GT number.
>>
>> So I guess I'm wondering if we're doing the right thing by assigning
>> device info pointers to the struct pci_device_id driver_data member in
>> pciidlist[] table.
>>
>> For one thing, that's a whole lot of bits that could be used directly
>> for assigning platform and subplatform, or features.
>>
>> Of course, we'd then need another table besides pciidlist[] to map to
>> the device info, but we're sort of doing some of that with the ULX/ULT
>> parts.
>>
>> I just overall feel that there must be a better way to do all this, and
>> we just haven't figured it out yet, and we're partially putting
>> ourselves into a box we can't break out of.
>>
>> Thoughts?
> 
> I think intel_device_info is still fundamentally useful. The
> disadvantage of having the feature discovery separate from use is
> outweighed by having consistent stanzas for those features - it makes
> comparing platforms, finding feature sets much easier. (The cost being
> that with the setting of the feature flag far away from the code using
> it, people updating the cost are more likely to forget the flag.)
> 
> One end goal of this madness, is that we can recompile the kernel module
> to only support a single sku and dce the rest. But what are the
> diminishing returns here? Without measurement, I'd say a single
> platform.
> 
> So that dictates what can be in the static intel_device_info, features
> that are constant across a whole platform. And as you point out, we
> don't need a pointer to the device_info itself, just a platform field
> which is an index into the device_info block, with plenty of room for
> subplatform flags.
> 
> While that says how we hook up device_info, I don't think that reflects
> on the use of feature flags themselves, or our ability to statically
> determine a reduced feature set.
> 
> So not a box, just a mere wet paper bag.

To check if I follow.. we are talking about potentially abolishing 
device info in favour of constructing something at probe time, which 
could potentially have fewer and overall smaller static data portion?

Because I don't see how we can eliminate the pciidlist itself, or even 
shrink it's size? It has to have one entry per device id, just the 
question for what we use driver_data for?

Static vs runtime I think shouldn't have effect on the per platform 
builds. As long as all feature tests are done via macros, or small 
static inlines, code can still be compiled out.

I do have a small nagging feeling about this series as well, but I have 
managed to convince myself it is better than the device id listed in 
i915_drv.h. So don't know.. we can always drop it and just expand 
platform mask to u64 to solve the immediate need and leave the rest for 
later.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

On 26/03/2019 08:39, Jani Nikula wrote:
> On Tue, 26 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Concept of a sub-platform already exist in our code (like ULX and ULT
>> platform variants and similar),implemented via the macros which check a
>> list of device ids to determine a match.
>>
>> With this patch we consolidate device ids checking into a single function
>> called during early driver load.
>>
>> A few low bits in the platform mask are reserved for sub-platform
>> identification and defined as a per-platform namespace.
>>
>> At the same time it future proofs the platform_mask handling by preparing
>> the code for easy extending, and tidies the very verbose WARN strings
>> generated when IS_PLATFORM macros are embedded into a WARN type
>> statements.
>>
>> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
>> v3: Chris was right, there is an ordering problem.
>>
>> v4:
>>   * Catch-up with new sub-platforms.
>>   * Rebase for RUNTIME_INFO.
>>   * Drop subplatform mask union tricks and convert platform_mask to an
>>     array for extensibility.
>>
>> v5:
>>   * Fix subplatform check.
>>   * Protect against forgetting to expand subplatform bits.
>>   * Remove platform enum tallying.
>>   * Add subplatform to error state. (Chris)
>>   * Drop macros and just use static inlines.
>>   * Remove redundant IRONLAKE_M. (Ville)
>>
>> v6:
>>   * Split out Ironlake change.
>>   * Optimize subplatform check.
>>   * Use __always_inline. (Lucas)
>>   * Add platform_mask comment. (Paulo)
>>   * Pass stored runtime info in error capture. (Chris)
>>
>> v7:
>>   * Rebased for new AML ULX device id.
>>   * Bump platform mask array size for EHL.
>>   * Stop mentioning device ids in intel_device_subplatform_init by using
>>     the trick of splitting macros i915_pciids.h. (Jani)
>>   * AML seems to be either a subplatform of KBL or CFL so express it like
>>     that.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jose Souza <jose.souza@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>>   drivers/gpu/drm/i915/i915_drv.h          | 124 +++++++++++++------
>>   drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>>   drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>>   drivers/gpu/drm/i915/intel_device_info.c | 145 +++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>>   6 files changed, 267 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5465b99b4392..74255374cc6b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>>   	if (i915_inject_load_failure())
>>   		return -ENODEV;
>>   
>> +	intel_device_info_subplatform_init(dev_priv);
>> +
>>   	spin_lock_init(&dev_priv->irq_lock);
>>   	spin_lock_init(&dev_priv->gpu_error.lock);
>>   	mutex_init(&dev_priv->backlight_lock);
>> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>>   	if (drm_debug & DRM_UT_DRIVER) {
>>   		struct drm_printer p = drm_debug_printer("i915 device info:");
>>   
>> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>>   			   INTEL_DEVID(dev_priv),
>>   			   INTEL_REVID(dev_priv),
>>   			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
>> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
>> +					     INTEL_INFO(dev_priv)->platform),
>>   			   INTEL_GEN(dev_priv));
>>   
>>   		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
>> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>>   	memcpy(device_info, match_info, sizeof(*device_info));
>>   	RUNTIME_INFO(i915)->device_id = pdev->device;
>>   
>> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> -		     BITS_PER_TYPE(device_info->platform_mask));
>>   	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>>   
>>   	return i915;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 48c3b139f36f..c29ebfd94065 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2298,7 +2298,68 @@ static inline unsigned int i915_sg_segment_size(void)
>>   #define IS_REVID(p, since, until) \
>>   	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>>   
>> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>> +static __always_inline unsigned int
>> +__platform_mask_index(const struct intel_runtime_info *info,
>> +		      enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	/* Expand the platform_mask array if this fails. */
>> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> +		     pbits * ARRAY_SIZE(info->platform_mask));
>> +
>> +	return p / pbits;
>> +}
>> +
>> +static __always_inline unsigned int
>> +__platform_mask_bit(const struct intel_runtime_info *info,
>> +		    enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static inline u32
>> +intel_subplatform(const struct intel_runtime_info *info,
>> +		      enum intel_platform p)
>> +{
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +
>> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static __always_inline bool
>> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +
>> +	return info->platform_mask[pi] & BIT(pb);
>> +}
>> +
>> +static __always_inline bool
>> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> +	       enum intel_platform p, unsigned int s)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
>> +	const u32 mask = info->platform_mask[pi];
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +	BUILD_BUG_ON(!__builtin_constant_p(s));
>> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
>> +
>> +	/* Shift and test on the MSB position so sign flag can be used. */
>> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
>> +}
>>   
>>   #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
>>   
>> @@ -2337,43 +2398,32 @@ static inline unsigned int i915_sg_segment_size(void)
>>   #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>>   #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>   				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
>> -/* ULX machines are also considered ULT. */
>> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> +#define IS_BDW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
>> +#define IS_BDW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
>>   #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> +#define IS_HSW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
>>   #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>>   #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 1)
>>   /* ULX machines are also considered ULT. */
>> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
>> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
>> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1926)
>> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
>> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x191E)
>> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5926)
>> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
>> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x591E)
>> -#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
>> -				 INTEL_DEVID(dev_priv) == 0x87C0 || \
>> -				 INTEL_DEVID(dev_priv) == 0x87CA)
>> +#define IS_HSW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
>> +#define IS_SKL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_SKL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_KBL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_KBL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_AML_ULX(dev_priv) \
>> +	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
>> +	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
>>   #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>> @@ -2384,16 +2434,16 @@ static inline unsigned int i915_sg_segment_size(void)
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> +#define IS_CFL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
>>   #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
>> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>> -#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
>> -					INTEL_DEVID(dev_priv) != 0x8A51)
>> +#define IS_CNL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
>> +#define IS_ICL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>>   
>>   #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index a9557f92756f..0c980b899056 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>>   	err_printf(m, "Reset count: %u\n", error->reset_count);
>>   	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>>   	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
>> +	err_printf(m, "Subplatform: 0x%x\n",
>> +		   intel_subplatform(&error->runtime_info,
>> +				     error->device_info.platform));
>>   	err_print_pciid(m, m->i915);
>>   
>>   	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 716f2f95c57d..39251586349a 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -32,7 +32,7 @@
>>   #include "i915_globals.h"
>>   #include "i915_selftest.h"
>>   
>> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
>> +#define PLATFORM(x) .platform = (x)
>>   #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>>   
>>   #define I845_PIPE_OFFSETS \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index e0ac908bb4e9..85da87e14c02 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -714,6 +714,151 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   	return 0;
>>   }
>>   
>> +#undef INTEL_VGA_DEVICE
>> +#define INTEL_VGA_DEVICE(id, info) (id)
>> +
>> +static const u16 hsw_ult_ids[] = {
>> +	INTEL_HSW_ULT_GT1_IDS(0),
>> +	INTEL_HSW_ULT_GT2_IDS(0),
>> +	INTEL_HSW_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 hsw_ulx_ids[] = {
>> +	INTEL_HSW_ULX_GT1_IDS(0),
>> +	INTEL_HSW_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 bdw_ult_ids[] = {
>> +	INTEL_BDW_ULT_GT1_IDS(0),
>> +	INTEL_BDW_ULT_GT2_IDS(0),
>> +	INTEL_BDW_ULT_GT3_IDS(0),
>> +	INTEL_BDW_ULT_RSVD_IDS(0)
>> +};
>> +
>> +static const u16 bdw_ulx_ids[] = {
>> +	INTEL_BDW_ULX_GT1_IDS(0),
>> +	INTEL_BDW_ULX_GT2_IDS(0),
>> +	INTEL_BDW_ULX_GT3_IDS(0),
>> +	INTEL_BDW_ULX_RSVD_IDS(0)
>> +};
>> +
>> +static const u16 skl_ult_ids[] = {
>> +	INTEL_SKL_ULT_GT1_IDS(0),
>> +	INTEL_SKL_ULT_GT2_IDS(0),
>> +	INTEL_SKL_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 skl_ulx_ids[] = {
>> +	INTEL_SKL_ULX_GT1_IDS(0),
>> +	INTEL_SKL_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 kbl_ult_ids[] = {
>> +	INTEL_KBL_ULT_GT1_IDS(0),
>> +	INTEL_KBL_ULT_GT2_IDS(0),
>> +	INTEL_KBL_ULT_GT3_IDS(0)
>> +};
>> +
>> +static const u16 kbl_ulx_ids[] = {
>> +	INTEL_KBL_ULX_GT1_IDS(0),
>> +	INTEL_KBL_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 kbl_aml_ids[] = {
>> +	INTEL_AML_KBL_GT2_IDS(0)
>> +};
>> +
>> +static const u16 cfl_ult_ids[] = {
>> +	INTEL_CFL_U_GT2_IDS(0),
>> +	INTEL_CFL_U_GT3_IDS(0),
>> +	INTEL_WHL_U_GT1_IDS(0),
>> +	INTEL_WHL_U_GT2_IDS(0),
>> +	INTEL_WHL_U_GT3_IDS(0)
>> +};
>> +
>> +static const u16 cfl_aml_ids[] = {
>> +	INTEL_AML_CFL_GT2_IDS(0)
>> +};
>> +
>> +static const u16 cnl_portf_ids[] = {
>> +	INTEL_CNL_PORT_F_IDS(0)
>> +};
>> +
>> +static const u16 icl_portf_ids[] = {
>> +	INTEL_ICL_PORT_F_IDS(0)
>> +};
> 
> What's the benefit of having platform split in the arrays and an if
> ladder in the function below?
> 
> I think I'd go with just the feature arrays.

Yeah agreed, it will look much better that way.

Regards,

Tvrtko

> 
> BR,
> Jani.
> 
>> +
>> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
>> +{
>> +	for (; num; num--, p++) {
>> +		if (*p == id)
>> +			return true;
>> +	}
>> +
>> +	return false;
>> +}
>> +
>> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> +{
>> +	const struct intel_device_info *info = INTEL_INFO(i915);
>> +	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
>> +	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
>> +	u16 devid = INTEL_DEVID(i915);
>> +	u32 mask = 0;
>> +
>> +	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
>> +
>> +	if (IS_HASWELL(i915)) {
>> +		if (find_devid(devid, hsw_ult_ids, ARRAY_SIZE(hsw_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, hsw_ulx_ids,
>> +				    ARRAY_SIZE(hsw_ulx_ids)))
>> +			/* ULX machines are also considered ULT. */
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
>> +			       BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_BROADWELL(i915)) {
>> +		if (find_devid(devid, bdw_ult_ids, ARRAY_SIZE(bdw_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, bdw_ulx_ids,
>> +				    ARRAY_SIZE(bdw_ulx_ids)))
>> +			/* ULX machines are also considered ULT. */
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT) |
>> +			       BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_SKYLAKE(i915)) {
>> +		if (find_devid(devid, skl_ult_ids, ARRAY_SIZE(skl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, skl_ulx_ids,
>> +				    ARRAY_SIZE(skl_ulx_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
>> +	} else if (IS_KABYLAKE(i915)) {
>> +		if (find_devid(devid, kbl_ult_ids, ARRAY_SIZE(kbl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, kbl_ulx_ids,
>> +				    ARRAY_SIZE(kbl_ulx_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULX);
>> +		else if (find_devid(devid, kbl_aml_ids,
>> +				    ARRAY_SIZE(kbl_aml_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_AML);
>> +	} else if (IS_COFFEELAKE(i915)) {
>> +		if (find_devid(devid, cfl_ult_ids, ARRAY_SIZE(cfl_ult_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +		else if (find_devid(devid, cfl_aml_ids,
>> +				    ARRAY_SIZE(cfl_aml_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_AML);
>> +	} else if (IS_CANNONLAKE(i915)) {
>> +		if (find_devid(devid, cnl_portf_ids, ARRAY_SIZE(cnl_portf_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
>> +	} else if (IS_ICELAKE(i915)) {
>> +		if (find_devid(devid, icl_portf_ids, ARRAY_SIZE(icl_portf_ids)))
>> +			mask = BIT(INTEL_SUBPLATFORM_PORTF);
>> +	}
>> +
>> +	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
>> +
>> +	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
>> +}
>> +
>>   /**
>>    * intel_device_info_runtime_init - initialize runtime info
>>    * @dev_priv: the i915 device
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 98acefaacec9..da1152eef46b 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -77,6 +77,21 @@ enum intel_platform {
>>   	INTEL_MAX_PLATFORMS
>>   };
>>   
>> +/*
>> + * Subplatform bits share the same namespace per parent platform. In other words
>> + * it is fine for the same bit to be used on multiple parent platforms.
>> + */
>> +
>> +#define INTEL_SUBPLATFORM_BITS (3)
>> +
>> +/* HSW/BDW/SKL/KBL/CFL */
>> +#define INTEL_SUBPLATFORM_ULT	(0)
>> +#define INTEL_SUBPLATFORM_ULX	(1)
>> +#define INTEL_SUBPLATFORM_AML	(2)
>> +
>> +/* CNL/ICL */
>> +#define INTEL_SUBPLATFORM_PORTF	(0)
>> +
>>   enum intel_ppgtt_type {
>>   	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
>>   	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
>> @@ -160,7 +175,6 @@ struct intel_device_info {
>>   	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>>   
>>   	enum intel_platform platform;
>> -	u32 platform_mask;
>>   
>>   	enum intel_ppgtt_type ppgtt_type;
>>   	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
>> @@ -197,6 +211,16 @@ struct intel_device_info {
>>   };
>>   
>>   struct intel_runtime_info {
>> +	/*
>> +	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
>> +	 * into single runtime conditionals, and also to provide groundwork
>> +	 * for future per platform, or per SKU build optimizations.
>> +	 *
>> +	 * Array can be extended when necessary if the corresponding
>> +	 * BUILD_BUG_ON is hit.
>> +	 */
>> +	u32 platform_mask[2];
>> +
>>   	u16 device_id;
>>   
>>   	u8 num_sprites[I915_MAX_PIPES];
>> @@ -271,6 +295,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>>   
>>   const char *intel_platform_name(enum intel_platform platform);
>>   
>> +void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
>>   void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>>   void intel_device_info_dump_flags(const struct intel_device_info *info,
>>   				  struct drm_printer *p);
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-27 11:35:41)
> 
> On 26/03/2019 09:53, Chris Wilson wrote:
> > Quoting Jani Nikula (2019-03-26 09:34:45)
> >> Not to block this series, but looking further outside the box...
> >>
> >> I've still got the constant vs. runtime device info split
> >> unfinished. We've got so many things that are mostly constant, but
> >> occasionally need changes. And we've got so many things that could be
> >> device info flags, but would lead to proliferation of plenty of almost
> >> identical device info structures. Like this ULX/ULT and GT number.
> >>
> >> So I guess I'm wondering if we're doing the right thing by assigning
> >> device info pointers to the struct pci_device_id driver_data member in
> >> pciidlist[] table.
> >>
> >> For one thing, that's a whole lot of bits that could be used directly
> >> for assigning platform and subplatform, or features.
> >>
> >> Of course, we'd then need another table besides pciidlist[] to map to
> >> the device info, but we're sort of doing some of that with the ULX/ULT
> >> parts.
> >>
> >> I just overall feel that there must be a better way to do all this, and
> >> we just haven't figured it out yet, and we're partially putting
> >> ourselves into a box we can't break out of.
> >>
> >> Thoughts?
> > 
> > I think intel_device_info is still fundamentally useful. The
> > disadvantage of having the feature discovery separate from use is
> > outweighed by having consistent stanzas for those features - it makes
> > comparing platforms, finding feature sets much easier. (The cost being
> > that with the setting of the feature flag far away from the code using
> > it, people updating the cost are more likely to forget the flag.)
> > 
> > One end goal of this madness, is that we can recompile the kernel module
> > to only support a single sku and dce the rest. But what are the
> > diminishing returns here? Without measurement, I'd say a single
> > platform.
> > 
> > So that dictates what can be in the static intel_device_info, features
> > that are constant across a whole platform. And as you point out, we
> > don't need a pointer to the device_info itself, just a platform field
> > which is an index into the device_info block, with plenty of room for
> > subplatform flags.
> > 
> > While that says how we hook up device_info, I don't think that reflects
> > on the use of feature flags themselves, or our ability to statically
> > determine a reduced feature set.
> > 
> > So not a box, just a mere wet paper bag.
> 
> To check if I follow.. we are talking about potentially abolishing 
> device info in favour of constructing something at probe time, which 
> could potentially have fewer and overall smaller static data portion?
> 
> Because I don't see how we can eliminate the pciidlist itself, or even 
> shrink it's size? It has to have one entry per device id, just the 
> question for what we use driver_data for?

Correct. What I think Jani was suggesting was that instead of encoding
the device_info pointer into driver_data, we encode the
platform/subplatform id. We then use the platform portion to lookup the
device_info, and subplatform to annotate the runtime_info.

> Static vs runtime I think shouldn't have effect on the per platform 
> builds. As long as all feature tests are done via macros, or small 
> static inlines, code can still be compiled out.
> 
> I do have a small nagging feeling about this series as well, but I have 
> managed to convince myself it is better than the device id listed in 
> i915_drv.h.

I still feel the pain from having the endless chains of || and so
welcome the removal of devid from the macros.

> So don't know.. we can always drop it and just expand 
> platform mask to u64 to solve the immediate need and leave the rest for 
> later.

Imo, this series is an improvement, and doesn't prevent us from changing
our minds later (although not back to devid macros please!).
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Wed, 27 Mar 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Tvrtko Ursulin (2019-03-27 11:35:41)
>> 
>> On 26/03/2019 09:53, Chris Wilson wrote:
>> > Quoting Jani Nikula (2019-03-26 09:34:45)
>> >> Not to block this series, but looking further outside the box...
>> >>
>> >> I've still got the constant vs. runtime device info split
>> >> unfinished. We've got so many things that are mostly constant, but
>> >> occasionally need changes. And we've got so many things that could be
>> >> device info flags, but would lead to proliferation of plenty of almost
>> >> identical device info structures. Like this ULX/ULT and GT number.
>> >>
>> >> So I guess I'm wondering if we're doing the right thing by assigning
>> >> device info pointers to the struct pci_device_id driver_data member in
>> >> pciidlist[] table.
>> >>
>> >> For one thing, that's a whole lot of bits that could be used directly
>> >> for assigning platform and subplatform, or features.
>> >>
>> >> Of course, we'd then need another table besides pciidlist[] to map to
>> >> the device info, but we're sort of doing some of that with the ULX/ULT
>> >> parts.
>> >>
>> >> I just overall feel that there must be a better way to do all this, and
>> >> we just haven't figured it out yet, and we're partially putting
>> >> ourselves into a box we can't break out of.
>> >>
>> >> Thoughts?
>> > 
>> > I think intel_device_info is still fundamentally useful. The
>> > disadvantage of having the feature discovery separate from use is
>> > outweighed by having consistent stanzas for those features - it makes
>> > comparing platforms, finding feature sets much easier. (The cost being
>> > that with the setting of the feature flag far away from the code using
>> > it, people updating the cost are more likely to forget the flag.)
>> > 
>> > One end goal of this madness, is that we can recompile the kernel module
>> > to only support a single sku and dce the rest. But what are the
>> > diminishing returns here? Without measurement, I'd say a single
>> > platform.
>> > 
>> > So that dictates what can be in the static intel_device_info, features
>> > that are constant across a whole platform. And as you point out, we
>> > don't need a pointer to the device_info itself, just a platform field
>> > which is an index into the device_info block, with plenty of room for
>> > subplatform flags.
>> > 
>> > While that says how we hook up device_info, I don't think that reflects
>> > on the use of feature flags themselves, or our ability to statically
>> > determine a reduced feature set.
>> > 
>> > So not a box, just a mere wet paper bag.
>> 
>> To check if I follow.. we are talking about potentially abolishing 
>> device info in favour of constructing something at probe time, which 
>> could potentially have fewer and overall smaller static data portion?
>> 
>> Because I don't see how we can eliminate the pciidlist itself, or even 
>> shrink it's size? It has to have one entry per device id, just the 
>> question for what we use driver_data for?
>
> Correct. What I think Jani was suggesting was that instead of encoding
> the device_info pointer into driver_data, we encode the
> platform/subplatform id. We then use the platform portion to lookup the
> device_info, and subplatform to annotate the runtime_info.
>
>> Static vs runtime I think shouldn't have effect on the per platform 
>> builds. As long as all feature tests are done via macros, or small 
>> static inlines, code can still be compiled out.
>> 
>> I do have a small nagging feeling about this series as well, but I have 
>> managed to convince myself it is better than the device id listed in 
>> i915_drv.h.
>
> I still feel the pain from having the endless chains of || and so
> welcome the removal of devid from the macros.
>
>> So don't know.. we can always drop it and just expand 
>> platform mask to u64 to solve the immediate need and leave the rest for 
>> later.
>
> Imo, this series is an improvement, and doesn't prevent us from changing
> our minds later (although not back to devid macros please!).

Okay, let me still ask this:

Why do we have gt member in device info, leading to plenty of device
info duplication? Why should we add ULT/ULX as separate tables instead
of flags in device info where they'd fid perfectly well. This choice is
purely arbitrary. The only reason ULT/ULX isn't in device info is
because it would lead to so much duplication.

A lot of this could go away if we were able to encode a bunch of the
flags in a single array similar to pciidtable.

(I agree this series, modulo some nitpicks, is an improvement over
status quo, I'm just playing the devil's advocate and trying to come up
with something better.)

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Concept of a sub-platform already exist in our code (like ULX and ULT
platform variants and similar),implemented via the macros which check a
list of device ids to determine a match.

With this patch we consolidate device ids checking into a single function
called during early driver load.

A few low bits in the platform mask are reserved for sub-platform
identification and defined as a per-platform namespace.

At the same time it future proofs the platform_mask handling by preparing
the code for easy extending, and tidies the very verbose WARN strings
generated when IS_PLATFORM macros are embedded into a WARN type
statements.

v2: Fixed IS_SUBPLATFORM. Updated commit msg.
v3: Chris was right, there is an ordering problem.

v4:
 * Catch-up with new sub-platforms.
 * Rebase for RUNTIME_INFO.
 * Drop subplatform mask union tricks and convert platform_mask to an
   array for extensibility.

v5:
 * Fix subplatform check.
 * Protect against forgetting to expand subplatform bits.
 * Remove platform enum tallying.
 * Add subplatform to error state. (Chris)
 * Drop macros and just use static inlines.
 * Remove redundant IRONLAKE_M. (Ville)

v6:
 * Split out Ironlake change.
 * Optimize subplatform check.
 * Use __always_inline. (Lucas)
 * Add platform_mask comment. (Paulo)
 * Pass stored runtime info in error capture. (Chris)

v7:
 * Rebased for new AML ULX device id.
 * Bump platform mask array size for EHL.
 * Stop mentioning device ids in intel_device_subplatform_init by using
   the trick of splitting macros i915_pciids.h. (Jani)
 * AML seems to be either a subplatform of KBL or CFL so express it like
   that.

v8:
 * Use one device id table per subplatform. (Jani)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
---
 drivers/gpu/drm/i915/i915_drv.c          |   8 +-
 drivers/gpu/drm/i915/i915_drv.h          | 123 ++++++++++++++++-------
 drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
 drivers/gpu/drm/i915/i915_pci.c          |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c |  93 +++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
 6 files changed, 214 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f1334f5d4ead..74734d7661e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 	if (i915_inject_load_failure())
 		return -ENODEV;
 
+	intel_device_info_subplatform_init(dev_priv);
+
 	spin_lock_init(&dev_priv->irq_lock);
 	spin_lock_init(&dev_priv->gpu_error.lock);
 	mutex_init(&dev_priv->backlight_lock);
@@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 	if (drm_debug & DRM_UT_DRIVER) {
 		struct drm_printer p = drm_debug_printer("i915 device info:");
 
-		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
+		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 			   INTEL_DEVID(dev_priv),
 			   INTEL_REVID(dev_priv),
 			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
+			   intel_subplatform(RUNTIME_INFO(dev_priv),
+					     INTEL_INFO(dev_priv)->platform),
 			   INTEL_GEN(dev_priv));
 
 		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
@@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 	memcpy(device_info, match_info, sizeof(*device_info));
 	RUNTIME_INFO(i915)->device_id = pdev->device;
 
-	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-		     BITS_PER_TYPE(device_info->platform_mask));
 	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
 
 	return i915;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d3cab9406e1..b7d3f3a45ed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_REVID(p, since, until) \
 	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
+static __always_inline unsigned int
+__platform_mask_index(const struct intel_runtime_info *info,
+		      enum intel_platform p)
+{
+	const unsigned int pbits =
+		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+	/* Expand the platform_mask array if this fails. */
+	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+		     pbits * ARRAY_SIZE(info->platform_mask));
+
+	return p / pbits;
+}
+
+static __always_inline unsigned int
+__platform_mask_bit(const struct intel_runtime_info *info,
+		    enum intel_platform p)
+{
+	const unsigned int pbits =
+		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+	return p % pbits + INTEL_SUBPLATFORM_BITS;
+}
+
+static inline u32
+intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
+{
+	const unsigned int pi = __platform_mask_index(info, p);
+
+	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
+}
+
+static __always_inline bool
+IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
+{
+	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(info, p);
+	const unsigned int pb = __platform_mask_bit(info, p);
+
+	BUILD_BUG_ON(!__builtin_constant_p(p));
+
+	return info->platform_mask[pi] & BIT(pb);
+}
+
+static __always_inline bool
+IS_SUBPLATFORM(const struct drm_i915_private *i915,
+	       enum intel_platform p, unsigned int s)
+{
+	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(info, p);
+	const unsigned int pb = __platform_mask_bit(info, p);
+	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
+	const u32 mask = info->platform_mask[pi];
+
+	BUILD_BUG_ON(!__builtin_constant_p(p));
+	BUILD_BUG_ON(!__builtin_constant_p(s));
+	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
+
+	/* Shift and test on the MSB position so sign flag can be used. */
+	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
+}
 
 #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
 
@@ -2337,43 +2397,32 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
-/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
+#define IS_BDW_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 1)
 /* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
-				 INTEL_DEVID(dev_priv) == 0x0A1E)
-#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
-				 INTEL_DEVID(dev_priv) == 0x1913 || \
-				 INTEL_DEVID(dev_priv) == 0x1916 || \
-				 INTEL_DEVID(dev_priv) == 0x1921 || \
-				 INTEL_DEVID(dev_priv) == 0x1926)
-#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
-				 INTEL_DEVID(dev_priv) == 0x1915 || \
-				 INTEL_DEVID(dev_priv) == 0x191E)
-#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
-				 INTEL_DEVID(dev_priv) == 0x5913 || \
-				 INTEL_DEVID(dev_priv) == 0x5916 || \
-				 INTEL_DEVID(dev_priv) == 0x5921 || \
-				 INTEL_DEVID(dev_priv) == 0x5926)
-#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
-				 INTEL_DEVID(dev_priv) == 0x5915 || \
-				 INTEL_DEVID(dev_priv) == 0x591E)
-#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
-				 INTEL_DEVID(dev_priv) == 0x87C0 || \
-				 INTEL_DEVID(dev_priv) == 0x87CA)
+#define IS_HSW_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
+#define IS_SKL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_SKL_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_KBL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_KBL_ULX(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_AML_ULX(dev_priv) \
+	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
+	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
@@ -2384,16 +2433,16 @@ static inline unsigned int i915_sg_segment_size(void)
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_ULT(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
 				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
-					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
-#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
-					INTEL_DEVID(dev_priv) != 0x8A51)
+#define IS_CNL_WITH_PORT_F(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
+#define IS_ICL_WITH_PORT_F(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a2a98ccda421..81a27b808273 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 	err_printf(m, "Reset count: %u\n", error->reset_count);
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
+	err_printf(m, "Subplatform: 0x%x\n",
+		   intel_subplatform(&error->runtime_info,
+				     error->device_info.platform));
 	err_print_pciid(m, m->i915);
 
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 716f2f95c57d..39251586349a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -32,7 +32,7 @@
 #include "i915_globals.h"
 #include "i915_selftest.h"
 
-#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
+#define PLATFORM(x) .platform = (x)
 #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
 
 #define I845_PIPE_OFFSETS \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e0f5e0231d04..0ed49d032c00 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -714,6 +714,99 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+#undef INTEL_VGA_DEVICE
+#define INTEL_VGA_DEVICE(id, info) (id)
+
+static const u16 subplatform_ult_ids[] = {
+	INTEL_HSW_ULT_GT1_IDS(0),
+	INTEL_HSW_ULT_GT2_IDS(0),
+	INTEL_HSW_ULT_GT3_IDS(0),
+	INTEL_BDW_ULT_GT1_IDS(0),
+	INTEL_BDW_ULT_GT2_IDS(0),
+	INTEL_BDW_ULT_GT3_IDS(0),
+	INTEL_BDW_ULT_RSVD_IDS(0),
+	INTEL_SKL_ULT_GT1_IDS(0),
+	INTEL_SKL_ULT_GT2_IDS(0),
+	INTEL_SKL_ULT_GT3_IDS(0),
+	INTEL_KBL_ULT_GT1_IDS(0),
+	INTEL_KBL_ULT_GT2_IDS(0),
+	INTEL_KBL_ULT_GT3_IDS(0),
+	INTEL_CFL_U_GT2_IDS(0),
+	INTEL_CFL_U_GT3_IDS(0),
+	INTEL_WHL_U_GT1_IDS(0),
+	INTEL_WHL_U_GT2_IDS(0),
+	INTEL_WHL_U_GT3_IDS(0)
+};
+
+static const u16 subplatform_ulx_ids[] = {
+	INTEL_HSW_ULX_GT1_IDS(0),
+	INTEL_HSW_ULX_GT2_IDS(0),
+	INTEL_BDW_ULX_GT1_IDS(0),
+	INTEL_BDW_ULX_GT2_IDS(0),
+	INTEL_BDW_ULX_GT3_IDS(0),
+	INTEL_BDW_ULX_RSVD_IDS(0),
+	INTEL_SKL_ULX_GT1_IDS(0),
+	INTEL_SKL_ULX_GT2_IDS(0),
+	INTEL_KBL_ULX_GT1_IDS(0),
+	INTEL_KBL_ULX_GT2_IDS(0)
+};
+
+static const u16 subplatform_aml_ids[] = {
+	INTEL_AML_KBL_GT2_IDS(0),
+	INTEL_AML_CFL_GT2_IDS(0)
+};
+
+static const u16 subplatform_portf_ids[] = {
+	INTEL_CNL_PORT_F_IDS(0),
+	INTEL_ICL_PORT_F_IDS(0)
+};
+
+static bool find_devid(u16 id, const u16 *p, unsigned int num)
+{
+	for (; num; num--, p++) {
+		if (*p == id)
+			return true;
+	}
+
+	return false;
+}
+
+void intel_device_info_subplatform_init(struct drm_i915_private *i915)
+{
+	const struct intel_device_info *info = INTEL_INFO(i915);
+	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
+	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
+	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
+	u16 devid = INTEL_DEVID(i915);
+	u32 mask;
+
+	/* Make sure IS_<platform> checks are working. */
+	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
+
+	/* Find and mark subplatform bits based on the PCI device id. */
+	if (find_devid(devid, subplatform_ult_ids,
+		       ARRAY_SIZE(subplatform_ult_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_ULT);
+	} else if (find_devid(devid, subplatform_ulx_ids,
+			      ARRAY_SIZE(subplatform_ulx_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_ULX);
+		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+			/* ULX machines are also considered ULT. */
+			mask |= BIT(INTEL_SUBPLATFORM_ULT);
+		}
+	} else if (find_devid(devid, subplatform_aml_ids,
+			      ARRAY_SIZE(subplatform_aml_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_AML);
+	} else if (find_devid(devid, subplatform_portf_ids,
+			      ARRAY_SIZE(subplatform_portf_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_PORTF);
+	}
+
+	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
+
+	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
+}
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 7e04b4829aba..616e9f707877 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -77,6 +77,21 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
+/*
+ * Subplatform bits share the same namespace per parent platform. In other words
+ * it is fine for the same bit to be used on multiple parent platforms.
+ */
+
+#define INTEL_SUBPLATFORM_BITS (3)
+
+/* HSW/BDW/SKL/KBL/CFL */
+#define INTEL_SUBPLATFORM_ULT	(0)
+#define INTEL_SUBPLATFORM_ULX	(1)
+#define INTEL_SUBPLATFORM_AML	(2)
+
+/* CNL/ICL */
+#define INTEL_SUBPLATFORM_PORTF	(0)
+
 enum intel_ppgtt_type {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
@@ -160,7 +175,6 @@ struct intel_device_info {
 	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
 
 	enum intel_platform platform;
-	u32 platform_mask;
 
 	enum intel_ppgtt_type ppgtt_type;
 	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
@@ -197,6 +211,16 @@ struct intel_device_info {
 };
 
 struct intel_runtime_info {
+	/*
+	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
+	 * into single runtime conditionals, and also to provide groundwork
+	 * for future per platform, or per SKU build optimizations.
+	 *
+	 * Array can be extended when necessary if the corresponding
+	 * BUILD_BUG_ON is hit.
+	 */
+	u32 platform_mask[2];
+
 	u16 device_id;
 
 	u8 num_sprites[I915_MAX_PIPES];
@@ -267,6 +291,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
 
 const char *intel_platform_name(enum intel_platform platform);
 
+void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);
-- 
2.19.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

On 27/03/2019 12:03, Jani Nikula wrote:
> On Wed, 27 Mar 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> Quoting Tvrtko Ursulin (2019-03-27 11:35:41)
>>>
>>> On 26/03/2019 09:53, Chris Wilson wrote:
>>>> Quoting Jani Nikula (2019-03-26 09:34:45)
>>>>> Not to block this series, but looking further outside the box...
>>>>>
>>>>> I've still got the constant vs. runtime device info split
>>>>> unfinished. We've got so many things that are mostly constant, but
>>>>> occasionally need changes. And we've got so many things that could be
>>>>> device info flags, but would lead to proliferation of plenty of almost
>>>>> identical device info structures. Like this ULX/ULT and GT number.
>>>>>
>>>>> So I guess I'm wondering if we're doing the right thing by assigning
>>>>> device info pointers to the struct pci_device_id driver_data member in
>>>>> pciidlist[] table.
>>>>>
>>>>> For one thing, that's a whole lot of bits that could be used directly
>>>>> for assigning platform and subplatform, or features.
>>>>>
>>>>> Of course, we'd then need another table besides pciidlist[] to map to
>>>>> the device info, but we're sort of doing some of that with the ULX/ULT
>>>>> parts.
>>>>>
>>>>> I just overall feel that there must be a better way to do all this, and
>>>>> we just haven't figured it out yet, and we're partially putting
>>>>> ourselves into a box we can't break out of.
>>>>>
>>>>> Thoughts?
>>>>
>>>> I think intel_device_info is still fundamentally useful. The
>>>> disadvantage of having the feature discovery separate from use is
>>>> outweighed by having consistent stanzas for those features - it makes
>>>> comparing platforms, finding feature sets much easier. (The cost being
>>>> that with the setting of the feature flag far away from the code using
>>>> it, people updating the cost are more likely to forget the flag.)
>>>>
>>>> One end goal of this madness, is that we can recompile the kernel module
>>>> to only support a single sku and dce the rest. But what are the
>>>> diminishing returns here? Without measurement, I'd say a single
>>>> platform.
>>>>
>>>> So that dictates what can be in the static intel_device_info, features
>>>> that are constant across a whole platform. And as you point out, we
>>>> don't need a pointer to the device_info itself, just a platform field
>>>> which is an index into the device_info block, with plenty of room for
>>>> subplatform flags.
>>>>
>>>> While that says how we hook up device_info, I don't think that reflects
>>>> on the use of feature flags themselves, or our ability to statically
>>>> determine a reduced feature set.
>>>>
>>>> So not a box, just a mere wet paper bag.
>>>
>>> To check if I follow.. we are talking about potentially abolishing
>>> device info in favour of constructing something at probe time, which
>>> could potentially have fewer and overall smaller static data portion?
>>>
>>> Because I don't see how we can eliminate the pciidlist itself, or even
>>> shrink it's size? It has to have one entry per device id, just the
>>> question for what we use driver_data for?
>>
>> Correct. What I think Jani was suggesting was that instead of encoding
>> the device_info pointer into driver_data, we encode the
>> platform/subplatform id. We then use the platform portion to lookup the
>> device_info, and subplatform to annotate the runtime_info.
>>
>>> Static vs runtime I think shouldn't have effect on the per platform
>>> builds. As long as all feature tests are done via macros, or small
>>> static inlines, code can still be compiled out.
>>>
>>> I do have a small nagging feeling about this series as well, but I have
>>> managed to convince myself it is better than the device id listed in
>>> i915_drv.h.
>>
>> I still feel the pain from having the endless chains of || and so
>> welcome the removal of devid from the macros.
>>
>>> So don't know.. we can always drop it and just expand
>>> platform mask to u64 to solve the immediate need and leave the rest for
>>> later.
>>
>> Imo, this series is an improvement, and doesn't prevent us from changing
>> our minds later (although not back to devid macros please!).
> 
> Okay, let me still ask this:
> 
> Why do we have gt member in device info, leading to plenty of device
> info duplication? Why should we add ULT/ULX as separate tables instead
> of flags in device info where they'd fid perfectly well. This choice is
> purely arbitrary. The only reason ULT/ULX isn't in device info is
> because it would lead to so much duplication.

Agreed with everything here.

Perhaps for instance moving GT into runtime would further improve 
things. Someone mentioned GT somewhere around here.. So same approach 
with id tables/macros as with subplatform. If the downside of not being 
to compile out GT configurations within a single platform is not a concern.

> A lot of this could go away if we were able to encode a bunch of the
> flags in a single array similar to pciidtable.

I don't see how we can encode everything to distinguish a platform in an 
unsigned long, not even on 64-bit?

> (I agree this series, modulo some nitpicks, is an improvement over
> status quo, I'm just playing the devil's advocate and trying to come up
> with something better.)

In this case an updated version should be in your mailbox.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Wed, 27 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 27/03/2019 12:03, Jani Nikula wrote:
>> A lot of this could go away if we were able to encode a bunch of the
>> flags in a single array similar to pciidtable.
>
> I don't see how we can encode everything to distinguish a platform in an 
> unsigned long, not even on 64-bit?

Me neither. That's why I'm blabbering here instead of writing a
patch. :p

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for Device id consolidation (rev2)

[Patchwork]

== Series Details ==

Series: Device id consolidation (rev2)
URL   : https://patchwork.freedesktop.org/series/58561/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
41661f3ceb00 drm/i915: Split Pineview device info into desktop and mobile
871661fc5d65 drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
-:44: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#44: FILE: drivers/gpu/drm/i915/i915_drv.h:2321:
+#define IS_IRONLAKE_M(dev_priv) \
+	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
8551b470ae66 drm/i915: Split some PCI ids into separate groups
-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#34: FILE: include/drm/i915_pciids.h:171:
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#34: FILE: include/drm/i915_pciids.h:171:
+#define INTEL_HSW_ULT_GT1_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
+	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
+	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */

-:66: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#66: FILE: include/drm/i915_pciids.h:199:
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#66: FILE: include/drm/i915_pciids.h:199:
+#define INTEL_HSW_ULT_GT2_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
+	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */

-:99: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#99: FILE: include/drm/i915_pciids.h:228:
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */

-:99: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#99: FILE: include/drm/i915_pciids.h:228:
+#define INTEL_HSW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
+	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */

-:134: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#134: FILE: include/drm/i915_pciids.h:265:
+#define INTEL_BDW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */

-:134: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#134: FILE: include/drm/i915_pciids.h:265:
+#define INTEL_BDW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x160B, info)  /* GT1 Iris */

-:143: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#143: FILE: include/drm/i915_pciids.h:272:
+#define INTEL_BDW_GT1_IDS(info) \
+	INTEL_BDW_ULT_GT1_IDS(info), \
+	INTEL_BDW_ULX_GT1_IDS(info), \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */

-:143: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#143: FILE: include/drm/i915_pciids.h:272:
+#define INTEL_BDW_GT1_IDS(info) \
+	INTEL_BDW_ULT_GT1_IDS(info), \
+	INTEL_BDW_ULX_GT1_IDS(info), \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info)  /* GT1 Workstation */

-:152: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#152: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */

-:152: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#152: FILE: include/drm/i915_pciids.h:279:
+#define INTEL_BDW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161B, info)  /* GT2 ULT */

-:161: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#161: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT2_IDS(info) \
+	INTEL_BDW_ULT_GT2_IDS(info), \
+	INTEL_BDW_ULX_GT2_IDS(info), \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */

-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#161: FILE: include/drm/i915_pciids.h:286:
+#define INTEL_BDW_GT2_IDS(info) \
+	INTEL_BDW_ULT_GT2_IDS(info), \
+	INTEL_BDW_ULX_GT2_IDS(info), \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */	\
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */

-:168: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#168: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
+

-:168: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#168: FILE: include/drm/i915_pciids.h:293:
+#define INTEL_BDW_ULT_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info)  /* Iris */ \
+

-:185: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#185: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info)  /* Iris */

-:185: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#185: FILE: include/drm/i915_pciids.h:307:
+#define INTEL_BDW_ULT_RSVD_IDS(info) \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info)  /* Iris */

-:222: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#222: FILE: include/drm/i915_pciids.h:346:
+#define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */

-:222: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#222: FILE: include/drm/i915_pciids.h:346:
+#define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info)  /* ULT GT2F */

-:231: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#231: FILE: include/drm/i915_pciids.h:353:
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_SKL_ULT_GT2_IDS(info), \
+	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */

-:231: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#231: FILE: include/drm/i915_pciids.h:353:
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_SKL_ULT_GT2_IDS(info), \
+	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */

-:256: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#256: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_KBL_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */

-:256: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#256: FILE: include/drm/i915_pciids.h:395:
+#define INTEL_KBL_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x5913, info)  /* ULT GT1.5 */

-:260: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#260: FILE: include/drm/i915_pciids.h:399:
+#define INTEL_KBL_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */

-:260: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#260: FILE: include/drm/i915_pciids.h:399:
+#define INTEL_KBL_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5915, info)  /* ULX GT1.5 */

-:264: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#264: FILE: include/drm/i915_pciids.h:403:
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_KBL_ULT_GT1_IDS(info), \
+	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */

-:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#264: FILE: include/drm/i915_pciids.h:403:
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_KBL_ULT_GT1_IDS(info), \
+	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
 	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */

-:273: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#273: FILE: include/drm/i915_pciids.h:411:
+#define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */

-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#273: FILE: include/drm/i915_pciids.h:411:
+#define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info)  /* ULT GT2F */

-:280: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#280: FILE: include/drm/i915_pciids.h:418:
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_KBL_ULT_GT2_IDS(info), \
+	INTEL_KBL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */

-:280: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#280: FILE: include/drm/i915_pciids.h:418:
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_KBL_ULT_GT2_IDS(info), \
+	INTEL_KBL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
 	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */

-:305: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#305: FILE: include/drm/i915_pciids.h:539:
+#define INTEL_CNL_PORT_F_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info), \
+	INTEL_VGA_DEVICE(0x5A44, info), \
+	INTEL_VGA_DEVICE(0x5A4C, info)

-:305: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#305: FILE: include/drm/i915_pciids.h:539:
+#define INTEL_CNL_PORT_F_IDS(info) \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info), \
+	INTEL_VGA_DEVICE(0x5A44, info), \
+	INTEL_VGA_DEVICE(0x5A4C, info)

-:329: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#329: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
 	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info), \
 	INTEL_VGA_DEVICE(0x8A59, info),	\

-:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#329: FILE: include/drm/i915_pciids.h:559:
+#define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
 	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info), \
 	INTEL_VGA_DEVICE(0x8A59, info),	\

-:339: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#339: FILE: include/drm/i915_pciids.h:574:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_ICL_PORT_F_IDS(info), \
+	INTEL_VGA_DEVICE(0x8A51, info)

-:339: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#339: FILE: include/drm/i915_pciids.h:574:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_ICL_PORT_F_IDS(info), \
+	INTEL_VGA_DEVICE(0x8A51, info)

total: 19 errors, 0 warnings, 19 checks, 305 lines checked
4f6f1609d5d1 drm/i915: Introduce concept of a sub-platform
-:235: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#235: FILE: drivers/gpu/drm/i915/i915_drv.h:2423:
+#define IS_AML_ULX(dev_priv) \
+	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
+	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))

total: 0 errors, 0 warnings, 1 checks, 348 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.SPARSE: warning for Device id consolidation (rev2)

[Patchwork]

== Series Details ==

Series: Device id consolidation (rev2)
URL   : https://patchwork.freedesktop.org/series/58561/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Split Pineview device info into desktop and mobile
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3564:16: warning: expression using sizeof(void)

Commit: drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3564:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void)

Commit: drm/i915: Split some PCI ids into separate groups
Okay!

Commit: drm/i915: Introduce concept of a sub-platform
-drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gpu_error.c:900:23: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for Device id consolidation (rev2)

[Patchwork]

== Series Details ==

Series: Device id consolidation (rev2)
URL   : https://patchwork.freedesktop.org/series/58561/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5827 -> Patchwork_12616
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58561/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12616 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@userptr:
    - fi-kbl-8809g:       PASS -> DMESG-WARN [fdo#108965]

  * igt@gem_exec_store@basic-bsd2:
    - fi-hsw-4770:        NOTRUN -> SKIP [fdo#109271] +41

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-skl-6700k2:      NOTRUN -> SKIP [fdo#109271] +26

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          PASS -> FAIL [fdo#103167]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-apl-guc:         NOTRUN -> DMESG-WARN [fdo#108529] / [fdo#108566]

  * igt@kms_psr@primary_page_flip:
    - fi-apl-guc:         NOTRUN -> SKIP [fdo#109271] +50

  
#### Possible fixes ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-skl-6700k2:      INCOMPLETE [fdo#104108] -> PASS

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-byt-clapper:     FAIL [fdo#107362] -> PASS

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720


Participating hosts (39 -> 35)
------------------------------

  Additional (2): fi-hsw-4770 fi-apl-guc 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus fi-kbl-r 


Build changes
-------------

    * Linux: CI_DRM_5827 -> Patchwork_12616

  CI_DRM_5827: d90542b50bfba088d53e8f520c05080e5ca764e7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4909: 7df3eeb4f3360cd2b511c31acc1c52bd7ce6587f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12616: 4f6f1609d5d18d208431f910a3b1e2d28cd623fa @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4f6f1609d5d1 drm/i915: Introduce concept of a sub-platform
8551b470ae66 drm/i915: Split some PCI ids into separate groups
871661fc5d65 drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
41661f3ceb00 drm/i915: Split Pineview device info into desktop and mobile

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12616/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/4] Device id consolidation

[Tvrtko Ursulin]

On 26/03/2019 07:40, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Series removes device id checks from i915_drv.h macros and consolidates them to
> i915_pciids.h as the main "database", while making intel_device_info.c reference
> the former, expanding the existing concept of a platform mask by a few low bits
> reserved for sub-platform mask.
> 
> This has a two-fold positive effect of firstly consolidating the list of device
> ids to one location, and secondly removing the if-ladders from every
> IS_<platfrom>_<subplatform> call site.
> 
> Maintenance burden is not completely removed but should be improved. One case in
> point is that I have found some disagreements between device id listed in
> i915_pciids.h and i915_drv.h.
> 
> At the same time platform mask code is generalized to an array of u32 to
> accomodate the addition of EHL and avoid spilling into u64 which would cause a
> small code size increase. Downside is that any platforms on the u32 boundary,
> like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE ||
> IS_ELKHARTLAKE" checks into a single conditional, although at the moment there
> aren't any such call-sites.
> 
> Before vs after for the whole series:
> 
>     text    data     bss     dec     hex filename
> 1891093   43903    7424 1942420  1da394 i915.ko.0
> 1890434   43903    7424 1941761  1da101 i915.ko.1
> 
> add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205)
> ...
> Total: Before=1286293, After=1286498, chg +0.02%

After patch 4 v8:

    text    data     bss     dec     hex filename
1904423   43891    7424 1955738  1dd79a i915.ko.0
1903354   43891    7424 1954669  1dd36d i915.ko.1

add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266)
...
Total: Before=1293823, After=1293557, chg -0.02%

Regards,

Tvrtko

> Tvrtko Ursulin (4):
>    drm/i915: Split Pineview device info into desktop and mobile
>    drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
>    drm/i915: Split some PCI ids into separate groups
>    drm/i915: Introduce concept of a sub-platform
> 
>   arch/x86/kernel/early-quirks.c           |   3 +-
>   drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>   drivers/gpu/drm/i915/i915_drv.h          | 133 +++++++++++------
>   drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>   drivers/gpu/drm/i915/i915_pci.c          |  14 +-
>   drivers/gpu/drm/i915/intel_device_info.c | 145 ++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  27 +++-
>   drivers/gpu/drm/i915/intel_pm.c          |   4 +-
>   include/drm/i915_pciids.h                | 179 ++++++++++++++++-------
>   9 files changed, 414 insertions(+), 102 deletions(-)
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/4] Device id consolidation

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-03-28 09:23:24)
> 
> On 26/03/2019 07:40, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > 
> > Series removes device id checks from i915_drv.h macros and consolidates them to
> > i915_pciids.h as the main "database", while making intel_device_info.c reference
> > the former, expanding the existing concept of a platform mask by a few low bits
> > reserved for sub-platform mask.
> > 
> > This has a two-fold positive effect of firstly consolidating the list of device
> > ids to one location, and secondly removing the if-ladders from every
> > IS_<platfrom>_<subplatform> call site.
> > 
> > Maintenance burden is not completely removed but should be improved. One case in
> > point is that I have found some disagreements between device id listed in
> > i915_pciids.h and i915_drv.h.
> > 
> > At the same time platform mask code is generalized to an array of u32 to
> > accomodate the addition of EHL and avoid spilling into u64 which would cause a
> > small code size increase. Downside is that any platforms on the u32 boundary,
> > like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE ||
> > IS_ELKHARTLAKE" checks into a single conditional, although at the moment there
> > aren't any such call-sites.
> > 
> > Before vs after for the whole series:
> > 
> >     text    data     bss     dec     hex filename
> > 1891093   43903    7424 1942420  1da394 i915.ko.0
> > 1890434   43903    7424 1941761  1da101 i915.ko.1
> > 
> > add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205)
> > ...
> > Total: Before=1286293, After=1286498, chg +0.02%
> 
> After patch 4 v8:
> 
>     text    data     bss     dec     hex filename
> 1904423   43891    7424 1955738  1dd79a i915.ko.0
> 1903354   43891    7424 1954669  1dd36d i915.ko.1
> 
> add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266)
> ...
> Total: Before=1293823, After=1293557, chg -0.02%

The series is an improvement, both for the reader and for the compiler,

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for Device id consolidation (rev2)

[Patchwork]

== Series Details ==

Series: Device id consolidation (rev2)
URL   : https://patchwork.freedesktop.org/series/58561/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5827_full -> Patchwork_12616_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12616_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          PASS -> INCOMPLETE [fdo#103665]

  * igt@gem_exec_parse@chained-batch:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109289]

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +1

  * igt@gem_exec_schedule@preempt-other-chain-blt:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +141

  * igt@gem_pread@stolen-snoop:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109277]

  * igt@gem_tiled_fence_blits@normal:
    - shard-iclb:         PASS -> TIMEOUT [fdo#109673]

  * igt@gem_tiled_swapping@non-threaded:
    - shard-iclb:         PASS -> FAIL [fdo#108686]

  * igt@i915_pm_rpm@basic-rte:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807] +1

  * igt@i915_pm_rpm@pc8-residency:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109293]

  * igt@i915_suspend@sysfs-reader:
    - shard-skl:          PASS -> INCOMPLETE [fdo#104108]

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-snb:          NOTRUN -> DMESG-WARN [fdo#110222]
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#110222]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-kbl:          PASS -> DMESG-WARN [fdo#110222] +1

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-f:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +1

  * igt@kms_busy@extended-modeset-hang-oldfb-render-d:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
    - shard-iclb:         NOTRUN -> DMESG-WARN [fdo#110222]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-kbl:          NOTRUN -> DMESG-WARN [fdo#110222]

  * igt@kms_chamelium@hdmi-hpd-after-suspend:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +2

  * igt@kms_color@pipe-c-degamma:
    - shard-iclb:         NOTRUN -> FAIL [fdo#104782]

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          NOTRUN -> FAIL [fdo#103833] +1

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +1

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          PASS -> FAIL [fdo#105363]

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          PASS -> INCOMPLETE [fdo#105411]

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +6

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +118

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-skl:          NOTRUN -> FAIL [fdo#105683]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-iclb:         PASS -> FAIL [fdo#109247]

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109247] +3

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +9

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] +23

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
    - shard-iclb:         PASS -> FAIL [fdo#105682] / [fdo#109247] +1

  * igt@kms_panel_fitting@legacy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105456]

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +19

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-kbl:          NOTRUN -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
    - shard-glk:          PASS -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +5

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#105763]

  * igt@kms_setmode@basic:
    - shard-apl:          PASS -> FAIL [fdo#99912]
    - shard-iclb:         NOTRUN -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-iclb:         PASS -> FAIL [fdo#104894]

  * igt@perf@polling:
    - shard-iclb:         PASS -> FAIL [fdo#108587]

  * igt@prime_nv_pcopy@test_semaphore:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291]

  
#### Possible fixes ####

  * igt@i915_pm_rpm@i2c:
    - shard-iclb:         DMESG-WARN [fdo#109982] -> PASS

  * igt@kms_flip_tiling@flip-changes-tiling:
    - shard-skl:          FAIL [fdo#108303] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +4

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-iclb:         FAIL [fdo#105682] / [fdo#108040] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-skl:          INCOMPLETE [fdo#104108] -> PASS

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-iclb:         FAIL [fdo#105682] / [fdo#109247] -> PASS +1

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +20

  * {igt@kms_plane@pixel-format-pipe-c-planes-source-clamping}:
    - shard-glk:          SKIP [fdo#109271] -> PASS

  * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         SKIP [fdo#109642] -> PASS

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +6

  * igt@kms_psr@sprite_mmap_cpu:
    - shard-iclb:         FAIL [fdo#107383] / [fdo#110215] -> PASS +4

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-iclb:         FAIL [fdo#104894] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
  [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108303]: https://bugs.freedesktop.org/show_bug.cgi?id=108303
  [fdo#108587]: https://bugs.freedesktop.org/show_bug.cgi?id=108587
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#109982]: https://bugs.freedesktop.org/show_bug.cgi?id=109982
  [fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
  [fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-hsw 


Build changes
-------------

    * Linux: CI_DRM_5827 -> Patchwork_12616

  CI_DRM_5827: d90542b50bfba088d53e8f520c05080e5ca764e7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4909: 7df3eeb4f3360cd2b511c31acc1c52bd7ce6587f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12616: 4f6f1609d5d18d208431f910a3b1e2d28cd623fa @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12616/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/4] Device id consolidation

[Tvrtko Ursulin]

On 28/03/2019 09:39, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-03-28 09:23:24)
>>
>> On 26/03/2019 07:40, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Series removes device id checks from i915_drv.h macros and consolidates them to
>>> i915_pciids.h as the main "database", while making intel_device_info.c reference
>>> the former, expanding the existing concept of a platform mask by a few low bits
>>> reserved for sub-platform mask.
>>>
>>> This has a two-fold positive effect of firstly consolidating the list of device
>>> ids to one location, and secondly removing the if-ladders from every
>>> IS_<platfrom>_<subplatform> call site.
>>>
>>> Maintenance burden is not completely removed but should be improved. One case in
>>> point is that I have found some disagreements between device id listed in
>>> i915_pciids.h and i915_drv.h.
>>>
>>> At the same time platform mask code is generalized to an array of u32 to
>>> accomodate the addition of EHL and avoid spilling into u64 which would cause a
>>> small code size increase. Downside is that any platforms on the u32 boundary,
>>> like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE ||
>>> IS_ELKHARTLAKE" checks into a single conditional, although at the moment there
>>> aren't any such call-sites.
>>>
>>> Before vs after for the whole series:
>>>
>>>      text    data     bss     dec     hex filename
>>> 1891093   43903    7424 1942420  1da394 i915.ko.0
>>> 1890434   43903    7424 1941761  1da101 i915.ko.1
>>>
>>> add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205)
>>> ...
>>> Total: Before=1286293, After=1286498, chg +0.02%
>>
>> After patch 4 v8:
>>
>>      text    data     bss     dec     hex filename
>> 1904423   43891    7424 1955738  1dd79a i915.ko.0
>> 1903354   43891    7424 1954669  1dd36d i915.ko.1
>>
>> add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266)
>> ...
>> Total: Before=1293823, After=1293557, chg -0.02%
> 
> The series is an improvement, both for the reader and for the compiler,
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks.

Jani, Lucas? Passable? Still some objections?

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Wed, 27 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Concept of a sub-platform already exist in our code (like ULX and ULT
> platform variants and similar),implemented via the macros which check a
> list of device ids to determine a match.
>
> With this patch we consolidate device ids checking into a single function
> called during early driver load.
>
> A few low bits in the platform mask are reserved for sub-platform
> identification and defined as a per-platform namespace.
>
> At the same time it future proofs the platform_mask handling by preparing
> the code for easy extending, and tidies the very verbose WARN strings
> generated when IS_PLATFORM macros are embedded into a WARN type
> statements.
>
> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
> v3: Chris was right, there is an ordering problem.
>
> v4:
>  * Catch-up with new sub-platforms.
>  * Rebase for RUNTIME_INFO.
>  * Drop subplatform mask union tricks and convert platform_mask to an
>    array for extensibility.
>
> v5:
>  * Fix subplatform check.
>  * Protect against forgetting to expand subplatform bits.
>  * Remove platform enum tallying.
>  * Add subplatform to error state. (Chris)
>  * Drop macros and just use static inlines.
>  * Remove redundant IRONLAKE_M. (Ville)
>
> v6:
>  * Split out Ironlake change.
>  * Optimize subplatform check.
>  * Use __always_inline. (Lucas)
>  * Add platform_mask comment. (Paulo)
>  * Pass stored runtime info in error capture. (Chris)
>
> v7:
>  * Rebased for new AML ULX device id.
>  * Bump platform mask array size for EHL.
>  * Stop mentioning device ids in intel_device_subplatform_init by using
>    the trick of splitting macros i915_pciids.h. (Jani)
>  * AML seems to be either a subplatform of KBL or CFL so express it like
>    that.
>
> v8:
>  * Use one device id table per subplatform. (Jani)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Souza <jose.souza@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
> ---
>  drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>  drivers/gpu/drm/i915/i915_drv.h          | 123 ++++++++++++++++-------
>  drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>  drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>  drivers/gpu/drm/i915/intel_device_info.c |  93 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>  6 files changed, 214 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f1334f5d4ead..74734d7661e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>  	if (i915_inject_load_failure())
>  		return -ENODEV;
>  
> +	intel_device_info_subplatform_init(dev_priv);
> +
>  	spin_lock_init(&dev_priv->irq_lock);
>  	spin_lock_init(&dev_priv->gpu_error.lock);
>  	mutex_init(&dev_priv->backlight_lock);
> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>  	if (drm_debug & DRM_UT_DRIVER) {
>  		struct drm_printer p = drm_debug_printer("i915 device info:");
>  
> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>  			   INTEL_DEVID(dev_priv),
>  			   INTEL_REVID(dev_priv),
>  			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
> +					     INTEL_INFO(dev_priv)->platform),
>  			   INTEL_GEN(dev_priv));
>  
>  		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>  	memcpy(device_info, match_info, sizeof(*device_info));
>  	RUNTIME_INFO(i915)->device_id = pdev->device;
>  
> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> -		     BITS_PER_TYPE(device_info->platform_mask));
>  	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>  
>  	return i915;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9d3cab9406e1..b7d3f3a45ed9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_REVID(p, since, until) \
>  	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>  
> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
> +static __always_inline unsigned int
> +__platform_mask_index(const struct intel_runtime_info *info,
> +		      enum intel_platform p)
> +{
> +	const unsigned int pbits =
> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
> +
> +	/* Expand the platform_mask array if this fails. */
> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> +		     pbits * ARRAY_SIZE(info->platform_mask));
> +
> +	return p / pbits;
> +}
> +
> +static __always_inline unsigned int
> +__platform_mask_bit(const struct intel_runtime_info *info,
> +		    enum intel_platform p)
> +{
> +	const unsigned int pbits =
> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
> +
> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
> +}
> +
> +static inline u32
> +intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
> +{
> +	const unsigned int pi = __platform_mask_index(info, p);
> +
> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
> +}
> +
> +static __always_inline bool
> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
> +{
> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(info, p);
> +	const unsigned int pb = __platform_mask_bit(info, p);
> +
> +	BUILD_BUG_ON(!__builtin_constant_p(p));
> +
> +	return info->platform_mask[pi] & BIT(pb);
> +}
> +
> +static __always_inline bool
> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
> +	       enum intel_platform p, unsigned int s)
> +{
> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(info, p);
> +	const unsigned int pb = __platform_mask_bit(info, p);
> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
> +	const u32 mask = info->platform_mask[pi];
> +
> +	BUILD_BUG_ON(!__builtin_constant_p(p));
> +	BUILD_BUG_ON(!__builtin_constant_p(s));
> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
> +
> +	/* Shift and test on the MSB position so sign flag can be used. */
> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
> +}

Hum, I wonder if the __builtin_constant_p()'s in an inline function are
going to be a problem for clang.

>  
>  #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
>  
> @@ -2337,43 +2397,32 @@ static inline unsigned int i915_sg_segment_size(void)
>  #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>  				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> -/* ULX machines are also considered ULT. */
> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> +#define IS_BDW_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
> +#define IS_BDW_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
>  #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> +#define IS_HSW_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
>  #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
>  #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 1)
>  /* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
> -				 INTEL_DEVID(dev_priv) == 0x1926)
> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
> -				 INTEL_DEVID(dev_priv) == 0x191E)
> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
> -				 INTEL_DEVID(dev_priv) == 0x5926)
> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
> -				 INTEL_DEVID(dev_priv) == 0x591E)
> -#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
> -				 INTEL_DEVID(dev_priv) == 0x87C0 || \
> -				 INTEL_DEVID(dev_priv) == 0x87CA)
> +#define IS_HSW_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
> +#define IS_SKL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_SKL_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_KBL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_KBL_ULX(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_AML_ULX(dev_priv) \
> +	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
> +	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
>  #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> @@ -2384,16 +2433,16 @@ static inline unsigned int i915_sg_segment_size(void)
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> +#define IS_CFL_ULT(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
>  #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 2)
>  #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>  				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
> -#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
> -					INTEL_DEVID(dev_priv) != 0x8A51)
> +#define IS_CNL_WITH_PORT_F(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
> +#define IS_ICL_WITH_PORT_F(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>  
>  #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index a2a98ccda421..81a27b808273 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "Reset count: %u\n", error->reset_count);
>  	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>  	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
> +	err_printf(m, "Subplatform: 0x%x\n",
> +		   intel_subplatform(&error->runtime_info,
> +				     error->device_info.platform));
>  	err_print_pciid(m, m->i915);
>  
>  	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 716f2f95c57d..39251586349a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -32,7 +32,7 @@
>  #include "i915_globals.h"
>  #include "i915_selftest.h"
>  
> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
> +#define PLATFORM(x) .platform = (x)
>  #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>  
>  #define I845_PIPE_OFFSETS \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index e0f5e0231d04..0ed49d032c00 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -714,6 +714,99 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +#undef INTEL_VGA_DEVICE
> +#define INTEL_VGA_DEVICE(id, info) (id)
> +
> +static const u16 subplatform_ult_ids[] = {
> +	INTEL_HSW_ULT_GT1_IDS(0),
> +	INTEL_HSW_ULT_GT2_IDS(0),
> +	INTEL_HSW_ULT_GT3_IDS(0),
> +	INTEL_BDW_ULT_GT1_IDS(0),
> +	INTEL_BDW_ULT_GT2_IDS(0),
> +	INTEL_BDW_ULT_GT3_IDS(0),
> +	INTEL_BDW_ULT_RSVD_IDS(0),
> +	INTEL_SKL_ULT_GT1_IDS(0),
> +	INTEL_SKL_ULT_GT2_IDS(0),
> +	INTEL_SKL_ULT_GT3_IDS(0),
> +	INTEL_KBL_ULT_GT1_IDS(0),
> +	INTEL_KBL_ULT_GT2_IDS(0),
> +	INTEL_KBL_ULT_GT3_IDS(0),
> +	INTEL_CFL_U_GT2_IDS(0),
> +	INTEL_CFL_U_GT3_IDS(0),
> +	INTEL_WHL_U_GT1_IDS(0),
> +	INTEL_WHL_U_GT2_IDS(0),
> +	INTEL_WHL_U_GT3_IDS(0)
> +};
> +
> +static const u16 subplatform_ulx_ids[] = {
> +	INTEL_HSW_ULX_GT1_IDS(0),
> +	INTEL_HSW_ULX_GT2_IDS(0),
> +	INTEL_BDW_ULX_GT1_IDS(0),
> +	INTEL_BDW_ULX_GT2_IDS(0),
> +	INTEL_BDW_ULX_GT3_IDS(0),
> +	INTEL_BDW_ULX_RSVD_IDS(0),
> +	INTEL_SKL_ULX_GT1_IDS(0),
> +	INTEL_SKL_ULX_GT2_IDS(0),
> +	INTEL_KBL_ULX_GT1_IDS(0),
> +	INTEL_KBL_ULX_GT2_IDS(0)
> +};
> +
> +static const u16 subplatform_aml_ids[] = {
> +	INTEL_AML_KBL_GT2_IDS(0),
> +	INTEL_AML_CFL_GT2_IDS(0)
> +};
> +
> +static const u16 subplatform_portf_ids[] = {
> +	INTEL_CNL_PORT_F_IDS(0),
> +	INTEL_ICL_PORT_F_IDS(0)
> +};
> +
> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
> +{
> +	for (; num; num--, p++) {
> +		if (*p == id)
> +			return true;
> +	}

Why such a convoluted way of doing what's supposed to be a simple thing?
I had to stop at that and wonder what's going on. While this would've
been obvious and reviewed with a 2-second glance:

	int i;

        for (i = 0; i < num; i++)
        	if (id == p[i])
                	return true;

The alternative is zero-terminating the arrays:

	for (; *p; p++)
        	if (id == *p)
                	return true;

> +
> +	return false;
> +}
> +
> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> +{
> +	const struct intel_device_info *info = INTEL_INFO(i915);
> +	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
> +	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
> +	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
> +	u16 devid = INTEL_DEVID(i915);
> +	u32 mask;
> +
> +	/* Make sure IS_<platform> checks are working. */
> +	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
> +
> +	/* Find and mark subplatform bits based on the PCI device id. */
> +	if (find_devid(devid, subplatform_ult_ids,
> +		       ARRAY_SIZE(subplatform_ult_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_ULT);
> +	} else if (find_devid(devid, subplatform_ulx_ids,
> +			      ARRAY_SIZE(subplatform_ulx_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_ULX);
> +		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> +			/* ULX machines are also considered ULT. */
> +			mask |= BIT(INTEL_SUBPLATFORM_ULT);
> +		}

*cringe* at special casing hsw/bdw ulx means ult here. Can be figured
out later though if needed.

Anyway,

Acked-by: Jani Nikula <jani.nikula@intel.com>



BR,
Jani.

> +	} else if (find_devid(devid, subplatform_aml_ids,
> +			      ARRAY_SIZE(subplatform_aml_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_AML);
> +	} else if (find_devid(devid, subplatform_portf_ids,
> +			      ARRAY_SIZE(subplatform_portf_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_PORTF);
> +	}
> +
> +	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
> +
> +	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
> +}
> +
>  /**
>   * intel_device_info_runtime_init - initialize runtime info
>   * @dev_priv: the i915 device
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 7e04b4829aba..616e9f707877 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -77,6 +77,21 @@ enum intel_platform {
>  	INTEL_MAX_PLATFORMS
>  };
>  
> +/*
> + * Subplatform bits share the same namespace per parent platform. In other words
> + * it is fine for the same bit to be used on multiple parent platforms.
> + */
> +
> +#define INTEL_SUBPLATFORM_BITS (3)
> +
> +/* HSW/BDW/SKL/KBL/CFL */
> +#define INTEL_SUBPLATFORM_ULT	(0)
> +#define INTEL_SUBPLATFORM_ULX	(1)
> +#define INTEL_SUBPLATFORM_AML	(2)
> +
> +/* CNL/ICL */
> +#define INTEL_SUBPLATFORM_PORTF	(0)
> +
>  enum intel_ppgtt_type {
>  	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
>  	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> @@ -160,7 +175,6 @@ struct intel_device_info {
>  	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
>  
>  	enum intel_platform platform;
> -	u32 platform_mask;
>  
>  	enum intel_ppgtt_type ppgtt_type;
>  	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
> @@ -197,6 +211,16 @@ struct intel_device_info {
>  };
>  
>  struct intel_runtime_info {
> +	/*
> +	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
> +	 * into single runtime conditionals, and also to provide groundwork
> +	 * for future per platform, or per SKU build optimizations.
> +	 *
> +	 * Array can be extended when necessary if the corresponding
> +	 * BUILD_BUG_ON is hit.
> +	 */
> +	u32 platform_mask[2];
> +
>  	u16 device_id;
>  
>  	u8 num_sprites[I915_MAX_PIPES];
> @@ -267,6 +291,7 @@ static inline void sseu_set_eus(struct sseu_dev_info *sseu,
>  
>  const char *intel_platform_name(enum intel_platform platform);
>  
> +void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
>  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
>  void intel_device_info_dump_flags(const struct intel_device_info *info,
>  				  struct drm_printer *p);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform

[Tvrtko Ursulin]

On 29/03/2019 09:54, Jani Nikula wrote:
> On Wed, 27 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Concept of a sub-platform already exist in our code (like ULX and ULT
>> platform variants and similar),implemented via the macros which check a
>> list of device ids to determine a match.
>>
>> With this patch we consolidate device ids checking into a single function
>> called during early driver load.
>>
>> A few low bits in the platform mask are reserved for sub-platform
>> identification and defined as a per-platform namespace.
>>
>> At the same time it future proofs the platform_mask handling by preparing
>> the code for easy extending, and tidies the very verbose WARN strings
>> generated when IS_PLATFORM macros are embedded into a WARN type
>> statements.
>>
>> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
>> v3: Chris was right, there is an ordering problem.
>>
>> v4:
>>   * Catch-up with new sub-platforms.
>>   * Rebase for RUNTIME_INFO.
>>   * Drop subplatform mask union tricks and convert platform_mask to an
>>     array for extensibility.
>>
>> v5:
>>   * Fix subplatform check.
>>   * Protect against forgetting to expand subplatform bits.
>>   * Remove platform enum tallying.
>>   * Add subplatform to error state. (Chris)
>>   * Drop macros and just use static inlines.
>>   * Remove redundant IRONLAKE_M. (Ville)
>>
>> v6:
>>   * Split out Ironlake change.
>>   * Optimize subplatform check.
>>   * Use __always_inline. (Lucas)
>>   * Add platform_mask comment. (Paulo)
>>   * Pass stored runtime info in error capture. (Chris)
>>
>> v7:
>>   * Rebased for new AML ULX device id.
>>   * Bump platform mask array size for EHL.
>>   * Stop mentioning device ids in intel_device_subplatform_init by using
>>     the trick of splitting macros i915_pciids.h. (Jani)
>>   * AML seems to be either a subplatform of KBL or CFL so express it like
>>     that.
>>
>> v8:
>>   * Use one device id table per subplatform. (Jani)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Jose Souza <jose.souza@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>>   drivers/gpu/drm/i915/i915_drv.h          | 123 ++++++++++++++++-------
>>   drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>>   drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>>   drivers/gpu/drm/i915/intel_device_info.c |  93 +++++++++++++++++
>>   drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>>   6 files changed, 214 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index f1334f5d4ead..74734d7661e5 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>>   	if (i915_inject_load_failure())
>>   		return -ENODEV;
>>   
>> +	intel_device_info_subplatform_init(dev_priv);
>> +
>>   	spin_lock_init(&dev_priv->irq_lock);
>>   	spin_lock_init(&dev_priv->gpu_error.lock);
>>   	mutex_init(&dev_priv->backlight_lock);
>> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>>   	if (drm_debug & DRM_UT_DRIVER) {
>>   		struct drm_printer p = drm_debug_printer("i915 device info:");
>>   
>> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>>   			   INTEL_DEVID(dev_priv),
>>   			   INTEL_REVID(dev_priv),
>>   			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
>> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
>> +					     INTEL_INFO(dev_priv)->platform),
>>   			   INTEL_GEN(dev_priv));
>>   
>>   		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
>> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>>   	memcpy(device_info, match_info, sizeof(*device_info));
>>   	RUNTIME_INFO(i915)->device_id = pdev->device;
>>   
>> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> -		     BITS_PER_TYPE(device_info->platform_mask));
>>   	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>>   
>>   	return i915;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 9d3cab9406e1..b7d3f3a45ed9 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
>>   #define IS_REVID(p, since, until) \
>>   	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>>   
>> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>> +static __always_inline unsigned int
>> +__platform_mask_index(const struct intel_runtime_info *info,
>> +		      enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	/* Expand the platform_mask array if this fails. */
>> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>> +		     pbits * ARRAY_SIZE(info->platform_mask));
>> +
>> +	return p / pbits;
>> +}
>> +
>> +static __always_inline unsigned int
>> +__platform_mask_bit(const struct intel_runtime_info *info,
>> +		    enum intel_platform p)
>> +{
>> +	const unsigned int pbits =
>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>> +
>> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static inline u32
>> +intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
>> +{
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +
>> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
>> +}
>> +
>> +static __always_inline bool
>> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +
>> +	return info->platform_mask[pi] & BIT(pb);
>> +}
>> +
>> +static __always_inline bool
>> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> +	       enum intel_platform p, unsigned int s)
>> +{
>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(info, p);
>> +	const unsigned int pb = __platform_mask_bit(info, p);
>> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
>> +	const u32 mask = info->platform_mask[pi];
>> +
>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>> +	BUILD_BUG_ON(!__builtin_constant_p(s));
>> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
>> +
>> +	/* Shift and test on the MSB position so sign flag can be used. */
>> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
>> +}
> 
> Hum, I wonder if the __builtin_constant_p()'s in an inline function are
> going to be a problem for clang.

No idea.. has something been happening along these lines in the past?

It could be a macro but then all WARN_ON's which use IS_PLATFORM expand 
to most unreadable mess.

> 
>>   
>>   #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
>>   
>> @@ -2337,43 +2397,32 @@ static inline unsigned int i915_sg_segment_size(void)
>>   #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>>   #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>>   				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
>> -/* ULX machines are also considered ULT. */
>> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> +#define IS_BDW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
>> +#define IS_BDW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
>>   #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> +#define IS_HSW_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
>>   #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>>   #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 1)
>>   /* ULX machines are also considered ULT. */
>> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
>> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
>> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x1926)
>> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
>> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x191E)
>> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
>> -				 INTEL_DEVID(dev_priv) == 0x5926)
>> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
>> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
>> -				 INTEL_DEVID(dev_priv) == 0x591E)
>> -#define IS_AML_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x591C || \
>> -				 INTEL_DEVID(dev_priv) == 0x87C0 || \
>> -				 INTEL_DEVID(dev_priv) == 0x87CA)
>> +#define IS_HSW_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
>> +#define IS_SKL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_SKL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_KBL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
>> +#define IS_KBL_ULX(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
>> +#define IS_AML_ULX(dev_priv) \
>> +	(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
>> +	 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
>>   #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
>> @@ -2384,16 +2433,16 @@ static inline unsigned int i915_sg_segment_size(void)
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> +#define IS_CFL_ULT(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
>>   #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 2)
>>   #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
>>   				 INTEL_INFO(dev_priv)->gt == 3)
>> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
>> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>> -#define IS_ICL_WITH_PORT_F(dev_priv)   (IS_ICELAKE(dev_priv) && \
>> -					INTEL_DEVID(dev_priv) != 0x8A51)
>> +#define IS_CNL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
>> +#define IS_ICL_WITH_PORT_F(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>>   
>>   #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index a2a98ccda421..81a27b808273 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -677,6 +677,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
>>   	err_printf(m, "Reset count: %u\n", error->reset_count);
>>   	err_printf(m, "Suspend count: %u\n", error->suspend_count);
>>   	err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
>> +	err_printf(m, "Subplatform: 0x%x\n",
>> +		   intel_subplatform(&error->runtime_info,
>> +				     error->device_info.platform));
>>   	err_print_pciid(m, m->i915);
>>   
>>   	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 716f2f95c57d..39251586349a 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -32,7 +32,7 @@
>>   #include "i915_globals.h"
>>   #include "i915_selftest.h"
>>   
>> -#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
>> +#define PLATFORM(x) .platform = (x)
>>   #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
>>   
>>   #define I845_PIPE_OFFSETS \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index e0f5e0231d04..0ed49d032c00 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -714,6 +714,99 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
>>   	return 0;
>>   }
>>   
>> +#undef INTEL_VGA_DEVICE
>> +#define INTEL_VGA_DEVICE(id, info) (id)
>> +
>> +static const u16 subplatform_ult_ids[] = {
>> +	INTEL_HSW_ULT_GT1_IDS(0),
>> +	INTEL_HSW_ULT_GT2_IDS(0),
>> +	INTEL_HSW_ULT_GT3_IDS(0),
>> +	INTEL_BDW_ULT_GT1_IDS(0),
>> +	INTEL_BDW_ULT_GT2_IDS(0),
>> +	INTEL_BDW_ULT_GT3_IDS(0),
>> +	INTEL_BDW_ULT_RSVD_IDS(0),
>> +	INTEL_SKL_ULT_GT1_IDS(0),
>> +	INTEL_SKL_ULT_GT2_IDS(0),
>> +	INTEL_SKL_ULT_GT3_IDS(0),
>> +	INTEL_KBL_ULT_GT1_IDS(0),
>> +	INTEL_KBL_ULT_GT2_IDS(0),
>> +	INTEL_KBL_ULT_GT3_IDS(0),
>> +	INTEL_CFL_U_GT2_IDS(0),
>> +	INTEL_CFL_U_GT3_IDS(0),
>> +	INTEL_WHL_U_GT1_IDS(0),
>> +	INTEL_WHL_U_GT2_IDS(0),
>> +	INTEL_WHL_U_GT3_IDS(0)
>> +};
>> +
>> +static const u16 subplatform_ulx_ids[] = {
>> +	INTEL_HSW_ULX_GT1_IDS(0),
>> +	INTEL_HSW_ULX_GT2_IDS(0),
>> +	INTEL_BDW_ULX_GT1_IDS(0),
>> +	INTEL_BDW_ULX_GT2_IDS(0),
>> +	INTEL_BDW_ULX_GT3_IDS(0),
>> +	INTEL_BDW_ULX_RSVD_IDS(0),
>> +	INTEL_SKL_ULX_GT1_IDS(0),
>> +	INTEL_SKL_ULX_GT2_IDS(0),
>> +	INTEL_KBL_ULX_GT1_IDS(0),
>> +	INTEL_KBL_ULX_GT2_IDS(0)
>> +};
>> +
>> +static const u16 subplatform_aml_ids[] = {
>> +	INTEL_AML_KBL_GT2_IDS(0),
>> +	INTEL_AML_CFL_GT2_IDS(0)
>> +};
>> +
>> +static const u16 subplatform_portf_ids[] = {
>> +	INTEL_CNL_PORT_F_IDS(0),
>> +	INTEL_ICL_PORT_F_IDS(0)
>> +};
>> +
>> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
>> +{
>> +	for (; num; num--, p++) {
>> +		if (*p == id)
>> +			return true;
>> +	}
> 
> Why such a convoluted way of doing what's supposed to be a simple thing?
> I had to stop at that and wonder what's going on. While this would've
> been obvious and reviewed with a 2-second glance:
> 
> 	int i;
> 
>          for (i = 0; i < num; i++)
>          	if (id == p[i])
>                  	return true;
> 
> The alternative is zero-terminating the arrays:
> 
> 	for (; *p; p++)
>          	if (id == *p)
>                  	return true;
> 

I think mine is not that complicated. It's a standard countdown pattern, 
no? Why add locals or null termination if not needed.

>> +
>> +	return false;
>> +}
>> +
>> +void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> +{
>> +	const struct intel_device_info *info = INTEL_INFO(i915);
>> +	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
>> +	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
>> +	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
>> +	u16 devid = INTEL_DEVID(i915);
>> +	u32 mask;
>> +
>> +	/* Make sure IS_<platform> checks are working. */
>> +	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
>> +
>> +	/* Find and mark subplatform bits based on the PCI device id. */
>> +	if (find_devid(devid, subplatform_ult_ids,
>> +		       ARRAY_SIZE(subplatform_ult_ids))) {
>> +		mask = BIT(INTEL_SUBPLATFORM_ULT);
>> +	} else if (find_devid(devid, subplatform_ulx_ids,
>> +			      ARRAY_SIZE(subplatform_ulx_ids))) {
>> +		mask = BIT(INTEL_SUBPLATFORM_ULX);
>> +		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
>> +			/* ULX machines are also considered ULT. */
>> +			mask |= BIT(INTEL_SUBPLATFORM_ULT);
>> +		}
> 
> *cringe* at special casing hsw/bdw ulx means ult here. Can be figured
> out later though if needed.

Yeah..

> 
> Anyway,
> 
> Acked-by: Jani Nikula <jani.nikula@intel.com>
> 

Thanks!

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform

[Jani Nikula]

On Fri, 29 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 29/03/2019 09:54, Jani Nikula wrote:
>> On Wed, 27 Mar 2019, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>
>>> Concept of a sub-platform already exist in our code (like ULX and ULT
>>> platform variants and similar),implemented via the macros which check a
>>> list of device ids to determine a match.
>>>
>>> With this patch we consolidate device ids checking into a single function
>>> called during early driver load.
>>>
>>> A few low bits in the platform mask are reserved for sub-platform
>>> identification and defined as a per-platform namespace.
>>>
>>> At the same time it future proofs the platform_mask handling by preparing
>>> the code for easy extending, and tidies the very verbose WARN strings
>>> generated when IS_PLATFORM macros are embedded into a WARN type
>>> statements.
>>>
>>> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
>>> v3: Chris was right, there is an ordering problem.
>>>
>>> v4:
>>>   * Catch-up with new sub-platforms.
>>>   * Rebase for RUNTIME_INFO.
>>>   * Drop subplatform mask union tricks and convert platform_mask to an
>>>     array for extensibility.
>>>
>>> v5:
>>>   * Fix subplatform check.
>>>   * Protect against forgetting to expand subplatform bits.
>>>   * Remove platform enum tallying.
>>>   * Add subplatform to error state. (Chris)
>>>   * Drop macros and just use static inlines.
>>>   * Remove redundant IRONLAKE_M. (Ville)
>>>
>>> v6:
>>>   * Split out Ironlake change.
>>>   * Optimize subplatform check.
>>>   * Use __always_inline. (Lucas)
>>>   * Add platform_mask comment. (Paulo)
>>>   * Pass stored runtime info in error capture. (Chris)
>>>
>>> v7:
>>>   * Rebased for new AML ULX device id.
>>>   * Bump platform mask array size for EHL.
>>>   * Stop mentioning device ids in intel_device_subplatform_init by using
>>>     the trick of splitting macros i915_pciids.h. (Jani)
>>>   * AML seems to be either a subplatform of KBL or CFL so express it like
>>>     that.
>>>
>>> v8:
>>>   * Use one device id table per subplatform. (Jani)
>>>
>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>>> Cc: Jose Souza <jose.souza@intel.com>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v6
>>> ---
>>>   drivers/gpu/drm/i915/i915_drv.c          |   8 +-
>>>   drivers/gpu/drm/i915/i915_drv.h          | 123 ++++++++++++++++-------
>>>   drivers/gpu/drm/i915/i915_gpu_error.c    |   3 +
>>>   drivers/gpu/drm/i915/i915_pci.c          |   2 +-
>>>   drivers/gpu/drm/i915/intel_device_info.c |  93 +++++++++++++++++
>>>   drivers/gpu/drm/i915/intel_device_info.h |  27 ++++-
>>>   6 files changed, 214 insertions(+), 42 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>>> index f1334f5d4ead..74734d7661e5 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>>>   	if (i915_inject_load_failure())
>>>   		return -ENODEV;
>>>   
>>> +	intel_device_info_subplatform_init(dev_priv);
>>> +
>>>   	spin_lock_init(&dev_priv->irq_lock);
>>>   	spin_lock_init(&dev_priv->gpu_error.lock);
>>>   	mutex_init(&dev_priv->backlight_lock);
>>> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
>>>   	if (drm_debug & DRM_UT_DRIVER) {
>>>   		struct drm_printer p = drm_debug_printer("i915 device info:");
>>>   
>>> -		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>>> +		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
>>>   			   INTEL_DEVID(dev_priv),
>>>   			   INTEL_REVID(dev_priv),
>>>   			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
>>> +			   intel_subplatform(RUNTIME_INFO(dev_priv),
>>> +					     INTEL_INFO(dev_priv)->platform),
>>>   			   INTEL_GEN(dev_priv));
>>>   
>>>   		intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
>>> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
>>>   	memcpy(device_info, match_info, sizeof(*device_info));
>>>   	RUNTIME_INFO(i915)->device_id = pdev->device;
>>>   
>>> -	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>>> -		     BITS_PER_TYPE(device_info->platform_mask));
>>>   	BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>>>   
>>>   	return i915;
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 9d3cab9406e1..b7d3f3a45ed9 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
>>>   #define IS_REVID(p, since, until) \
>>>   	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>>>   
>>> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
>>> +static __always_inline unsigned int
>>> +__platform_mask_index(const struct intel_runtime_info *info,
>>> +		      enum intel_platform p)
>>> +{
>>> +	const unsigned int pbits =
>>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>>> +
>>> +	/* Expand the platform_mask array if this fails. */
>>> +	BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>>> +		     pbits * ARRAY_SIZE(info->platform_mask));
>>> +
>>> +	return p / pbits;
>>> +}
>>> +
>>> +static __always_inline unsigned int
>>> +__platform_mask_bit(const struct intel_runtime_info *info,
>>> +		    enum intel_platform p)
>>> +{
>>> +	const unsigned int pbits =
>>> +		BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
>>> +
>>> +	return p % pbits + INTEL_SUBPLATFORM_BITS;
>>> +}
>>> +
>>> +static inline u32
>>> +intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
>>> +{
>>> +	const unsigned int pi = __platform_mask_index(info, p);
>>> +
>>> +	return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
>>> +}
>>> +
>>> +static __always_inline bool
>>> +IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
>>> +{
>>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>>> +	const unsigned int pi = __platform_mask_index(info, p);
>>> +	const unsigned int pb = __platform_mask_bit(info, p);
>>> +
>>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>>> +
>>> +	return info->platform_mask[pi] & BIT(pb);
>>> +}
>>> +
>>> +static __always_inline bool
>>> +IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>> +	       enum intel_platform p, unsigned int s)
>>> +{
>>> +	const struct intel_runtime_info *info = RUNTIME_INFO(i915);
>>> +	const unsigned int pi = __platform_mask_index(info, p);
>>> +	const unsigned int pb = __platform_mask_bit(info, p);
>>> +	const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
>>> +	const u32 mask = info->platform_mask[pi];
>>> +
>>> +	BUILD_BUG_ON(!__builtin_constant_p(p));
>>> +	BUILD_BUG_ON(!__builtin_constant_p(s));
>>> +	BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
>>> +
>>> +	/* Shift and test on the MSB position so sign flag can be used. */
>>> +	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
>>> +}
>> 
>> Hum, I wonder if the __builtin_constant_p()'s in an inline function are
>> going to be a problem for clang.
>
> No idea.. has something been happening along these lines in the past?

The thread and two patches starting from [1] may be related.

[1] http://mid.mail-archive.com/20181016122938.18757-1-jani.nikula@intel.com

> It could be a macro but then all WARN_ON's which use IS_PLATFORM expand 
> to most unreadable mess.

I know.

>>> +static bool find_devid(u16 id, const u16 *p, unsigned int num)
>>> +{
>>> +	for (; num; num--, p++) {
>>> +		if (*p == id)
>>> +			return true;
>>> +	}
>> 
>> Why such a convoluted way of doing what's supposed to be a simple thing?
>> I had to stop at that and wonder what's going on. While this would've
>> been obvious and reviewed with a 2-second glance:
>> 
>> 	int i;
>> 
>>          for (i = 0; i < num; i++)
>>          	if (id == p[i])
>>                  	return true;
>> 
>> The alternative is zero-terminating the arrays:
>> 
>> 	for (; *p; p++)
>>          	if (id == *p)
>>                  	return true;
>> 
>
> I think mine is not that complicated. It's a standard countdown pattern, 
> no? Why add locals or null termination if not needed.

I just like to simplify the code for the humans, not for the compiler.

BR,
Jani.



-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✓ Fi.CI.BAT: success for Device id consolidation (rev2)

[Tvrtko Ursulin]

On 27/03/2019 18:38, Patchwork wrote:
> == Series Details ==
> 
> Series: Device id consolidation (rev2)
> URL   : https://patchwork.freedesktop.org/series/58561/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5827 -> Patchwork_12616
> ====================================================
> 
> Summary
> -------
> 
>    **SUCCESS**
> 
>    No regressions found.
> 
>    External URL: https://patchwork.freedesktop.org/api/1.0/series/58561/revisions/2/mbox/
> 
> Known issues
> ------------
> 
>    Here are the changes found in Patchwork_12616 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>    * igt@amdgpu/amd_basic@userptr:
>      - fi-kbl-8809g:       PASS -> DMESG-WARN [fdo#108965]
> 
>    * igt@gem_exec_store@basic-bsd2:
>      - fi-hsw-4770:        NOTRUN -> SKIP [fdo#109271] +41
> 
>    * igt@i915_selftest@live_execlists:
>      - fi-apl-guc:         NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]
> 
>    * igt@kms_force_connector_basic@force-load-detect:
>      - fi-skl-6700k2:      NOTRUN -> SKIP [fdo#109271] +26
> 
>    * igt@kms_frontbuffer_tracking@basic:
>      - fi-icl-u2:          PASS -> FAIL [fdo#103167]
> 
>    * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
>      - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]
> 
>    * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
>      - fi-apl-guc:         NOTRUN -> DMESG-WARN [fdo#108529] / [fdo#108566]
> 
>    * igt@kms_psr@primary_page_flip:
>      - fi-apl-guc:         NOTRUN -> SKIP [fdo#109271] +50
> 
>    
> #### Possible fixes ####
> 
>    * igt@kms_chamelium@common-hpd-after-suspend:
>      - fi-skl-6700k2:      INCOMPLETE [fdo#104108] -> PASS
> 
>    * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
>      - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS
> 
>    * igt@kms_pipe_crc_basic@read-crc-pipe-b:
>      - fi-byt-clapper:     FAIL [fdo#107362] -> PASS
> 
>    
>    [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>    [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
>    [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>    [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>    [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
>    [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
>    [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
>    [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
>    [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>    [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
> 
> 
> Participating hosts (39 -> 35)
> ------------------------------
> 
>    Additional (2): fi-hsw-4770 fi-apl-guc
>    Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus fi-kbl-r
> 
> 
> Build changes
> -------------
> 
>      * Linux: CI_DRM_5827 -> Patchwork_12616
> 
>    CI_DRM_5827: d90542b50bfba088d53e8f520c05080e5ca764e7 @ git://anongit.freedesktop.org/gfx-ci/linux
>    IGT_4909: 7df3eeb4f3360cd2b511c31acc1c52bd7ce6587f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>    Patchwork_12616: 4f6f1609d5d18d208431f910a3b1e2d28cd623fa @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 4f6f1609d5d1 drm/i915: Introduce concept of a sub-platform
> 8551b470ae66 drm/i915: Split some PCI ids into separate groups
> 871661fc5d65 drm/i915: Remove redundant device id from IS_IRONLAKE_M macro
> 41661f3ceb00 drm/i915: Split Pineview device info into desktop and mobile

Pushed, thanks for the feedback and review.

If there will be any problems with Clang I am counting on people 
familiar with the problem space suggesting workarounds.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx