* [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates
@ 2019-03-27 12:41 Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Geert Uytterhoeven
Hi Mike, Stephen,
This patch series updates the R-Car Gen3 and RZ/G2e clock drivers to
bring it in-line with recent revisions of the Hardware Manual.
None of these should have any run-time impact, as the clock consumers
don't care about actual clock rates or naming.
I plan to queue these in clk-renesas-for-v5.2.
Kazuya Mizuguchi (2):
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
Takeshi Kihara (3):
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
clk: renesas: rcar-gen3: Rename DRIF clock names
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 ++++-----
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 6 ++--
drivers/clk/renesas/r8a7795-cpg-mssr.c | 38 ++++++++++++-------------
drivers/clk/renesas/r8a7796-cpg-mssr.c | 30 +++++++++----------
drivers/clk/renesas/r8a77965-cpg-mssr.c | 31 ++++++++++----------
drivers/clk/renesas/r8a77990-cpg-mssr.c | 24 ++++++++--------
drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
7 files changed, 73 insertions(+), 72 deletions(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
@ 2019-03-27 12:41 ` Geert Uytterhoeven
2019-03-29 9:02 ` Simon Horman
2019-03-27 12:41 ` [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Geert Uytterhoeven
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Kazuya Mizuguchi, Takeshi Kihara,
Geert Uytterhoeven
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7795-cpg-mssr.c | 8 ++++----
drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 44161fd0a09caaba..bce0e6d6d02c7e7b 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -165,8 +165,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 57098b7e3d0eea3c..d095787f7d851fc9 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -178,7 +178,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 8287816523c3c602..b9e42da38b72bdcb 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -195,10 +195,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
- DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
- DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
- DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 5cde1bff89235e90..97b58f13111441a8 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -177,8 +177,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index fefa26a1a797d9a8..ab25bd5f1371869e 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 99f602cb30a55913..3f22b8565648d590 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -181,7 +181,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
@ 2019-03-27 12:41 ` Geert Uytterhoeven
2019-03-29 9:20 ` Simon Horman
2019-03-27 12:41 ` [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Geert Uytterhoeven
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Kazuya Mizuguchi, Takeshi Kihara,
Geert Uytterhoeven
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index bce0e6d6d02c7e7b..676e6a1120900b17 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D2),
DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index d095787f7d851fc9..c33d3b0370812840 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -179,7 +179,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b9e42da38b72bdcb..5b658b0861180268 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -199,8 +199,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
+ DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 97b58f13111441a8..fa1c1ac14d5caa1c 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -179,7 +179,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index ab25bd5f1371869e..48a9add7d4db8975 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -177,7 +177,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 3f22b8565648d590..3a88d2247cf5cb17 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -182,7 +182,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
- DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
+ DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Geert Uytterhoeven
@ 2019-03-27 12:41 ` Geert Uytterhoeven
2019-03-29 9:32 ` Simon Horman
2019-03-27 12:41 ` [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks Geert Uytterhoeven
4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Takeshi Kihara, Geert Uytterhoeven
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:
Channel R-Car H3 R-Car M3-W R-Car M3-N
-------------------------------------------------
SYS-DMAC0 S0D3 S0D3 S0D3
SYS-DMAC1 S3D1 S3D1 S3D1
SYS-DMAC2 S3D1 S3D1 S3D1
As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.
NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 676e6a1120900b17..13bf7260204f5078 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 5b658b0861180268..a576a42f104442ff 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -130,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index fa1c1ac14d5caa1c..369092e8d893255f 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -127,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 48a9add7d4db8975..623bbda2d24ec112 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
` (2 preceding siblings ...)
2019-03-27 12:41 ` [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Geert Uytterhoeven
@ 2019-03-27 12:41 ` Geert Uytterhoeven
2019-03-29 9:34 ` Simon Horman
2019-03-27 12:41 ` [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks Geert Uytterhoeven
4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Takeshi Kihara, Geert Uytterhoeven
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:
Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
---------------------------------------------------------------
Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
Audio-DMAC1 S1D2 S1D2 S1D2 -
As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.
NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
7 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 13bf7260204f5078..76ed7d1bae368adc 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
+ DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2),
DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index c33d3b0370812840..f91e7a4847537926 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -158,7 +158,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4),
+ DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a576a42f104442ff..e5fa9f6c1ec4b9cb 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -154,8 +154,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
+ DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 369092e8d893255f..73c69152c77b02ed 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -147,8 +147,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
+ DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 623bbda2d24ec112..a0ce2ecb656d3d48 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
+ DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 3a88d2247cf5cb17..53973201a9f576ad 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -153,7 +153,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
+ DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index eee3874865a95b1a..68707277b17b42c4 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
- DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
` (3 preceding siblings ...)
2019-03-27 12:41 ` [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Geert Uytterhoeven
@ 2019-03-27 12:41 ` Geert Uytterhoeven
2019-03-29 9:39 ` Simon Horman
4 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-27 12:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Takeshi Kihara, Geert Uytterhoeven
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
12, 2019, the DRIF clocks have been renamed as follows:
DRIF0 to DRIF00
DRIF1 to DRIF01
DRIF2 to DRIF10
DRIF3 to DRIF11
DRIF4 to DRIF20
DRIF5 to DRIF21
DRIF6 to DRIF30
DRIF7 to DRIF31
Therefore, this patch renames the DRIF clock names from DRIFn to DRIFmm.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 18 +++++++++---------
drivers/clk/renesas/r8a7796-cpg-mssr.c | 16 ++++++++--------
drivers/clk/renesas/r8a77965-cpg-mssr.c | 17 +++++++++--------
drivers/clk/renesas/r8a77990-cpg-mssr.c | 18 +++++++++---------
4 files changed, 35 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index e5fa9f6c1ec4b9cb..9e9a6f2c31e808eb 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -3,7 +3,7 @@
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015 Glider bvba
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on clk-rcar-gen3.c
*
@@ -156,14 +156,14 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
- DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
+ DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 73c69152c77b02ed..d8e9af5d9ae9cf6e 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -149,14 +149,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
- DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
+ DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index a0ce2ecb656d3d48..8f87e314d9490498 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -3,6 +3,7 @@
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -148,14 +149,14 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
- DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
+ DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 53973201a9f576ad..9570404baa583a8f 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -2,7 +2,7 @@
/*
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* Based on r8a7795-cpg-mssr.c
*
@@ -154,14 +154,14 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
- DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
+ DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
@ 2019-03-29 9:02 ` Simon Horman
2019-03-29 9:07 ` Geert Uytterhoeven
0 siblings, 1 reply; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:02 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Kazuya Mizuguchi, Takeshi Kihara
On Wed, Mar 27, 2019 at 01:41:36PM +0100, Geert Uytterhoeven wrote:
> From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
>
> According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
> Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
> clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> [takeshi: Update R-Car H3, M3-N, and E3]
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [geert: Update RZ/G2M and RZ/G2E]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
During my review I saw that R-Car E3 (r8a77990) is already using
the correct parent clock. And with this change all R-Car Gen3 and RZ/G2
SoCs do so.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 8 ++++----
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
> 6 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index 44161fd0a09caaba..bce0e6d6d02c7e7b 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -165,8 +165,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
> DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
> DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
> - DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
> - DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
> + DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
> + DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
> DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index 57098b7e3d0eea3c..d095787f7d851fc9 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -178,7 +178,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
>
> - DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
> + DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
> DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
> DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index 8287816523c3c602..b9e42da38b72bdcb 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -195,10 +195,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
> DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
> DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
> - DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
> - DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
> - DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
> - DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
> + DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
> + DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
> + DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
> + DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
> DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
> DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 5cde1bff89235e90..97b58f13111441a8 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -177,8 +177,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
> DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
> - DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
> - DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
> + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
> + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
> DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index fefa26a1a797d9a8..ab25bd5f1371869e 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
>
> - DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
> - DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
> + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
> + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
> DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 99f602cb30a55913..3f22b8565648d590 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -181,7 +181,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
> DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
> DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
>
> - DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
> + DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
> DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
> DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
> DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
2019-03-29 9:02 ` Simon Horman
@ 2019-03-29 9:07 ` Geert Uytterhoeven
2019-03-29 9:19 ` Simon Horman
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2019-03-29 9:07 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Linux-Renesas, linux-clk, Kazuya Mizuguchi, Takeshi Kihara
Hi Simon,
On Fri, Mar 29, 2019 at 10:03 AM Simon Horman <horms@verge.net.au> wrote:
> On Wed, Mar 27, 2019 at 01:41:36PM +0100, Geert Uytterhoeven wrote:
> > From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> >
> > According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
> > Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
> > clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
> >
> > Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> > [takeshi: Update R-Car H3, M3-N, and E3]
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > [geert: Update RZ/G2M and RZ/G2E]
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> During my review I saw that R-Car E3 (r8a77990) is already using
D3 (r8a77995)?
> the correct parent clock. And with this change all R-Car Gen3 and RZ/G2
> SoCs do so.
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
2019-03-29 9:07 ` Geert Uytterhoeven
@ 2019-03-29 9:19 ` Simon Horman
0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:19 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Linux-Renesas, linux-clk, Kazuya Mizuguchi, Takeshi Kihara
On Fri, Mar 29, 2019 at 10:07:13AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Mar 29, 2019 at 10:03 AM Simon Horman <horms@verge.net.au> wrote:
> > On Wed, Mar 27, 2019 at 01:41:36PM +0100, Geert Uytterhoeven wrote:
> > > From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> > >
> > > According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
> > > Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
> > > clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
> > >
> > > Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> > > [takeshi: Update R-Car H3, M3-N, and E3]
> > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > > [geert: Update RZ/G2M and RZ/G2E]
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > During my review I saw that R-Car E3 (r8a77990) is already using
>
> D3 (r8a77995)?
Yes, my bad.
> > the correct parent clock. And with this change all R-Car Gen3 and RZ/G2
> > SoCs do so.
> >
> > Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB
2019-03-27 12:41 ` [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Geert Uytterhoeven
@ 2019-03-29 9:20 ` Simon Horman
0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:20 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Kazuya Mizuguchi, Takeshi Kihara
On Wed, Mar 27, 2019 at 01:41:37PM +0100, Geert Uytterhoeven wrote:
> From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
>
> According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
> Hardware Manual Rev. 0.61, the parent clock of the HS-USB module
> clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.
>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> [takeshi: Update R-Car H3, M3-N, and E3]
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [geert: Update RZ/G2M and RZ/G2E]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
During my review I saw that R-Car D3 (r8a77995) is already using the
correct parent clock. And with this change all R-Car Gen3 and RZ/G2 SoCs do
so.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
> 6 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index bce0e6d6d02c7e7b..676e6a1120900b17 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
> DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
> DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D2),
> DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D2),
> DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
> DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index d095787f7d851fc9..c33d3b0370812840 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -179,7 +179,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
>
> DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D2),
> DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
> DEF_MOD("du1", 723, R8A774C0_CLK_S1D1),
> DEF_MOD("du0", 724, R8A774C0_CLK_S1D1),
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index b9e42da38b72bdcb..5b658b0861180268 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -199,8 +199,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
> DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
> DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
> DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
> - DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
> + DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
> DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
> DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
> DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 97b58f13111441a8..fa1c1ac14d5caa1c 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -179,7 +179,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
> DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
> DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
> DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
> DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index ab25bd5f1371869e..48a9add7d4db8975 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -177,7 +177,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
>
> DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
> DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
> DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
> DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
> DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 3f22b8565648d590..3a88d2247cf5cb17 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -182,7 +182,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
> DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
>
> DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
> - DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
> + DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
> DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
> DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
> DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
2019-03-27 12:41 ` [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Geert Uytterhoeven
@ 2019-03-29 9:32 ` Simon Horman
0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Takeshi Kihara
On Wed, Mar 27, 2019 at 01:41:38PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
> DMA transfers are:
>
> Channel R-Car H3 R-Car M3-W R-Car M3-N
> -------------------------------------------------
> SYS-DMAC0 S0D3 S0D3 S0D3
> SYS-DMAC1 S3D1 S3D1 S3D1
> SYS-DMAC2 S3D1 S3D1 S3D1
>
> As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
> on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.
>
> NOTE: This information will be reflected in a future revision of the
> R-Car Gen3 Hardware Manual.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [geert: Update RZ/G2M]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index 676e6a1120900b17..13bf7260204f5078 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
> DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
> DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
> DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
> - DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
> - DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
> + DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1),
> + DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1),
> DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
> DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
> DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index 5b658b0861180268..a576a42f104442ff 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -130,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
> DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
> DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
> DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
> - DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
> - DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
> + DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
> + DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
> DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
> DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
> DEF_MOD("cmt3", 300, R8A7795_CLK_R),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index fa1c1ac14d5caa1c..369092e8d893255f 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -127,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
> DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
> DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
> - DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
> - DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
> + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
> + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
> DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
> DEF_MOD("cmt3", 300, R8A7796_CLK_R),
> DEF_MOD("cmt2", 301, R8A7796_CLK_R),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index 48a9add7d4db8975..623bbda2d24ec112 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
> DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
> DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
> - DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
> - DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
> + DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
> + DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
> DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
>
> DEF_MOD("cmt3", 300, R8A77965_CLK_R),
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
2019-03-27 12:41 ` [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Geert Uytterhoeven
@ 2019-03-29 9:34 ` Simon Horman
0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Takeshi Kihara
On Wed, Mar 27, 2019 at 01:41:39PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
> DMA transfers are:
>
> Channel R-Car H3 R-Car M3-W R-Car M3-N R-Car E3
> ---------------------------------------------------------------
> Audio-DMAC0 S1D2 S1D2 S1D2 S1D2
> Audio-DMAC1 S1D2 S1D2 S1D2 -
>
> As a result, change the parent clocks of the Audio-DMAC{0,1} module
> clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
> parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.
>
> NOTE: This information will be reflected in a future revision of the
> R-Car Gen3 Hardware Manual.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 ++--
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +-
> drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 +-
> 7 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> index 13bf7260204f5078..76ed7d1bae368adc 100644
> --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
> @@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
> DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
> DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
> - DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
> - DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
> + DEF_MOD("audmac1", 501, R8A774A1_CLK_S1D2),
> + DEF_MOD("audmac0", 502, R8A774A1_CLK_S1D2),
> DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
> DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
> DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> index c33d3b0370812840..f91e7a4847537926 100644
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -158,7 +158,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
>
> - DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4),
> + DEF_MOD("audmac0", 502, R8A774C0_CLK_S1D2),
> DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
> DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
> DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index a576a42f104442ff..e5fa9f6c1ec4b9cb 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -154,8 +154,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
> DEF_MOD("rwdt", 402, R8A7795_CLK_R),
> DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
> - DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
> - DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
> + DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
> + DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
> DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
> DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
> DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 369092e8d893255f..73c69152c77b02ed 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -147,8 +147,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> DEF_MOD("rwdt", 402, R8A7796_CLK_R),
> DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
> - DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
> - DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
> + DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
> + DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
> DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
> DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
> DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index 623bbda2d24ec112..a0ce2ecb656d3d48 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
>
> - DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
> - DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
> + DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
> + DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
> DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
> DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
> DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 3a88d2247cf5cb17..53973201a9f576ad 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -153,7 +153,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
> DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
>
> - DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
> + DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
> DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
> DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
> DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
> diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> index eee3874865a95b1a..68707277b17b42c4 100644
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
> DEF_MOD("rwdt", 402, R8A77995_CLK_R),
> DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
> DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
> - DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
> + DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
> DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
> DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
> DEF_MOD("thermal", 522, R8A77995_CLK_CP),
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks
2019-03-27 12:41 ` [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks Geert Uytterhoeven
@ 2019-03-29 9:39 ` Simon Horman
0 siblings, 0 replies; 13+ messages in thread
From: Simon Horman @ 2019-03-29 9:39 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Takeshi Kihara
On Wed, Mar 27, 2019 at 01:41:40PM +0100, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> According to the R-Car Gen3 Hardware Manual Errata for Rev. 1.50 of Feb
> 12, 2019, the DRIF clocks have been renamed as follows:
>
> DRIF0 to DRIF00
> DRIF1 to DRIF01
> DRIF2 to DRIF10
> DRIF3 to DRIF11
> DRIF4 to DRIF20
> DRIF5 to DRIF21
> DRIF6 to DRIF30
> DRIF7 to DRIF31
>
> Therefore, this patch renames the DRIF clock names from DRIFn to DRIFmm.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/renesas/r8a7795-cpg-mssr.c | 18 +++++++++---------
> drivers/clk/renesas/r8a7796-cpg-mssr.c | 16 ++++++++--------
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 17 +++++++++--------
> drivers/clk/renesas/r8a77990-cpg-mssr.c | 18 +++++++++---------
> 4 files changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index e5fa9f6c1ec4b9cb..9e9a6f2c31e808eb 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -3,7 +3,7 @@
> * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
> *
> * Copyright (C) 2015 Glider bvba
> - * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018-2019 Renesas Electronics Corp.
> *
> * Based on clk-rcar-gen3.c
> *
> @@ -156,14 +156,14 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
> DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
> DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
> DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
> - DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
> - DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
> - DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
> - DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
> - DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
> - DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
> - DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
> - DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
> + DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
> + DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
> + DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
> + DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
> + DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
> + DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
> + DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
> + DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
> DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
> DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
> DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index 73c69152c77b02ed..d8e9af5d9ae9cf6e 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -149,14 +149,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
> DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
> DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
> - DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
> - DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
> - DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
> - DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
> - DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
> - DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
> - DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
> - DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
> + DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
> + DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
> + DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
> + DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
> + DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
> + DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
> + DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
> + DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
> DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
> DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
> DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> index a0ce2ecb656d3d48..8f87e314d9490498 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -3,6 +3,7 @@
> * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
> *
> * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
> + * Copyright (C) 2019 Renesas Electronics Corp.
> *
> * Based on r8a7795-cpg-mssr.c
> *
> @@ -148,14 +149,14 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
>
> DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
> DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
> - DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
> - DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
> - DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
> - DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
> - DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
> - DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
> - DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
> - DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
> + DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
> + DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
> + DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
> + DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
> + DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
> + DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
> + DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
> + DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
> DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
> DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
> DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
> diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> index 53973201a9f576ad..9570404baa583a8f 100644
> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -2,7 +2,7 @@
> /*
> * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
> *
> - * Copyright (C) 2018 Renesas Electronics Corp.
> + * Copyright (C) 2018-2019 Renesas Electronics Corp.
> *
> * Based on r8a7795-cpg-mssr.c
> *
> @@ -154,14 +154,14 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
> DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
>
> DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
> - DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
> - DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
> - DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
> - DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
> - DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
> - DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
> - DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
> - DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
> + DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
> + DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
> + DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
> + DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
> + DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
> + DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
> + DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
> + DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
> DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
> DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
> DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-03-29 9:39 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-27 12:41 [PATCH 0/5] clk: renesas: rcar-gen3: Errata Updates Geert Uytterhoeven
2019-03-27 12:41 ` [PATCH 1/5] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI Geert Uytterhoeven
2019-03-29 9:02 ` Simon Horman
2019-03-29 9:07 ` Geert Uytterhoeven
2019-03-29 9:19 ` Simon Horman
2019-03-27 12:41 ` [PATCH 2/5] clk: renesas: rcar-gen3: Correct parent clock of HS-USB Geert Uytterhoeven
2019-03-29 9:20 ` Simon Horman
2019-03-27 12:41 ` [PATCH 3/5] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC Geert Uytterhoeven
2019-03-29 9:32 ` Simon Horman
2019-03-27 12:41 ` [PATCH 4/5] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC Geert Uytterhoeven
2019-03-29 9:34 ` Simon Horman
2019-03-27 12:41 ` [PATCH 5/5] clk: renesas: rcar-gen3: Rename DRIF clocks Geert Uytterhoeven
2019-03-29 9:39 ` Simon Horman
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