All of lore.kernel.org
 help / color / mirror / Atom feed
* [igt-dev] [RFC v16 0/8] new engine discovery interface
@ 2019-03-28 19:21 Andi Shyti
  2019-03-28 19:21 ` [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument Andi Shyti
                   ` (9 more replies)
  0 siblings, 10 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:21 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

Hi,

In this patchset I propose an alternative way of engine discovery
thanks to the new interfaces developed by Tvrtko and Chris[4].

The changes to perf_pmu are a proposal, most probably they don't
work (it's anyway an RFC) because the dependency to legacy code
is still too strong.

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the
previous RFCs.

Andi

v15 --> v16
===========
 - few changes to the gem_engine_topology stuff
 - added une more dummy test which loops through the physical
   engines, as well.
 - changes to test/perf_pmu required some more changes than
   expected (the 3 last patches)

v14 --> v15
===========
PATCH v14: [16]

 - virtual engines will be called "virtual" like unrecognised
   engines will be called "unknown"

 - renamed the for_each loops to more meaningful names
   (__for_each_static_engine and for_each_context_engine) and
   moved into gem_engine_topology.h

 - minor changes about data types.

v13 --> v14
===========
PATCH v13: [15]
minor changes this time:
 - squashed patch 2 and 3 (from v13) with a little rename and
   added Chris r-b

 - fixed some index issues and string assignement leaks

 - squashed patches 5, 6, 7 and 8 from v13

v12 --> v13
===========
PATCH v12: [14]
This patch is also very different from the previous other than
some reorganization of the code these are the main changes:

 - the previous version lacked the case when the context had its
   engines mapped. checks in the following order

 if the driver doesn't have the new API
  -> get the engines from the static list
 if the driver has the API but the context has nothing mapped
  -> get the engines from "query" and map them
 if the driver has the API and the context has engines mapped
  -> get the engines from the context

 - the helper functions have been removed as they were of no use.

v11 --> v12
===========
PATCH v11: [13]
This 12th version starts from a completely different thought.
Here's the main differences:

 - The list of engines is provided in an engine_data structure
   which contains an index (useful for looping through and for
   engine/context index mapping) instead of an array of engines.

 - The list of engines is generated every time the init function
   is called and nothing is allocated in heap memory.

 - The ioctl check is done already during the initialization part
   and if the new ioctls are not implemented, then the init
   function still stores only those present in the GPU.

 - The for_each loop is implemented by re-using the previous
   'for_each_engine_class_instance()' implemented by Tvrtko.

 - The gem_topology library offers few helper functions for
   checking the engine presence, checking the implementation of
   the ioctls and executing the buffer, in order to be completely
   unaware of the driver implementation.

Thanks Tvrtko for all your inputs.

v10 --> v11
===========
RFC v10: [12]
few cosmetic changes in v11 and minor architectural details.
Thanks Tvrtko.

- the 'query_engines()' functions are static as no one is using
  them yet.

- removed the 'gem_has_engine_topology()' function because it's
  very little used, 'get_active_engines()' can be used instead.

- a minor ring -> engine renaming coming from Chris. 

v9 --> v10
==========
RFC v9: [11]
also this time quite many changes, thanks Chris for the reviews,
here the most relevant of them.

- gem_query.[ch] have been renamed to gem_engine_topology.[ch]
  and all the functions ended up there as they are referring to
  the topology of the engines.

- the functions 'get_active_engines()',
  'gem_set_context_get_engines()' and
  'igt_require_gem_engine_list()' will be the main interface to
  the gem_engine_topology library, refer to patch 2 for details.

- the define 'for_each_engine2()' doesn't expose anymore the
  iterator.

- 'gem_context_has_engine()' has been moved from ioctl_wrappers.c
  to gem_context.c.

- the gem_exec_basic exec-ctx subtest does not abort if the new
  getparam/setparam and query apis are not implemented as it can
  work with both (as it was done at the beginning).

v8 --> v9
=========
RFC v8: [10]
quite many changes, please refer to the review in [10]. Thanks
Chris for the review. These are the most relevant:

- all the allocation in gem_query have been made in stack, not
  anymore allocated dynamically.

- removed get/set_context as it was already implemented and I
  didn't know.

- renamed some functions and variables to hopefully more
  meaningful names.

V7 --> v8
=========
RFC v7: [9]

- all functions have been moved from lib/igt_gt.{c,h} and
  lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks
  Chris)

- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to
  be consistent with the '2' that indicates the new 'struct
  intel_execution_engine2' data structure.

V6 --> V7
=========
RFC v6: [8]

- a new patch has been added (patch 3) which adds a new
  requirement check through the igt_require_gem_engine_list()
  function. (thanks Chris) This function will initialize the
  engine list instead of the instead of igt_require_gem() as it
  was in v6

- all the ioctls have been wrapped (thanks Chris and Antonio) and
  new library functions have been added and assert the ioctls

- gem_init_engine_list() function returns the errno from the
  GETPARAM ioctl in order to be used as a requirement. (thanks
  Chris)

- fixed few requires/asserts

- The engine list "intel_active_engines2" is allocated of the
  number of engines instead of a political 64 (thanks Antonio).

- some parameter renaming in gem_has_ring_by_idx(). (thanks
  Chris).

- the original "intel_execution_engines2" has not been renamed,
  because it is used to create subtests before even executing any
  test/ioctl. By renaming it, some subtest generations failed.
  (thanks Petri)

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test
  to figure otu whether the new interface has been implemented.
  This way the for_each_engine_ctx() is able to work with new and
  old kernel uapi (thanks Chris)

V4 --> V5
=========
RFC v4: [6]

- the engine list is now built in 'igt_require_gem()' instead of
  '__open_driver()' so that we keep this discovery method
  specific to the i915 driver (thanks Chris).

- All the query/setparam structures dynamic allocation based on
  the number of engines, now are politically allocated 64 times,
  to avoid extra ioctl calls that retrieve the engine number
  (thanks Chris)

- use igt_ioctl instead of ioctl (thanks Chris)

- allocate intel_execution_engines2 dynamically instead of
  statically (thanks Tvrtko)

- simplify the test in 'gem_exec_basic()' so that simply checks
  the presence of the engine instead of executing a buffer
  (thank Chris)

- a new patch has been added (patch 3) that extends the
  'gem_has_ring()' boolean function. The new version sets the
  index as it's mapped in the kernel.The previous function is now
  a wrapper to the new function.

V3 --> V4
=========
PATCH v3: [3]

- re-architectured the discovery mechanism based on Tvrtko's
  sugestion and reviews.. In this version the discovery is done
  during the device opening and stored in a NULL terminated
  array, which replaces the existing intel_execution_engines2
  that is mainly used as a reference.

V2 --> V3
=========
RFC v2: [2]

- removed a standalone gem_query_engines_demo test and added the
  exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).

- fixed most of Tvrtko's comments in [5], which consist in
  putting the mallocs igt_assert and ictls in igt_require and few
  refactoring (thanks Tvrtko).

V1 --> V2
=========
RFC v1: [1]

- added a demo test that simply queries the driver about the
  engines and executes a buffer (thanks Tvrtko)

- refactored the for_each_engine_ctx() macro so that what in the
  previous version was done by the "bind" function, now it's done
  in the first iteration. (Thanks Crhis)

- removed the "gem_has_ring_ctx()" because it was out of the
  scope.

- rename functions to more meaningful names

[1] RFC v1: https://lists.freedesktop.org/archives/igt-dev/2018-November/007025.html
[2] RFC v2: https://lists.freedesktop.org/archives/igt-dev/2018-November/007079.html
[3] PATCH v3: https://lists.freedesktop.org/archives/igt-dev/2018-November/007148.html
[4] https://cgit.freedesktop.org/~tursulin/drm-intel/log/?h=media
[5] https://lists.freedesktop.org/archives/igt-dev/2018-November/007100.html
[6] https://lists.freedesktop.org/archives/igt-dev/2019-January/008029.html
[7] https://lists.freedesktop.org/archives/igt-dev/2019-January/008165.html
[8] https://lists.freedesktop.org/archives/igt-dev/2019-February/008902.html
[9] https://lists.freedesktop.org/archives/igt-dev/2019-February/009185.html
[10] https://lists.freedesktop.org/archives/igt-dev/2019-February/009205.html
[11] https://lists.freedesktop.org/archives/igt-dev/2019-February/009277.html
[12] https://lists.freedesktop.org/archives/igt-dev/2019-March/010197.html
[13] https://lists.freedesktop.org/archives/igt-dev/2019-March/010467.html
[14] https://lists.freedesktop.org/archives/igt-dev/2019-March/010776.html
[15] https://lists.freedesktop.org/archives/igt-dev/2019-March/010827.html
[16] https://lists.freedesktop.org/archives/igt-dev/2019-March/010916.html

*** BLURB HERE ***

Andi Shyti (8):
  lib/igt_gt: remove unnecessary argument
  lib: ioctl_wrappers: reach engines by index as well
  include/drm-uapi: import i915_drm.h header file
  lib/i915: add gem_engine_topology library and for_each loop definition
  tests: gem_exec_basic: add engine discovery test
  lib: igt_gt: make gem_engine_can_store_dword() check engine class
  lib: igt_dummyload: use for_each_context_engine()
  test: perf_pmu: use the gem_engine_topology library

 include/drm-uapi/i915_drm.h    | 361 +++++++++++++++++++++++++++------
 lib/Makefile.sources           |   2 +
 lib/i915/gem_context.c         |  28 +++
 lib/i915/gem_context.h         |   2 +
 lib/i915/gem_engine_topology.c | 252 +++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  65 ++++++
 lib/igt.h                      |   1 +
 lib/igt_dummyload.c            |  21 +-
 lib/igt_gt.c                   |  46 ++++-
 lib/igt_gt.h                   |  15 +-
 lib/ioctl_wrappers.c           |  19 --
 lib/ioctl_wrappers.h           |   3 +-
 lib/meson.build                |   1 +
 tests/i915/gem_exec_basic.c    |  26 +++
 tests/perf_pmu.c               |  37 ++--
 15 files changed, 759 insertions(+), 120 deletions(-)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
@ 2019-03-28 19:21 ` Andi Shyti
  2019-03-29 11:34   ` Tvrtko Ursulin
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
                   ` (8 subsequent siblings)
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:21 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

__for_each_engine_class_instance(fd, e) doesn't need and doesn't
use the fd argument. Remove it.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 lib/igt_gt.h     | 2 +-
 tests/perf_pmu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 54e95da98084..475c0b3c3cc6 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(fd__, e__) \
+#define __for_each_engine_class_instance(e__) \
 	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
 
 #define for_each_engine_class_instance(fd__, e__) \
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 1a08f564b066..4f552bc2ae28 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1693,7 +1693,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(fd, e) {
+	__for_each_engine_class_instance(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1897,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(render_fd, e) {
+		__for_each_engine_class_instance(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
  2019-03-28 19:21 ` [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 11:36   ` Tvrtko Ursulin
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 3/8] include/drm-uapi: import i915_drm.h header file Andi Shyti
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

With the new engine query method engines are reachable through
an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
requires the index that the engine is mapped within the driver.
The function has been moved from lib/ioctl_wappers to
lib/i915/gem_context where it is more appropriate.

The previous 'gem_has_ring()' function becomes a wrapper to the
new 'gem_context_has_engine()'.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/i915/gem_context.c | 28 ++++++++++++++++++++++++++++
 lib/i915/gem_context.h |  2 ++
 lib/ioctl_wrappers.c   | 19 -------------------
 lib/ioctl_wrappers.h   |  3 ++-
 4 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index 8b4d5b704650..732f66b4273e 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -271,3 +271,31 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
 {
 	igt_assert_eq(__gem_context_set_priority(fd, ctx_id, prio), 0);
 }
+
+bool gem_context_has_engine(int fd, uint64_t ctx, uint64_t engine)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 exec;
+
+	/*
+	 * 'engine' value can either store an execbuf engine selector
+	 * or a context map index; for the latter case we do not expect
+	 * to have any value at bit 13 and 14 (BSD1/2 selector),
+	 * therefore, we assume that the following check is safe it wouldn't
+	 * produce any result and we don't exepct anyway to have more than
+	 * one engine mapped in 'unit64_t engine'.
+	 */
+	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
+		if (engine & (3 << 13) && !gem_has_bsd2(fd))
+			return false;
+	}
+
+	memset(&exec, 0, sizeof(exec));
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&exec);
+	execbuf.buffer_count = 1;
+	execbuf.flags = engine;
+	execbuf.rsvd1 = ctx;
+
+	return __gem_execbuf(fd, &execbuf) == -ENOENT;
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index aef68dda6b26..d4e8fec3acf0 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
 int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
 void gem_context_set_priority(int fd, uint32_t ctx, int prio);
 
+bool gem_context_has_engine(int fd, uint64_t ctx, uint64_t engine);
+
 #endif /* GEM_CONTEXT_H */
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index a66eb4bc0f4f..3f8f0874bc4b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
-{
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 exec;
-
-	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
-	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
-		if (ring & (3 << 13) && !gem_has_bsd2(fd))
-			return false;
-	}
-
-	memset(&exec, 0, sizeof(exec));
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&exec);
-	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
-	return __gem_execbuf(fd, &execbuf) == -ENOENT;
-}
-
 /**
  * gem_require_ring:
  * @fd: open i915 drm file descriptor
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index ad93daffcfd5..e712f1973142 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(f, r) gem_context_has_engine(f, 0, r)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 3/8] include/drm-uapi: import i915_drm.h header file
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
  2019-03-28 19:21 ` [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument Andi Shyti
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

This header file is imported in order to include the two new
ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM,
DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 include/drm-uapi/i915_drm.h | 361 ++++++++++++++++++++++++++++++------
 1 file changed, 304 insertions(+), 57 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 4ae1c6ff6ae6..2bbad08eb9d2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@@ -104,6 +124,9 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+#define I915_ENGINE_CLASS_INVALID_VIRTUAL 0
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *
@@ -321,6 +344,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
 /* Must be kept compact -- no holes */
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -370,6 +395,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -380,6 +406,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -563,6 +591,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT	52
 
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -1085,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_ARRAY   (1<<19)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
+/*
+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
+ * the batch.
+ *
+ * Returns -EINVAL if the sync_file fd cannot be found.
+ */
+#define I915_EXEC_FENCE_SUBMIT		(1 << 20)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1421,65 +1464,18 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
-	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)
+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE	(1u << 1)
+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
+	(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {
@@ -1520,7 +1516,43 @@ struct drm_i915_gem_context_param {
  * On creation, all new contexts are marked as recoverable.
  */
 #define I915_CONTEXT_PARAM_RECOVERABLE	0x8
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retrieved and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x9
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ *
+ * Extensions:
+ *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
+ *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0xa
 /* Must be kept compact -- no holes and well documented */
+
 	__u64 value;
 };
 
@@ -1553,9 +1585,10 @@ struct drm_i915_gem_context_param_sseu {
 	__u16 engine_instance;
 
 	/*
-	 * Unused for now. Must be cleared to zero.
+	 * Unknown flags must be cleared to zero.
 	 */
 	__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
 
 	/*
 	 * Mask of slices to enable for the context. Valid values are a subset
@@ -1583,6 +1616,175 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+/*
+ * i915_context_engines_load_balance:
+ *
+ * Enable load balancing across this set of engines.
+ *
+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
+ * used will proxy the execbuffer request onto one of the set of engines
+ * in such a way as to distribute the load evenly across the set.
+ *
+ * The set of engines must be compatible (e.g. the same HW class) as they
+ * will share the same logical GPU context and ring.
+ *
+ * To intermix rendering with the virtual engine and direct rendering onto
+ * the backing engines (bypassing the load balancing proxy), the context must
+ * be defined to use a single timeline for all engines.
+ */
+struct i915_context_engines_load_balance {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz16; /* reserved for future use; must be zero */
+	__u32 flags; /* all undefined flags must be zero */
+
+	__u64 engines_mask; /* selection mask of engines[] */
+
+	__u64 mbz64[4]; /* reserved for future use; must be zero */
+};
+
+/*
+ * i915_context_engines_bond:
+ *
+ */
+struct i915_context_engines_bond {
+	struct i915_user_extension base;
+
+	__u16 engine_index;
+	__u16 mbz;
+
+	__u16 master_class;
+	__u16 master_instance;
+
+	__u64 sibling_mask;
+	__u64 flags; /* all undefined flags must be zero */
+};
+
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0
+#define I915_CONTEXT_ENGINES_EXT_BOND 1
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+} __attribute__((packed));
+
+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
+	__u64 extensions; \
+	struct { \
+		__u16 engine_class; \
+		__u16 engine_instance; \
+	} class_instance[N__]; \
+} __attribute__((packed)) name__
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+	struct i915_user_extension base;
+	__u32 clone_id;
+	__u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS	(1u << 0)
+#define I915_CONTEXT_CLONE_SCHED	(1u << 1)
+#define I915_CONTEXT_CLONE_SSEU		(1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE	(1u << 3)
+#define I915_CONTEXT_CLONE_VM		(1u << 4)
+#define I915_CONTEXT_CLONE_ENGINES	(1u << 5)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_ENGINES << 1)
+	__u64 rsvd;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned in the outparam @id.
+ *
+ * No flags are defined, with all bits reserved and must be zero.
+ *
+ * An extension chain maybe provided, starting with @extensions, and terminated
+ * by the @next_extension being 0. Currently, no extensions are defined.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id, specified in @id.
+ *
+ * No extensions or flags are allowed currently, and so must be zero.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
@@ -1744,6 +1946,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 /* Must be kept compact -- no holes and well documented */
 
 	/*
@@ -1842,6 +2045,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 engine_class;
+
+	/** Engine instance number. */
+	__u16 engine_instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (2 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 3/8] include/drm-uapi: import i915_drm.h header file Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 11:34   ` Tvrtko Ursulin
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test Andi Shyti
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.

The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.

The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.

The gem_engine_topology library provides some iteration helpers:

 - intel_get_current_engine(): provides the current engine in the
   iteration.

 - intel_get_current_physical_engine(): provides the current
   physical engine, if the current engine is a virtual engine,
   it moves forward until it finds a physical engine.

 - intel_next_engine() it just increments the counter so that it
   points to the next engine.

Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()' and rename it to
'for_each_context_engine'.

Move '__for_each_engine_class_instance' to gem_engine_topology.h
and rename it to '__for_each_static_engine'.

Update accordingly tests/perf_pmu.c to use correctly the new
for_each loops.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/gem_engine_topology.c | 252 +++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  65 +++++++++
 lib/igt.h                      |   1 +
 lib/igt_gt.h                   |   2 +
 lib/meson.build                |   1 +
 6 files changed, 323 insertions(+)
 create mode 100644 lib/i915/gem_engine_topology.c
 create mode 100644 lib/i915/gem_engine_topology.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index e00347f945c5..41331c2f2b80 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list =	 	\
 	i915/gem_ring.c	\
 	i915/gem_mman.c	\
 	i915/gem_mman.h	\
+	i915/gem_engine_topology.c	\
+	i915/gem_engine_topology.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..4d27237bcf64
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+/*
+ * Limit what we support for simplicity due limitation in how much we
+ * can address via execbuf2.
+ */
+#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
+
+#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
+					class_instance[GEM_MAX_ENGINES])
+#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
+					engines[GEM_MAX_ENGINES])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+	int err = 0;
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+	igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+			  struct drm_i915_query_engine_info *query_engines,
+			  int length)
+{
+	struct drm_i915_query_item item = { };
+	struct drm_i915_query query = { };
+
+	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+	query.items_ptr = to_user_pointer(&item);
+	query.num_items = 1;
+	item.length = length;
+
+	item.data_ptr = to_user_pointer(query_engines);
+
+	gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+			    struct drm_i915_gem_context_param *param)
+{
+	struct i915_context_param_engines *engines =
+			(struct i915_context_param_engines*) param->value;
+	int i = 0;
+
+	for (typeof(engines->class_instance[0]) *p =
+			&engines->class_instance[0];
+						i < ed->nengines; i++, p++) {
+		p->engine_class = ed->engines[i].class;
+		p->engine_instance = ed->engines[i].instance;
+	}
+
+	param->size = offsetof(typeof(*engines), class_instance[i]);
+	engines->extensions = 0;
+
+	gem_context_set_param(fd, param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2,
+			int class, int instance, uint64_t flags)
+{
+	const struct intel_execution_engine2 *__e2;
+	static const char *unknown_name = "unknown",
+			  *virtual_name = "virtual";
+
+	e2->class    = class;
+	e2->instance = instance;
+	e2->flags    = flags;
+
+	/* engine is a virtual engine */
+	if (class == I915_ENGINE_CLASS_INVALID) {
+		e2->name = virtual_name;
+		e2->is_virtual = true;
+		return;
+	}
+
+	__for_each_static_engine(__e2)
+		if (__e2->class == class && __e2->instance == instance)
+			break;
+
+	if (__e2->name) {
+		e2->name = __e2->name;
+	} else {
+		igt_warn("found unknown engine (%d, %d)", class, instance);
+		e2->name = unknown_name;
+	}
+
+	/* just to remark it */
+	e2->is_virtual = false;
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+	uint8_t buff[SIZEOF_QUERY] = { };
+	struct drm_i915_query_engine_info *query_engine =
+			(struct drm_i915_query_engine_info *) buff;
+	int i;
+
+	query_engines(fd, query_engine, SIZEOF_QUERY);
+
+	for (i = 0; i < query_engine->num_engines; i++)
+		init_engine(&ed->engines[i],
+			    query_engine->engines[i].engine_class,
+			    query_engine->engines[i].engine_instance, i);
+
+	ed->nengines = query_engine->num_engines;
+}
+
+struct intel_execution_engine2
+*intel_get_current_engine(struct intel_engine_data *ed)
+{
+	return ed->current_engine;
+}
+
+void intel_next_engine(struct intel_engine_data *ed)
+{
+	if (ed->n + 1 < ed->nengines) {
+		ed->n++;
+		ed->current_engine = &ed->engines[ed->n];
+	} else {
+		ed->current_engine = NULL;
+	}
+}
+
+struct intel_execution_engine2
+*intel_get_current_physical_engine(struct intel_engine_data *ed)
+{
+	struct intel_execution_engine2 *e;
+
+	for (e = intel_get_current_engine(ed);
+	     e && e->is_virtual;
+	     intel_next_engine(ed))
+		;
+
+	ed->current_phys_engine = e;
+
+	return e;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
+	struct intel_engine_data engine_data = { };
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+		.ctx_id = ctx_id,
+		.size = SIZEOF_CTX_PARAM,
+		.value = to_user_pointer(&engines),
+	};
+	int i;
+	unsigned int nengines;
+
+	if(__gem_context_get_param(fd, &param)) {
+		/* if kernel does not support engine/context mapping */
+		const struct intel_execution_engine2 *e2;
+
+		igt_debug("using pre-allocated engine list\n");
+
+		__for_each_static_engine(e2) {
+			struct intel_execution_engine2 *__e2;
+
+			__e2 = &engine_data.engines[engine_data.nengines];
+			__e2->flags = gem_class_instance_to_eb_flags(fd,
+						e2->class, e2->instance);
+
+			if (!gem_has_ring(fd, __e2->flags))
+				continue;
+
+			__e2->name       = e2->name;
+			__e2->instance   = e2->instance;
+			__e2->class      = e2->class;
+			__e2->is_virtual = false;
+
+			engine_data.nengines++;
+		}
+		goto exit;
+	}
+
+	nengines = param.size > sizeof(struct i915_context_param_engines) ?
+		   (param.size - sizeof(struct i915_context_param_engines)) /
+		   sizeof(engines.class_instance[0]) :
+		   0;
+
+	igt_assert_f(nengines < GEM_MAX_ENGINES, "unsupported engine count\n");
+
+	if (!param.size) {
+		/* else if context doesn't have mapped engines */
+		query_engine_list(fd, &engine_data);
+		ctx_map_engines(fd, &engine_data, &param);
+
+	} else {
+		/* context has a list of mapped engines */
+
+		for (i = 0; i < nengines; i++)
+			init_engine(&engine_data.engines[i],
+				    engines.class_instance[i].engine_class,
+				    engines.class_instance[i].engine_instance,
+				    i);
+
+		engine_data.nengines = i;
+	}
+
+exit:
+	engine_data.current_engine = &engine_data.engines[0];
+	engine_data.current_phys_engine =
+		intel_get_current_physical_engine(&engine_data);
+
+	return engine_data;
+}
+
+bool gem_has_engine_topology(int fd)
+{
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_ENGINES,
+	};
+
+	return !__gem_context_get_param(fd, &param);
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..d3275737add4
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "igt_gt.h"
+#include "i915_drm.h"
+
+struct intel_engine_data {
+	uint32_t nengines;
+	uint32_t n;
+	int error;
+	struct intel_execution_engine2 *current_engine;
+	struct intel_execution_engine2 *current_phys_engine;
+	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+bool gem_has_engine_topology(int fd);
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+/* iteration functions */
+struct intel_execution_engine2
+*intel_get_current_engine(struct intel_engine_data *ed);
+
+struct intel_execution_engine2
+*intel_get_current_physical_engine(struct intel_engine_data *ed);
+
+void intel_next_engine(struct intel_engine_data *ed);
+
+#define __for_each_static_engine(e__) \
+	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
+
+#define for_each_context_engine(fd__, ctx__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+	     ((e__) = intel_get_current_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+/* needs to replace "for_each_physical_engine" when conflicts are fixed */
+#define __for_each_physical_engine(fd__, e__) \
+	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
+	     ((e__) = intel_get_current_physical_engine(&i__)); \
+	     intel_next_engine(&i__))
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt.h b/lib/igt.h
index 6654a659c062..03f19ca2dfb6 100644
--- a/lib/igt.h
+++ b/lib/igt.h
@@ -53,5 +53,6 @@
 #include "media_spin.h"
 #include "rendercopy.h"
 #include "i915/gem_mman.h"
+#include "i915/gem_engine_topology.h"
 
 #endif /* IGT_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..52b2f1ea95a5 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,8 @@ extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;
+	uint64_t flags;
+	bool is_virtual;
 } intel_execution_engines2[];
 
 unsigned int
diff --git a/lib/meson.build b/lib/meson.build
index 89de06e6924a..93c01daa4222 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
+	'i915/gem_engine_topology.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (3 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 11:39   ` Tvrtko Ursulin
  2019-03-29 23:36   ` Chris Wilson
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class Andi Shyti
                   ` (4 subsequent siblings)
  9 siblings, 2 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

The "exec-engines-ctx" and "exec-physical-engines-ctx" are two
demo subtest inserted in the gem_exec_basic
test. The main goal is to reach the engines by using
the new uapi interfacing with 'gem_topology_has_engine()'.

The two cases get the list of both virtual and physical and only
physical engines and makes sure they actually exist.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 tests/i915/gem_exec_basic.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index dcb83864b1c1..ed3388952146 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -135,6 +135,32 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-engines-ctx") {
+		uint64_t ctx_id;
+		struct intel_execution_engine2 *e2;
+
+		ctx_id = gem_context_create(fd);
+
+		for_each_context_engine(fd, ctx_id, e2)
+			igt_assert(gem_context_has_engine(fd, ctx_id,
+							  e2->flags));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
+	igt_subtest("exec-physical-engines-ctx") {
+		uint64_t ctx_id;
+		struct intel_execution_engine2 *e2;
+
+		ctx_id = gem_context_create(fd);
+
+		__for_each_physical_engine(fd, e2)
+			igt_assert(gem_context_has_engine(fd, ctx_id,
+							  e2->flags));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (4 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 12:22   ` Tvrtko Ursulin
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine() Andi Shyti
                   ` (3 subsequent siblings)
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

Engines referred by class and instance are getting more populare,
gem_engine_can_store_dword() should handle the situation.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_gt.c | 46 +++++++++++++++++++++++++++++++++++++++-------
 lib/igt_gt.h |  6 ++++--
 2 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 5999524326d0..630aa421ffb3 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -41,6 +41,7 @@
 #include "intel_reg.h"
 #include "intel_chipset.h"
 #include "igt_dummyload.h"
+#include "i915/gem_engine_topology.h"
 
 /**
  * SECTION:igt_gt
@@ -556,27 +557,58 @@ const struct intel_execution_engine intel_execution_engines[] = {
 	{ NULL, 0, 0 }
 };
 
-bool gem_can_store_dword(int fd, unsigned int engine)
+static bool __gem_can_store_dword(const int gen, const struct intel_device_info *info)
 {
-	uint16_t devid = intel_get_drm_devid(fd);
-	const struct intel_device_info *info = intel_get_device_info(devid);
-	const int gen = ffs(info->gen);
-
 	if (gen <= 2) /* requires physical addresses */
 		return false;
 
 	if (gen == 3 && (info->is_grantsdale || info->is_alviso))
 		return false; /* only supports physical addresses */
 
+	if (info->is_broadwater)
+		return false; /* Not sure yet... */
+
+	return true;
+}
+
+bool gem_can_store_dword(int fd, uint64_t engine)
+{
+	uint16_t devid = intel_get_drm_devid(fd);
+	const struct intel_device_info *info = intel_get_device_info(devid);
+	const int gen = ffs(info->gen);
+
+	if (!__gem_can_store_dword(gen, info))
+		return false;
+
 	if (gen == 6 && ((engine & 0x3f) == I915_EXEC_BSD))
 		return false; /* kills the machine! */
 
-	if (info->is_broadwater)
-		return false; /* Not sure yet... */
+	return true;
+}
+
+bool gem_class_can_store_dword(int fd, uint64_t class)
+{
+	uint16_t devid = intel_get_drm_devid(fd);
+	const struct intel_device_info *info = intel_get_device_info(devid);
+	const int gen = ffs(info->gen);
+
+	if (!__gem_can_store_dword(gen, info))
+		return false;
+
+	if (gen == 6 && class == I915_ENGINE_CLASS_VIDEO)
+		return false;
 
 	return true;
 }
 
+bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e)
+{
+	if (!gem_has_engine_topology(fd))
+		return gem_can_store_dword(fd, e->flags);
+
+	return gem_class_can_store_dword(fd, e->class);
+}
+
 const struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
 	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 52b2f1ea95a5..f3f07e895733 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -89,8 +89,6 @@ extern const struct intel_execution_engine {
 bool gem_ring_is_physical_engine(int fd, unsigned int ring);
 bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
-bool gem_can_store_dword(int fd, unsigned int engine);
-
 extern const struct intel_execution_engine2 {
 	const char *name;
 	int class;
@@ -99,6 +97,10 @@ extern const struct intel_execution_engine2 {
 	bool is_virtual;
 } intel_execution_engines2[];
 
+bool gem_can_store_dword(int fd, uint64_t);
+bool gem_class_can_store_dword(int fd, uint64_t class);
+bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e);
+
 unsigned int
 gem_class_instance_to_eb_flags(int gem_fd,
 			       enum drm_i915_gem_engine_class class,
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine()
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (5 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 12:33   ` Tvrtko Ursulin
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library Andi Shyti
                   ` (2 subsequent siblings)
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

With the new getparam/setparam api, engines are mapped to
context. Use for_each_context_engine() to loop through existing
engines.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 lib/igt_dummyload.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 47f6b92b424b..4e94ccc448ba 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -39,6 +39,7 @@
 #include "ioctl_wrappers.h"
 #include "sw_sync.h"
 #include "igt_vgem.h"
+#include "i915/gem_engine_topology.h"
 #include "i915/gem_mman.h"
 
 /**
@@ -86,7 +87,7 @@ emit_recursive_batch(igt_spin_t *spin,
 	struct drm_i915_gem_relocation_entry relocs[2], *r;
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *obj;
-	unsigned int engines[16];
+	unsigned int flags[16];
 	unsigned int nengine;
 	int fence_fd = -1;
 	uint32_t *batch, *batch_start;
@@ -94,17 +95,17 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	nengine = 0;
 	if (opts->engine == ALL_ENGINES) {
-		unsigned int engine;
+		struct intel_execution_engine2 *engine;
 
-		for_each_physical_engine(fd, engine) {
+		for_each_context_engine(fd, opts->ctx, engine) {
 			if (opts->flags & IGT_SPIN_POLL_RUN &&
-			    !gem_can_store_dword(fd, engine))
+			    !gem_engine_can_store_dword(fd, engine))
 				continue;
 
-			engines[nengine++] = engine;
+			flags[nengine++] = engine->flags;
 		}
 	} else {
-		engines[nengine++] = opts->engine;
+		flags[nengine++] = opts->engine;
 	}
 	igt_require(nengine);
 
@@ -234,7 +235,7 @@ emit_recursive_batch(igt_spin_t *spin,
 
 	for (i = 0; i < nengine; i++) {
 		execbuf->flags &= ~ENGINE_MASK;
-		execbuf->flags |= engines[i];
+		execbuf->flags |= flags[i];
 
 		gem_execbuf_wr(fd, execbuf);
 
@@ -308,12 +309,6 @@ igt_spin_batch_factory(int fd, const struct igt_spin_factory *opts)
 
 	igt_require_gem(fd);
 
-	if (opts->engine != ALL_ENGINES) {
-		gem_require_ring(fd, opts->engine);
-		if (opts->flags & IGT_SPIN_POLL_RUN)
-			igt_require(gem_can_store_dword(fd, opts->engine));
-	}
-
 	spin = spin_batch_create(fd, opts);
 
 	igt_assert(gem_bo_busy(fd, spin->handle));
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (6 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine() Andi Shyti
@ 2019-03-28 19:22 ` Andi Shyti
  2019-03-29 12:40   ` Tvrtko Ursulin
  2019-03-28 20:15 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
  2019-03-29  7:40 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  9 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-28 19:22 UTC (permalink / raw)
  To: IGT dev; +Cc: Andi Shyti

Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.

Use whenever possible gem_engine_can_store_dword() that checks
class instead of flags.

Now the __for_each_engine_class_instance and
for_each_engine_class_instance are unused, remove them.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 lib/igt_gt.h     |  7 -------
 tests/perf_pmu.c | 37 +++++++++++++++++++++++--------------
 2 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index f3f07e895733..cd6d7e4f8967 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -118,11 +118,4 @@ void gem_require_engine(int gem_fd,
 	igt_require(gem_has_engine(gem_fd, class, instance));
 }
 
-#define __for_each_engine_class_instance(e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-
-#define for_each_engine_class_instance(fd__, e__) \
-	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
-		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
-
 #endif /* IGT_GT_H */
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4f552bc2ae28..1487688781ab 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -170,14 +170,14 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 #define FLAG_LONG (16)
 #define FLAG_HANG (32)
 
-static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
+static igt_spin_t * __spin_poll(int fd, uint32_t ctx, const struct intel_execution_engine2 *e)
 {
 	struct igt_spin_factory opts = {
 		.ctx = ctx,
-		.engine = flags,
+		.engine = e->flags,
 	};
 
-	if (gem_can_store_dword(fd, flags))
+	if (gem_engine_can_store_dword(fd, e))
 		opts.flags |= IGT_SPIN_POLL_RUN;
 
 	return __igt_spin_batch_factory(fd, &opts);
@@ -211,7 +211,16 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
 
 static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
 {
-	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
+	struct igt_spin_factory opts = {
+		.ctx = ctx,
+		.engine = flags,
+	};
+	igt_spin_t *spin;
+
+	if (gem_can_store_dword(fd, flags))
+		opts.flags |= IGT_SPIN_POLL_RUN;
+
+	spin = __igt_spin_batch_factory(fd, &opts);
 
 	__spin_wait(fd, spin);
 
@@ -434,8 +443,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	i = 0;
 	fd[0] = -1;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			busy_idx = i;
 
 		fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
@@ -497,13 +506,13 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	unsigned int idle_idx, i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e_) {
-		if (e == e_)
+	__for_each_physical_engine(gem_fd, e_) {
+		if (e->class == e_->class && e->instance == e_->instance)
 			idle_idx = i;
 		else if (spin)
 			__submit_spin_batch(gem_fd, spin, e_, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
+			spin = __spin_poll(gem_fd, 0, e);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
 	}
@@ -554,11 +563,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
 	unsigned int i;
 
 	i = 0;
-	for_each_engine_class_instance(gem_fd, e) {
+	__for_each_physical_engine(gem_fd, e) {
 		if (spin)
 			__submit_spin_batch(gem_fd, spin, e, 64);
 		else
-			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
+			spin = __spin_poll(gem_fd, 0, e);
 
 		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
 	}
@@ -1683,7 +1692,7 @@ igt_main
 		igt_require_gem(fd);
 		igt_require(i915_type_id() > 0);
 
-		for_each_engine_class_instance(fd, e)
+		__for_each_physical_engine(fd, e)
 			num_engines++;
 	}
 
@@ -1693,7 +1702,7 @@ igt_main
 	igt_subtest("invalid-init")
 		invalid_init();
 
-	__for_each_engine_class_instance(e) {
+	__for_each_static_engine(e) {
 		const unsigned int pct[] = { 2, 50, 98 };
 
 		/**
@@ -1897,7 +1906,7 @@ igt_main
 			gem_quiescent_gpu(fd);
 		}
 
-		__for_each_engine_class_instance(e) {
+		__for_each_static_engine(e) {
 			igt_subtest_group {
 				igt_fixture {
 					gem_require_engine(render_fd,
-- 
2.20.1

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply related	[flat|nested] 29+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (7 preceding siblings ...)
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library Andi Shyti
@ 2019-03-28 20:15 ` Patchwork
  2019-03-29  7:40 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  9 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-03-28 20:15 UTC (permalink / raw)
  To: Andi Shyti; +Cc: igt-dev

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58689/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5832 -> IGTPW_2730
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58689/revisions/1/mbox/

Known issues
------------

  Here are the changes found in IGTPW_2730 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-hsw-4770:        PASS -> SKIP [fdo#109271] +3

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         PASS -> FAIL [fdo#104008]

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS +1

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720


Participating hosts (43 -> 37)
------------------------------

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-bsw-cyan fi-pnv-d510 


Build changes
-------------

    * IGT: IGT_4911 -> IGTPW_2730

  CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2730: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
  IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@exec-engines-ctx
+igt@gem_exec_basic@exec-physical-engines-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for new engine discovery interface
  2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
                   ` (8 preceding siblings ...)
  2019-03-28 20:15 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
@ 2019-03-29  7:40 ` Patchwork
  9 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2019-03-29  7:40 UTC (permalink / raw)
  To: Andi Shyti; +Cc: igt-dev

== Series Details ==

Series: new engine discovery interface
URL   : https://patchwork.freedesktop.org/series/58689/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5832_full -> IGTPW_2730_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_2730_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_2730_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/58689/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_2730_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf_pmu@most-busy-check-all-rcs0:
    - shard-kbl:          PASS -> FAIL +1
    - shard-apl:          PASS -> FAIL +1
    - shard-snb:          PASS -> FAIL +1
    - shard-hsw:          PASS -> FAIL +1

  * igt@perf_pmu@most-busy-idle-check-all-rcs0:
    - shard-glk:          PASS -> FAIL +1

  
#### Warnings ####

  * igt@gem_wait@await-vebox:
    - shard-snb:          SKIP [fdo#109271] -> FAIL +4

  
New tests
---------

  New tests have been introduced between CI_DRM_5832_full and IGTPW_2730_full:

### New IGT tests (2) ###

  * igt@gem_exec_basic@exec-engines-ctx:
    - Statuses : 4 pass(s)
    - Exec time: [0.0] s

  * igt@gem_exec_basic@exec-physical-engines-ctx:
    - Statuses : 5 pass(s)
    - Exec time: [0.0, 0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_2730_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
    - shard-apl:          PASS -> FAIL [fdo#109660]

  * igt@kms_atomic_transition@3x-modeset-transitions:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10

  * igt@kms_atomic_transition@6x-modeset-transitions-fencing:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#110222]
    - shard-kbl:          PASS -> DMESG-WARN [fdo#110222]

  * igt@kms_cursor_crc@cursor-256x85-onscreen:
    - shard-apl:          PASS -> FAIL [fdo#103232]
    - shard-kbl:          PASS -> FAIL [fdo#103232]

  * igt@kms_fbcon_fbt@fbc:
    - shard-glk:          NOTRUN -> SKIP [fdo#109271] +14

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          PASS -> FAIL [fdo#105363] +1

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-apl:          PASS -> FAIL [fdo#103060]

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +96

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_setmode@basic:
    - shard-hsw:          PASS -> FAIL [fdo#99912]

  * igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm:
    - shard-apl:          PASS -> FAIL [fdo#104894] +2

  * igt@kms_vblank@pipe-c-ts-continuation-modeset-hang:
    - shard-kbl:          PASS -> FAIL [fdo#104894]

  * igt@perf_pmu@busy-hang-vcs1:
    - shard-apl:          NOTRUN -> SKIP [fdo#109271]

  * igt@tools_test@tools_test:
    - shard-hsw:          PASS -> SKIP [fdo#109271]

  
#### Possible fixes ####

  * igt@gem_wait@await-bsd2:
    - shard-apl:          SKIP [fdo#109271] -> PASS +9

  * igt@gem_wait@wait-bsd2:
    - shard-snb:          SKIP [fdo#109271] -> PASS +7

  * igt@gem_wait@write-busy-bsd2:
    - shard-hsw:          SKIP [fdo#109271] -> PASS +9

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-kbl:          DMESG-WARN [fdo#110222] -> PASS
    - shard-hsw:          DMESG-WARN [fdo#110222] -> PASS

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-glk:          DMESG-WARN [fdo#110222] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-dpms:
    - shard-kbl:          FAIL [fdo#103232] -> PASS
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_draw_crc@draw-method-xrgb8888-render-xtiled:
    - shard-glk:          FAIL [fdo#107791] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-apl:          FAIL [fdo#103167] -> PASS
    - shard-kbl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
    - shard-glk:          FAIL [fdo#103167] -> PASS

  * {igt@kms_plane@pixel-format-pipe-b-planes-source-clamping}:
    - shard-glk:          SKIP [fdo#109271] -> PASS +8

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-glk:          FAIL [fdo#108145] -> PASS

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_setmode@basic:
    - shard-apl:          FAIL [fdo#99912] -> PASS

  * igt@kms_vblank@pipe-a-ts-continuation-modeset:
    - shard-apl:          FAIL [fdo#104894] -> PASS
    - shard-kbl:          FAIL [fdo#104894] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109660]: https://bugs.freedesktop.org/show_bug.cgi?id=109660
  [fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 5)
------------------------------

  Missing    (5): shard-skl pig-hsw-4770r pig-glk-j5005 shard-iclb pig-skl-6260u 


Build changes
-------------

    * IGT: IGT_4911 -> IGTPW_2730
    * Piglit: piglit_4509 -> None

  CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_2730: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
  IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2730/
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
@ 2019-03-29 11:34   ` Tvrtko Ursulin
  2019-03-29 12:05     ` Andi Shyti
  0 siblings, 1 reply; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 11:34 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> The gem_engine_topology library is a set of functions that
> interface with the query and getparam/setparam ioctls.
> 
> The library's access point is the 'intel_init_engine_list()'
> function that, everytime is called, generates the list of active
> engines and returns them in a 'struct intel_engine_data'. The
> structure contains only the engines that are actively present in
> the GPU.
> 
> The function can work in both the cases that the query and
> getparam ioctls are implemented or not by the running kernel. In
> case they are implemented, a query is made to the driver to fetch
> the list of active engines. In case they are not implemented, the
> list is taken from the 'intel_execution_engines2' array and
> stored only after checking their presence.
> 
> The gem_engine_topology library provides some iteration helpers:
> 
>   - intel_get_current_engine(): provides the current engine in the
>     iteration.
> 
>   - intel_get_current_physical_engine(): provides the current
>     physical engine, if the current engine is a virtual engine,
>     it moves forward until it finds a physical engine.
> 
>   - intel_next_engine() it just increments the counter so that it
>     points to the next engine.
> 
> Extend the 'for_each_engine_class_instance' so that it can loop
> using the new 'intel_init_engine_list()' and rename it to
> 'for_each_context_engine'.
> 
> Move '__for_each_engine_class_instance' to gem_engine_topology.h
> and rename it to '__for_each_static_engine'.
> 
> Update accordingly tests/perf_pmu.c to use correctly the new
> for_each loops.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/Makefile.sources           |   2 +
>   lib/i915/gem_engine_topology.c | 252 +++++++++++++++++++++++++++++++++
>   lib/i915/gem_engine_topology.h |  65 +++++++++
>   lib/igt.h                      |   1 +
>   lib/igt_gt.h                   |   2 +
>   lib/meson.build                |   1 +
>   6 files changed, 323 insertions(+)
>   create mode 100644 lib/i915/gem_engine_topology.c
>   create mode 100644 lib/i915/gem_engine_topology.h
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index e00347f945c5..41331c2f2b80 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -13,6 +13,8 @@ lib_source_list =	 	\
>   	i915/gem_ring.c	\
>   	i915/gem_mman.c	\
>   	i915/gem_mman.h	\
> +	i915/gem_engine_topology.c	\
> +	i915/gem_engine_topology.h	\
>   	i915_3d.h		\
>   	i915_reg.h		\
>   	i915_pciids.h		\
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> new file mode 100644
> index 000000000000..4d27237bcf64
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.c
> @@ -0,0 +1,252 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "drmtest.h"
> +#include "ioctl_wrappers.h"
> +
> +#include "i915/gem_engine_topology.h"
> +
> +/*
> + * Limit what we support for simplicity due limitation in how much we
> + * can address via execbuf2.
> + */
> +#define GEM_MAX_ENGINES		I915_EXEC_RING_MASK + 1
> +
> +#define SIZEOF_CTX_PARAM	offsetof(struct i915_context_param_engines, \
> +					class_instance[GEM_MAX_ENGINES])
> +#define SIZEOF_QUERY		offsetof(struct drm_i915_query_engine_info, \
> +					engines[GEM_MAX_ENGINES])
> +
> +static int __gem_query(int fd, struct drm_i915_query *q)
> +{
> +	int err = 0;
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
> +		err = -errno;
> +
> +	errno = 0;
> +	return err;
> +}
> +
> +static void gem_query(int fd, struct drm_i915_query *q)
> +{
> +	igt_assert_eq(__gem_query(fd, q), 0);
> +}
> +
> +static void query_engines(int fd,
> +			  struct drm_i915_query_engine_info *query_engines,
> +			  int length)
> +{
> +	struct drm_i915_query_item item = { };
> +	struct drm_i915_query query = { };
> +
> +	item.query_id = DRM_I915_QUERY_ENGINE_INFO;
> +	query.items_ptr = to_user_pointer(&item);
> +	query.num_items = 1;
> +	item.length = length;
> +
> +	item.data_ptr = to_user_pointer(query_engines);
> +
> +	gem_query(fd, &query);
> +}
> +
> +static void ctx_map_engines(int fd, struct intel_engine_data *ed,
> +			    struct drm_i915_gem_context_param *param)
> +{
> +	struct i915_context_param_engines *engines =
> +			(struct i915_context_param_engines*) param->value;
> +	int i = 0;
> +
> +	for (typeof(engines->class_instance[0]) *p =
> +			&engines->class_instance[0];
> +						i < ed->nengines; i++, p++) {
> +		p->engine_class = ed->engines[i].class;
> +		p->engine_instance = ed->engines[i].instance;
> +	}
> +
> +	param->size = offsetof(typeof(*engines), class_instance[i]);
> +	engines->extensions = 0;
> +
> +	gem_context_set_param(fd, param);
> +}
> +
> +static void init_engine(struct intel_execution_engine2 *e2,
> +			int class, int instance, uint64_t flags)
> +{
> +	const struct intel_execution_engine2 *__e2;
> +	static const char *unknown_name = "unknown",
> +			  *virtual_name = "virtual";
> +
> +	e2->class    = class;
> +	e2->instance = instance;
> +	e2->flags    = flags;
> +
> +	/* engine is a virtual engine */
> +	if (class == I915_ENGINE_CLASS_INVALID) {
> +		e2->name = virtual_name;
> +		e2->is_virtual = true;
> +		return;
> +	}
> +
> +	__for_each_static_engine(__e2)
> +		if (__e2->class == class && __e2->instance == instance)
> +			break;
> +
> +	if (__e2->name) {
> +		e2->name = __e2->name;
> +	} else {
> +		igt_warn("found unknown engine (%d, %d)", class, instance);
> +		e2->name = unknown_name;
> +	}
> +
> +	/* just to remark it */
> +	e2->is_virtual = false;
> +}
> +
> +static void query_engine_list(int fd, struct intel_engine_data *ed)
> +{
> +	uint8_t buff[SIZEOF_QUERY] = { };
> +	struct drm_i915_query_engine_info *query_engine =
> +			(struct drm_i915_query_engine_info *) buff;
> +	int i;
> +
> +	query_engines(fd, query_engine, SIZEOF_QUERY);
> +
> +	for (i = 0; i < query_engine->num_engines; i++)
> +		init_engine(&ed->engines[i],
> +			    query_engine->engines[i].engine_class,
> +			    query_engine->engines[i].engine_instance, i);
> +
> +	ed->nengines = query_engine->num_engines;
> +}
> +
> +struct intel_execution_engine2
> +*intel_get_current_engine(struct intel_engine_data *ed)
> +{
> +	return ed->current_engine;
> +}
> +
> +void intel_next_engine(struct intel_engine_data *ed)
> +{
> +	if (ed->n + 1 < ed->nengines) {
> +		ed->n++;
> +		ed->current_engine = &ed->engines[ed->n];
> +	} else {
> +		ed->current_engine = NULL;
> +	}
> +}
> +
> +struct intel_execution_engine2
> +*intel_get_current_physical_engine(struct intel_engine_data *ed)
> +{
> +	struct intel_execution_engine2 *e;
> +
> +	for (e = intel_get_current_engine(ed);
> +	     e && e->is_virtual;
> +	     intel_next_engine(ed))
> +		;
> +
> +	ed->current_phys_engine = e;
> +
> +	return e;
> +}
> +
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
> +{
> +	I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, GEM_MAX_ENGINES);
> +	struct intel_engine_data engine_data = { };
> +	struct drm_i915_gem_context_param param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +		.ctx_id = ctx_id,
> +		.size = SIZEOF_CTX_PARAM,
> +		.value = to_user_pointer(&engines),
> +	};
> +	int i;
> +	unsigned int nengines;
> +
> +	if(__gem_context_get_param(fd, &param)) {
> +		/* if kernel does not support engine/context mapping */
> +		const struct intel_execution_engine2 *e2;
> +
> +		igt_debug("using pre-allocated engine list\n");
> +
> +		__for_each_static_engine(e2) {
> +			struct intel_execution_engine2 *__e2;
> +
> +			__e2 = &engine_data.engines[engine_data.nengines];
> +			__e2->flags = gem_class_instance_to_eb_flags(fd,
> +						e2->class, e2->instance);

Once we add more engines to the static list they would have legacy eb 
engine selector. So I think this will have to be changed so that it 
skips those here rather than hits the assert in 
gem_class_instance_to_eb_flags.

> +
> +			if (!gem_has_ring(fd, __e2->flags))
> +				continue;
> +
> +			__e2->name       = e2->name;
> +			__e2->instance   = e2->instance;
> +			__e2->class      = e2->class;
> +			__e2->is_virtual = false;
> +
> +			engine_data.nengines++;
> +		}
> +		goto exit;
> +	}
> +
> +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> +		   (param.size - sizeof(struct i915_context_param_engines)) /
> +		   sizeof(engines.class_instance[0]) :
> +		   0;
> +
> +	igt_assert_f(nengines < GEM_MAX_ENGINES, "unsupported engine count\n");

Should this be <= ?

> +
> +	if (!param.size) {
> +		/* else if context doesn't have mapped engines */
> +		query_engine_list(fd, &engine_data);
> +		ctx_map_engines(fd, &engine_data, &param);
> +
> +	} else {
> +		/* context has a list of mapped engines */
> +
> +		for (i = 0; i < nengines; i++)
> +			init_engine(&engine_data.engines[i],
> +				    engines.class_instance[i].engine_class,
> +				    engines.class_instance[i].engine_instance,
> +				    i);
> +
> +		engine_data.nengines = i;
> +	}
> +
> +exit:
> +	engine_data.current_engine = &engine_data.engines[0];
> +	engine_data.current_phys_engine =
> +		intel_get_current_physical_engine(&engine_data);
> +
> +	return engine_data;
> +}
> +
> +bool gem_has_engine_topology(int fd)
> +{
> +	struct drm_i915_gem_context_param param = {
> +		.param = I915_CONTEXT_PARAM_ENGINES,
> +	};
> +
> +	return !__gem_context_get_param(fd, &param);
> +}
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> new file mode 100644
> index 000000000000..d3275737add4
> --- /dev/null
> +++ b/lib/i915/gem_engine_topology.h
> @@ -0,0 +1,65 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef GEM_ENGINE_TOPOLOGY_H
> +#define GEM_ENGINE_TOPOLOGY_H
> +
> +#include "igt_gt.h"
> +#include "i915_drm.h"
> +
> +struct intel_engine_data {
> +	uint32_t nengines;
> +	uint32_t n;
> +	int error;
> +	struct intel_execution_engine2 *current_engine;
> +	struct intel_execution_engine2 *current_phys_engine;

This field seem only ever assigned, never otherwise used. Do you need it 
for something later?

> +	struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
> +};
> +
> +bool gem_has_engine_topology(int fd);
> +struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
> +
> +/* iteration functions */
> +struct intel_execution_engine2
> +*intel_get_current_engine(struct intel_engine_data *ed);
> +
> +struct intel_execution_engine2
> +*intel_get_current_physical_engine(struct intel_engine_data *ed);
> +
> +void intel_next_engine(struct intel_engine_data *ed);
> +
> +#define __for_each_static_engine(e__) \
> +	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> +
> +#define for_each_context_engine(fd__, ctx__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> +	     ((e__) = intel_get_current_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +

I would probably have the physical vs virtual logic in the "next" helper 
and just one intel_get_current_engine but it is not very relevant.

> +/* needs to replace "for_each_physical_engine" when conflicts are fixed */
> +#define __for_each_physical_engine(fd__, e__) \
> +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, 0); \
> +	     ((e__) = intel_get_current_physical_engine(&i__)); \
> +	     intel_next_engine(&i__))
> +
> +#endif /* GEM_ENGINE_TOPOLOGY_H */
> diff --git a/lib/igt.h b/lib/igt.h
> index 6654a659c062..03f19ca2dfb6 100644
> --- a/lib/igt.h
> +++ b/lib/igt.h
> @@ -53,5 +53,6 @@
>   #include "media_spin.h"
>   #include "rendercopy.h"
>   #include "i915/gem_mman.h"
> +#include "i915/gem_engine_topology.h"
>   
>   #endif /* IGT_H */
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 475c0b3c3cc6..52b2f1ea95a5 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -95,6 +95,8 @@ extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
>   	int instance;
> +	uint64_t flags;
> +	bool is_virtual;
>   } intel_execution_engines2[];
>   
>   unsigned int
> diff --git a/lib/meson.build b/lib/meson.build
> index 89de06e6924a..93c01daa4222 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -5,6 +5,7 @@ lib_sources = [
>   	'i915/gem_submission.c',
>   	'i915/gem_ring.c',
>   	'i915/gem_mman.c',
> +	'i915/gem_engine_topology.c',
>   	'igt_color_encoding.c',
>   	'igt_debugfs.c',
>   	'igt_device.c',
> 

Looks mostly as expected. I trust you tested it works. :) With the 
assert fixed and unused struct member removed:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument
  2019-03-28 19:21 ` [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument Andi Shyti
@ 2019-03-29 11:34   ` Tvrtko Ursulin
  0 siblings, 0 replies; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 11:34 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:21, Andi Shyti wrote:
> __for_each_engine_class_instance(fd, e) doesn't need and doesn't
> use the fd argument. Remove it.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
>   lib/igt_gt.h     | 2 +-
>   tests/perf_pmu.c | 4 ++--
>   2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 54e95da98084..475c0b3c3cc6 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -114,7 +114,7 @@ void gem_require_engine(int gem_fd,
>   	igt_require(gem_has_engine(gem_fd, class, instance));
>   }
>   
> -#define __for_each_engine_class_instance(fd__, e__) \
> +#define __for_each_engine_class_instance(e__) \
>   	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
>   
>   #define for_each_engine_class_instance(fd__, e__) \
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 1a08f564b066..4f552bc2ae28 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -1693,7 +1693,7 @@ igt_main
>   	igt_subtest("invalid-init")
>   		invalid_init();
>   
> -	__for_each_engine_class_instance(fd, e) {
> +	__for_each_engine_class_instance(e) {
>   		const unsigned int pct[] = { 2, 50, 98 };
>   
>   		/**
> @@ -1897,7 +1897,7 @@ igt_main
>   			gem_quiescent_gpu(fd);
>   		}
>   
> -		__for_each_engine_class_instance(render_fd, e) {
> +		__for_each_engine_class_instance(e) {
>   			igt_subtest_group {
>   				igt_fixture {
>   					gem_require_engine(render_fd,
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
@ 2019-03-29 11:36   ` Tvrtko Ursulin
  2019-03-29 11:59     ` Andi Shyti
  0 siblings, 1 reply; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 11:36 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> With the new engine query method engines are reachable through
> an index and context they are combined with.
> 
> The 'gem_has_ring()' becomes 'gem_context_has_engine()' that
> requires the index that the engine is mapped within the driver.
> The function has been moved from lib/ioctl_wappers to
> lib/i915/gem_context where it is more appropriate.
> 
> The previous 'gem_has_ring()' function becomes a wrapper to the
> new 'gem_context_has_engine()'.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   lib/i915/gem_context.c | 28 ++++++++++++++++++++++++++++
>   lib/i915/gem_context.h |  2 ++
>   lib/ioctl_wrappers.c   | 19 -------------------
>   lib/ioctl_wrappers.h   |  3 ++-
>   4 files changed, 32 insertions(+), 20 deletions(-)
> 
> diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
> index 8b4d5b704650..732f66b4273e 100644
> --- a/lib/i915/gem_context.c
> +++ b/lib/i915/gem_context.c
> @@ -271,3 +271,31 @@ void gem_context_set_priority(int fd, uint32_t ctx_id, int prio)
>   {
>   	igt_assert_eq(__gem_context_set_priority(fd, ctx_id, prio), 0);
>   }
> +
> +bool gem_context_has_engine(int fd, uint64_t ctx, uint64_t engine)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct drm_i915_gem_exec_object2 exec;
> +
> +	/*
> +	 * 'engine' value can either store an execbuf engine selector
> +	 * or a context map index; for the latter case we do not expect
> +	 * to have any value at bit 13 and 14 (BSD1/2 selector),
> +	 * therefore, we assume that the following check is safe it wouldn't
> +	 * produce any result and we don't exepct anyway to have more than
> +	 * one engine mapped in 'unit64_t engine'.

typo in expect and uint.

I think here you meant that we don't expect more than (1 << 13 - 1) engines?

> +	 */
> +	if ((engine & ~(3<<13)) == I915_EXEC_BSD) {
> +		if (engine & (3 << 13) && !gem_has_bsd2(fd))
> +			return false;
> +	}
> +
> +	memset(&exec, 0, sizeof(exec));
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(&exec);
> +	execbuf.buffer_count = 1;
> +	execbuf.flags = engine;
> +	execbuf.rsvd1 = ctx;
> +
> +	return __gem_execbuf(fd, &execbuf) == -ENOENT;
> +}
> diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
> index aef68dda6b26..d4e8fec3acf0 100644
> --- a/lib/i915/gem_context.h
> +++ b/lib/i915/gem_context.h
> @@ -45,4 +45,6 @@ int __gem_context_get_param(int fd, struct drm_i915_gem_context_param *p);
>   int __gem_context_set_priority(int fd, uint32_t ctx, int prio);
>   void gem_context_set_priority(int fd, uint32_t ctx, int prio);
>   
> +bool gem_context_has_engine(int fd, uint64_t ctx, uint64_t engine);
> +
>   #endif /* GEM_CONTEXT_H */
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index a66eb4bc0f4f..3f8f0874bc4b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -1253,25 +1253,6 @@ void igt_require_gem(int fd)
>   	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
>   }
>   
> -bool gem_has_ring(int fd, unsigned ring)
> -{
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 exec;
> -
> -	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
> -	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
> -		if (ring & (3 << 13) && !gem_has_bsd2(fd))
> -			return false;
> -	}
> -
> -	memset(&exec, 0, sizeof(exec));
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(&exec);
> -	execbuf.buffer_count = 1;
> -	execbuf.flags = ring;
> -	return __gem_execbuf(fd, &execbuf) == -ENOENT;
> -}
> -
>   /**
>    * gem_require_ring:
>    * @fd: open i915 drm file descriptor
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index ad93daffcfd5..e712f1973142 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -142,11 +142,12 @@ bool gem_has_exec_fence(int fd);
>   
>   /* check functions which auto-skip tests by calling igt_skip() */
>   void gem_require_caching(int fd);
> -bool gem_has_ring(int fd, unsigned ring);
>   void gem_require_ring(int fd, unsigned ring);
>   bool gem_has_mocs_registers(int fd);
>   void gem_require_mocs_registers(int fd);
>   
> +#define gem_has_ring(f, r) gem_context_has_engine(f, 0, r)
> +
>   /* prime */
>   struct local_dma_buf_sync {
>   	uint64_t flags;
> 

With the comment tidied:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test Andi Shyti
@ 2019-03-29 11:39   ` Tvrtko Ursulin
  2019-03-29 12:06     ` Andi Shyti
  2019-03-29 23:36   ` Chris Wilson
  1 sibling, 1 reply; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 11:39 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> The "exec-engines-ctx" and "exec-physical-engines-ctx" are two
> demo subtest inserted in the gem_exec_basic
> test. The main goal is to reach the engines by using
> the new uapi interfacing with 'gem_topology_has_engine()'.
> 
> The two cases get the list of both virtual and physical and only
> physical engines and makes sure they actually exist.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   tests/i915/gem_exec_basic.c | 26 ++++++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
> 
> diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
> index dcb83864b1c1..ed3388952146 100644
> --- a/tests/i915/gem_exec_basic.c
> +++ b/tests/i915/gem_exec_basic.c
> @@ -135,6 +135,32 @@ igt_main
>   			gtt(fd, e->exec_id | e->flags);
>   	}
>   
> +	igt_subtest("exec-engines-ctx") {
> +		uint64_t ctx_id;
> +		struct intel_execution_engine2 *e2;
> +
> +		ctx_id = gem_context_create(fd);
> +
> +		for_each_context_engine(fd, ctx_id, e2)
> +			igt_assert(gem_context_has_engine(fd, ctx_id,
> +							  e2->flags));
> +
> +		gem_context_destroy(fd, ctx_id);
> +	}
> +
> +	igt_subtest("exec-physical-engines-ctx") {
> +		uint64_t ctx_id;
> +		struct intel_execution_engine2 *e2;
> +
> +		ctx_id = gem_context_create(fd);

In this one you don't want a context. It creates a mismatch between 
execbuf sent by gem_context_has_engine and a context which hasn't been 
configured to use engine index addressing.

Regards,

Tvrtko

> +
> +		__for_each_physical_engine(fd, e2)
> +			igt_assert(gem_context_has_engine(fd, ctx_id,
> +							  e2->flags));
> +
> +		gem_context_destroy(fd, ctx_id);
> +	}
> +
>   	igt_fixture {
>   		igt_stop_hang_detector();
>   		close(fd);
> 
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well
  2019-03-29 11:36   ` Tvrtko Ursulin
@ 2019-03-29 11:59     ` Andi Shyti
  0 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-29 11:59 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti

Hi Tvrtko,

> > +	/*
> > +	 * 'engine' value can either store an execbuf engine selector
> > +	 * or a context map index; for the latter case we do not expect
> > +	 * to have any value at bit 13 and 14 (BSD1/2 selector),
> > +	 * therefore, we assume that the following check is safe it wouldn't
> > +	 * produce any result and we don't exepct anyway to have more than
> > +	 * one engine mapped in 'unit64_t engine'.
> 
> typo in expect and uint.

thanks :)

> I think here you meant that we don't expect more than (1 << 13 - 1) engines?

Yes, indeed :)

> With the comment tidied:
> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Thanks a lot!

Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition
  2019-03-29 11:34   ` Tvrtko Ursulin
@ 2019-03-29 12:05     ` Andi Shyti
  0 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-29 12:05 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti

Hi Tvrtko,

> > +	nengines = param.size > sizeof(struct i915_context_param_engines) ?
> > +		   (param.size - sizeof(struct i915_context_param_engines)) /
> > +		   sizeof(engines.class_instance[0]) :
> > +		   0;
> > +
> > +	igt_assert_f(nengines < GEM_MAX_ENGINES, "unsupported engine count\n");
> 
> Should this be <= ?

yes

> > +struct intel_engine_data {
> > +	uint32_t nengines;
> > +	uint32_t n;
> > +	int error;
> > +	struct intel_execution_engine2 *current_engine;
> > +	struct intel_execution_engine2 *current_phys_engine;
> 
> This field seem only ever assigned, never otherwise used. Do you need it for
> something later?

I took the comment from Chris that wanted to have two separate
lists, but indeed this doen't look fully right (or maybe I didn't
fully get what he meant exactly)

> > +#define for_each_context_engine(fd__, ctx__, e__) \
> > +	for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
> > +	     ((e__) = intel_get_current_engine(&i__)); \
> > +	     intel_next_engine(&i__))
> > +
> 
> I would probably have the physical vs virtual logic in the "next" helper and
> just one intel_get_current_engine but it is not very relevant.

Sure! It's simpler.

> Looks mostly as expected. I trust you tested it works. :) With the assert
> fixed and unused struct member removed:
> 
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Thanks a lot for your reviews!

Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-29 11:39   ` Tvrtko Ursulin
@ 2019-03-29 12:06     ` Andi Shyti
  2019-03-29 12:41       ` Tvrtko Ursulin
  0 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-29 12:06 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti

> > +	igt_subtest("exec-physical-engines-ctx") {
> > +		uint64_t ctx_id;
> > +		struct intel_execution_engine2 *e2;
> > +
> > +		ctx_id = gem_context_create(fd);
> 
> In this one you don't want a context. It creates a mismatch between execbuf
> sent by gem_context_has_engine and a context which hasn't been configured to
> use engine index addressing.

Yes, I forgot to remove it... BTW, is this test needed at all? I
added it just as a proposal.

Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class Andi Shyti
@ 2019-03-29 12:22   ` Tvrtko Ursulin
  2019-03-29 12:43     ` Andi Shyti
  0 siblings, 1 reply; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 12:22 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> Engines referred by class and instance are getting more populare,

Italian typo. ;)

> gem_engine_can_store_dword() should handle the situation.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/igt_gt.c | 46 +++++++++++++++++++++++++++++++++++++++-------
>   lib/igt_gt.h |  6 ++++--
>   2 files changed, 43 insertions(+), 9 deletions(-)
> 
> diff --git a/lib/igt_gt.c b/lib/igt_gt.c
> index 5999524326d0..630aa421ffb3 100644
> --- a/lib/igt_gt.c
> +++ b/lib/igt_gt.c
> @@ -41,6 +41,7 @@
>   #include "intel_reg.h"
>   #include "intel_chipset.h"
>   #include "igt_dummyload.h"
> +#include "i915/gem_engine_topology.h"
>   
>   /**
>    * SECTION:igt_gt
> @@ -556,27 +557,58 @@ const struct intel_execution_engine intel_execution_engines[] = {
>   	{ NULL, 0, 0 }
>   };
>   
> -bool gem_can_store_dword(int fd, unsigned int engine)
> +static bool __gem_can_store_dword(const int gen, const struct intel_device_info *info)
>   {
> -	uint16_t devid = intel_get_drm_devid(fd);
> -	const struct intel_device_info *info = intel_get_device_info(devid);
> -	const int gen = ffs(info->gen);
> -
>   	if (gen <= 2) /* requires physical addresses */
>   		return false;
>   
>   	if (gen == 3 && (info->is_grantsdale || info->is_alviso))
>   		return false; /* only supports physical addresses */
>   
> +	if (info->is_broadwater)
> +		return false; /* Not sure yet... */
> +
> +	return true;
> +}
> +
> +bool gem_can_store_dword(int fd, uint64_t engine)

Yeah eb->flags is u64, although we don't need it all here. Okay, I don't mind.

> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +	const struct intel_device_info *info = intel_get_device_info(devid);
> +	const int gen = ffs(info->gen);
> +
> +	if (!__gem_can_store_dword(gen, info))
> +		return false;
> +
>   	if (gen == 6 && ((engine & 0x3f) == I915_EXEC_BSD))
>   		return false; /* kills the machine! */
>   
> -	if (info->is_broadwater)
> -		return false; /* Not sure yet... */
> +	return true;
> +}
> +
> +bool gem_class_can_store_dword(int fd, uint64_t class)

But for class we definitely do not need 64 bits. u16 or unsigned int.

> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +	const struct intel_device_info *info = intel_get_device_info(devid);
> +	const int gen = ffs(info->gen);
> +
> +	if (!__gem_can_store_dword(gen, info))
> +		return false;
> +
> +	if (gen == 6 && class == I915_ENGINE_CLASS_VIDEO)
> +		return false;
>   
>   	return true;
>   }
>   
> +bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e)
> +{
> +	if (!gem_has_engine_topology(fd))
> +		return gem_can_store_dword(fd, e->flags);
> +
> +	return gem_class_can_store_dword(fd, e->class);
> +}

Couldn't you always use class?

It could be refactored with a eb_flags_to_class helper if you would like this solution. Then it wouldn't need to call gem_has_engine_topology I think.

bool gem_class_can_store_dword(int fd, uint64_t class)
{
	uint16_t devid = intel_get_drm_devid(fd);
	const struct intel_device_info *info = intel_get_device_info(devid);
	const int gen = ffs(info->gen);

	if (!__gem_can_store_dword(gen, info))
		return false;

	if (gen == 6 && class == I915_ENGINE_CLASS_VIDEO)
		return false;
 
 	return true;
 }

bool gem_can_store_dword(int fd, uint64_t engine)
{
	u16 class = eb_engine_to_class(engine);

	return gem_class_can_store_dword(class);
}

bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e)
{
	return gem_class_can_store_dword(fd, e->class);
}

Unless I missed something fundamental..

Let me see the next patches first..

Regards,

Tvrtko

> +
>   const struct intel_execution_engine2 intel_execution_engines2[] = {
>   	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
>   	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index 52b2f1ea95a5..f3f07e895733 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -89,8 +89,6 @@ extern const struct intel_execution_engine {
>   bool gem_ring_is_physical_engine(int fd, unsigned int ring);
>   bool gem_ring_has_physical_engine(int fd, unsigned int ring);
>   
> -bool gem_can_store_dword(int fd, unsigned int engine);
> -
>   extern const struct intel_execution_engine2 {
>   	const char *name;
>   	int class;
> @@ -99,6 +97,10 @@ extern const struct intel_execution_engine2 {
>   	bool is_virtual;
>   } intel_execution_engines2[];
>   
> +bool gem_can_store_dword(int fd, uint64_t);
> +bool gem_class_can_store_dword(int fd, uint64_t class);
> +bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e);
> +
>   unsigned int
>   gem_class_instance_to_eb_flags(int gem_fd,
>   			       enum drm_i915_gem_engine_class class,
> 
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine()
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine() Andi Shyti
@ 2019-03-29 12:33   ` Tvrtko Ursulin
  0 siblings, 0 replies; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 12:33 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> With the new getparam/setparam api, engines are mapped to
> context. Use for_each_context_engine() to loop through existing
> engines.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   lib/igt_dummyload.c | 21 ++++++++-------------
>   1 file changed, 8 insertions(+), 13 deletions(-)
> 
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 47f6b92b424b..4e94ccc448ba 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -39,6 +39,7 @@
>   #include "ioctl_wrappers.h"
>   #include "sw_sync.h"
>   #include "igt_vgem.h"
> +#include "i915/gem_engine_topology.h"
>   #include "i915/gem_mman.h"
>   
>   /**
> @@ -86,7 +87,7 @@ emit_recursive_batch(igt_spin_t *spin,
>   	struct drm_i915_gem_relocation_entry relocs[2], *r;
>   	struct drm_i915_gem_execbuffer2 *execbuf;
>   	struct drm_i915_gem_exec_object2 *obj;
> -	unsigned int engines[16];
> +	unsigned int flags[16];

Bump it to I915_EXEC_RING_MASK + 1 while at it.

>   	unsigned int nengine;
>   	int fence_fd = -1;
>   	uint32_t *batch, *batch_start;
> @@ -94,17 +95,17 @@ emit_recursive_batch(igt_spin_t *spin,
>   
>   	nengine = 0;
>   	if (opts->engine == ALL_ENGINES) {
> -		unsigned int engine;
> +		struct intel_execution_engine2 *engine;
>   
> -		for_each_physical_engine(fd, engine) {
> +		for_each_context_engine(fd, opts->ctx, engine) {
>   			if (opts->flags & IGT_SPIN_POLL_RUN &&
> -			    !gem_can_store_dword(fd, engine))
> +			    !gem_engine_can_store_dword(fd, engine))
>   				continue;
>   
> -			engines[nengine++] = engine;
> +			flags[nengine++] = engine->flags;
>   		}
>   	} else {
> -		engines[nengine++] = opts->engine;
> +		flags[nengine++] = opts->engine;

Single engine case needs the can_store_dword test as well.

You have to ioctl get_param.engines to figure out how to get engine 
class. And then just call either gem_class_can_store_dword or 
gem_can_store_dword depending on whether there is engine map on the 
context or not.

If there is no engine map also do gem_require_ring here (it was lost 
from the hunk below). In case of engine map I think you don't need to check.

Regards,

Tvrtko

>   	}
>   	igt_require(nengine);
>   
> @@ -234,7 +235,7 @@ emit_recursive_batch(igt_spin_t *spin,
>   
>   	for (i = 0; i < nengine; i++) {
>   		execbuf->flags &= ~ENGINE_MASK;
> -		execbuf->flags |= engines[i];
> +		execbuf->flags |= flags[i];
>   
>   		gem_execbuf_wr(fd, execbuf);
>   
> @@ -308,12 +309,6 @@ igt_spin_batch_factory(int fd, const struct igt_spin_factory *opts)
>   
>   	igt_require_gem(fd);
>   
> -	if (opts->engine != ALL_ENGINES) {
> -		gem_require_ring(fd, opts->engine);
> -		if (opts->flags & IGT_SPIN_POLL_RUN)
> -			igt_require(gem_can_store_dword(fd, opts->engine));
> -	}
> -
>   	spin = spin_batch_create(fd, opts);
>   
>   	igt_assert(gem_bo_busy(fd, spin->handle));
> 
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library Andi Shyti
@ 2019-03-29 12:40   ` Tvrtko Ursulin
  2019-03-29 12:47     ` Andi Shyti
  0 siblings, 1 reply; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 12:40 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti


On 28/03/2019 19:22, Andi Shyti wrote:
> Replace the legacy for_each_engine* defines with the ones
> implemented in the gem_engine_topology library.
> 
> Use whenever possible gem_engine_can_store_dword() that checks
> class instead of flags.
> 
> Now the __for_each_engine_class_instance and
> for_each_engine_class_instance are unused, remove them.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
>   lib/igt_gt.h     |  7 -------
>   tests/perf_pmu.c | 37 +++++++++++++++++++++++--------------
>   2 files changed, 23 insertions(+), 21 deletions(-)
> 
> diff --git a/lib/igt_gt.h b/lib/igt_gt.h
> index f3f07e895733..cd6d7e4f8967 100644
> --- a/lib/igt_gt.h
> +++ b/lib/igt_gt.h
> @@ -118,11 +118,4 @@ void gem_require_engine(int gem_fd,
>   	igt_require(gem_has_engine(gem_fd, class, instance));
>   }
>   
> -#define __for_each_engine_class_instance(e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
> -
> -#define for_each_engine_class_instance(fd__, e__) \
> -	for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
> -		for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
> -
>   #endif /* IGT_GT_H */
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 4f552bc2ae28..1487688781ab 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -170,14 +170,14 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
>   #define FLAG_LONG (16)
>   #define FLAG_HANG (32)
>   
> -static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
> +static igt_spin_t * __spin_poll(int fd, uint32_t ctx, const struct intel_execution_engine2 *e)
>   {
>   	struct igt_spin_factory opts = {
>   		.ctx = ctx,
> -		.engine = flags,
> +		.engine = e->flags,
>   	};
>   
> -	if (gem_can_store_dword(fd, flags))
> +	if (gem_engine_can_store_dword(fd, e))
>   		opts.flags |= IGT_SPIN_POLL_RUN;
>   
>   	return __igt_spin_batch_factory(fd, &opts);
> @@ -211,7 +211,16 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>   
>   static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)

__spin_sync should also take engine instead of flags, like __spin_poll.

>   {
> -	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
> +	struct igt_spin_factory opts = {
> +		.ctx = ctx,
> +		.engine = flags,
> +	};
> +	igt_spin_t *spin;
> +
> +	if (gem_can_store_dword(fd, flags))
> +		opts.flags |= IGT_SPIN_POLL_RUN;
> +
> +	spin = __igt_spin_batch_factory(fd, &opts);

And then you don't need this hunk at all, making the whole thing 
completely ready for more engines.

And e2ring will end up with no callers so can be removed.

>   
>   	__spin_wait(fd, spin);
>   
> @@ -434,8 +443,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   
>   	i = 0;
>   	fd[0] = -1;
> -	for_each_engine_class_instance(gem_fd, e_) {
> -		if (e == e_)
> +	__for_each_physical_engine(gem_fd, e_) {
> +		if (e->class == e_->class && e->instance == e_->instance)
>   			busy_idx = i;
>   
>   		fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> @@ -497,13 +506,13 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	unsigned int idle_idx, i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e_) {
> -		if (e == e_)
> +	__for_each_physical_engine(gem_fd, e_) {
> +		if (e->class == e_->class && e->instance == e_->instance)
>   			idle_idx = i;
>   		else if (spin)
>   			__submit_spin_batch(gem_fd, spin, e_, 64);
>   		else
> -			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e_));
> +			spin = __spin_poll(gem_fd, 0, e);
>   
>   		val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
>   	}
> @@ -554,11 +563,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>   	unsigned int i;
>   
>   	i = 0;
> -	for_each_engine_class_instance(gem_fd, e) {
> +	__for_each_physical_engine(gem_fd, e) {
>   		if (spin)
>   			__submit_spin_batch(gem_fd, spin, e, 64);
>   		else
> -			spin = __spin_poll(gem_fd, 0, e2ring(gem_fd, e));
> +			spin = __spin_poll(gem_fd, 0, e);
>   
>   		val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
>   	}
> @@ -1683,7 +1692,7 @@ igt_main
>   		igt_require_gem(fd);
>   		igt_require(i915_type_id() > 0);
>   
> -		for_each_engine_class_instance(fd, e)
> +		__for_each_physical_engine(fd, e)
>   			num_engines++;
>   	}
>   
> @@ -1693,7 +1702,7 @@ igt_main
>   	igt_subtest("invalid-init")
>   		invalid_init();
>   
> -	__for_each_engine_class_instance(e) {
> +	__for_each_static_engine(e) {
>   		const unsigned int pct[] = { 2, 50, 98 };
>   
>   		/**
> @@ -1897,7 +1906,7 @@ igt_main
>   			gem_quiescent_gpu(fd);
>   		}
>   
> -		__for_each_engine_class_instance(e) {
> +		__for_each_static_engine(e) {
>   			igt_subtest_group {
>   				igt_fixture {
>   					gem_require_engine(render_fd,
> 

Yep, modulo __spin_sync change, this is what I had in mind.

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-29 12:06     ` Andi Shyti
@ 2019-03-29 12:41       ` Tvrtko Ursulin
  0 siblings, 0 replies; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 12:41 UTC (permalink / raw)
  To: Andi Shyti; +Cc: IGT dev, Andi Shyti


On 29/03/2019 12:06, Andi Shyti wrote:
>>> +	igt_subtest("exec-physical-engines-ctx") {
>>> +		uint64_t ctx_id;
>>> +		struct intel_execution_engine2 *e2;
>>> +
>>> +		ctx_id = gem_context_create(fd);
>>
>> In this one you don't want a context. It creates a mismatch between execbuf
>> sent by gem_context_has_engine and a context which hasn't been configured to
>> use engine index addressing.
> 
> Yes, I forgot to remove it... BTW, is this test needed at all? I
> added it just as a proposal.

In my opinion you can drop this patch since you use both new iterators 
later in the series.

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class
  2019-03-29 12:22   ` Tvrtko Ursulin
@ 2019-03-29 12:43     ` Andi Shyti
  0 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-29 12:43 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti

> > +bool gem_can_store_dword(int fd, uint64_t engine)
> 
> Yeah eb->flags is u64, although we don't need it all here. Okay, I don't mind.

here flags (u64), class (u16) and engine (u8 is enough) are
somehow confusingly mixed... need to check better the type range
I need.

> > +bool gem_engine_can_store_dword(int fd, const struct intel_execution_engine2 *e)
> > +{
> > +	if (!gem_has_engine_topology(fd))
> > +		return gem_can_store_dword(fd, e->flags);
> > +
> > +	return gem_class_can_store_dword(fd, e->class);
> > +}
> 
> Couldn't you always use class?

How do you distinguish between eb flags as engine and context
mapping, then?

In theory this function should not work in all the cases, because
it assumes that e->flags has always a meningful value.

While if this is called during a __for_each_static_engine (which
should never be used in my dream world), flags is always '0'. In
the next patches I tried to be careful to this case (_tried_, eh?  :) )

(BTW, this is a proposal, because the legacy usage of
intel_execution_engines2 list is used a lot)

> bool gem_can_store_dword(int fd, uint64_t engine)
> {
> 	u16 class = eb_engine_to_class(engine);

Yes, I need this extra step, assuming that engine is always an
eb_flag.

In the last patchset you recommended the following:

  // ioctl and stuff.. bummer... :(
  ret = gem_context_get_engine_map_class_instance(fd, opts->ctx, opts->engine,
  &class, &instance);     
  if (ret) // error = no map = means opts->engine is eb flags
          check legacy gem_can_store_dword
  else
          check using new gem_engine_can_store_dword(class, instance)

which I did here (still it works only out from
__for_each_static_engine).

Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library
  2019-03-29 12:40   ` Tvrtko Ursulin
@ 2019-03-29 12:47     ` Andi Shyti
  2019-03-29 12:56       ` Tvrtko Ursulin
  0 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-29 12:47 UTC (permalink / raw)
  To: Tvrtko Ursulin; +Cc: IGT dev, Andi Shyti

> > -static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
> > +static igt_spin_t * __spin_poll(int fd, uint32_t ctx, const struct intel_execution_engine2 *e)
> >   {
> >   	struct igt_spin_factory opts = {
> >   		.ctx = ctx,
> > -		.engine = flags,
> > +		.engine = e->flags,
> >   	};
> > -	if (gem_can_store_dword(fd, flags))
> > +	if (gem_engine_can_store_dword(fd, e))
> >   		opts.flags |= IGT_SPIN_POLL_RUN;
> >   	return __igt_spin_batch_factory(fd, &opts);
> > @@ -211,7 +211,16 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> >   static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
> 
> __spin_sync should also take engine instead of flags, like __spin_poll.

But if __spin_sync is called inside __for_each_physical_engine
(which in this code never happens), engine doesn't have any flags
set. right?

> >   {
> > -	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
> > +	struct igt_spin_factory opts = {
> > +		.ctx = ctx,
> > +		.engine = flags,
> > +	};
> > +	igt_spin_t *spin;
> > +
> > +	if (gem_can_store_dword(fd, flags))
> > +		opts.flags |= IGT_SPIN_POLL_RUN;
> > +
> > +	spin = __igt_spin_batch_factory(fd, &opts);
> 
> And then you don't need this hunk at all, making the whole thing completely
> ready for more engines.
> 
> And e2ring will end up with no callers so can be removed.

Same reason as above, which is this one:

> > -		__for_each_engine_class_instance(e) {
> > +		__for_each_static_engine(e) {
> >   			igt_subtest_group {
> >   				igt_fixture {
> >   					gem_require_engine(render_fd,
> > 
> 
> Yep, modulo __spin_sync change, this is what I had in mind.

at this point I don't have any flag set, any check whether the
engine really exists, no context mapping (still flags) :/

Am I missing it?

Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library
  2019-03-29 12:47     ` Andi Shyti
@ 2019-03-29 12:56       ` Tvrtko Ursulin
  0 siblings, 0 replies; 29+ messages in thread
From: Tvrtko Ursulin @ 2019-03-29 12:56 UTC (permalink / raw)
  To: Andi Shyti; +Cc: IGT dev, Andi Shyti


On 29/03/2019 12:47, Andi Shyti wrote:
>>> -static igt_spin_t * __spin_poll(int fd, uint32_t ctx, unsigned long flags)
>>> +static igt_spin_t * __spin_poll(int fd, uint32_t ctx, const struct intel_execution_engine2 *e)
>>>    {
>>>    	struct igt_spin_factory opts = {
>>>    		.ctx = ctx,
>>> -		.engine = flags,
>>> +		.engine = e->flags,
>>>    	};
>>> -	if (gem_can_store_dword(fd, flags))
>>> +	if (gem_engine_can_store_dword(fd, e))
>>>    		opts.flags |= IGT_SPIN_POLL_RUN;
>>>    	return __igt_spin_batch_factory(fd, &opts);
>>> @@ -211,7 +211,16 @@ static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>>>    static igt_spin_t * __spin_sync(int fd, uint32_t ctx, unsigned long flags)
>>
>> __spin_sync should also take engine instead of flags, like __spin_poll.
> 
> But if __spin_sync is called inside __for_each_physical_engine
> (which in this code never happens), engine doesn't have any flags
> set. right?
> 
>>>    {
>>> -	igt_spin_t *spin = __spin_poll(fd, ctx, flags);
>>> +	struct igt_spin_factory opts = {
>>> +		.ctx = ctx,
>>> +		.engine = flags,
>>> +	};
>>> +	igt_spin_t *spin;
>>> +
>>> +	if (gem_can_store_dword(fd, flags))
>>> +		opts.flags |= IGT_SPIN_POLL_RUN;
>>> +
>>> +	spin = __igt_spin_batch_factory(fd, &opts);
>>
>> And then you don't need this hunk at all, making the whole thing completely
>> ready for more engines.
>>
>> And e2ring will end up with no callers so can be removed.
> 
> Same reason as above, which is this one:
> 
>>> -		__for_each_engine_class_instance(e) {
>>> +		__for_each_static_engine(e) {
>>>    			igt_subtest_group {
>>>    				igt_fixture {
>>>    					gem_require_engine(render_fd,
>>>
>>
>> Yep, modulo __spin_sync change, this is what I had in mind.
> 
> at this point I don't have any flag set, any check whether the
> engine really exists, no context mapping (still flags) :/
> 
> Am I missing it?

No I missed it. How about this then...

We make __for_each_physical_engine call igt_only_list_subtests during 
setup and decide whether or not it is allowed to open the device.

Therefore in subtest enumeration it doesn't, uses the static list, and 
we don't need e->flags to be correct, just e->name.

In normal test runs it is allowed to do everything and engines are 
always properly initialized?

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-28 19:22 ` [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test Andi Shyti
  2019-03-29 11:39   ` Tvrtko Ursulin
@ 2019-03-29 23:36   ` Chris Wilson
  2019-03-31 17:36     ` Andi Shyti
  1 sibling, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-03-29 23:36 UTC (permalink / raw)
  To: Andi Shyti, IGT dev; +Cc: Andi Shyti

Quoting Andi Shyti (2019-03-28 19:22:03)
> The "exec-engines-ctx" and "exec-physical-engines-ctx" are two
> demo subtest inserted in the gem_exec_basic
> test. The main goal is to reach the engines by using
> the new uapi interfacing with 'gem_topology_has_engine()'.
> 
> The two cases get the list of both virtual and physical and only
> physical engines and makes sure they actually exist.
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>  tests/i915/gem_exec_basic.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
> index dcb83864b1c1..ed3388952146 100644
> --- a/tests/i915/gem_exec_basic.c
> +++ b/tests/i915/gem_exec_basic.c
> @@ -135,6 +135,32 @@ igt_main
>                         gtt(fd, e->exec_id | e->flags);
>         }
>  
> +       igt_subtest("exec-engines-ctx") {
> +               uint64_t ctx_id;
> +               struct intel_execution_engine2 *e2;
> +
> +               ctx_id = gem_context_create(fd);
> +
> +               for_each_context_engine(fd, ctx_id, e2)
> +                       igt_assert(gem_context_has_engine(fd, ctx_id,
> +                                                         e2->flags));
> +
> +               gem_context_destroy(fd, ctx_id);
> +       }

Starting subtest: exec-engines-ctx
(gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
(gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
Stack trace:
  #0 ../lib/igt_core.c:1474 __igt_fail_assert()
  #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
  #2 ../tests/i915/gem_exec_basic.c:117 main()
  #3 ../csu/libc-start.c:342 __libc_start_main()
  #4 [_start+0x2a]
Subtest exec-engines-ctx failed.
**** DEBUG ****
(gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
(gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
(gem_exec_basic:17617) igt_core-INFO: Stack trace:
(gem_exec_basic:17617) igt_core-INFO:   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
(gem_exec_basic:17617) igt_core-INFO:   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
(gem_exec_basic:17617) igt_core-INFO:   #2 ../tests/i915/gem_exec_basic.c:117 main()
(gem_exec_basic:17617) igt_core-INFO:   #3 ../csu/libc-start.c:342 __libc_start_main()
(gem_exec_basic:17617) igt_core-INFO:   #4 [_start+0x2a]
****  END  ****

I'd say that is worth a little polishing on what the error might have
been.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-29 23:36   ` Chris Wilson
@ 2019-03-31 17:36     ` Andi Shyti
  2019-03-31 17:42       ` Chris Wilson
  0 siblings, 1 reply; 29+ messages in thread
From: Andi Shyti @ 2019-03-31 17:36 UTC (permalink / raw)
  To: Chris Wilson; +Cc: IGT dev, Andi Shyti

> > +       igt_subtest("exec-engines-ctx") {
> > +               uint64_t ctx_id;
> > +               struct intel_execution_engine2 *e2;
> > +
> > +               ctx_id = gem_context_create(fd);
> > +
> > +               for_each_context_engine(fd, ctx_id, e2)
> > +                       igt_assert(gem_context_has_engine(fd, ctx_id,
> > +                                                         e2->flags));
> > +
> > +               gem_context_destroy(fd, ctx_id);
> > +       }
> 
> Starting subtest: exec-engines-ctx
> (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> Stack trace:
>   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
>   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
>   #2 ../tests/i915/gem_exec_basic.c:117 main()
>   #3 ../csu/libc-start.c:342 __libc_start_main()
>   #4 [_start+0x2a]
> Subtest exec-engines-ctx failed.
> **** DEBUG ****
> (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> (gem_exec_basic:17617) igt_core-INFO: Stack trace:
> (gem_exec_basic:17617) igt_core-INFO:   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
> (gem_exec_basic:17617) igt_core-INFO:   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
> (gem_exec_basic:17617) igt_core-INFO:   #2 ../tests/i915/gem_exec_basic.c:117 main()
> (gem_exec_basic:17617) igt_core-INFO:   #3 ../csu/libc-start.c:342 __libc_start_main()
> (gem_exec_basic:17617) igt_core-INFO:   #4 [_start+0x2a]
> ****  END  ****
> 
> I'd say that is worth a little polishing on what the error might have
> been.

mmmhhh... how did you get it? I tested it on drm-tip kernel
(different versions), mainline kernel (different versions) and
Tvrtko's kernel and didn't get any failure.

All the patches were applied on latest igt until this one (to
make sure I didn't forget any dependency with future patches).

I executed it in loop several times and I have other tests on
top, I might have forgotten something.

Thanks for testing it,
Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-31 17:36     ` Andi Shyti
@ 2019-03-31 17:42       ` Chris Wilson
  2019-03-31 20:19         ` Andi Shyti
  0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-03-31 17:42 UTC (permalink / raw)
  To: Andi Shyti; +Cc: IGT dev, Andi Shyti

Quoting Andi Shyti (2019-03-31 18:36:59)
> > > +       igt_subtest("exec-engines-ctx") {
> > > +               uint64_t ctx_id;
> > > +               struct intel_execution_engine2 *e2;
> > > +
> > > +               ctx_id = gem_context_create(fd);
> > > +
> > > +               for_each_context_engine(fd, ctx_id, e2)
> > > +                       igt_assert(gem_context_has_engine(fd, ctx_id,
> > > +                                                         e2->flags));
> > > +
> > > +               gem_context_destroy(fd, ctx_id);
> > > +       }
> > 
> > Starting subtest: exec-engines-ctx
> > (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> > (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> > Stack trace:
> >   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
> >   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
> >   #2 ../tests/i915/gem_exec_basic.c:117 main()
> >   #3 ../csu/libc-start.c:342 __libc_start_main()
> >   #4 [_start+0x2a]
> > Subtest exec-engines-ctx failed.
> > **** DEBUG ****
> > (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> > (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> > (gem_exec_basic:17617) igt_core-INFO: Stack trace:
> > (gem_exec_basic:17617) igt_core-INFO:   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
> > (gem_exec_basic:17617) igt_core-INFO:   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
> > (gem_exec_basic:17617) igt_core-INFO:   #2 ../tests/i915/gem_exec_basic.c:117 main()
> > (gem_exec_basic:17617) igt_core-INFO:   #3 ../csu/libc-start.c:342 __libc_start_main()
> > (gem_exec_basic:17617) igt_core-INFO:   #4 [_start+0x2a]
> > ****  END  ****
> > 
> > I'd say that is worth a little polishing on what the error might have
> > been.
> 
> mmmhhh... how did you get it? I tested it on drm-tip kernel
> (different versions), mainline kernel (different versions) and
> Tvrtko's kernel and didn't get any failure.

I'm testing on the patches posted for upstream. The point is not that it
failed, but that the failure message doesn't give a clue: e2->flags and
e2->name would definitely be helpful. igt_debug of the query results may
help, but be judicious and avoid spammy debug.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
* Re: [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test
  2019-03-31 17:42       ` Chris Wilson
@ 2019-03-31 20:19         ` Andi Shyti
  0 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2019-03-31 20:19 UTC (permalink / raw)
  To: Chris Wilson; +Cc: IGT dev, Andi Shyti

> > > > +       igt_subtest("exec-engines-ctx") {
> > > > +               uint64_t ctx_id;
> > > > +               struct intel_execution_engine2 *e2;
> > > > +
> > > > +               ctx_id = gem_context_create(fd);
> > > > +
> > > > +               for_each_context_engine(fd, ctx_id, e2)
> > > > +                       igt_assert(gem_context_has_engine(fd, ctx_id,
> > > > +                                                         e2->flags));
> > > > +
> > > > +               gem_context_destroy(fd, ctx_id);
> > > > +       }
> > > 
> > > Starting subtest: exec-engines-ctx
> > > (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> > > (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> > > Stack trace:
> > >   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
> > >   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
> > >   #2 ../tests/i915/gem_exec_basic.c:117 main()
> > >   #3 ../csu/libc-start.c:342 __libc_start_main()
> > >   #4 [_start+0x2a]
> > > Subtest exec-engines-ctx failed.
> > > **** DEBUG ****
> > > (gem_exec_basic:17617) CRITICAL: Test assertion failure function __real_main117, file ../tests/i915/gem_exec_basic.c:146:
> > > (gem_exec_basic:17617) CRITICAL: Failed assertion: gem_context_has_engine(fd, ctx_id, e2->flags)
> > > (gem_exec_basic:17617) igt_core-INFO: Stack trace:
> > > (gem_exec_basic:17617) igt_core-INFO:   #0 ../lib/igt_core.c:1474 __igt_fail_assert()
> > > (gem_exec_basic:17617) igt_core-INFO:   #1 ../tests/i915/gem_exec_basic.c:144 __real_main117()
> > > (gem_exec_basic:17617) igt_core-INFO:   #2 ../tests/i915/gem_exec_basic.c:117 main()
> > > (gem_exec_basic:17617) igt_core-INFO:   #3 ../csu/libc-start.c:342 __libc_start_main()
> > > (gem_exec_basic:17617) igt_core-INFO:   #4 [_start+0x2a]
> > > ****  END  ****
> > > 
> > > I'd say that is worth a little polishing on what the error might have
> > > been.
> > 
> > mmmhhh... how did you get it? I tested it on drm-tip kernel
> > (different versions), mainline kernel (different versions) and
> > Tvrtko's kernel and didn't get any failure.
> 
> I'm testing on the patches posted for upstream. The point is not that it
> failed, but that the failure message doesn't give a clue: e2->flags and
> e2->name would definitely be helpful. igt_debug of the query results may
> help, but be judicious and avoid spammy debug.

Ah... OK, I see your point, you're right. Indeed, I could
understand nothing from the log :)

Thanks,
Andi
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

^ permalink raw reply	[flat|nested] 29+ messages in thread
end of thread, other threads:[~2019-03-31 22:46 UTC | newest]

Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-28 19:21 [igt-dev] [RFC v16 0/8] new engine discovery interface Andi Shyti
2019-03-28 19:21 ` [igt-dev] [PATCH v16 1/8] lib/igt_gt: remove unnecessary argument Andi Shyti
2019-03-29 11:34   ` Tvrtko Ursulin
2019-03-28 19:22 ` [igt-dev] [PATCH v16 2/8] lib: ioctl_wrappers: reach engines by index as well Andi Shyti
2019-03-29 11:36   ` Tvrtko Ursulin
2019-03-29 11:59     ` Andi Shyti
2019-03-28 19:22 ` [igt-dev] [PATCH v16 3/8] include/drm-uapi: import i915_drm.h header file Andi Shyti
2019-03-28 19:22 ` [igt-dev] [PATCH v16 4/8] lib/i915: add gem_engine_topology library and for_each loop definition Andi Shyti
2019-03-29 11:34   ` Tvrtko Ursulin
2019-03-29 12:05     ` Andi Shyti
2019-03-28 19:22 ` [igt-dev] [PATCH v16 5/8] tests: gem_exec_basic: add engine discovery test Andi Shyti
2019-03-29 11:39   ` Tvrtko Ursulin
2019-03-29 12:06     ` Andi Shyti
2019-03-29 12:41       ` Tvrtko Ursulin
2019-03-29 23:36   ` Chris Wilson
2019-03-31 17:36     ` Andi Shyti
2019-03-31 17:42       ` Chris Wilson
2019-03-31 20:19         ` Andi Shyti
2019-03-28 19:22 ` [igt-dev] [PATCH v16 6/8] lib: igt_gt: make gem_engine_can_store_dword() check engine class Andi Shyti
2019-03-29 12:22   ` Tvrtko Ursulin
2019-03-29 12:43     ` Andi Shyti
2019-03-28 19:22 ` [igt-dev] [PATCH v16 7/8] lib: igt_dummyload: use for_each_context_engine() Andi Shyti
2019-03-29 12:33   ` Tvrtko Ursulin
2019-03-28 19:22 ` [igt-dev] [PATCH v16 8/8] test: perf_pmu: use the gem_engine_topology library Andi Shyti
2019-03-29 12:40   ` Tvrtko Ursulin
2019-03-29 12:47     ` Andi Shyti
2019-03-29 12:56       ` Tvrtko Ursulin
2019-03-28 20:15 ` [igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface Patchwork
2019-03-29  7:40 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.