* ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts
2019-03-29 12:49 [PATCH 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
@ 2019-03-29 12:39 ` Patchwork
2019-03-29 12:49 ` [PATCH 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-29 12:39 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts
URL : https://patchwork.freedesktop.org/series/58734/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecab4c425422 drm/i915: Fix GCMAX color register programming
ca881c02da68 drm/i915: Program EXT2 GC MAX registers
-:21: WARNING:LONG_LINE: line over 100 characters
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:10147:
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
total: 0 errors, 1 warnings, 0 checks, 47 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/2] Fixed GC MAX register programming for gamma luts
@ 2019-03-29 12:49 Uma Shankar
2019-03-29 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Uma Shankar @ 2019-03-29 12:49 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Register offsets used to program GC max were not correct. This series
fixes the same, also limits the values to accurately clamp at 1.0.
Also added support to program EXT2 GC Max needed for values from 3.0
to 7.0. Limiting it again to 1.0 due to ABI limitations.
Uma Shankar (2):
drm/i915: Fix GCMAX color register programming
drm/i915: Program EXT2 GC MAX registers
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 50 +++++++++++++++++++++++++++++---------
2 files changed, 40 insertions(+), 11 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] drm/i915: Fix GCMAX color register programming
2019-03-29 12:49 [PATCH 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2019-03-29 12:49 ` Uma Shankar
2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 12:49 ` [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
2019-03-29 13:07 ` ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Uma Shankar @ 2019-03-29 12:49 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index ff910ed..dd179a8 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_DATA(pipe), word);
}
- /* Program the max register to clamp values > 1.0. */
- i = lut_size - 1;
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
- drm_color_lut_extract(lut[i].red, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
- drm_color_lut_extract(lut[i].green, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
- drm_color_lut_extract(lut[i].blue, 16));
+ /*
+ * Program the max register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 1.0 to 3.0
+ */
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
(v << 20) | (v << 10) | v);
}
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
}
/*
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
2019-03-29 12:49 [PATCH 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-03-29 12:49 ` [PATCH 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
@ 2019-03-29 12:49 ` Uma Shankar
2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 13:07 ` ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Uma Shankar @ 2019-03-29 12:49 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379..341f03e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10144,6 +10144,7 @@ enum skl_power_gate {
#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index dd179a8..84aa5e7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
+
+ /*
+ * Program the gc max 2 register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 3.0 to 7.0
+ */
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ (1 << 16) - 1);
+ }
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -537,6 +551,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
+
+ /*
+ * Program the gc max 2 register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 3.0 to 7.0
+ */
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ (1 << 16) - 1);
+ }
}
/*
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts
2019-03-29 12:49 [PATCH 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
` (2 preceding siblings ...)
2019-03-29 12:49 ` [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
@ 2019-03-29 13:07 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-29 13:07 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12628
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58734/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12628 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_basic@semaphore:
- fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +28
* igt@gem_exec_store@basic-bsd1:
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: PASS -> DMESG-WARN [fdo#105128] / [fdo#107139]
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: PASS -> INCOMPLETE [fdo#108569]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602]
* igt@kms_chamelium@vga-edid-read:
- fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: DMESG-WARN [fdo#103841] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (46 -> 42)
------------------------------
Additional (2): fi-hsw-4770r fi-kbl-r
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5837 -> Patchwork_12628
CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12628: ca881c02da6850d30d460ac48aa7ffe065bf0237 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ca881c02da68 drm/i915: Program EXT2 GC MAX registers
ecab4c425422 drm/i915: Fix GCMAX color register programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12628/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915: Fix GCMAX color register programming
2019-03-29 12:49 ` [PATCH 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
@ 2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 13:50 ` Shankar, Uma
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-29 13:10 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Fri, Mar 29, 2019 at 06:19:18PM +0530, Uma Shankar wrote:
> GC MAX register is used to program values from 1.0 to
> less than 3.0. A different register was used instead of
> the intended one. Fixed the same.
>
> Currently limiting it to 1.0 due to ABI limitations.
>
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index ff910ed..dd179a8 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_DATA(pipe), word);
> }
>
> - /* Program the max register to clamp values > 1.0. */
> - i = lut_size - 1;
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
> - drm_color_lut_extract(lut[i].red, 16));
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
> - drm_color_lut_extract(lut[i].green, 16));
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
> - drm_color_lut_extract(lut[i].blue, 16));
> + /*
> + * Program the max register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 1.0 to 3.0
> + */
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
Maybe we want these to be just 1<<16 to match how we set up the glk+
degamma?
> } else {
> for (i = 0; i < lut_size; i++) {
> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> @@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
> (v << 20) | (v << 10) | v);
> }
>
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> }
>
> /*
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
2019-03-29 12:49 ` [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
@ 2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 13:51 ` Shankar, Uma
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-29 13:10 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote:
> EXT2 GC MAX registers are introduced from Gen10+ to
> program values from 3.0 to 7.0. Enabled the same, but
> currently limiting it to 1.0 as userspace ABI is limited
> at that currently.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_color.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c866379..341f03e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10144,6 +10144,7 @@ enum skl_power_gate {
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
>
> #define _PRE_CSC_GAMC_INDEX_A 0x4A484
> #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index dd179a8..84aa5e7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> +
> + /*
> + * Program the gc max 2 register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 3.0 to 7.0
> + */
> + if (INTEL_GEN(dev_priv) >= 10) {
|| IS_GEMINILAKE
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
> + (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
> + (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
> + (1 << 16) - 1);
> + }
> } else {
> for (i = 0; i < lut_size; i++) {
> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> @@ -537,6 +551,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> +
> + /*
> + * Program the gc max 2 register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 3.0 to 7.0
> + */
> + if (INTEL_GEN(dev_priv) >= 10) {
same
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
> + (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
> + (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
> + (1 << 16) - 1);
> + }
> }
>
> /*
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915: Fix GCMAX color register programming
2019-03-29 13:10 ` Ville Syrjälä
@ 2019-03-29 13:50 ` Shankar, Uma
0 siblings, 0 replies; 9+ messages in thread
From: Shankar, Uma @ 2019-03-29 13:50 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, March 29, 2019 6:40 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst,
>Maarten <maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register programming
>
>On Fri, Mar 29, 2019 at 06:19:18PM +0530, Uma Shankar wrote:
>> GC MAX register is used to program values from 1.0 to less than 3.0. A
>> different register was used instead of the intended one. Fixed the
>> same.
>>
>> Currently limiting it to 1.0 due to ABI limitations.
>>
>> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++-----------
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index ff910ed..dd179a8 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct
>intel_crtc_state *crtc_state, u32 of
>> I915_WRITE(PREC_PAL_DATA(pipe), word);
>> }
>>
>> - /* Program the max register to clamp values > 1.0. */
>> - i = lut_size - 1;
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
>> - drm_color_lut_extract(lut[i].red, 16));
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
>> - drm_color_lut_extract(lut[i].green, 16));
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
>> - drm_color_lut_extract(lut[i].blue, 16));
>> + /*
>> + * Program the max register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 1.0 to 3.0
>> + */
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>
>Maybe we want these to be just 1<<16 to match how we set up the glk+ degamma?
Sure, will update it.
>> } else {
>> for (i = 0; i < lut_size; i++) {
>> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -534,9 +534,9
>> @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32
>of
>> (v << 20) | (v << 10) | v);
>> }
>>
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
>> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> }
>>
>> /*
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
2019-03-29 13:10 ` Ville Syrjälä
@ 2019-03-29 13:51 ` Shankar, Uma
0 siblings, 0 replies; 9+ messages in thread
From: Shankar, Uma @ 2019-03-29 13:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, March 29, 2019 6:41 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst,
>Maarten <maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
>
>On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote:
>> EXT2 GC MAX registers are introduced from Gen10+ to program values
>> from 3.0 to 7.0. Enabled the same, but currently limiting it to 1.0 as
>> userspace ABI is limited at that currently.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_color.c | 28 ++++++++++++++++++++++++++++
>> 2 files changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index c866379..341f03e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10144,6 +10144,7 @@ enum skl_power_gate {
>> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe,
>_PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
>> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
>_PAL_PREC_GC_MAX_B) + (i) * 4)
>> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
>_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
>> +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
>_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
>>
>> #define _PRE_CSC_GAMC_INDEX_A 0x4A484
>> #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index dd179a8..84aa5e7 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct
>intel_crtc_state *crtc_state, u32 of
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> +
>> + /*
>> + * Program the gc max 2 register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 3.0 to 7.0
>> + */
>> + if (INTEL_GEN(dev_priv) >= 10) {
>
>|| IS_GEMINILAKE
Yeah, GLK needs to be added here. Will update it.
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
>> + (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
>> + (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
>> + (1 << 16) - 1);
>> + }
>> } else {
>> for (i = 0; i < lut_size; i++) {
>> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -537,6 +551,20
>> @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32
>of
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> +
>> + /*
>> + * Program the gc max 2 register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 3.0 to 7.0
>> + */
>> + if (INTEL_GEN(dev_priv) >= 10) {
>
>same
>
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
>> + (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
>> + (1 << 16) - 1);
>> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
>> + (1 << 16) - 1);
>> + }
>> }
>>
>> /*
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-03-29 13:52 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-29 12:49 [PATCH 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 12:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-03-29 12:49 ` [PATCH 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 13:50 ` Shankar, Uma
2019-03-29 12:49 ` [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
2019-03-29 13:10 ` Ville Syrjälä
2019-03-29 13:51 ` Shankar, Uma
2019-03-29 13:07 ` ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.