[U-Boot] [PATCH 0/8] rockchip: enable spl/tpl for px5-evb

[U-Boot] [PATCH 0/8] rockchip: enable spl/tpl for px5-evb

[Kever Yang]

This patch set enable spl/tpl and also suppot ATF elf,
and the timer is using rockchip timer, we may switch to stimer
based ARM generic timer later if we get STIMER patches mergerd.



Kever Yang (8):
  rockchip: rk3368: support UART2/4 in board_debug_uart_init()
  rockchip: px5 update dts for spl/tpl
  rockchip: px5: update SPL size for spl/tpl
  rockchip: px5: update defconfig for TPL/SPL
  rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only
  rockchip: dmc: rk3368: update rank number for evb-px5
  rockchip: rk3368: remove uart iomux init in SPL
  rockchip: px5: add timer0 dts node as tick timer

 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi    | 36 ++++++++++++++
 arch/arm/include/asm/arch-rockchip/boot0.h |  3 +-
 arch/arm/mach-rockchip/rk3368-board-spl.c  | 13 -----
 arch/arm/mach-rockchip/rk3368/rk3368.c     | 40 ++++++++++++++++
 configs/evb-px5_defconfig                  | 56 +++++++++++++++++++++-
 drivers/ram/rockchip/dmc-rk3368.c          |  4 ++
 include/configs/evb_px5.h                  |  1 +
 include/configs/rk3368_common.h            |  3 +-
 8 files changed, 139 insertions(+), 17 deletions(-)

-- 
2.20.1

[U-Boot] [PATCH 1/8] rockchip: rk3368: support UART2/4 in board_debug_uart_init()

[Kever Yang]

evb-rk3368 is using UART2 and PX5 evb is using UART4

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index 1ed06c5352..f06d27717d 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -124,6 +124,46 @@ void board_debug_uart_init(void)
 		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
 	rk_clrsetreg(&grf->gpio2d_iomux,
 		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
+	struct rk3368_pmu_grf * const pmugrf __maybe_unused =
+		(struct rk3368_pmu_grf * const)0xff738000;
+
+	enum {
+		/* UART4 */
+		GPIO0D2_MASK		= GENMASK(5, 4),
+		GPIO0D2_GPIO		= 0,
+		GPIO0D2_UART4_SOUT	= (3 << 4),
+
+		GPIO0D3_MASK		= GENMASK(7, 6),
+		GPIO0D3_GPIO		= 0,
+		GPIO0D3_UART4_SIN	= (3 << 6),
+	};
+
+	/* Enable early UART4 on the PX5 */
+	rk_clrsetreg(&pmugrf->gpio0d_iomux,
+		     GPIO0D2_MASK | GPIO0D3_MASK,
+		     GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2A6_SHIFT           = 12,
+		GPIO2A6_MASK            = GENMASK(13, 12),
+		GPIO2A6_GPIO            = 0,
+		GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),
+
+		GPIO2A5_SHIFT           = 10,
+		GPIO2A5_MASK            = GENMASK(11, 10),
+		GPIO2A5_GPIO            = 0,
+		GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),
+	};
+
+	/* Enable early UART2 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A6_MASK, GPIO2A6_UART2_SIN);
+	rk_clrsetreg(&grf->gpio2a_iomux,
+		     GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
 #endif
 }
 #endif
-- 
2.20.1

[U-Boot] [PATCH 2/8] rockchip: px5 update dts for spl/tpl

[Kever Yang]

TPL need dmc to init ddr sdram, and emmc, boot-order.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 7495781454..18b841864c 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -2,6 +2,27 @@
 /*
  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  */
+/ {
+	chosen {
+		u-boot,spl-boot-order = &emmc;
+	};
+};
+
+&dmc {
+	u-boot,dm-pre-reloc;
+
+	/*
+	 * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
+	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+	 * details on the 'rockchip,memory-schedule' property and how it
+	 * affects the physical-address to device-address mapping.
+	 */
+	rockchip,memory-schedule = <DMC_MSCH_CBRD>;
+	rockchip,ddr-frequency = <800000000>;
+	rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+	status = "okay";
+};
 
 &pinctrl {
 	u-boot,dm-pre-reloc;
@@ -20,6 +41,10 @@
 	u-boot,dm-pre-reloc;
 };
 
+&sgrf {
+	u-boot,dm-pre-reloc;
+};
+
 &cru {
 	u-boot,dm-pre-reloc;
 };
@@ -31,3 +56,7 @@
 &uart4 {
 	u-boot,dm-pre-reloc;
 };
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
-- 
2.20.1

[U-Boot] [PATCH 3/8] rockchip: px5: update SPL size for spl/tpl

[Kever Yang]

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/configs/evb_px5.h       | 1 +
 include/configs/rk3368_common.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h
index e67bee1721..e9304206bb 100644
--- a/include/configs/evb_px5.h
+++ b/include/configs/evb_px5.h
@@ -9,5 +9,6 @@
 #include <configs/rk3368_common.h>
 
 #define CONFIG_CONSOLE_SCROLL_LINES	10
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #endif
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 5aa598287a..bb5490c3c2 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -28,9 +28,10 @@
 #define CONFIG_SYS_LOAD_ADDR		0x00280000
 
 #define CONFIG_SPL_TEXT_BASE            0x00000000
-#define CONFIG_SPL_MAX_SIZE             0x40000
+#define CONFIG_SPL_MAX_SIZE             0x60000
 #define CONFIG_SPL_BSS_START_ADDR       0x400000
 #define CONFIG_SPL_BSS_MAX_SIZE         0x20000
+#define CONFIG_SPL_STACK		0x00188000
 
 #ifndef CONFIG_SPL_BUILD
 #define ENV_MEM_LAYOUT_SETTINGS \
-- 
2.20.1

[U-Boot] [PATCH 4/8] rockchip: px5: update defconfig for TPL/SPL

[Kever Yang]

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 configs/evb-px5_defconfig | 56 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 1d428e7ac8..f99943de08 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -1,30 +1,82 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3368=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_TARGET_EVB_PX5=y
+CONFIG_SPL=y
 CONFIG_DEBUG_UART_BASE=0xFF1c0000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+CONFIG_BOOTSTAGE=y
+CONFIG_SPL_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_BOOTSTAGE_FDT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+CONFIG_TPL_BOOTROM_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
 CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
 CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYSRESET=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_TPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.20.1

[U-Boot] [PATCH 5/8] rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only

[Kever Yang]

The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/include/asm/arch-rockchip/boot0.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
index 9ea4708ada..0c375e543a 100644
--- a/arch/arm/include/asm/arch-rockchip/boot0.h
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -54,6 +54,7 @@ _start:
 	ARM_VECTORS
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
+#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
+	(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
 	.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM	/* space for the ATF data */
 #endif
-- 
2.20.1

[U-Boot] [PATCH 6/8] rockchip: dmc: rk3368: update rank number for evb-px5

[Kever Yang]

evb-px5 has only 1 CS, update for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/ram/rockchip/dmc-rk3368.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index 92f584fadc..e52fc3baad 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev)
 	move_to_access_state(pctl);
 
 	/* TODO(prt): could detect rank in training... */
+#ifdef CONFIG_TARGET_EVB_PX5
+	params->chan.rank = 1;
+#else
 	params->chan.rank = 2;
+#endif
 	/* TODO(prt): bus width is not auto-detected (yet)... */
 	params->chan.bw = 2;  /* 32bit wide bus */
 	params->chan.dbw = params->chan.dbw;  /* 32bit wide bus */
-- 
2.20.1

[U-Boot] [PATCH 7/8] rockchip: rk3368: remove uart iomux init in SPL

[Kever Yang]

The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3368-board-spl.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
index b055ed4aee..9cb5eab8ae 100644
--- a/arch/arm/mach-rockchip/rk3368-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
@@ -24,19 +24,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	/* Set up our preloader console */
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
-		hang();
-	}
-
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
-	if (ret) {
-		pr_err("%s: failed to set up console UART\n", __func__);
-		hang();
-	}
-
 	preloader_console_init();
 
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-- 
2.20.1

[U-Boot] [PATCH 8/8] rockchip: px5: add timer0 dts node as tick timer

[Kever Yang]

Let's use rockchip timer before stimer patches can be merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 18b841864c..f5406d4c7e 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -5,6 +5,7 @@
 / {
 	chosen {
 		u-boot,spl-boot-order = &emmc;
+		tick-timer = "/timer at ff810000";
 	};
 };
 
@@ -60,3 +61,9 @@
 &emmc {
 	u-boot,dm-pre-reloc;
 };
+
+&timer0 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
-- 
2.20.1

[U-Boot] [PATCH 2/8] rockchip: px5 update dts for spl/tpl

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:52写道：

> TPL need dmc to init ddr sdram, and emmc, boot-order.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
>
Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> index 7495781454..18b841864c 100644
> --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> @@ -2,6 +2,27 @@
>  /*
>   * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>   */
> +/ {
> +       chosen {
> +               u-boot,spl-boot-order = &emmc;
> +       };
> +};
> +
> +&dmc {
> +       u-boot,dm-pre-reloc;
> +
> +       /*
> +        * PX5-evb(2GB) need to use CBRD mode, or else the dram is not
> correct
> +        * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
> +        * details on the 'rockchip,memory-schedule' property and how it
> +        * affects the physical-address to device-address mapping.
> +        */
> +       rockchip,memory-schedule = <DMC_MSCH_CBRD>;
> +       rockchip,ddr-frequency = <800000000>;
> +       rockchip,ddr-speed-bin = <DDR3_1600K>;
> +
> +       status = "okay";
> +};
>
>  &pinctrl {
>         u-boot,dm-pre-reloc;
> @@ -20,6 +41,10 @@
>         u-boot,dm-pre-reloc;
>  };
>
> +&sgrf {
> +       u-boot,dm-pre-reloc;
> +};
> +
>  &cru {
>         u-boot,dm-pre-reloc;
>  };
> @@ -31,3 +56,7 @@
>  &uart4 {
>         u-boot,dm-pre-reloc;
>  };
> +
> +&emmc {
> +       u-boot,dm-pre-reloc;
> +};
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>

[U-Boot] [PATCH 6/8] rockchip: dmc: rk3368: update rank number for evb-px5

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:53写道：

> evb-px5 has only 1 CS, update for it.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/ram/rockchip/dmc-rk3368.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
>
Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/drivers/ram/rockchip/dmc-rk3368.c
> b/drivers/ram/rockchip/dmc-rk3368.c
> index 92f584fadc..e52fc3baad 100644
> --- a/drivers/ram/rockchip/dmc-rk3368.c
> +++ b/drivers/ram/rockchip/dmc-rk3368.c
> @@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev)
>         move_to_access_state(pctl);
>
>         /* TODO(prt): could detect rank in training... */
> +#ifdef CONFIG_TARGET_EVB_PX5
> +       params->chan.rank = 1;
> +#else
>         params->chan.rank = 2;
> +#endif
>         /* TODO(prt): bus width is not auto-detected (yet)... */
>         params->chan.bw = 2;  /* 32bit wide bus */
>         params->chan.dbw = params->chan.dbw;  /* 32bit wide bus */
> --
> 2.20.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>

[U-Boot] [PATCH 4/8] rockchip: px5: update defconfig for TPL/SPL

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:54写道：

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  configs/evb-px5_defconfig | 56 +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 54 insertions(+), 2 deletions(-)
>
>
Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
> index 1d428e7ac8..f99943de08 100644
> --- a/configs/evb-px5_defconfig
> +++ b/configs/evb-px5_defconfig
> @@ -1,30 +1,82 @@
>  CONFIG_ARM=y
>  CONFIG_ARCH_ROCKCHIP=y
>  CONFIG_SYS_TEXT_BASE=0x00200000
> -CONFIG_SYS_MALLOC_F_LEN=0x1000
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>  CONFIG_ROCKCHIP_RK3368=y
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
> +CONFIG_TPL_LIBCOMMON_SUPPORT=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
>  CONFIG_TARGET_EVB_PX5=y
> +CONFIG_SPL=y
>  CONFIG_DEBUG_UART_BASE=0xFF1c0000
>  CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
>  CONFIG_DEBUG_UART=y
>  CONFIG_NR_DRAM_BANKS=1
>  CONFIG_ANDROID_BOOT_IMAGE=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
> +CONFIG_BOOTSTAGE=y
> +CONFIG_SPL_BOOTSTAGE=y
> +CONFIG_BOOTSTAGE_REPORT=y
> +CONFIG_BOOTSTAGE_FDT=y
>  CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
>  # CONFIG_DISPLAY_CPUINFO is not set
>  CONFIG_DISPLAY_BOARDINFO_LATE=y
>  CONFIG_ARCH_EARLY_INIT_R=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
> +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_ATF=y
> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_TPL=y
> +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
> +CONFIG_TPL_BOOTROM_SUPPORT=y
>  CONFIG_CMD_MMC=y
>  CONFIG_CMD_CACHE=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_TPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
>  CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb"
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
> +CONFIG_TPL_OF_PLATDATA=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_TPL_DM=y
>  CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_TPL_REGMAP=y
>  CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_TPL_SYSCON=y
>  CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_TPL_CLK=y
>  CONFIG_MMC_DW=y
>  CONFIG_MMC_DW_ROCKCHIP=y
>  CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
>  CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_DM_RESET=y
>  CONFIG_DEBUG_UART_SHIFT=2
> -CONFIG_DEBUG_UART_ANNOUNCE=y
>  CONFIG_DEBUG_UART_SKIP_INIT=y
>  CONFIG_SYSRESET=y
> +CONFIG_TIMER=y
> +CONFIG_SPL_TIMER=y
> +CONFIG_TPL_TIMER=y
> +CONFIG_ROCKCHIP_TIMER=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_PANIC_HANG=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
>  CONFIG_ERRNO_STR=y
> --
> 2.20.1
>
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> https://lists.denx.de/listinfo/u-boot
>

[U-Boot] [PATCH 1/8] rockchip: rk3368: support UART2/4 in board_debug_uart_init()

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:54写道：

> evb-rk3368 is using UART2 and PX5 evb is using UART4
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
>
Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c
> b/arch/arm/mach-rockchip/rk3368/rk3368.c
> index 1ed06c5352..f06d27717d 100644
> --- a/arch/arm/mach-rockchip/rk3368/rk3368.c
> +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
> @@ -124,6 +124,46 @@ void board_debug_uart_init(void)
>                      GPIO2D0_MASK, GPIO2D0_UART0_SIN);
>         rk_clrsetreg(&grf->gpio2d_iomux,
>                      GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff1c0000)
> +       struct rk3368_pmu_grf * const pmugrf __maybe_unused =
> +               (struct rk3368_pmu_grf * const)0xff738000;
> +
> +       enum {
> +               /* UART4 */
> +               GPIO0D2_MASK            = GENMASK(5, 4),
> +               GPIO0D2_GPIO            = 0,
> +               GPIO0D2_UART4_SOUT      = (3 << 4),
> +
> +               GPIO0D3_MASK            = GENMASK(7, 6),
> +               GPIO0D3_GPIO            = 0,
> +               GPIO0D3_UART4_SIN       = (3 << 6),
> +       };
> +
> +       /* Enable early UART4 on the PX5 */
> +       rk_clrsetreg(&pmugrf->gpio0d_iomux,
> +                    GPIO0D2_MASK | GPIO0D3_MASK,
> +                    GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
> +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE ==
> 0xff690000)
> +       struct rk3368_grf * const grf =
> +               (struct rk3368_grf * const)0xff770000;
> +
> +       enum {
> +               GPIO2A6_SHIFT           = 12,
> +               GPIO2A6_MASK            = GENMASK(13, 12),
> +               GPIO2A6_GPIO            = 0,
> +               GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),
> +
> +               GPIO2A5_SHIFT           = 10,
> +               GPIO2A5_MASK            = GENMASK(11, 10),
> +               GPIO2A5_GPIO            = 0,
> +               GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),
> +       };
> +
> +       /* Enable early UART2 on the RK3368 */
> +       rk_clrsetreg(&grf->gpio2a_iomux,
> +                    GPIO2A6_MASK, GPIO2A6_UART2_SIN);
> +       rk_clrsetreg(&grf->gpio2a_iomux,
> +                    GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
>  #endif
>  }
>  #endif
> --
> 2.20.1
>
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>

[U-Boot] [PATCH 8/8] rockchip: px5: add timer0 dts node as tick timer

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:54写道：

> Let's use rockchip timer before stimer patches can be merged.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> index 18b841864c..f5406d4c7e 100644
> --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
> @@ -5,6 +5,7 @@
>  / {
>         chosen {
>                 u-boot,spl-boot-order = &emmc;
> +               tick-timer = "/timer at ff810000";
>         };
>  };
>
> @@ -60,3 +61,9 @@
>  &emmc {
>         u-boot,dm-pre-reloc;
>  };
> +
> +&timer0 {
> +       u-boot,dm-pre-reloc;
> +       clock-frequency = <24000000>;
> +       status = "okay";
> +};
> --
> 2.20.1
>
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>

[U-Boot] [PATCH 3/8] rockchip: px5: update SPL size for spl/tpl

[Andy Yan]

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:55写道：

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  include/configs/evb_px5.h       | 1 +
>  include/configs/rk3368_common.h | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
>
Tested-by: Andy Yan <andy.yan@rock-chips.com>


> diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h
> index e67bee1721..e9304206bb 100644
> --- a/include/configs/evb_px5.h
> +++ b/include/configs/evb_px5.h
> @@ -9,5 +9,6 @@
>  #include <configs/rk3368_common.h>
>
>  #define CONFIG_CONSOLE_SCROLL_LINES    10
> +#define CONFIG_SYS_MMC_ENV_DEV 0
>
>  #endif
> diff --git a/include/configs/rk3368_common.h
> b/include/configs/rk3368_common.h
> index 5aa598287a..bb5490c3c2 100644
> --- a/include/configs/rk3368_common.h
> +++ b/include/configs/rk3368_common.h
> @@ -28,9 +28,10 @@
>  #define CONFIG_SYS_LOAD_ADDR           0x00280000
>
>  #define CONFIG_SPL_TEXT_BASE            0x00000000
> -#define CONFIG_SPL_MAX_SIZE             0x40000
> +#define CONFIG_SPL_MAX_SIZE             0x60000
>  #define CONFIG_SPL_BSS_START_ADDR       0x400000
>  #define CONFIG_SPL_BSS_MAX_SIZE         0x20000
> +#define CONFIG_SPL_STACK               0x00188000
>
>  #ifndef CONFIG_SPL_BUILD
>  #define ENV_MEM_LAYOUT_SETTINGS \
> --
> 2.20.1
>
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[U-Boot] [PATCH 7/8] rockchip: rk3368: remove uart iomux init in SPL

[Andy Yan]

Hi Kever:

Kever Yang <kever.yang@rock-chips.com> 于2019年3月29日周五 下午10:55写道：

> The iomux should have been set in board_debug_uart_init(),
> do not set in board_init_f(), remove it.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  arch/arm/mach-rockchip/rk3368-board-spl.c | 13 -------------
>  1 file changed, 13 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c
> b/arch/arm/mach-rockchip/rk3368-board-spl.c
> index b055ed4aee..9cb5eab8ae 100644
> --- a/arch/arm/mach-rockchip/rk3368-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
> @@ -24,19 +24,6 @@ void board_init_f(ulong dummy)
>                 hang();
>         }
>
> -       /* Set up our preloader console */
> -       ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>


the struct udevice* pinctrl definition should also be removed.



> -       if (ret) {
> -               pr_err("%s: pinctrl init failed: %d\n", __func__, ret);
> -               hang();
> -       }
> -
> -       ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
> -       if (ret) {
> -               pr_err("%s: failed to set up console UART\n", __func__);
> -               hang();
> -       }
> -
>         preloader_console_init();
>
>         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> --
> 2.20.1
>
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