[RFC 0/5] MIPS: ralink: peripheral clock gating driver

[RFC 0/5] MIPS: ralink: peripheral clock gating driver

[NOGUCHI Hiroshi]

This series introduce Mediatek/Ralink SoC's clock gating driver.
The gating clock items are different at individual SoCs.
Driver loads gating clock item table defined in individual SoC source files,
via OF device id data.

NOGUCHI Hiroshi (5):
  mips: ralink: add rt2880-clock driver
  mips: ralink: add dt-binding document for rt2880-clock driver
  mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver
  mips: ralink: mt7628: add nodes for clock provider
  mips: ralink: mt7620: add nodes for clock provider

 .../bindings/clock/ralink,rt2880-clock.txt    |  20 +++
 arch/mips/boot/dts/ralink/mt7620a.dtsi        |  34 ++++-
 arch/mips/boot/dts/ralink/mt7628a.dtsi        |  37 +++++
 arch/mips/ralink/Kconfig                      |   6 +
 arch/mips/ralink/Makefile                     |   2 +
 arch/mips/ralink/clk.c                        |  30 ++++
 arch/mips/ralink/common.h                     |   3 +
 arch/mips/ralink/mt7620.c                     | 132 ++++++++++++++---
 arch/mips/ralink/rt2880-clk_internal.h        |  21 +++
 arch/mips/ralink/rt2880-clock.c               | 134 ++++++++++++++++++
 include/dt-bindings/clock/mt7620-clk.h        |  17 +++
 11 files changed, 411 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
 create mode 100644 arch/mips/ralink/rt2880-clk_internal.h
 create mode 100644 arch/mips/ralink/rt2880-clock.c
 create mode 100644 include/dt-bindings/clock/mt7620-clk.h

-- 
2.20.1

[RFC 1/5] mips: ralink: add rt2880-clock driver

[NOGUCHI Hiroshi]

This patch adds SoC peripheral clock gating driver.
The driver loads gating clock table from of_device_id.data in individual SoC sources.

Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 arch/mips/ralink/rt2880-clk_internal.h |  21 ++++
 arch/mips/ralink/rt2880-clock.c        | 134 +++++++++++++++++++++++++
 2 files changed, 155 insertions(+)
 create mode 100644 arch/mips/ralink/rt2880-clk_internal.h
 create mode 100644 arch/mips/ralink/rt2880-clock.c

diff --git a/arch/mips/ralink/rt2880-clk_internal.h b/arch/mips/ralink/rt2880-clk_internal.h
new file mode 100644
index 000000000000..9d5dded16a80
--- /dev/null
+++ b/arch/mips/ralink/rt2880-clk_internal.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
+ */
+
+#ifndef __RT2880_CLOCK_INTERNAL_H
+
+
+#define GATE_CLK_NUM	(32)
+
+struct gate_clk_desc {
+	const char *name;
+	const char *parent_name;
+};
+
+extern const struct of_device_id __initconst of_match_rt2880_clk[];
+
+
+#endif
+
+
diff --git a/arch/mips/ralink/rt2880-clock.c b/arch/mips/ralink/rt2880-clock.c
new file mode 100644
index 000000000000..46cc067225ab
--- /dev/null
+++ b/arch/mips/ralink/rt2880-clock.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/bug.h>
+
+#include "rt2880-clk_internal.h"
+
+
+/* clock configuration 1 */
+#define	SYSC_REG_CLKCFG1	0x30
+
+struct rt2880_gate {
+	struct clk_hw	hw;
+	u8	shift;
+};
+
+#define	to_rt2880_gate(_hw)	container_of(_hw, struct rt2880_gate, hw)
+
+static struct clk_onecell_data	clk_data;
+static struct clk *clks[GATE_CLK_NUM];
+
+static struct regmap *syscon_regmap;
+
+static int rt2880_gate_enable(struct clk_hw *hw)
+{
+	struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
+	u32 val = 0x01UL << clk_gate->shift;
+
+	regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, val);
+
+	return 0;
+}
+
+static void rt2880_gate_disable(struct clk_hw *hw)
+{
+	struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
+	u32 val = 0x01UL << clk_gate->shift;
+
+	regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, 0);
+}
+
+static int rt2880_gate_is_enabled(struct clk_hw *hw)
+{
+	struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
+	unsigned int rdval;
+
+	if (regmap_read(syscon_regmap, SYSC_REG_CLKCFG1, &rdval))
+		return 0;
+
+	return (!!(rdval & (0x01UL << clk_gate->shift)));
+}
+
+static const struct clk_ops rt2880_gate_ops = {
+	.enable = rt2880_gate_enable,
+	.disable = rt2880_gate_disable,
+	.is_enabled = rt2880_gate_is_enabled,
+};
+
+static struct clk * __init
+rt2880_register_gate(const char *name, const char *parent_name, u8 shift)
+{
+	struct rt2880_gate	*clk_gate;
+	struct clk		*clk;
+	struct clk_init_data	init;
+	const char *_parent_names[1] = { parent_name };
+
+	clk_gate = kzalloc(sizeof(*clk_gate), GFP_KERNEL);
+	if (!clk_gate)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &rt2880_gate_ops;
+	init.flags = 0;
+	init.parent_names = parent_name ? _parent_names : NULL;
+	init.num_parents = parent_name ? 1 : 0;
+
+	clk_gate->hw.init = &init;
+	clk_gate->shift = shift;
+
+	clk = clk_register(NULL, &clk_gate->hw);
+	if (IS_ERR(clk))
+		kfree(clk_gate);
+
+	return clk;
+}
+
+static void __init rt2880_clkctrl_init_dt(struct device_node *np)
+{
+	struct clk *clk;
+	int i;
+	const struct of_device_id *match;
+	struct gate_clk_desc *clk_tbl;
+
+	match = of_match_node(of_match_rt2880_clk, np);
+	if (!match) {
+		pr_info("rt2880-clock: could not get compatible node");
+		return;
+	}
+	clk_tbl = (struct gate_clk_desc *)match->data;
+
+	syscon_regmap = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl");
+	if (IS_ERR(syscon_regmap)) {
+		pr_info("rt2880-clock: could not get syscon regmap");
+		return;
+	}
+
+	clk_data.clk_num = GATE_CLK_NUM;
+	clk_data.clks = clks;
+
+	for (i = 0; i < GATE_CLK_NUM; i++) {
+		if (clk_tbl[i].name) {
+			clk = rt2880_register_gate(
+				clk_tbl[i].name, clk_tbl[i].parent_name, i);
+			if (IS_ERR_OR_NULL(clk))
+				panic("rt2880-clock : could not register gate clock");
+			clk_data.clks[i] = clk;
+		}
+	}
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(rt2880, "ralink,rt2880-clock", rt2880_clkctrl_init_dt);
-- 
2.20.1

Re: [RFC 1/5] mips: ralink: add rt2880-clock driver

[Stephen Boyd]

Quoting NOGUCHI Hiroshi (2019-03-30 05:33:13)
> This patch adds SoC peripheral clock gating driver.
> The driver loads gating clock table from of_device_id.data in individual SoC sources.

Please line wrap this to the column length standard of something like 76
columns.

> 
> Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
> diff --git a/arch/mips/ralink/rt2880-clk_internal.h b/arch/mips/ralink/rt2880-clk_internal.h
> new file mode 100644
> index 000000000000..9d5dded16a80
> --- /dev/null
> +++ b/arch/mips/ralink/rt2880-clk_internal.h
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
> + */
> +
> +#ifndef __RT2880_CLOCK_INTERNAL_H
> +
> +
> +#define GATE_CLK_NUM   (32)
> +
> +struct gate_clk_desc {
> +       const char *name;
> +       const char *parent_name;
> +};
> +
> +extern const struct of_device_id __initconst of_match_rt2880_clk[];

Why is it extern?

> +
> +
> +#endif
> +
> +
> diff --git a/arch/mips/ralink/rt2880-clock.c b/arch/mips/ralink/rt2880-clock.c
> new file mode 100644
> index 000000000000..46cc067225ab
> --- /dev/null
> +++ b/arch/mips/ralink/rt2880-clock.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/jiffies.h>

Used?

> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>

Used?

> +#include <linux/clkdev.h>

Used?

> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/bug.h>

Drop? Don't use panic().

> +
> +#include "rt2880-clk_internal.h"
> +
> +
> +/* clock configuration 1 */
> +#define        SYSC_REG_CLKCFG1        0x30
> +
> +struct rt2880_gate {
> +       struct clk_hw   hw;
> +       u8      shift;
> +};
> +
> +#define        to_rt2880_gate(_hw)     container_of(_hw, struct rt2880_gate, hw)
> +
> +static struct clk_onecell_data clk_data;
> +static struct clk *clks[GATE_CLK_NUM];

Why does it need to be static? Why not allocate at runtime?

> +
> +static struct regmap *syscon_regmap;
> +
> +static int rt2880_gate_enable(struct clk_hw *hw)
> +{
> +       struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
> +       u32 val = 0x01UL << clk_gate->shift;

Just write BIT(clk_gate->shift) instead.

> +
> +       regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, val);

return regmap_udpate_bits()?

> +
> +       return 0;
> +}
> +
> +static void rt2880_gate_disable(struct clk_hw *hw)
> +{
> +       struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
> +       u32 val = 0x01UL << clk_gate->shift;

Same, use BIT() macro.

> +
> +       regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, 0);
> +}
> +
> +static int rt2880_gate_is_enabled(struct clk_hw *hw)
> +{
> +       struct rt2880_gate *clk_gate = to_rt2880_gate(hw);
> +       unsigned int rdval;
> +
> +       if (regmap_read(syscon_regmap, SYSC_REG_CLKCFG1, &rdval))
> +               return 0;
> +
> +       return (!!(rdval & (0x01UL << clk_gate->shift)));

Doesn't need to be a bool. Just 'return rdval & BIT(clk_gate->shift)'

> +}
> +
> +static const struct clk_ops rt2880_gate_ops = {
> +       .enable = rt2880_gate_enable,
> +       .disable = rt2880_gate_disable,
> +       .is_enabled = rt2880_gate_is_enabled,
> +};
> +
> +static struct clk * __init
> +rt2880_register_gate(const char *name, const char *parent_name, u8 shift)
> +{
> +       struct rt2880_gate      *clk_gate;
> +       struct clk              *clk;
> +       struct clk_init_data    init;
> +       const char *_parent_names[1] = { parent_name };
> +
> +       clk_gate = kzalloc(sizeof(*clk_gate), GFP_KERNEL);
> +       if (!clk_gate)
> +               return ERR_PTR(-ENOMEM);
> +
> +       init.name = name;
> +       init.ops = &rt2880_gate_ops;
> +       init.flags = 0;
> +       init.parent_names = parent_name ? _parent_names : NULL;
> +       init.num_parents = parent_name ? 1 : 0;
> +
> +       clk_gate->hw.init = &init;
> +       clk_gate->shift = shift;
> +
> +       clk = clk_register(NULL, &clk_gate->hw);

Please use clk_hw_register() instead of clk_register().

> +       if (IS_ERR(clk))
> +               kfree(clk_gate);
> +
> +       return clk;
> +}
> +
> +static void __init rt2880_clkctrl_init_dt(struct device_node *np)
> +{
> +       struct clk *clk;
> +       int i;
> +       const struct of_device_id *match;
> +       struct gate_clk_desc *clk_tbl;
> +
> +       match = of_match_node(of_match_rt2880_clk, np);
> +       if (!match) {
> +               pr_info("rt2880-clock: could not get compatible node");

How is this possible?

> +               return;
> +       }
> +       clk_tbl = (struct gate_clk_desc *)match->data;

Drop useless cast from void.

> +
> +       syscon_regmap = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl");
> +       if (IS_ERR(syscon_regmap)) {
> +               pr_info("rt2880-clock: could not get syscon regmap");

Why are error messages at 'info' print level? Should be pr_err().

> +               return;
> +       }
> +
> +       clk_data.clk_num = GATE_CLK_NUM;
> +       clk_data.clks = clks;
> +
> +       for (i = 0; i < GATE_CLK_NUM; i++) {
> +               if (clk_tbl[i].name) {
> +                       clk = rt2880_register_gate(
> +                               clk_tbl[i].name, clk_tbl[i].parent_name, i);
> +                       if (IS_ERR_OR_NULL(clk))
> +                               panic("rt2880-clock : could not register gate clock");

Do we need to panic here? Maybe things will still work?

> +                       clk_data.clks[i] = clk;
> +               }
> +       }
> +
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

Please add a clk_hw provider instead of a clk provider.

> +}
> +CLK_OF_DECLARE(rt2880, "ralink,rt2880-clock", rt2880_clkctrl_init_dt);

Can this be a platform driver?

[RFC 2/5] mips: ralink: add dt-binding document for rt2880-clock driver

[NOGUCHI Hiroshi]

Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 .../bindings/clock/ralink,rt2880-clock.txt    | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt

diff --git a/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
new file mode 100644
index 000000000000..6f0757046df4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
@@ -0,0 +1,20 @@
+* Clock bindings for Ralink/Mediatek MIPS based SoCs
+
+Required properties:
+ - compatible: must be "ralink,rt2880-clock" and
+     one of the following, to identify SoC series
+        "mediatek,mt7620-clock"   for MT7620
+        "mediatek,mt7628-clock"   for MT7628/MT7688
+        "mediatek,mt7621-clock"   for MT7621
+ - #clock-cells: must be 1
+ - ralink,sysctl: a phandle to a ralink syscon register region
+
+
+Example:
+
+clkctrl: clkctrl {
+	compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
+	#clock-cells = <1>;
+
+	ralink,sysctl = <&sysc>;
+};
-- 
2.20.1

[RFC 3/5] mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver

[NOGUCHI Hiroshi]

- add clock provider for reference clocks by PLL
- add gating clock tables referred by rt2880-clock driver

Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 arch/mips/ralink/Kconfig               |   6 ++
 arch/mips/ralink/Makefile              |   2 +
 arch/mips/ralink/clk.c                 |  30 ++++++
 arch/mips/ralink/common.h              |   3 +
 arch/mips/ralink/mt7620.c              | 132 ++++++++++++++++++++-----
 include/dt-bindings/clock/mt7620-clk.h |  17 ++++
 6 files changed, 168 insertions(+), 22 deletions(-)
 create mode 100644 include/dt-bindings/clock/mt7620-clk.h

diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 49c22ddd9c41..13301de113bb 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -18,6 +18,10 @@ config IRQ_INTC
 	default y
 	depends on !SOC_MT7621
 
+config RT2880_CLK
+	bool
+	default n
+
 choice
 	prompt "Ralink SoC selection"
 	default SOC_RT305X
@@ -40,6 +44,8 @@ choice
 		bool "MT7620/8"
 		select CPU_MIPSR2_IRQ_VI
 		select HAVE_PCI
+		select COMMON_CLK
+		select RT2880_CLK
 
 	config SOC_MT7621
 		bool "MT7621"
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index fe3471533820..af72c03ed544 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -25,6 +25,8 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o
 obj-$(CONFIG_SOC_MT7620) += mt7620.o
 obj-$(CONFIG_SOC_MT7621) += mt7621.o
 
+obj-$(CONFIG_RT2880_CLK) += rt2880-clock.o
+
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 
 obj-$(CONFIG_DEBUG_FS) += bootrom.o
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 1b7df115eb60..8715a44ebc4c 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -15,8 +15,15 @@
 
 #include <asm/time.h>
 
+#ifdef CONFIG_COMMON_CLK
+#include <linux/clk-provider.h>
+#endif
+
 #include "common.h"
 
+
+#ifndef CONFIG_COMMON_CLK
+
 struct clk {
 	struct clk_lookup cl;
 	unsigned long rate;
@@ -72,6 +79,26 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL_GPL(clk_round_rate);
 
+#else	/* CONFIG_COMMON_CLK */
+
+struct clk * __init add_sys_clkdev(const char *id, unsigned long rate)
+{
+	struct clk *clk;
+	int err;
+
+	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
+	if (IS_ERR(clk))
+		panic("failed to allocate %s clock structure", id);
+
+	err = clk_register_clkdev(clk, NULL, id);
+	if (err)
+		panic("unable to register %s clock device", id);
+
+	return clk;
+}
+
+#endif	/* CONFIG_COMMON_CLK */
+
 void __init plat_time_init(void)
 {
 	struct clk *clk;
@@ -79,6 +106,9 @@ void __init plat_time_init(void)
 	ralink_of_remap();
 
 	ralink_clk_init();
+#ifdef CONFIG_COMMON_CLK
+	of_clk_init(NULL);
+#endif
 	clk = clk_get_sys("cpu", NULL);
 	if (IS_ERR(clk))
 		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index b8245d0940d6..9f26ca96c411 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -26,6 +26,9 @@ extern void ralink_of_remap(void);
 
 extern void ralink_clk_init(void);
 extern void ralink_clk_add(const char *dev, unsigned long rate);
+#ifdef CONFIG_COMMON_CLK
+extern struct clk *add_sys_clkdev(const char *id, unsigned long rate);
+#endif
 
 extern void ralink_rst_init(void);
 
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index c1ce6f43642b..65dd8f7b7b9a 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -12,7 +12,13 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/jiffies.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <dt-bindings/clock/mt7620-clk.h>
 #include <linux/bug.h>
+#include <linux/of.h>
 
 #include <asm/mipsregs.h>
 #include <asm/mach-ralink/ralink_regs.h>
@@ -20,6 +26,7 @@
 #include <asm/mach-ralink/pinmux.h>
 
 #include "common.h"
+#include "rt2880-clk_internal.h"
 
 /* analog */
 #define PMU0_CFG		0x88
@@ -504,6 +511,17 @@ mt7620_get_sys_rate(unsigned long cpu_rate)
 	return cpu_rate / div;
 }
 
+static struct clk *clks[MT7620_CLK_MAX];
+
+static struct clk_onecell_data	clk_data = {
+	.clks	= clks,
+	.clk_num = ARRAY_SIZE(clks),
+};
+
+#define RFMT(label)	label ":%lu.%03luMHz "
+#define RINT(x)		((x) / 1000000)
+#define RFRAC(x)	(((x) / 1000) % 1000)
+
 void __init ralink_clk_init(void)
 {
 	unsigned long xtal_rate;
@@ -517,10 +535,6 @@ void __init ralink_clk_init(void)
 
 	xtal_rate = mt7620_get_xtal_rate();
 
-#define RFMT(label)	label ":%lu.%03luMHz "
-#define RINT(x)		((x) / 1000000)
-#define RFRAC(x)	(((x) / 1000) % 1000)
-
 	if (is_mt76x8()) {
 		if (xtal_rate == MHZ(40))
 			cpu_rate = MHZ(580);
@@ -529,9 +543,6 @@ void __init ralink_clk_init(void)
 		dram_rate = sys_rate = cpu_rate / 3;
 		periph_rate = MHZ(40);
 		pcmi2s_rate = MHZ(480);
-
-		ralink_clk_add("10000d00.uartlite", periph_rate);
-		ralink_clk_add("10000e00.uartlite", periph_rate);
 	} else {
 		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -547,7 +558,6 @@ void __init ralink_clk_init(void)
 			 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
 			 RINT(pll_rate), RFRAC(pll_rate));
 
-		ralink_clk_add("10000500.uart", periph_rate);
 	}
 
 	pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
@@ -555,21 +565,19 @@ void __init ralink_clk_init(void)
 		 RINT(dram_rate), RFRAC(dram_rate),
 		 RINT(sys_rate), RFRAC(sys_rate),
 		 RINT(periph_rate), RFRAC(periph_rate));
-#undef RFRAC
-#undef RINT
-#undef RFMT
 
-	ralink_clk_add("cpu", cpu_rate);
-	ralink_clk_add("10000100.timer", periph_rate);
-	ralink_clk_add("10000120.watchdog", periph_rate);
-	ralink_clk_add("10000900.i2c", periph_rate);
-	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
-	ralink_clk_add("10000b00.spi", sys_rate);
-	ralink_clk_add("10000b40.spi", sys_rate);
-	ralink_clk_add("10000c00.uartlite", periph_rate);
-	ralink_clk_add("10000d00.uart1", periph_rate);
-	ralink_clk_add("10000e00.uart2", periph_rate);
-	ralink_clk_add("10180000.wmac", xtal_rate);
+	/* system global */
+	clks[MT7620_CLK_CPU] = add_sys_clkdev("cpu", cpu_rate);
+
+	/* parent reference clocks */
+	clks[MT7620_CLK_SYS] =
+		clk_register_fixed_rate(NULL, "sys", NULL, 0, sys_rate);
+	clks[MT7620_CLK_PERIPH] =
+		clk_register_fixed_rate(NULL, "periph", NULL, 0, periph_rate);
+	clks[MT7620_CLK_PCMI2S] =
+		clk_register_fixed_rate(NULL, "pcmi2s", NULL, 0, pcmi2s_rate);
+	clks[MT7620_CLK_XTAL] =
+		clk_register_fixed_rate(NULL, "xtal", NULL, 0, xtal_rate);
 
 	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
 		/*
@@ -586,6 +594,86 @@ void __init ralink_clk_init(void)
 	}
 }
 
+#undef RFRAC
+#undef RINT
+#undef RFMT
+
+static void __init mt7620_clk_init_dt(struct device_node *np)
+{
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(mt7620, "mediatek,mt7620-pll", mt7620_clk_init_dt);
+
+
+/*
+ * resources for rt2880-clock
+ */
+
+static const struct gate_clk_desc clk_mt7620[GATE_CLK_NUM] __initconst = {
+	[12] = { .name = "uart", .parent_name = "periph" },
+	[16] = { .name = "i2c", .parent_name = "periph" },
+	[17] = { .name = "i2s", .parent_name = "pcmi2s" },
+	[18] = { .name = "spi", .parent_name = "sys" },
+	[19] = { .name = "uartl", .parent_name = "periph" },
+	/*
+	 * Now we exclude to avoid that clk framework disables no used clocks.
+	 * After implementing clk API calls in peripheral drivers,
+	 * we can activate their entries.
+	 */
+#if 0
+	[6] = { .name = "ge1" },
+	[7] = { .name = "ge2" },
+	[8] = { .name = "timer", .parent_name = "periph" },
+	[9] = { .name = "intc" },
+	[10] = { .name = "mc" },
+	[11] = { .name = "pcm" },
+	[13] = { .name = "pio" },
+	[14] = { .name = "gdma" },
+	[15] = { .name = "nand" },
+	[21] = { .name = "fe" },
+	[23] = { .name = "esw" },
+	[25] = { .name = "uphy" },
+	[26] = { .name = "pcie" },
+	[28] = { .name = "aux" },
+	[30] = { .name = "sdhc" },
+#endif
+};
+
+static const struct gate_clk_desc clk_mt76x8[GATE_CLK_NUM] __initconst = {
+	[12] = { .name = "uart0", .parent_name = "periph" },
+	[16] = { .name = "i2c", .parent_name = "periph" },
+	[17] = { .name = "i2s", .parent_name = "pcmi2s" },
+	[18] = { .name = "spi", .parent_name = "sys" },
+	[19] = { .name = "uart1", .parent_name = "periph" },
+	[20] = { .name = "uart2", .parent_name = "periph" },
+#if 0
+	[8] = { .name = "timer", .parent_name = "periph" },
+	[9] = { .name = "intc" },
+	[10] = { .name = "mc" },
+	[11] = { .name = "pcm" },
+	[13] = { .name = "pio" },
+	[14] = { .name = "gdma" },
+	[23] = { .name = "eth" },
+	[25] = { .name = "uphy" },
+	[26] = { .name = "pcie" },
+	[28] = { .name = "mipsc" },
+	[29] = { .name = "crypto" },
+	[30] = { .name = "sdxc" },
+	[31] = { .name = "pwm", .parent_name = "periph" },
+#endif
+};
+
+const struct of_device_id of_match_rt2880_clk[] __initconst = {
+	{
+		.compatible = "mediatek,mt7620-clock",
+		.data = clk_mt7620 },
+	{
+		.compatible = "mediatek,mt7628-clock",
+		.data = clk_mt76x8 },
+	{	/* sentinel */	},
+};
+
+
 void __init ralink_of_remap(void)
 {
 	rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
diff --git a/include/dt-bindings/clock/mt7620-clk.h b/include/dt-bindings/clock/mt7620-clk.h
new file mode 100644
index 000000000000..2e70e7df2ed2
--- /dev/null
+++ b/include/dt-bindings/clock/mt7620-clk.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_MT7620_CLK_H
+#define __DT_BINDINGS_MT7620_CLK_H
+
+#define MT7620_CLK_CPU		0
+#define	MT7620_CLK_SYS		1
+#define	MT7620_CLK_PERIPH	2
+#define	MT7620_CLK_PCMI2S	3
+#define	MT7620_CLK_XTAL		4
+
+#define MT7620_CLK_MAX		5
+
+#endif /* __DT_BINDINGS_MT7620_CLK_H */
-- 
2.20.1

Re: [RFC 3/5] mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver

[Stephen Boyd]

Quoting NOGUCHI Hiroshi (2019-03-30 05:33:15)
> diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
> index 49c22ddd9c41..13301de113bb 100644
> --- a/arch/mips/ralink/Kconfig
> +++ b/arch/mips/ralink/Kconfig
> @@ -18,6 +18,10 @@ config IRQ_INTC
>         default y
>         depends on !SOC_MT7621
>  
> +config RT2880_CLK
> +       bool
> +       default n

We don't need the default line here, it's n already.

> +
>  choice
>         prompt "Ralink SoC selection"
>         default SOC_RT305X
> diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
> index 1b7df115eb60..8715a44ebc4c 100644
> --- a/arch/mips/ralink/clk.c
> +++ b/arch/mips/ralink/clk.c
> @@ -15,8 +15,15 @@
>  
>  #include <asm/time.h>
>  
> +#ifdef CONFIG_COMMON_CLK

Does something go wrong if it's included when CONFIG_COMMON_CLK=n?
Hopefully not, so that this isn't a problem.

> +#include <linux/clk-provider.h>
> +#endif
> +
>  #include "common.h"
>  
> +
> +#ifndef CONFIG_COMMON_CLK
> +
>  struct clk {
>         struct clk_lookup cl;
>         unsigned long rate;
> @@ -72,6 +79,26 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
>  }
>  EXPORT_SYMBOL_GPL(clk_round_rate);
>  
> +#else  /* CONFIG_COMMON_CLK */
> +
> +struct clk * __init add_sys_clkdev(const char *id, unsigned long rate)
> +{
> +       struct clk *clk;
> +       int err;
> +
> +       clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
> +       if (IS_ERR(clk))
> +               panic("failed to allocate %s clock structure", id);
> +
> +       err = clk_register_clkdev(clk, NULL, id);
> +       if (err)
> +               panic("unable to register %s clock device", id);

Why do we need to panic?

> +
> +       return clk;
> +}
> +
> +#endif /* CONFIG_COMMON_CLK */
> +
>  void __init plat_time_init(void)
>  {
>         struct clk *clk;
> @@ -79,6 +106,9 @@ void __init plat_time_init(void)
>         ralink_of_remap();
>  
>         ralink_clk_init();
> +#ifdef CONFIG_COMMON_CLK

if (IS_ENABLED(CONFIG_COMMON_CLK)) {

perhaps?

> +       of_clk_init(NULL);
> +#endif
>         clk = clk_get_sys("cpu", NULL);
>         if (IS_ERR(clk))
>                 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
> diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
> index b8245d0940d6..9f26ca96c411 100644
> --- a/arch/mips/ralink/common.h
> +++ b/arch/mips/ralink/common.h
> @@ -26,6 +26,9 @@ extern void ralink_of_remap(void);
>  
>  extern void ralink_clk_init(void);
>  extern void ralink_clk_add(const char *dev, unsigned long rate);
> +#ifdef CONFIG_COMMON_CLK
> +extern struct clk *add_sys_clkdev(const char *id, unsigned long rate);
> +#endif
>  
>  extern void ralink_rst_init(void);
>  
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index c1ce6f43642b..65dd8f7b7b9a 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -12,7 +12,13 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/jiffies.h>

Is this used?

> +#include <linux/clk.h>

Is this used?

> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <dt-bindings/clock/mt7620-clk.h>
>  #include <linux/bug.h>
> +#include <linux/of.h>
>  
>  #include <asm/mipsregs.h>
>  #include <asm/mach-ralink/ralink_regs.h>
> @@ -20,6 +26,7 @@
>  #include <asm/mach-ralink/pinmux.h>
>  
>  #include "common.h"
> +#include "rt2880-clk_internal.h"
>  
>  /* analog */
>  #define PMU0_CFG               0x88
> @@ -504,6 +511,17 @@ mt7620_get_sys_rate(unsigned long cpu_rate)
>         return cpu_rate / div;
>  }
>  
> +static struct clk *clks[MT7620_CLK_MAX];
> +
> +static struct clk_onecell_data clk_data = {

Please use clk_hw based APIs instead of clk based ones.

> +       .clks   = clks,
> +       .clk_num = ARRAY_SIZE(clks),
> +};
> +
> +#define RFMT(label)    label ":%lu.%03luMHz "
> +#define RINT(x)                ((x) / 1000000)
> +#define RFRAC(x)       (((x) / 1000) % 1000)
> +
>  void __init ralink_clk_init(void)
>  {
>         unsigned long xtal_rate;
> @@ -517,10 +535,6 @@ void __init ralink_clk_init(void)
>  
>         xtal_rate = mt7620_get_xtal_rate();
>  
> -#define RFMT(label)    label ":%lu.%03luMHz "
> -#define RINT(x)                ((x) / 1000000)
> -#define RFRAC(x)       (((x) / 1000) % 1000)
> -
>         if (is_mt76x8()) {
>                 if (xtal_rate == MHZ(40))
>                         cpu_rate = MHZ(580);
> @@ -529,9 +543,6 @@ void __init ralink_clk_init(void)
>                 dram_rate = sys_rate = cpu_rate / 3;
>                 periph_rate = MHZ(40);
>                 pcmi2s_rate = MHZ(480);
> -
> -               ralink_clk_add("10000d00.uartlite", periph_rate);
> -               ralink_clk_add("10000e00.uartlite", periph_rate);
>         } else {
>                 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
>                 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
> @@ -547,7 +558,6 @@ void __init ralink_clk_init(void)
>                          RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
>                          RINT(pll_rate), RFRAC(pll_rate));
>  
> -               ralink_clk_add("10000500.uart", periph_rate);
>         }
>  
>         pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
> @@ -555,21 +565,19 @@ void __init ralink_clk_init(void)
>                  RINT(dram_rate), RFRAC(dram_rate),
>                  RINT(sys_rate), RFRAC(sys_rate),
>                  RINT(periph_rate), RFRAC(periph_rate));
> -#undef RFRAC
> -#undef RINT
> -#undef RFMT
>  
> -       ralink_clk_add("cpu", cpu_rate);
> -       ralink_clk_add("10000100.timer", periph_rate);
> -       ralink_clk_add("10000120.watchdog", periph_rate);
> -       ralink_clk_add("10000900.i2c", periph_rate);
> -       ralink_clk_add("10000a00.i2s", pcmi2s_rate);
> -       ralink_clk_add("10000b00.spi", sys_rate);
> -       ralink_clk_add("10000b40.spi", sys_rate);
> -       ralink_clk_add("10000c00.uartlite", periph_rate);
> -       ralink_clk_add("10000d00.uart1", periph_rate);
> -       ralink_clk_add("10000e00.uart2", periph_rate);
> -       ralink_clk_add("10180000.wmac", xtal_rate);
> +       /* system global */
> +       clks[MT7620_CLK_CPU] = add_sys_clkdev("cpu", cpu_rate);
> +
> +       /* parent reference clocks */
> +       clks[MT7620_CLK_SYS] =
> +               clk_register_fixed_rate(NULL, "sys", NULL, 0, sys_rate);
> +       clks[MT7620_CLK_PERIPH] =
> +               clk_register_fixed_rate(NULL, "periph", NULL, 0, periph_rate);
> +       clks[MT7620_CLK_PCMI2S] =
> +               clk_register_fixed_rate(NULL, "pcmi2s", NULL, 0, pcmi2s_rate);
> +       clks[MT7620_CLK_XTAL] =
> +               clk_register_fixed_rate(NULL, "xtal", NULL, 0, xtal_rate);
>  
>         if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
>                 /*
> @@ -586,6 +594,86 @@ void __init ralink_clk_init(void)
>         }
>  }
>  
> +#undef RFRAC
> +#undef RINT
> +#undef RFMT
> +
> +static void __init mt7620_clk_init_dt(struct device_node *np)
> +{
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +}
> +CLK_OF_DECLARE(mt7620, "mediatek,mt7620-pll", mt7620_clk_init_dt);

Same question, why not platform driver?

> +
> +
> +/*
> + * resources for rt2880-clock
> + */
> +
> +static const struct gate_clk_desc clk_mt7620[GATE_CLK_NUM] __initconst = {
> +       [12] = { .name = "uart", .parent_name = "periph" },
> +       [16] = { .name = "i2c", .parent_name = "periph" },
> +       [17] = { .name = "i2s", .parent_name = "pcmi2s" },
> +       [18] = { .name = "spi", .parent_name = "sys" },
> +       [19] = { .name = "uartl", .parent_name = "periph" },
> +       /*
> +        * Now we exclude to avoid that clk framework disables no used clocks.
> +        * After implementing clk API calls in peripheral drivers,
> +        * we can activate their entries.
> +        */
> +#if 0

Why can't we just add them later? I'd rather not add dead code.

> +       [6] = { .name = "ge1" },
> +       [7] = { .name = "ge2" },
> +       [8] = { .name = "timer", .parent_name = "periph" },
> +       [9] = { .name = "intc" },
> +       [10] = { .name = "mc" },
> +       [11] = { .name = "pcm" },
[...]
> +
> +const struct of_device_id of_match_rt2880_clk[] __initconst = {

static?

> +       {
> +               .compatible = "mediatek,mt7620-clock",
> +               .data = clk_mt7620 },
> +       {
> +               .compatible = "mediatek,mt7628-clock",
> +               .data = clk_mt76x8 },
> +       {       /* sentinel */  },
> +};
> +
> +
>  void __init ralink_of_remap(void)
>  {
>         rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
> diff --git a/include/dt-bindings/clock/mt7620-clk.h b/include/dt-bindings/clock/mt7620-clk.h
> new file mode 100644
> index 000000000000..2e70e7df2ed2
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt7620-clk.h
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 NOGUCHI Hiroshi <drvlabo@gmail.com>
> + */
> +
> +#ifndef __DT_BINDINGS_MT7620_CLK_H
> +#define __DT_BINDINGS_MT7620_CLK_H
> +
> +#define MT7620_CLK_CPU         0
> +#define        MT7620_CLK_SYS          1
> +#define        MT7620_CLK_PERIPH       2
> +#define        MT7620_CLK_PCMI2S       3
> +#define        MT7620_CLK_XTAL         4
> +
> +#define MT7620_CLK_MAX         5
> +
> +#endif /* __DT_BINDINGS_MT7620_CLK_H */

Can this file change go into the binding patch?

[RFC 4/5] mips: ralink: mt7628: add nodes for clock provider

[NOGUCHI Hiroshi]

Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7628a.dtsi | 37 ++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8faaecc..67ce939f6b2b 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -26,6 +26,18 @@
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	pll: pll {
+		compatible = "mediatek,mt7620-pll", "syscon";
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+	};
+
+	clkctrl: clkctrl {
+		compatible = "mediatek,mt7628-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+		ralink,sysctl = <&sysc>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus";
 		reg = <0x10000000 0x200000>;
@@ -62,10 +74,29 @@
 			reg = <0x300 0x100>;
 		};
 
+		spi0: spi@b00 {
+			compatible = "ralink,mt7621-spi";
+			reg = <0xb00 0x100>;
+
+			clocks = <&clkctrl 18>;
+			clock-names = "spi";
+
+			resets = <&resetc 18>;
+			reset-names = "spi";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
 		uart0: uartlite@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&clkctrl 12>;
+			clock-names = "uart0";
+
 			resets = <&resetc 12>;
 			reset-names = "uart0";
 
@@ -79,6 +110,9 @@
 			compatible = "ns16550a";
 			reg = <0xd00 0x100>;
 
+			clocks = <&clkctrl 19>;
+			clock-names = "uart1";
+
 			resets = <&resetc 19>;
 			reset-names = "uart1";
 
@@ -92,6 +126,9 @@
 			compatible = "ns16550a";
 			reg = <0xe00 0x100>;
 
+			clocks = <&clkctrl 20>;
+			clock-names = "uart2";
+
 			resets = <&resetc 20>;
 			reset-names = "uart2";
 
-- 
2.20.1

[RFC 5/5] mips: ralink: mt7620: add nodes for clock provider

[NOGUCHI Hiroshi]

Signed-off-by: NOGUCHI Hiroshi <drvlabo@gmail.com>
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi | 34 +++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..bc56b8f9a530 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -5,11 +5,21 @@
 	compatible = "ralink,mtk7620a-soc";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "mips,mips24KEc";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 
+	resetc: reset-controller {
+		compatible = "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
 	cpuintc: cpuintc {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -17,6 +27,18 @@
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	pll: pll {
+		compatible = "mediatek,mt7620-pll", "syscon";
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+	};
+
+	clkctrl: clkctrl {
+		compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+		ralink,sysctl = <&sysc>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus";
 		reg = <0x10000000 0x200000>;
@@ -25,8 +47,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,mt7620a-sysc";
+		sysc: sysc@0 {
+			compatible = "ralink,mt7620a-sysc", "syscon";
 			reg = <0x0 0x100>;
 		};
 
@@ -46,10 +68,16 @@
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		uartlite: uartlite@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&clkctrl 19>;
+			clock-names = "uartl";
+
+			resets = <&resetc 19>;
+			reset-names = "uartl";
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;
 
-- 
2.20.1

Re: [RFC 5/5] mips: ralink: mt7620: add nodes for clock provider

[Stephen Boyd]

Quoting NOGUCHI Hiroshi (2019-03-30 05:33:17)
> @@ -17,6 +27,18 @@
>                 compatible = "mti,cpu-interrupt-controller";
>         };
>  
> +       pll: pll {
> +               compatible = "mediatek,mt7620-pll", "syscon";

This binding looks wrong. It's making a node per clk in DT when we
should be making nodes only for the clk controller. The use of syscon is
also a sign that things are heading in the wrong direction.

> +               #clock-cells = <1>;
> +               clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
> +       };
> +
> +       clkctrl: clkctrl {
> +               compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock";
> +               #clock-cells = <1>;
> +               ralink,sysctl = <&sysc>;
> +       };

Re: [RFC 0/5] MIPS: ralink: peripheral clock gating driver

[John Crispin]

On 30/03/2019 13:33, NOGUCHI Hiroshi wrote:
> This series introduce Mediatek/Ralink SoC's clock gating driver.
> The gating clock items are different at individual SoCs.
> Driver loads gating clock item table defined in individual SoC source files,
> via OF device id data.

Hi,

I am not an expert on clk drivers but looks good at first glance. should 
the main driver not go into drivers/clk/ ?

     John



> NOGUCHI Hiroshi (5):
>    mips: ralink: add rt2880-clock driver
>    mips: ralink: add dt-binding document for rt2880-clock driver
>    mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver
>    mips: ralink: mt7628: add nodes for clock provider
>    mips: ralink: mt7620: add nodes for clock provider
>
>   .../bindings/clock/ralink,rt2880-clock.txt    |  20 +++
>   arch/mips/boot/dts/ralink/mt7620a.dtsi        |  34 ++++-
>   arch/mips/boot/dts/ralink/mt7628a.dtsi        |  37 +++++
>   arch/mips/ralink/Kconfig                      |   6 +
>   arch/mips/ralink/Makefile                     |   2 +
>   arch/mips/ralink/clk.c                        |  30 ++++
>   arch/mips/ralink/common.h                     |   3 +
>   arch/mips/ralink/mt7620.c                     | 132 ++++++++++++++---
>   arch/mips/ralink/rt2880-clk_internal.h        |  21 +++
>   arch/mips/ralink/rt2880-clock.c               | 134 ++++++++++++++++++
>   include/dt-bindings/clock/mt7620-clk.h        |  17 +++
>   11 files changed, 411 insertions(+), 25 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt
>   create mode 100644 arch/mips/ralink/rt2880-clk_internal.h
>   create mode 100644 arch/mips/ralink/rt2880-clock.c
>   create mode 100644 include/dt-bindings/clock/mt7620-clk.h
>