[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Richard Henderson]

There's new support in decodetree for pattern groups.
I believe that patch 5, or something close to it, was
posted as an RFC as part of the original pattern group
patch set, but this cleans that up further.


r~


Richard Henderson (8):
  target/riscv: Name the argument sets for all of insn32 formats
  target/riscv: Use --static-decode for decodetree
  target/riscv: Merge argument sets for insn32 and insn16
  target/riscv: Merge argument decode for RVC shifti
  target/riscv: Use pattern groups in insn16.decode
  target/riscv: Split RVC32 and RVC64 insns into separate files
  target/riscv: Split gen_arith_imm into functional and temp
  target/riscv: Remove spaces from register names

 target/riscv/cpu.c                      |  16 +-
 target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
 target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
 target/riscv/translate.c                |  40 ++-
 target/riscv/Makefile.objs              |  15 +-
 target/riscv/insn16-32.decode           |  28 ++
 target/riscv/insn16-64.decode           |  30 ++
 target/riscv/insn16.decode              | 154 ++++++-----
 target/riscv/insn32.decode              |  10 +-
 9 files changed, 205 insertions(+), 455 deletions(-)
 delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode

-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn32.decode | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6f3ab7aa52..77f794ed70 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,9 +34,13 @@
 %imm_u    12:s20                 !function=ex_shift_12
 
 # Argument sets:
+&empty
 &b    imm rs2 rs1
 &i    imm rs1 rd
+&j    imm rd
 &r    rd rs1 rs2
+&s    imm rs1 rs2
+&u    imm rd
 &shift     shamt rs1 rd
 &atomic    aq rl rs2 rs1 rd
 
@@ -44,9 +48,9 @@
 @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
 @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
 @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
-@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
-@u       ....................      ..... .......         imm=%imm_u          %rd
-@j       ....................      ..... .......         imm=%imm_j          %rd
+@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
+@u       ....................      ..... ....... &u      imm=%imm_u          %rd
+@j       ....................      ..... ....... &j      imm=%imm_j          %rd
 
 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Richard Henderson]

The generated functions are only used within translate.c
and do not need to be global, or declared.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/translate.c   | 2 --
 target/riscv/Makefile.objs | 8 ++++----
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index dd763647ea..7ebd590486 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
     return 8 + reg;
 }
 
-bool decode_insn32(DisasContext *ctx, uint32_t insn);
 /* Include the auto-generated decoder for 32 bit insn */
 #include "decode_insn32.inc.c"
 
@@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rvd.inc.c"
 #include "insn_trans/trans_privileged.inc.c"
 
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
 /* auto-generated decoder*/
 #include "decode_insn16.inc.c"
 #include "insn_trans/trans_rvc.inc.c"
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index 9c6c109327..c7a1b063ed 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
 
 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
 	$(call quiet-command, \
-	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
-	  "GEN", $(TARGET_DIR)$@)
+	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
+          $(decode32-y), "GEN", $(TARGET_DIR)$@)
 
 target/riscv/decode_insn16.inc.c: \
   $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
 	$(call quiet-command, \
-	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
-	  "GEN", $(TARGET_DIR)$@)
+	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
+          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
 
 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
 	target/riscv/decode_insn16.inc.c
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

In some cases this allows us to directly use the insn32
translator function.  In some cases we still need a shim.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 144 ++----------------------
 target/riscv/translate.c                |  13 ++-
 target/riscv/insn16.decode              |  82 ++++++++------
 3 files changed, 69 insertions(+), 170 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index ebcd977b2f..dfb46a2348 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
     return trans_addi(ctx, &arg);
 }
 
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
-    arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
-    return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
-    arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
-    return trans_lw(ctx, &arg);
-}
-
 static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
 {
 #ifdef TARGET_RISCV32
@@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    arg_c_lw tmp;
-    decode_insn16_extract_cl_w(&tmp, ctx->opcode);
-    arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+    arg_i arg;
+    decode_insn16_extract_cl_w(&arg, ctx->opcode);
     return trans_flw(ctx, &arg);
 #else
     /* C.LD ( RV64C/RV128C-only ) */
-    arg_c_fld tmp;
-    decode_insn16_extract_cl_d(&tmp, ctx->opcode);
-    arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
+    arg_i arg;
+    decode_insn16_extract_cl_d(&arg, ctx->opcode);
     return trans_ld(ctx, &arg);
 #endif
 }
 
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
-    arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
-    return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
-    arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
-    return trans_sw(ctx, &arg);
-}
-
 static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
 {
 #ifdef TARGET_RISCV32
@@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    arg_c_sw tmp;
-    decode_insn16_extract_cs_w(&tmp, ctx->opcode);
-    arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+    arg_s arg;
+    decode_insn16_extract_cs_w(&arg, ctx->opcode);
     return trans_fsw(ctx, &arg);
 #else
     /* C.SD ( RV64C/RV128C-only ) */
-    arg_c_fsd tmp;
-    decode_insn16_extract_cs_d(&tmp, ctx->opcode);
-    arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
+    arg_s arg;
+    decode_insn16_extract_cs_d(&arg, ctx->opcode);
     return trans_sd(ctx, &arg);
 #endif
 }
 
-static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
-{
-    if (a->imm == 0) {
-        /* Hint: insn is valid but does not affect state */
-        return true;
-    }
-    arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
-    return trans_addi(ctx, &arg);
-}
-
 static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
 {
 #ifdef TARGET_RISCV32
     /* C.JAL */
-    arg_c_j tmp;
+    arg_j tmp;
     decode_insn16_extract_cj(&tmp, ctx->opcode);
     arg_jal arg = { .rd = 1, .imm = tmp.imm };
     return trans_jal(ctx, &arg);
@@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
 #endif
 }
 
-static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
-{
-    if (a->rd == 0) {
-        /* Hint: insn is valid but does not affect state */
-        return true;
-    }
-    arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
-    return trans_addi(ctx, &arg);
-}
-
 static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
 {
     if (a->rd == 2) {
@@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
     return trans_srai(ctx, &arg);
 }
 
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
-    arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
-    return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
-    arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
-    arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
-    arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
-    arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_and(ctx, &arg);
-}
-
 static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
 {
 #ifdef TARGET_RISCV64
-    arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_subw(ctx, &arg);
+    return trans_subw(ctx, a);
 #else
     return false;
 #endif
@@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
 static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
 {
 #ifdef TARGET_RISCV64
-    arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-    return trans_addw(ctx, &arg);
+    return trans_addw(ctx, a);
 #else
     return false;
 #endif
 }
 
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
-    arg_jal arg = { .rd = 0, .imm = a->imm };
-    return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
-    arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
-    return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
-    arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
-    return trans_bne(ctx, &arg);
-}
-
 static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
 {
     int shamt = a->shamt;
@@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
     return trans_slli(ctx, &arg);
 }
 
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
-    arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
-    return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
-    arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
-    return trans_lw(ctx, &arg);
-}
-
 static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
 {
 #ifdef TARGET_RISCV32
@@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
     return false;
 }
 
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
-    arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
-    return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
-    arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
-    return trans_sw(ctx, &arg);
-}
-
 static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
 {
 #ifdef TARGET_RISCV32
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7ebd590486..9e016d8e50 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -666,8 +666,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 #include "insn_trans/trans_rvd.inc.c"
 #include "insn_trans/trans_privileged.inc.c"
 
-/* auto-generated decoder*/
+/*
+ * Auto-generated decoder.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * initially declared by the 32-bit decoder, which results in duplicate
+ * declaration warnings.  Suppress them.
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+
 #include "decode_insn16.inc.c"
+
+#pragma GCC diagnostic pop
+
 #include "insn_trans/trans_rvc.inc.c"
 
 static void decode_opc(DisasContext *ctx)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 17cc52cf2a..d0cc778bc9 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -40,17 +40,24 @@
 %imm_lui       12:s1 2:5             !function=ex_shift_12
 
 
+# Argument sets imported from insn32.decode:
+&empty                  !extern
+&r         rd rs1 rs2   !extern
+&i         imm rs1 rd   !extern
+&s         imm rs1 rs2  !extern
+&j         imm rd       !extern
+&b         imm rs2 rs1  !extern
+&u         imm rd       !extern
+&shift     shamt rs1 rd !extern
 
 # Argument sets:
 &cl               rs1 rd
 &cl_dw     uimm   rs1 rd
-&ci        imm        rd
 &ciw       nzuimm     rd
 &cs               rs1 rs2
 &cs_dw     uimm   rs1 rs2
 &cb        imm    rs1
 &cr               rd  rs2
-&cj       imm
 &c_shift   shamt      rd
 
 &c_ld      uimm  rd
@@ -61,23 +68,24 @@
 &cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
 
 # Formats 16:
-@cr        ....  ..... .....  .. &cr                      rs2=%rs2_5  %rd
-@ci        ... . ..... .....  .. &ci     imm=%imm_ci                  %rd
+@cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
+@ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
 @ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
-@cl_d      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
-@cl_w      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
+@cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
+@cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
 @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
 @cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
-@cs_2      ... ... ... .. ... .. &cr                      rd=%rs1_3   rs2=%rs2_3
-@cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
-@cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
-@cb        ... ... ... .. ... .. &cb     imm=%imm_cb      rs1=%rs1_3
-@cj        ...    ........... .. &cj     imm=%imm_cj
+@cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
+@cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
+@cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
+@cj        ...    ........... .. &j      imm=%imm_cj
+@cb_z      ... ... ... .. ... .. &b      imm=%imm_cb      rs1=%rs1_3  rs2=0
 
-@c_ld      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_ld  %rd
-@c_lw      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_lw  %rd
-@c_sd      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sd  rs2=%rs2_5
-@c_sw      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sw  rs2=%rs2_5
+@c_ldsp    ... . .....  ..... .. &i      imm=%uimm_6bit_ld rs1=2 %rd
+@c_lwsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lw rs1=2 %rd
+@c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
+@c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
+@c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
 
 @c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
 @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
@@ -85,45 +93,47 @@
 @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
     uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
 
-@c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
-@c_shift2       ... . .. ... ..... .. &c_shift rd=%rd    shamt=%nzuimm_6bit
+@c_shift        ... . .. ... ..... .. \
+                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
+@c_shift2       ... . .. ... ..... .. \
+                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
 
-@c_andi         ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
+@c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
 
 # *** RV64C Standard Extension (Quadrant 0) ***
 c_addi4spn        000    ........ ... 00 @ciw
-c_fld             001  ... ... .. ... 00 @cl_d
-c_lw              010  ... ... .. ... 00 @cl_w
+fld               001  ... ... .. ... 00 @cl_d
+lw                010  ... ... .. ... 00 @cl_w
 c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
-c_fsd             101  ... ... .. ... 00 @cs_d
-c_sw              110  ... ... .. ... 00 @cs_w
+fsd               101  ... ... .. ... 00 @cs_d
+sw                110  ... ... .. ... 00 @cs_w
 c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
 
 # *** RV64C Standard Extension (Quadrant 1) ***
-c_addi            000 .  .....  ..... 01 @ci
+addi              000 .  .....  ..... 01 @ci
 c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
-c_li              010 .  .....  ..... 01 @ci
+addi              010 .  .....  ..... 01 @c_li
 c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
 c_srli            100 . 00 ...  ..... 01 @c_shift
 c_srai            100 . 01 ...  ..... 01 @c_shift
-c_andi            100 . 10 ...  ..... 01 @c_andi
-c_sub             100 0 11 ... 00 ... 01 @cs_2
-c_xor             100 0 11 ... 01 ... 01 @cs_2
-c_or              100 0 11 ... 10 ... 01 @cs_2
-c_and             100 0 11 ... 11 ... 01 @cs_2
+andi              100 . 10 ...  ..... 01 @c_andi
+sub               100 0 11 ... 00 ... 01 @cs_2
+xor               100 0 11 ... 01 ... 01 @cs_2
+or                100 0 11 ... 10 ... 01 @cs_2
+and               100 0 11 ... 11 ... 01 @cs_2
 c_subw            100 1 11 ... 00 ... 01 @cs_2
 c_addw            100 1 11 ... 01 ... 01 @cs_2
-c_j               101     ........... 01 @cj
-c_beqz            110  ... ...  ..... 01 @cb
-c_bnez            111  ... ...  ..... 01 @cb
+jal               101     ........... 01 @cj    rd=0  # C.J
+beq               110  ... ...  ..... 01 @cb_z
+bne               111  ... ...  ..... 01 @cb_z
 
 # *** RV64C Standard Extension (Quadrant 2) ***
 c_slli            000 .  .....  ..... 10 @c_shift2
-c_fldsp           001 .  .....  ..... 10 @c_ld
-c_lwsp            010 .  .....  ..... 10 @c_lw
+fld               001 .  .....  ..... 10 @c_ldsp
+lw                010 .  .....  ..... 10 @c_lwsp
 c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
 c_jr_mv           100 0  .....  ..... 10 @cr
 c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
-c_fsdsp           101   ......  ..... 10 @c_sd
-c_swsp            110 .  .....  ..... 10 @c_sw
+fsd               101   ......  ..... 10 @c_sdsp
+sw                110 .  .....  ..... 10 @c_swsp
 c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Richard Henderson]

Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti.  This can be handled with !function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 47 -------------------------
 target/riscv/translate.c                |  6 ++++
 target/riscv/insn16.decode              | 12 +++----
 3 files changed, 12 insertions(+), 53 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index dfb46a2348..691b1e2725 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
     return false;
 }
 
-static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
-{
-    int shamt = a->shamt;
-    if (shamt == 0) {
-        /* For RV128 a shamt of 0 means a shift by 64 */
-        shamt = 64;
-    }
-    /* Ensure, that shamt[5] is zero for RV32 */
-    if (shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
-    return trans_srli(ctx, &arg);
-}
-
-static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
-{
-    int shamt = a->shamt;
-    if (shamt == 0) {
-        /* For RV128 a shamt of 0 means a shift by 64 */
-        shamt = 64;
-    }
-    /* Ensure, that shamt[5] is zero for RV32 */
-    if (shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
-    return trans_srai(ctx, &arg);
-}
 
 static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
 {
@@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
 #endif
 }
 
-static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
-{
-    int shamt = a->shamt;
-    if (shamt == 0) {
-        /* For RV128 a shamt of 0 means a shift by 64 */
-        shamt = 64;
-    }
-    /* Ensure, that shamt[5] is zero for RV32 */
-    if (shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
-    return trans_slli(ctx, &arg);
-}
-
 static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
 {
 #ifdef TARGET_RISCV32
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9e016d8e50..a1cd29f80f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -538,6 +538,12 @@ static int ex_rvc_register(int reg)
     return 8 + reg;
 }
 
+static int ex_rvc_shifti(int imm)
+{
+    /* For RV128 a shamt of 0 means a shift by 64. */
+    return imm ? imm : 64;
+}
+
 /* Include the auto-generated decoder for 32 bit insn */
 #include "decode_insn32.inc.c"
 
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index d0cc778bc9..add9cf3923 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -30,7 +30,7 @@
 %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
 %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
 
-%nzuimm_6bit   12:1 2:5
+%shimm_6bit   12:1 2:5               !function=ex_rvc_shifti
 %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
 %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
 %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
@@ -94,9 +94,9 @@
     uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
 
 @c_shift        ... . .. ... ..... .. \
-                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
+                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
 @c_shift2       ... . .. ... ..... .. \
-                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
+                &shift rd=%rd rs1=%rd shamt=%shimm_6bit
 
 @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
 
@@ -114,8 +114,8 @@ addi              000 .  .....  ..... 01 @ci
 c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
 addi              010 .  .....  ..... 01 @c_li
 c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
-c_srli            100 . 00 ...  ..... 01 @c_shift
-c_srai            100 . 01 ...  ..... 01 @c_shift
+srli              100 . 00 ...  ..... 01 @c_shift
+srai              100 . 01 ...  ..... 01 @c_shift
 andi              100 . 10 ...  ..... 01 @c_andi
 sub               100 0 11 ... 00 ... 01 @cs_2
 xor               100 0 11 ... 01 ... 01 @cs_2
@@ -128,7 +128,7 @@ beq               110  ... ...  ..... 01 @cb_z
 bne               111  ... ...  ..... 01 @cb_z
 
 # *** RV64C Standard Extension (Quadrant 2) ***
-c_slli            000 .  .....  ..... 10 @c_shift2
+slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
 lw                010 .  .....  ..... 10 @c_lwsp
 c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode

[Richard Henderson]

This eliminates about half of the complicated decode
bits within insn_trans/trans_rvc.inc.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 63 -------------------------
 target/riscv/insn_trans/trans_rvi.inc.c |  6 +++
 target/riscv/insn16.decode              | 29 +++++++++---
 3 files changed, 29 insertions(+), 69 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 691b1e2725..43bff97f66 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -18,16 +18,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
-{
-    if (a->nzuimm == 0) {
-        /* Reserved in ISA */
-        return false;
-    }
-    arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
-    return trans_addi(ctx, &arg);
-}
-
 static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
 {
 #ifdef TARGET_RISCV32
@@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
 #endif
 }
 
-static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
-{
-    if (a->rd == 2) {
-        /* C.ADDI16SP */
-        arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
-        return trans_addi(ctx, &arg);
-    } else if (a->imm_lui != 0) {
-        /* C.LUI */
-        if (a->rd == 0) {
-            /* Hint: insn is valid but does not affect state */
-            return true;
-        }
-        arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
-        return trans_lui(ctx, &arg);
-    }
-    return false;
-}
-
-
 static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
 {
 #ifdef TARGET_RISCV64
@@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
     return false;
 }
 
-static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
-{
-    if (a->rd != 0 && a->rs2 == 0) {
-        /* C.JR */
-        arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
-        return trans_jalr(ctx, &arg);
-    } else if (a->rd != 0 && a->rs2 != 0) {
-        /* C.MV */
-        arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
-        return trans_add(ctx, &arg);
-    }
-    return false;
-}
-
-static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
-{
-    if (a->rd == 0 && a->rs2 == 0) {
-        /* C.EBREAK */
-        arg_ebreak arg = { };
-        return trans_ebreak(ctx, &arg);
-    } else if (a->rd != 0) {
-        if (a->rs2 == 0) {
-            /* C.JALR */
-            arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
-            return trans_jalr(ctx, &arg);
-        } else {
-            /* C.ADD */
-            arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
-            return trans_add(ctx, &arg);
-        }
-    }
-    return false;
-}
-
 static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
 {
 #ifdef TARGET_RISCV32
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index d420a4d8b2..caf91f9a05 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -18,6 +18,12 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+static bool trans_illegal(DisasContext *ctx, arg_empty *a)
+{
+    gen_exception_illegal(ctx);
+    return true;
+}
+
 static bool trans_lui(DisasContext *ctx, arg_lui *a)
 {
     if (a->rd != 0) {
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index add9cf3923..3c79edf1c9 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -70,7 +70,6 @@
 # Formats 16:
 @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
 @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
-@ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
 @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
 @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
 @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
@@ -86,8 +85,12 @@
 @c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
 @c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
 @c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
+@c_lui     ... . .....  ..... .. &u      imm=%imm_lui %rd
+@c_jalr    ... . .....  ..... .. &i      imm=0 rs1=%rd
+@c_mv      ... . ..... .....  .. &i      imm=0 rs1=%rs2_5 %rd
 
-@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
+@c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
+@c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
 @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
     uimm_ldsp=%uimm_6bit_ld %rd
 @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
@@ -101,7 +104,11 @@
 @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
 
 # *** RV64C Standard Extension (Quadrant 0) ***
-c_addi4spn        000    ........ ... 00 @ciw
+{
+  # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
+  illegal         000  000 000 00 --- 00
+  addi            000  ... ... .. ... 00 @c_addi4spn
+}
 fld               001  ... ... .. ... 00 @cl_d
 lw                010  ... ... .. ... 00 @cl_w
 c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
@@ -113,7 +120,10 @@ c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
 addi              000 .  .....  ..... 01 @ci
 c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
 addi              010 .  .....  ..... 01 @c_li
-c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
+{
+  addi            011 .  00010  ..... 01 @c_addi16sp
+  lui             011 .  .....  ..... 01 @c_lui
+}
 srli              100 . 00 ...  ..... 01 @c_shift
 srai              100 . 01 ...  ..... 01 @c_shift
 andi              100 . 10 ...  ..... 01 @c_andi
@@ -132,8 +142,15 @@ slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
 lw                010 .  .....  ..... 10 @c_lwsp
 c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
-c_jr_mv           100 0  .....  ..... 10 @cr
-c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
+{
+  jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
+  addi            100 0  .....  ..... 10 @c_mv
+}
+{
+  ebreak          100 1  00000  00000 10
+  jalr            100 1  .....  00000 10 @c_jalr rd=1  # C.JALR
+  add             100 1  .....  ..... 10 @cr
+}
 fsd               101   ......  ..... 10 @c_sdsp
 sw                110 .  .....  ..... 10 @c_swsp
 c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Richard Henderson]

This eliminates all functions in insn_trans/trans_rvc.inc.c,
so the entire file can be removed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
 target/riscv/translate.c                |   2 -
 target/riscv/Makefile.objs              |   9 +-
 target/riscv/insn16-32.decode           |  28 ++++++
 target/riscv/insn16-64.decode           |  30 +++++++
 target/riscv/insn16.decode              |  35 +-------
 6 files changed, 67 insertions(+), 152 deletions(-)
 delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
deleted file mode 100644
index 43bff97f66..0000000000
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * RISC-V translation routines for the RVC Compressed Instruction Set.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
-    /* C.FLW ( RV32FC-only ) */
-    REQUIRE_FPU;
-    REQUIRE_EXT(ctx, RVF);
-
-    arg_i arg;
-    decode_insn16_extract_cl_w(&arg, ctx->opcode);
-    return trans_flw(ctx, &arg);
-#else
-    /* C.LD ( RV64C/RV128C-only ) */
-    arg_i arg;
-    decode_insn16_extract_cl_d(&arg, ctx->opcode);
-    return trans_ld(ctx, &arg);
-#endif
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
-    /* C.FSW ( RV32FC-only ) */
-    REQUIRE_FPU;
-    REQUIRE_EXT(ctx, RVF);
-
-    arg_s arg;
-    decode_insn16_extract_cs_w(&arg, ctx->opcode);
-    return trans_fsw(ctx, &arg);
-#else
-    /* C.SD ( RV64C/RV128C-only ) */
-    arg_s arg;
-    decode_insn16_extract_cs_d(&arg, ctx->opcode);
-    return trans_sd(ctx, &arg);
-#endif
-}
-
-static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
-{
-#ifdef TARGET_RISCV32
-    /* C.JAL */
-    arg_j tmp;
-    decode_insn16_extract_cj(&tmp, ctx->opcode);
-    arg_jal arg = { .rd = 1, .imm = tmp.imm };
-    return trans_jal(ctx, &arg);
-#else
-    /* C.ADDIW */
-    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
-    return trans_addiw(ctx, &arg);
-#endif
-}
-
-static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
-{
-#ifdef TARGET_RISCV64
-    return trans_subw(ctx, a);
-#else
-    return false;
-#endif
-}
-
-static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
-{
-#ifdef TARGET_RISCV64
-    return trans_addw(ctx, a);
-#else
-    return false;
-#endif
-}
-
-static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
-{
-#ifdef TARGET_RISCV32
-    /* C.FLWSP */
-    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
-    return trans_flw(ctx, &arg_flw);
-#else
-    /* C.LDSP */
-    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
-    return trans_ld(ctx, &arg_ld);
-#endif
-    return false;
-}
-
-static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
-{
-#ifdef TARGET_RISCV32
-    /* C.FSWSP */
-    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
-    return trans_fsw(ctx, &a_fsw);
-#else
-    /* C.SDSP */
-    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
-    return trans_sd(ctx, &a_sd);
-#endif
-}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a1cd29f80f..50d8f58e4b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 
 #pragma GCC diagnostic pop
 
-#include "insn_trans/trans_rvc.inc.c"
-
 static void decode_opc(DisasContext *ctx)
 {
     /* check for compressed insn */
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index c7a1b063ed..b1c79bc1d1 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
 decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
 
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
 	$(call quiet-command, \
 	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
           $(decode32-y), "GEN", $(TARGET_DIR)$@)
 
-target/riscv/decode_insn16.inc.c: \
-  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
 	$(call quiet-command, \
 	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
-          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
+          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
 
 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
 	target/riscv/decode_insn16.inc.c
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
new file mode 100644
index 0000000000..0819b17028
--- /dev/null
+++ b/target/riscv/insn16-32.decode
@@ -0,0 +1,28 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw               011  ... ... .. ... 00 @cl_w
+fsw               111  ... ... .. ... 00 @cs_w
+
+# *** RV32C Standard Extension (Quadrant 1) ***
+jal               001     ........... 01 @cj    rd=1  # C.JAL
+
+# *** RV32C Standard Extension (Quadrant 2) ***
+flw               011 .  .....  ..... 10 @c_lwsp
+fsw               111 .  .....  ..... 10 @c_swsp
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
new file mode 100644
index 0000000000..055859d29f
--- /dev/null
+++ b/target/riscv/insn16-64.decode
@@ -0,0 +1,30 @@
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld                011  ... ... .. ... 00 @cl_d
+sd                111  ... ... .. ... 00 @cs_d
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+addiw             001 .  .....  ..... 01 @ci
+subw              100 1 11 ... 00 ... 01 @cs_2
+addw              100 1 11 ... 01 ... 01 @cs_2
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+ld                011 .  .....  ..... 10 @c_ldsp
+sd                111 .  .....  ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 3c79edf1c9..433c0e8c68 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -50,30 +50,12 @@
 &u         imm rd       !extern
 &shift     shamt rs1 rd !extern
 
-# Argument sets:
-&cl               rs1 rd
-&cl_dw     uimm   rs1 rd
-&ciw       nzuimm     rd
-&cs               rs1 rs2
-&cs_dw     uimm   rs1 rs2
-&cb        imm    rs1
-&cr               rd  rs2
-&c_shift   shamt      rd
-
-&c_ld      uimm  rd
-&c_sd      uimm  rs2
-
-&caddi16sp_lui  imm_lui imm_addi16sp rd
-&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
-&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
 
 # Formats 16:
 @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
 @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
 @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
 @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
-@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
-@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
 @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
 @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
 @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
@@ -91,10 +73,6 @@
 
 @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
 @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
-@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
-    uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
-    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
 
 @c_shift        ... . .. ... ..... .. \
                 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
@@ -103,7 +81,7 @@
 
 @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
 
-# *** RV64C Standard Extension (Quadrant 0) ***
+# *** RV32/64C Standard Extension (Quadrant 0) ***
 {
   # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
   illegal         000  000 000 00 --- 00
@@ -111,14 +89,11 @@
 }
 fld               001  ... ... .. ... 00 @cl_d
 lw                010  ... ... .. ... 00 @cl_w
-c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
 fsd               101  ... ... .. ... 00 @cs_d
 sw                110  ... ... .. ... 00 @cs_w
-c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
 
-# *** RV64C Standard Extension (Quadrant 1) ***
+# *** RV32/64C Standard Extension (Quadrant 1) ***
 addi              000 .  .....  ..... 01 @ci
-c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
 addi              010 .  .....  ..... 01 @c_li
 {
   addi            011 .  00010  ..... 01 @c_addi16sp
@@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
 xor               100 0 11 ... 01 ... 01 @cs_2
 or                100 0 11 ... 10 ... 01 @cs_2
 and               100 0 11 ... 11 ... 01 @cs_2
-c_subw            100 1 11 ... 00 ... 01 @cs_2
-c_addw            100 1 11 ... 01 ... 01 @cs_2
 jal               101     ........... 01 @cj    rd=0  # C.J
 beq               110  ... ...  ..... 01 @cb_z
 bne               111  ... ...  ..... 01 @cb_z
 
-# *** RV64C Standard Extension (Quadrant 2) ***
+# *** RV32/64C Standard Extension (Quadrant 2) ***
 slli              000 .  .....  ..... 10 @c_shift2
 fld               001 .  .....  ..... 10 @c_ldsp
 lw                010 .  .....  ..... 10 @c_lwsp
-c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
 {
   jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
   addi            100 0  .....  ..... 10 @c_mv
@@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
 }
 fsd               101   ......  ..... 10 @c_sdsp
 sw                110 .  .....  ..... 10 @c_swsp
-c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp

[Richard Henderson]

The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
 target/riscv/translate.c                | 19 +++++++++++++++++--
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index caf91f9a05..620df5f323 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
 
 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 {
-    return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
+    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
 }
 
 static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
@@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
 
 static bool trans_slti(DisasContext *ctx, arg_slti *a)
 {
-    return gen_arith_imm(ctx, a, &gen_slt);
+    return gen_arith_imm_tl(ctx, a, &gen_slt);
 }
 
 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 {
-    return gen_arith_imm(ctx, a, &gen_sltu);
+    return gen_arith_imm_tl(ctx, a, &gen_sltu);
 }
 
 static bool trans_xori(DisasContext *ctx, arg_xori *a)
 {
-    return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
+    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
 }
 static bool trans_ori(DisasContext *ctx, arg_ori *a)
 {
-    return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
+    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
 }
 static bool trans_andi(DisasContext *ctx, arg_andi *a)
 {
-    return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
+    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
 }
 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 {
@@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
 #ifdef TARGET_RISCV64
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
-    return gen_arith_imm(ctx, a, &gen_addw);
+    return gen_arith_imm_tl(ctx, a, &gen_addw);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 50d8f58e4b..fb66e886bf 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -547,8 +547,23 @@ static int ex_rvc_shifti(int imm)
 /* Include the auto-generated decoder for 32 bit insn */
 #include "decode_insn32.inc.c"
 
-static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
-                          void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
+                             void (*func)(TCGv, TCGv, target_long))
+{
+    TCGv source1;
+    source1 = tcg_temp_new();
+
+    gen_get_gpr(source1, a->rs1);
+
+    (*func)(source1, source1, a->imm);
+
+    gen_set_gpr(a->rd, source1);
+    tcg_temp_free(source1);
+    return true;
+}
+
+static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
+                             void (*func)(TCGv, TCGv, TCGv))
 {
     TCGv source1, source2;
     source1 = tcg_temp_new();
-- 
2.17.1

[Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names

[Richard Henderson]

These extra spaces make the "-d op" dump look weird.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d61bce6d55..624528efb5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -29,17 +29,17 @@
 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
 
 const char * const riscv_int_regnames[] = {
-  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",
-  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",
-  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",
-  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "
+  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
+  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
+  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
+  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
 };
 
 const char * const riscv_fpr_regnames[] = {
-  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",
-  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",
-  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",
-  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"
+  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
+  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
+  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
+  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
 };
 
 const char * const riscv_excp_names[] = {
-- 
2.17.1

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Alistair Francis]

On Sun, Mar 31, 2019 at 8:12 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn32.decode | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f3ab7aa52..77f794ed70 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,9 +34,13 @@
>  %imm_u    12:s20                 !function=ex_shift_12
>
>  # Argument sets:
> +&empty
>  &b    imm rs2 rs1
>  &i    imm rs1 rd
> +&j    imm rd
>  &r    rd rs1 rs2
> +&s    imm rs1 rs2
> +&u    imm rd
>  &shift     shamt rs1 rd
>  &atomic    aq rl rs2 rs1 rd
>
> @@ -44,9 +48,9 @@
>  @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
>  @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
>  @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
> -@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
> -@u       ....................      ..... .......         imm=%imm_u          %rd
> -@j       ....................      ..... .......         imm=%imm_j          %rd
> +@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
> +@u       ....................      ..... ....... &u      imm=%imm_u          %rd
> +@j       ....................      ..... ....... &j      imm=%imm_j          %rd
>
>  @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
>  @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
> --
> 2.17.1
>
>

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Alistair Francis]

On Sun, Mar 31, 2019 at 8:12 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn32.decode | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f3ab7aa52..77f794ed70 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,9 +34,13 @@
>  %imm_u    12:s20                 !function=ex_shift_12
>
>  # Argument sets:
> +&empty
>  &b    imm rs2 rs1
>  &i    imm rs1 rd
> +&j    imm rd
>  &r    rd rs1 rs2
> +&s    imm rs1 rs2
> +&u    imm rd
>  &shift     shamt rs1 rd
>  &atomic    aq rl rs2 rs1 rd
>
> @@ -44,9 +48,9 @@
>  @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
>  @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
>  @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
> -@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
> -@u       ....................      ..... .......         imm=%imm_u          %rd
> -@j       ....................      ..... .......         imm=%imm_j          %rd
> +@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
> +@u       ....................      ..... ....... &u      imm=%imm_u          %rd
> +@j       ....................      ..... ....... &j      imm=%imm_j          %rd
>
>  @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
>  @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
> --
> 2.17.1
>
>

Re: [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Alistair Francis]

On Sun, Mar 31, 2019 at 8:15 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The generated functions are only used within translate.c
> and do not need to be global, or declared.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c   | 2 --
>  target/riscv/Makefile.objs | 8 ++++----
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index dd763647ea..7ebd590486 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> -bool decode_insn32(DisasContext *ctx, uint32_t insn);
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -bool decode_insn16(DisasContext *ctx, uint16_t insn);
>  /* auto-generated decoder*/
>  #include "decode_insn16.inc.c"
>  #include "insn_trans/trans_rvc.inc.c"
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index 9c6c109327..c7a1b063ed 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>         $(call quiet-command, \
> -         $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
> -         "GEN", $(TARGET_DIR)$@)
> +         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> +          $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/decode_insn16.inc.c: \
>    $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
>         $(call quiet-command, \
> -         $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
> -         "GEN", $(TARGET_DIR)$@)
> +         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> +          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>         target/riscv/decode_insn16.inc.c
> --
> 2.17.1
>
>

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Alistair Francis]

On Sun, Mar 31, 2019 at 8:15 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The generated functions are only used within translate.c
> and do not need to be global, or declared.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c   | 2 --
>  target/riscv/Makefile.objs | 8 ++++----
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index dd763647ea..7ebd590486 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> -bool decode_insn32(DisasContext *ctx, uint32_t insn);
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -bool decode_insn16(DisasContext *ctx, uint16_t insn);
>  /* auto-generated decoder*/
>  #include "decode_insn16.inc.c"
>  #include "insn_trans/trans_rvc.inc.c"
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index 9c6c109327..c7a1b063ed 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>         $(call quiet-command, \
> -         $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
> -         "GEN", $(TARGET_DIR)$@)
> +         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> +          $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/decode_insn16.inc.c: \
>    $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
>         $(call quiet-command, \
> -         $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
> -         "GEN", $(TARGET_DIR)$@)
> +         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> +          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>         target/riscv/decode_insn16.inc.c
> --
> 2.17.1
>
>

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Bastian Koppelmann]

On 4/1/19 5:11 AM, Richard Henderson wrote:
>   
>   # *** RV64C Standard Extension (Quadrant 0) ***
>   c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w

This leads to a redefinition of arg_lw and arg_fld for which clang emits 
a warning as found by Peter as he wanted to merge the original pull 
request for RISC-V-dt. The same goes for all other merged args.

Cheers,

Bastian

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Bastian Koppelmann]

On 4/1/19 5:11 AM, Richard Henderson wrote:
>   
>   # *** RV64C Standard Extension (Quadrant 0) ***
>   c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w

This leads to a redefinition of arg_lw and arg_fld for which clang emits 
a warning as found by Peter as he wanted to merge the original pull 
request for RISC-V-dt. The same goes for all other merged args.

Cheers,

Bastian

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Bastian Koppelmann]

On 4/1/19 5:11 AM, Richard Henderson wrote:
>   
>   # *** RV64C Standard Extension (Quadrant 0) ***
>   c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w

This leads to a redefinition of arg_lw and arg_fld for which clang emits 
a warning as found by Peter as he wanted to merge the original pull 
request for RISC-V-dt. The same goes for all other merged args.

Cheers,

Bastian

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 2:02 AM, Bastian Koppelmann wrote:
> 
> On 4/1/19 5:11 AM, Richard Henderson wrote:
>>     # *** RV64C Standard Extension (Quadrant 0) ***
>>   c_addi4spn        000    ........ ... 00 @ciw
>> -c_fld             001  ... ... .. ... 00 @cl_d
>> -c_lw              010  ... ... .. ... 00 @cl_w
>> +fld               001  ... ... .. ... 00 @cl_d
>> +lw                010  ... ... .. ... 00 @cl_w
> 
> This leads to a redefinition of arg_lw and arg_fld for which clang emits a
> warning as found by Peter as he wanted to merge the original pull request for
> RISC-V-dt. The same goes for all other merged args.

I thought that would be handled by the #pragma, but it seems
that we need another one for clang-6.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..c96c616539 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  */
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wredundant-decls"
+#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

 #include "decode_insn16.inc.c"

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 2:02 AM, Bastian Koppelmann wrote:
> 
> On 4/1/19 5:11 AM, Richard Henderson wrote:
>>     # *** RV64C Standard Extension (Quadrant 0) ***
>>   c_addi4spn        000    ........ ... 00 @ciw
>> -c_fld             001  ... ... .. ... 00 @cl_d
>> -c_lw              010  ... ... .. ... 00 @cl_w
>> +fld               001  ... ... .. ... 00 @cl_d
>> +lw                010  ... ... .. ... 00 @cl_w
> 
> This leads to a redefinition of arg_lw and arg_fld for which clang emits a
> warning as found by Peter as he wanted to merge the original pull request for
> RISC-V-dt. The same goes for all other merged args.

I thought that would be handled by the #pragma, but it seems
that we need another one for clang-6.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..c96c616539 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  */
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wredundant-decls"
+#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

 #include "decode_insn16.inc.c"

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 2:02 AM, Bastian Koppelmann wrote:
> 
> On 4/1/19 5:11 AM, Richard Henderson wrote:
>>     # *** RV64C Standard Extension (Quadrant 0) ***
>>   c_addi4spn        000    ........ ... 00 @ciw
>> -c_fld             001  ... ... .. ... 00 @cl_d
>> -c_lw              010  ... ... .. ... 00 @cl_w
>> +fld               001  ... ... .. ... 00 @cl_d
>> +lw                010  ... ... .. ... 00 @cl_w
> 
> This leads to a redefinition of arg_lw and arg_fld for which clang emits a
> warning as found by Peter as he wanted to merge the original pull request for
> RISC-V-dt. The same goes for all other merged args.

I thought that would be handled by the #pragma, but it seems
that we need another one for clang-6.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..c96c616539 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  */
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wredundant-decls"
+#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

 #include "decode_insn16.inc.c"

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 7:22 AM, Richard Henderson wrote:
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fb66e886bf..c96c616539 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>   */
>  #pragma GCC diagnostic push
>  #pragma GCC diagnostic ignored "-Wredundant-decls"
> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
we've got a configure test for the pragmas, which I suppose I ought to use.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..b62ca04281 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -693,12 +693,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  * initially declared by the 32-bit decoder, which results in duplicate
  * declaration warnings.  Suppress them.
  */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wredundant-decls"
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+#  pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif

 #include "decode_insn16.inc.c"

-#pragma GCC diagnostic pop
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif

 static void decode_opc(DisasContext *ctx)
 {

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 7:22 AM, Richard Henderson wrote:
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fb66e886bf..c96c616539 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>   */
>  #pragma GCC diagnostic push
>  #pragma GCC diagnostic ignored "-Wredundant-decls"
> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
we've got a configure test for the pragmas, which I suppose I ought to use.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..b62ca04281 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -693,12 +693,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  * initially declared by the 32-bit decoder, which results in duplicate
  * declaration warnings.  Suppress them.
  */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wredundant-decls"
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+#  pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif

 #include "decode_insn16.inc.c"

-#pragma GCC diagnostic pop
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif

 static void decode_opc(DisasContext *ctx)
 {

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 7:22 AM, Richard Henderson wrote:
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index fb66e886bf..c96c616539 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>   */
>  #pragma GCC diagnostic push
>  #pragma GCC diagnostic ignored "-Wredundant-decls"
> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"

Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
we've got a configure test for the pragmas, which I suppose I ought to use.


r~


diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fb66e886bf..b62ca04281 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -693,12 +693,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  * initially declared by the 32-bit decoder, which results in duplicate
  * declaration warnings.  Suppress them.
  */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wredundant-decls"
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+#  pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif

 #include "decode_insn16.inc.c"

-#pragma GCC diagnostic pop
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif

 static void decode_opc(DisasContext *ctx)
 {

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Thomas Huth]

On 16/04/2019 19.32, Richard Henderson wrote:
> On 4/16/19 7:22 AM, Richard Henderson wrote:
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index fb66e886bf..c96c616539 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>>   */
>>  #pragma GCC diagnostic push
>>  #pragma GCC diagnostic ignored "-Wredundant-decls"
>> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> 
> Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
> we've got a configure test for the pragmas, which I suppose I ought to use.

I wonder whether we should maybe always add "-Wno-typedef-redefinition"
in the configure script when we detect clang. All the versions of GCC
that we currently support seem to ignore typedef redefinitions anyway...?
(I think I've seen that warning with GCC in the past, too, see e.g.
commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
to be the case anymore with GCC >= 4.8)

 Thomas

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Thomas Huth]

On 16/04/2019 19.32, Richard Henderson wrote:
> On 4/16/19 7:22 AM, Richard Henderson wrote:
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index fb66e886bf..c96c616539 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>>   */
>>  #pragma GCC diagnostic push
>>  #pragma GCC diagnostic ignored "-Wredundant-decls"
>> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> 
> Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
> we've got a configure test for the pragmas, which I suppose I ought to use.

I wonder whether we should maybe always add "-Wno-typedef-redefinition"
in the configure script when we detect clang. All the versions of GCC
that we currently support seem to ignore typedef redefinitions anyway...?
(I think I've seen that warning with GCC in the past, too, see e.g.
commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
to be the case anymore with GCC >= 4.8)

 Thomas

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Thomas Huth]

On 16/04/2019 19.32, Richard Henderson wrote:
> On 4/16/19 7:22 AM, Richard Henderson wrote:
>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
>> index fb66e886bf..c96c616539 100644
>> --- a/target/riscv/translate.c
>> +++ b/target/riscv/translate.c
>> @@ -695,6 +695,7 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>>   */
>>  #pragma GCC diagnostic push
>>  #pragma GCC diagnostic ignored "-Wredundant-decls"
>> +#pragma GCC diagnostic ignored "-Wtypedef-redefinition"
> 
> Bah.  Of course gcc doesn't know this one.  And looking closer elsewhere, I see
> we've got a configure test for the pragmas, which I suppose I ought to use.

I wonder whether we should maybe always add "-Wno-typedef-redefinition"
in the configure script when we detect clang. All the versions of GCC
that we currently support seem to ignore typedef redefinitions anyway...?
(I think I've seen that warning with GCC in the past, too, see e.g.
commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
to be the case anymore with GCC >= 4.8)

 Thomas

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 9:43 AM, Thomas Huth wrote:
> I wonder whether we should maybe always add "-Wno-typedef-redefinition"
> in the configure script when we detect clang. All the versions of GCC
> that we currently support seem to ignore typedef redefinitions anyway...?
> (I think I've seen that warning with GCC in the past, too, see e.g.
> commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
> to be the case anymore with GCC >= 4.8)

That would work for me too.  Anything to minimize Werror divergence between the
two compilers makes less work.


r~

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 9:43 AM, Thomas Huth wrote:
> I wonder whether we should maybe always add "-Wno-typedef-redefinition"
> in the configure script when we detect clang. All the versions of GCC
> that we currently support seem to ignore typedef redefinitions anyway...?
> (I think I've seen that warning with GCC in the past, too, see e.g.
> commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
> to be the case anymore with GCC >= 4.8)

That would work for me too.  Anything to minimize Werror divergence between the
two compilers makes less work.


r~

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/16/19 9:43 AM, Thomas Huth wrote:
> I wonder whether we should maybe always add "-Wno-typedef-redefinition"
> in the configure script when we detect clang. All the versions of GCC
> that we currently support seem to ignore typedef redefinitions anyway...?
> (I think I've seen that warning with GCC in the past, too, see e.g.
> commit eeb61d4f8270a6849d9a584fc83da3869b79066d, but that does not seem
> to be the case anymore with GCC >= 4.8)

That would work for me too.  Anything to minimize Werror divergence between the
two compilers makes less work.


r~

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:48 PDT (-0700), richard.henderson@linaro.org wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn32.decode | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f3ab7aa52..77f794ed70 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,9 +34,13 @@
>  %imm_u    12:s20                 !function=ex_shift_12
>
>  # Argument sets:
> +&empty

If I understand decodetree correctly, this isn't used until patch 5.
Otherwise,

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

I don't care enough about this to make you re-spin the patch set, so I'm OK
taking it as it stands unless there's anything else that crops up as I look
through the rest of the patches...

Thanks!

>  &b    imm rs2 rs1
>  &i    imm rs1 rd
> +&j    imm rd
>  &r    rd rs1 rs2
> +&s    imm rs1 rs2
> +&u    imm rd
>  &shift     shamt rs1 rd
>  &atomic    aq rl rs2 rs1 rd
>
> @@ -44,9 +48,9 @@
>  @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
>  @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
>  @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
> -@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
> -@u       ....................      ..... .......         imm=%imm_u          %rd
> -@j       ....................      ..... .......         imm=%imm_j          %rd
> +@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
> +@u       ....................      ..... ....... &u      imm=%imm_u          %rd
> +@j       ....................      ..... ....... &j      imm=%imm_j          %rd
>
>  @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
>  @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:48 PDT (-0700), richard.henderson@linaro.org wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn32.decode | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f3ab7aa52..77f794ed70 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,9 +34,13 @@
>  %imm_u    12:s20                 !function=ex_shift_12
>
>  # Argument sets:
> +&empty

If I understand decodetree correctly, this isn't used until patch 5.
Otherwise,

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

I don't care enough about this to make you re-spin the patch set, so I'm OK
taking it as it stands unless there's anything else that crops up as I look
through the rest of the patches...

Thanks!

>  &b    imm rs2 rs1
>  &i    imm rs1 rd
> +&j    imm rd
>  &r    rd rs1 rs2
> +&s    imm rs1 rs2
> +&u    imm rd
>  &shift     shamt rs1 rd
>  &atomic    aq rl rs2 rs1 rd
>
> @@ -44,9 +48,9 @@
>  @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
>  @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
>  @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
> -@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
> -@u       ....................      ..... .......         imm=%imm_u          %rd
> -@j       ....................      ..... .......         imm=%imm_j          %rd
> +@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
> +@u       ....................      ..... ....... &u      imm=%imm_u          %rd
> +@j       ....................      ..... ....... &j      imm=%imm_j          %rd
>
>  @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
>  @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd

Re: [Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:48 PDT (-0700), richard.henderson@linaro.org wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn32.decode | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6f3ab7aa52..77f794ed70 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -34,9 +34,13 @@
>  %imm_u    12:s20                 !function=ex_shift_12
>
>  # Argument sets:
> +&empty

If I understand decodetree correctly, this isn't used until patch 5.
Otherwise,

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

I don't care enough about this to make you re-spin the patch set, so I'm OK
taking it as it stands unless there's anything else that crops up as I look
through the rest of the patches...

Thanks!

>  &b    imm rs2 rs1
>  &i    imm rs1 rd
> +&j    imm rd
>  &r    rd rs1 rs2
> +&s    imm rs1 rs2
> +&u    imm rd
>  &shift     shamt rs1 rd
>  &atomic    aq rl rs2 rs1 rd
>
> @@ -44,9 +48,9 @@
>  @r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
>  @i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
>  @b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
> -@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
> -@u       ....................      ..... .......         imm=%imm_u          %rd
> -@j       ....................      ..... .......         imm=%imm_j          %rd
> +@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
> +@u       ....................      ..... ....... &u      imm=%imm_u          %rd
> +@j       ....................      ..... ....... &j      imm=%imm_j          %rd
>
>  @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
>  @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd

Re: [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:49 PDT (-0700), richard.henderson@linaro.org wrote:
> The generated functions are only used within translate.c
> and do not need to be global, or declared.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/translate.c   | 2 --
>  target/riscv/Makefile.objs | 8 ++++----
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index dd763647ea..7ebd590486 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> -bool decode_insn32(DisasContext *ctx, uint32_t insn);
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -bool decode_insn16(DisasContext *ctx, uint16_t insn);
>  /* auto-generated decoder*/
>  #include "decode_insn16.inc.c"
>  #include "insn_trans/trans_rvc.inc.c"
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index 9c6c109327..c7a1b063ed 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> +          $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/decode_insn16.inc.c: \
>    $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> +          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:49 PDT (-0700), richard.henderson@linaro.org wrote:
> The generated functions are only used within translate.c
> and do not need to be global, or declared.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/translate.c   | 2 --
>  target/riscv/Makefile.objs | 8 ++++----
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index dd763647ea..7ebd590486 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> -bool decode_insn32(DisasContext *ctx, uint32_t insn);
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -bool decode_insn16(DisasContext *ctx, uint16_t insn);
>  /* auto-generated decoder*/
>  #include "decode_insn16.inc.c"
>  #include "insn_trans/trans_rvc.inc.c"
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index 9c6c109327..c7a1b063ed 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> +          $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/decode_insn16.inc.c: \
>    $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> +          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:49 PDT (-0700), richard.henderson@linaro.org wrote:
> The generated functions are only used within translate.c
> and do not need to be global, or declared.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/translate.c   | 2 --
>  target/riscv/Makefile.objs | 8 ++++----
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index dd763647ea..7ebd590486 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> -bool decode_insn32(DisasContext *ctx, uint32_t insn);
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -bool decode_insn16(DisasContext *ctx, uint16_t insn);
>  /* auto-generated decoder*/
>  #include "decode_insn16.inc.c"
>  #include "insn_trans/trans_rvc.inc.c"
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index 9c6c109327..c7a1b063ed 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> +          $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/decode_insn16.inc.c: \
>    $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
>  	$(call quiet-command, \
> -	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
> -	  "GEN", $(TARGET_DIR)$@)
> +	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> +          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Richard Henderson]

On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
>>  # Argument sets:
>> +&empty
> 
> If I understand decodetree correctly, this isn't used until patch 5.
> Otherwise,
> 

I think it's used as early as patch 3, but I haven't looked in detail to be sure.


r~

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Richard Henderson]

On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
>>  # Argument sets:
>> +&empty
> 
> If I understand decodetree correctly, this isn't used until patch 5.
> Otherwise,
> 

I think it's used as early as patch 3, but I haven't looked in detail to be sure.


r~

Re: [Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Richard Henderson]

On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
>>  # Argument sets:
>> +&empty
> 
> If I understand decodetree correctly, this isn't used until patch 5.
> Otherwise,
> 

I think it's used as early as patch 3, but I haven't looked in detail to be sure.


r~

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Aleksandar Markovic]

On Apr 25, 2019 7:17 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
> >>  # Argument sets:
> >> +&empty
> >
> > If I understand decodetree correctly, this isn't used until patch 5.
> > Otherwise,
> >
>
> I think it's used as early as patch 3, but I haven't looked in detail to
be sure.
>
>
> r~
>

I think it is a very bad practice to leave the commit message empty, and,
in my view, the long-time contributor, like you, Richard, have the
obligation to always give examples of commit messages of good quality.
Leaving empty commit messages should not be a ”privelage” that comes with
seniority, IMHO. On the contrary.

Sincerely,
Aleksandar

Re: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Aleksandar Markovic]

On Apr 25, 2019 7:17 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
> >>  # Argument sets:
> >> +&empty
> >
> > If I understand decodetree correctly, this isn't used until patch 5.
> > Otherwise,
> >
>
> I think it's used as early as patch 3, but I haven't looked in detail to
be sure.
>
>
> r~
>

I think it is a very bad practice to leave the commit message empty, and,
in my view, the long-time contributor, like you, Richard, have the
obligation to always give examples of commit messages of good quality.
Leaving empty commit messages should not be a ”privelage” that comes with
seniority, IMHO. On the contrary.

Sincerely,
Aleksandar

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 732 bytes --]

On Apr 25, 2019 7:17 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> On 4/24/19 8:31 PM, Palmer Dabbelt wrote:
> >>  # Argument sets:
> >> +&empty
> >
> > If I understand decodetree correctly, this isn't used until patch 5.
> > Otherwise,
> >
>
> I think it's used as early as patch 3, but I haven't looked in detail to
be sure.
>
>
> r~
>

I think it is a very bad practice to leave the commit message empty, and,
in my view, the long-time contributor, like you, Richard, have the
obligation to always give examples of commit messages of good quality.
Leaving empty commit messages should not be a ”privelage” that comes with
seniority, IMHO. On the contrary.

Sincerely,
Aleksandar

[-- Attachment #2: Type: text/html, Size: 996 bytes --]

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:50 PDT (-0700), richard.henderson@linaro.org wrote:
> In some cases this allows us to directly use the insn32
> translator function.  In some cases we still need a shim.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 144 ++----------------------
>  target/riscv/translate.c                |  13 ++-
>  target/riscv/insn16.decode              |  82 ++++++++------
>  3 files changed, 69 insertions(+), 170 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index ebcd977b2f..dfb46a2348 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
>      return trans_addi(ctx, &arg);
>  }
>
> -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_lw tmp;
> -    decode_insn16_extract_cl_w(&tmp, ctx->opcode);
> -    arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_w(&arg, ctx->opcode);
>      return trans_flw(ctx, &arg);
>  #else
>      /* C.LD ( RV64C/RV128C-only ) */
> -    arg_c_fld tmp;
> -    decode_insn16_extract_cl_d(&tmp, ctx->opcode);
> -    arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_d(&arg, ctx->opcode);
>      return trans_ld(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
> -{
> -    arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
> -{
> -    arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_sw tmp;
> -    decode_insn16_extract_cs_w(&tmp, ctx->opcode);
> -    arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_w(&arg, ctx->opcode);
>      return trans_fsw(ctx, &arg);
>  #else
>      /* C.SD ( RV64C/RV128C-only ) */
> -    arg_c_fsd tmp;
> -    decode_insn16_extract_cs_d(&tmp, ctx->opcode);
> -    arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_d(&arg, ctx->opcode);
>      return trans_sd(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
> -{
> -    if (a->imm == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  {
>  #ifdef TARGET_RISCV32
>      /* C.JAL */
> -    arg_c_j tmp;
> +    arg_j tmp;
>      decode_insn16_extract_cj(&tmp, ctx->opcode);
>      arg_jal arg = { .rd = 1, .imm = tmp.imm };
>      return trans_jal(ctx, &arg);
> @@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
> -{
> -    if (a->rd == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>  {
>      if (a->rd == 2) {
> @@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
>      return trans_srai(ctx, &arg);
>  }
>
> -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
> -{
> -    arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_andi(ctx, &arg);
> -}
> -
> -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
> -{
> -    arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_sub(ctx, &arg);
> -}
> -
> -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
> -{
> -    arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_xor(ctx, &arg);
> -}
> -
> -static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
> -{
> -    arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_or(ctx, &arg);
> -}
> -
> -static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
> -{
> -    arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_and(ctx, &arg);
> -}
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_subw(ctx, &arg);
> +    return trans_subw(ctx, a);
>  #else
>      return false;
>  #endif
> @@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_addw(ctx, &arg);
> +    return trans_addw(ctx, a);
>  #else
>      return false;
>  #endif
>  }
>
> -static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
> -{
> -    arg_jal arg = { .rd = 0, .imm = a->imm };
> -    return trans_jal(ctx, &arg);
> -}
> -
> -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
> -{
> -    arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_beq(ctx, &arg);
> -}
> -
> -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
> -{
> -    arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_bne(ctx, &arg);
> -}
> -
>  static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>  {
>      int shamt = a->shamt;
> @@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>      return trans_slli(ctx, &arg);
>  }
>
> -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}

c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
re-introduce the shim to handle that quirk, but since it's not actually a new
bug I'm OK taking the patch set and fixing that later.

> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
>      return false;
>  }
>
> -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
> -{
> -    arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
> -{
> -    arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7ebd590486..9e016d8e50 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -666,8 +666,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -/* auto-generated decoder*/
> +/*
> + * Auto-generated decoder.
> + * Note that the 16-bit decoder reuses some of the trans_* functions
> + * initially declared by the 32-bit decoder, which results in duplicate
> + * declaration warnings.  Suppress them.
> + */
> +#pragma GCC diagnostic push
> +#pragma GCC diagnostic ignored "-Wredundant-decls"
> +
>  #include "decode_insn16.inc.c"
> +
> +#pragma GCC diagnostic pop
> +
>  #include "insn_trans/trans_rvc.inc.c"
>
>  static void decode_opc(DisasContext *ctx)
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 17cc52cf2a..d0cc778bc9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -40,17 +40,24 @@
>  %imm_lui       12:s1 2:5             !function=ex_shift_12
>
>
> +# Argument sets imported from insn32.decode:
> +&empty                  !extern
> +&r         rd rs1 rs2   !extern
> +&i         imm rs1 rd   !extern
> +&s         imm rs1 rs2  !extern
> +&j         imm rd       !extern
> +&b         imm rs2 rs1  !extern
> +&u         imm rd       !extern
> +&shift     shamt rs1 rd !extern
>
>  # Argument sets:
>  &cl               rs1 rd
>  &cl_dw     uimm   rs1 rd
> -&ci        imm        rd
>  &ciw       nzuimm     rd
>  &cs               rs1 rs2
>  &cs_dw     uimm   rs1 rs2
>  &cb        imm    rs1
>  &cr               rd  rs2
> -&cj       imm
>  &c_shift   shamt      rd
>
>  &c_ld      uimm  rd
> @@ -61,23 +68,24 @@
>  &cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
> -@cr        ....  ..... .....  .. &cr                      rs2=%rs2_5  %rd
> -@ci        ... . ..... .....  .. &ci     imm=%imm_ci                  %rd
> +@cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> +@ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
> -@cl_d      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
> -@cl_w      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
> +@cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> +@cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
>  @cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> -@cs_2      ... ... ... .. ... .. &cr                      rd=%rs1_3   rs2=%rs2_3
> -@cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
> -@cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
> -@cb        ... ... ... .. ... .. &cb     imm=%imm_cb      rs1=%rs1_3
> -@cj        ...    ........... .. &cj     imm=%imm_cj
> +@cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> +@cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> +@cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> +@cj        ...    ........... .. &j      imm=%imm_cj
> +@cb_z      ... ... ... .. ... .. &b      imm=%imm_cb      rs1=%rs1_3  rs2=0
>
> -@c_ld      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_ld  %rd
> -@c_lw      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_lw  %rd
> -@c_sd      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sd  rs2=%rs2_5
> -@c_sw      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sw  rs2=%rs2_5
> +@c_ldsp    ... . .....  ..... .. &i      imm=%uimm_6bit_ld rs1=2 %rd
> +@c_lwsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lw rs1=2 %rd
> +@c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
> +@c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
> +@c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
>
>  @c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> @@ -85,45 +93,47 @@
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
> -@c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
> -@c_shift2       ... . .. ... ..... .. &c_shift rd=%rd    shamt=%nzuimm_6bit
> +@c_shift        ... . .. ... ..... .. \
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +@c_shift2       ... . .. ... ..... .. \
> +                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
>
> -@c_andi         ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
> +@c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
>  c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> -c_fsd             101  ... ... .. ... 00 @cs_d
> -c_sw              110  ... ... .. ... 00 @cs_w
> +fsd               101  ... ... .. ... 00 @cs_d
> +sw                110  ... ... .. ... 00 @cs_w
>  c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
>  # *** RV64C Standard Extension (Quadrant 1) ***
> -c_addi            000 .  .....  ..... 01 @ci
> +addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> -c_li              010 .  .....  ..... 01 @ci
> +addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
>  c_srli            100 . 00 ...  ..... 01 @c_shift
>  c_srai            100 . 01 ...  ..... 01 @c_shift
> -c_andi            100 . 10 ...  ..... 01 @c_andi
> -c_sub             100 0 11 ... 00 ... 01 @cs_2
> -c_xor             100 0 11 ... 01 ... 01 @cs_2
> -c_or              100 0 11 ... 10 ... 01 @cs_2
> -c_and             100 0 11 ... 11 ... 01 @cs_2
> +andi              100 . 10 ...  ..... 01 @c_andi
> +sub               100 0 11 ... 00 ... 01 @cs_2
> +xor               100 0 11 ... 01 ... 01 @cs_2
> +or                100 0 11 ... 10 ... 01 @cs_2
> +and               100 0 11 ... 11 ... 01 @cs_2
>  c_subw            100 1 11 ... 00 ... 01 @cs_2
>  c_addw            100 1 11 ... 01 ... 01 @cs_2
> -c_j               101     ........... 01 @cj
> -c_beqz            110  ... ...  ..... 01 @cb
> -c_bnez            111  ... ...  ..... 01 @cb
> +jal               101     ........... 01 @cj    rd=0  # C.J
> +beq               110  ... ...  ..... 01 @cb_z
> +bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
>  c_slli            000 .  .....  ..... 10 @c_shift2
> -c_fldsp           001 .  .....  ..... 10 @c_ld
> -c_lwsp            010 .  .....  ..... 10 @c_lw
> +fld               001 .  .....  ..... 10 @c_ldsp
> +lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  c_jr_mv           100 0  .....  ..... 10 @cr
>  c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> -c_fsdsp           101   ......  ..... 10 @c_sd
> -c_swsp            110 .  .....  ..... 10 @c_sw
> +fsd               101   ......  ..... 10 @c_sdsp
> +sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:50 PDT (-0700), richard.henderson@linaro.org wrote:
> In some cases this allows us to directly use the insn32
> translator function.  In some cases we still need a shim.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 144 ++----------------------
>  target/riscv/translate.c                |  13 ++-
>  target/riscv/insn16.decode              |  82 ++++++++------
>  3 files changed, 69 insertions(+), 170 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index ebcd977b2f..dfb46a2348 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
>      return trans_addi(ctx, &arg);
>  }
>
> -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_lw tmp;
> -    decode_insn16_extract_cl_w(&tmp, ctx->opcode);
> -    arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_w(&arg, ctx->opcode);
>      return trans_flw(ctx, &arg);
>  #else
>      /* C.LD ( RV64C/RV128C-only ) */
> -    arg_c_fld tmp;
> -    decode_insn16_extract_cl_d(&tmp, ctx->opcode);
> -    arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_d(&arg, ctx->opcode);
>      return trans_ld(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
> -{
> -    arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
> -{
> -    arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_sw tmp;
> -    decode_insn16_extract_cs_w(&tmp, ctx->opcode);
> -    arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_w(&arg, ctx->opcode);
>      return trans_fsw(ctx, &arg);
>  #else
>      /* C.SD ( RV64C/RV128C-only ) */
> -    arg_c_fsd tmp;
> -    decode_insn16_extract_cs_d(&tmp, ctx->opcode);
> -    arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_d(&arg, ctx->opcode);
>      return trans_sd(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
> -{
> -    if (a->imm == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  {
>  #ifdef TARGET_RISCV32
>      /* C.JAL */
> -    arg_c_j tmp;
> +    arg_j tmp;
>      decode_insn16_extract_cj(&tmp, ctx->opcode);
>      arg_jal arg = { .rd = 1, .imm = tmp.imm };
>      return trans_jal(ctx, &arg);
> @@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
> -{
> -    if (a->rd == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>  {
>      if (a->rd == 2) {
> @@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
>      return trans_srai(ctx, &arg);
>  }
>
> -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
> -{
> -    arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_andi(ctx, &arg);
> -}
> -
> -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
> -{
> -    arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_sub(ctx, &arg);
> -}
> -
> -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
> -{
> -    arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_xor(ctx, &arg);
> -}
> -
> -static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
> -{
> -    arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_or(ctx, &arg);
> -}
> -
> -static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
> -{
> -    arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_and(ctx, &arg);
> -}
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_subw(ctx, &arg);
> +    return trans_subw(ctx, a);
>  #else
>      return false;
>  #endif
> @@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_addw(ctx, &arg);
> +    return trans_addw(ctx, a);
>  #else
>      return false;
>  #endif
>  }
>
> -static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
> -{
> -    arg_jal arg = { .rd = 0, .imm = a->imm };
> -    return trans_jal(ctx, &arg);
> -}
> -
> -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
> -{
> -    arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_beq(ctx, &arg);
> -}
> -
> -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
> -{
> -    arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_bne(ctx, &arg);
> -}
> -
>  static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>  {
>      int shamt = a->shamt;
> @@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>      return trans_slli(ctx, &arg);
>  }
>
> -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}

c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
re-introduce the shim to handle that quirk, but since it's not actually a new
bug I'm OK taking the patch set and fixing that later.

> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
>      return false;
>  }
>
> -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
> -{
> -    arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
> -{
> -    arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7ebd590486..9e016d8e50 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -666,8 +666,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -/* auto-generated decoder*/
> +/*
> + * Auto-generated decoder.
> + * Note that the 16-bit decoder reuses some of the trans_* functions
> + * initially declared by the 32-bit decoder, which results in duplicate
> + * declaration warnings.  Suppress them.
> + */
> +#pragma GCC diagnostic push
> +#pragma GCC diagnostic ignored "-Wredundant-decls"
> +
>  #include "decode_insn16.inc.c"
> +
> +#pragma GCC diagnostic pop
> +
>  #include "insn_trans/trans_rvc.inc.c"
>
>  static void decode_opc(DisasContext *ctx)
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 17cc52cf2a..d0cc778bc9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -40,17 +40,24 @@
>  %imm_lui       12:s1 2:5             !function=ex_shift_12
>
>
> +# Argument sets imported from insn32.decode:
> +&empty                  !extern
> +&r         rd rs1 rs2   !extern
> +&i         imm rs1 rd   !extern
> +&s         imm rs1 rs2  !extern
> +&j         imm rd       !extern
> +&b         imm rs2 rs1  !extern
> +&u         imm rd       !extern
> +&shift     shamt rs1 rd !extern
>
>  # Argument sets:
>  &cl               rs1 rd
>  &cl_dw     uimm   rs1 rd
> -&ci        imm        rd
>  &ciw       nzuimm     rd
>  &cs               rs1 rs2
>  &cs_dw     uimm   rs1 rs2
>  &cb        imm    rs1
>  &cr               rd  rs2
> -&cj       imm
>  &c_shift   shamt      rd
>
>  &c_ld      uimm  rd
> @@ -61,23 +68,24 @@
>  &cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
> -@cr        ....  ..... .....  .. &cr                      rs2=%rs2_5  %rd
> -@ci        ... . ..... .....  .. &ci     imm=%imm_ci                  %rd
> +@cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> +@ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
> -@cl_d      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
> -@cl_w      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
> +@cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> +@cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
>  @cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> -@cs_2      ... ... ... .. ... .. &cr                      rd=%rs1_3   rs2=%rs2_3
> -@cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
> -@cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
> -@cb        ... ... ... .. ... .. &cb     imm=%imm_cb      rs1=%rs1_3
> -@cj        ...    ........... .. &cj     imm=%imm_cj
> +@cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> +@cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> +@cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> +@cj        ...    ........... .. &j      imm=%imm_cj
> +@cb_z      ... ... ... .. ... .. &b      imm=%imm_cb      rs1=%rs1_3  rs2=0
>
> -@c_ld      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_ld  %rd
> -@c_lw      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_lw  %rd
> -@c_sd      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sd  rs2=%rs2_5
> -@c_sw      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sw  rs2=%rs2_5
> +@c_ldsp    ... . .....  ..... .. &i      imm=%uimm_6bit_ld rs1=2 %rd
> +@c_lwsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lw rs1=2 %rd
> +@c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
> +@c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
> +@c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
>
>  @c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> @@ -85,45 +93,47 @@
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
> -@c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
> -@c_shift2       ... . .. ... ..... .. &c_shift rd=%rd    shamt=%nzuimm_6bit
> +@c_shift        ... . .. ... ..... .. \
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +@c_shift2       ... . .. ... ..... .. \
> +                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
>
> -@c_andi         ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
> +@c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
>  c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> -c_fsd             101  ... ... .. ... 00 @cs_d
> -c_sw              110  ... ... .. ... 00 @cs_w
> +fsd               101  ... ... .. ... 00 @cs_d
> +sw                110  ... ... .. ... 00 @cs_w
>  c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
>  # *** RV64C Standard Extension (Quadrant 1) ***
> -c_addi            000 .  .....  ..... 01 @ci
> +addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> -c_li              010 .  .....  ..... 01 @ci
> +addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
>  c_srli            100 . 00 ...  ..... 01 @c_shift
>  c_srai            100 . 01 ...  ..... 01 @c_shift
> -c_andi            100 . 10 ...  ..... 01 @c_andi
> -c_sub             100 0 11 ... 00 ... 01 @cs_2
> -c_xor             100 0 11 ... 01 ... 01 @cs_2
> -c_or              100 0 11 ... 10 ... 01 @cs_2
> -c_and             100 0 11 ... 11 ... 01 @cs_2
> +andi              100 . 10 ...  ..... 01 @c_andi
> +sub               100 0 11 ... 00 ... 01 @cs_2
> +xor               100 0 11 ... 01 ... 01 @cs_2
> +or                100 0 11 ... 10 ... 01 @cs_2
> +and               100 0 11 ... 11 ... 01 @cs_2
>  c_subw            100 1 11 ... 00 ... 01 @cs_2
>  c_addw            100 1 11 ... 01 ... 01 @cs_2
> -c_j               101     ........... 01 @cj
> -c_beqz            110  ... ...  ..... 01 @cb
> -c_bnez            111  ... ...  ..... 01 @cb
> +jal               101     ........... 01 @cj    rd=0  # C.J
> +beq               110  ... ...  ..... 01 @cb_z
> +bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
>  c_slli            000 .  .....  ..... 10 @c_shift2
> -c_fldsp           001 .  .....  ..... 10 @c_ld
> -c_lwsp            010 .  .....  ..... 10 @c_lw
> +fld               001 .  .....  ..... 10 @c_ldsp
> +lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  c_jr_mv           100 0  .....  ..... 10 @cr
>  c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> -c_fsdsp           101   ......  ..... 10 @c_sd
> -c_swsp            110 .  .....  ..... 10 @c_sw
> +fsd               101   ......  ..... 10 @c_sdsp
> +sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:50 PDT (-0700), richard.henderson@linaro.org wrote:
> In some cases this allows us to directly use the insn32
> translator function.  In some cases we still need a shim.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 144 ++----------------------
>  target/riscv/translate.c                |  13 ++-
>  target/riscv/insn16.decode              |  82 ++++++++------
>  3 files changed, 69 insertions(+), 170 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index ebcd977b2f..dfb46a2348 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
>      return trans_addi(ctx, &arg);
>  }
>
> -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_lw tmp;
> -    decode_insn16_extract_cl_w(&tmp, ctx->opcode);
> -    arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_w(&arg, ctx->opcode);
>      return trans_flw(ctx, &arg);
>  #else
>      /* C.LD ( RV64C/RV128C-only ) */
> -    arg_c_fld tmp;
> -    decode_insn16_extract_cl_d(&tmp, ctx->opcode);
> -    arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
> +    arg_i arg;
> +    decode_insn16_extract_cl_d(&arg, ctx->opcode);
>      return trans_ld(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
> -{
> -    arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
> -{
> -    arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    arg_c_sw tmp;
> -    decode_insn16_extract_cs_w(&tmp, ctx->opcode);
> -    arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_w(&arg, ctx->opcode);
>      return trans_fsw(ctx, &arg);
>  #else
>      /* C.SD ( RV64C/RV128C-only ) */
> -    arg_c_fsd tmp;
> -    decode_insn16_extract_cs_d(&tmp, ctx->opcode);
> -    arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
> +    arg_s arg;
> +    decode_insn16_extract_cs_d(&arg, ctx->opcode);
>      return trans_sd(ctx, &arg);
>  #endif
>  }
>
> -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
> -{
> -    if (a->imm == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  {
>  #ifdef TARGET_RISCV32
>      /* C.JAL */
> -    arg_c_j tmp;
> +    arg_j tmp;
>      decode_insn16_extract_cj(&tmp, ctx->opcode);
>      arg_jal arg = { .rd = 1, .imm = tmp.imm };
>      return trans_jal(ctx, &arg);
> @@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
> -{
> -    if (a->rd == 0) {
> -        /* Hint: insn is valid but does not affect state */
> -        return true;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>  {
>      if (a->rd == 2) {
> @@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
>      return trans_srai(ctx, &arg);
>  }
>
> -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
> -{
> -    arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_andi(ctx, &arg);
> -}
> -
> -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
> -{
> -    arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_sub(ctx, &arg);
> -}
> -
> -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
> -{
> -    arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_xor(ctx, &arg);
> -}
> -
> -static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
> -{
> -    arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_or(ctx, &arg);
> -}
> -
> -static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
> -{
> -    arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_and(ctx, &arg);
> -}
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_subw(ctx, &arg);
> +    return trans_subw(ctx, a);
>  #else
>      return false;
>  #endif
> @@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  {
>  #ifdef TARGET_RISCV64
> -    arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -    return trans_addw(ctx, &arg);
> +    return trans_addw(ctx, a);
>  #else
>      return false;
>  #endif
>  }
>
> -static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
> -{
> -    arg_jal arg = { .rd = 0, .imm = a->imm };
> -    return trans_jal(ctx, &arg);
> -}
> -
> -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
> -{
> -    arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_beq(ctx, &arg);
> -}
> -
> -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
> -{
> -    arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
> -    return trans_bne(ctx, &arg);
> -}
> -
>  static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>  {
>      int shamt = a->shamt;
> @@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
>      return trans_slli(ctx, &arg);
>  }
>
> -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
> -{
> -    arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_fld(ctx, &arg);
> -}
> -
> -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
> -{
> -    arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
> -    return trans_lw(ctx, &arg);
> -}

c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
re-introduce the shim to handle that quirk, but since it's not actually a new
bug I'm OK taking the patch set and fixing that later.

> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
>      return false;
>  }
>
> -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
> -{
> -    arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_fsd(ctx, &arg);
> -}
> -
> -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
> -{
> -    arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
> -    return trans_sw(ctx, &arg);
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7ebd590486..9e016d8e50 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -666,8 +666,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>  #include "insn_trans/trans_rvd.inc.c"
>  #include "insn_trans/trans_privileged.inc.c"
>
> -/* auto-generated decoder*/
> +/*
> + * Auto-generated decoder.
> + * Note that the 16-bit decoder reuses some of the trans_* functions
> + * initially declared by the 32-bit decoder, which results in duplicate
> + * declaration warnings.  Suppress them.
> + */
> +#pragma GCC diagnostic push
> +#pragma GCC diagnostic ignored "-Wredundant-decls"
> +
>  #include "decode_insn16.inc.c"
> +
> +#pragma GCC diagnostic pop
> +
>  #include "insn_trans/trans_rvc.inc.c"
>
>  static void decode_opc(DisasContext *ctx)
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 17cc52cf2a..d0cc778bc9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -40,17 +40,24 @@
>  %imm_lui       12:s1 2:5             !function=ex_shift_12
>
>
> +# Argument sets imported from insn32.decode:
> +&empty                  !extern
> +&r         rd rs1 rs2   !extern
> +&i         imm rs1 rd   !extern
> +&s         imm rs1 rs2  !extern
> +&j         imm rd       !extern
> +&b         imm rs2 rs1  !extern
> +&u         imm rd       !extern
> +&shift     shamt rs1 rd !extern
>
>  # Argument sets:
>  &cl               rs1 rd
>  &cl_dw     uimm   rs1 rd
> -&ci        imm        rd
>  &ciw       nzuimm     rd
>  &cs               rs1 rs2
>  &cs_dw     uimm   rs1 rs2
>  &cb        imm    rs1
>  &cr               rd  rs2
> -&cj       imm
>  &c_shift   shamt      rd
>
>  &c_ld      uimm  rd
> @@ -61,23 +68,24 @@
>  &cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
> -@cr        ....  ..... .....  .. &cr                      rs2=%rs2_5  %rd
> -@ci        ... . ..... .....  .. &ci     imm=%imm_ci                  %rd
> +@cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> +@ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
> -@cl_d      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rd=%rs2_3
> -@cl_w      ... ... ... .. ... .. &cl_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rd=%rs2_3
> +@cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> +@cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
>  @cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> -@cs_2      ... ... ... .. ... .. &cr                      rd=%rs1_3   rs2=%rs2_3
> -@cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d  rs1=%rs1_3  rs2=%rs2_3
> -@cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w  rs1=%rs1_3  rs2=%rs2_3
> -@cb        ... ... ... .. ... .. &cb     imm=%imm_cb      rs1=%rs1_3
> -@cj        ...    ........... .. &cj     imm=%imm_cj
> +@cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> +@cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> +@cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> +@cj        ...    ........... .. &j      imm=%imm_cj
> +@cb_z      ... ... ... .. ... .. &b      imm=%imm_cb      rs1=%rs1_3  rs2=0
>
> -@c_ld      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_ld  %rd
> -@c_lw      ... . .....  ..... .. &c_ld     uimm=%uimm_6bit_lw  %rd
> -@c_sd      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sd  rs2=%rs2_5
> -@c_sw      ... . .....  ..... .. &c_sd     uimm=%uimm_6bit_sw  rs2=%rs2_5
> +@c_ldsp    ... . .....  ..... .. &i      imm=%uimm_6bit_ld rs1=2 %rd
> +@c_lwsp    ... . .....  ..... .. &i      imm=%uimm_6bit_lw rs1=2 %rd
> +@c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
> +@c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
> +@c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
>
>  @c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> @@ -85,45 +93,47 @@
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
> -@c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
> -@c_shift2       ... . .. ... ..... .. &c_shift rd=%rd    shamt=%nzuimm_6bit
> +@c_shift        ... . .. ... ..... .. \
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +@c_shift2       ... . .. ... ..... .. \
> +                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
>
> -@c_andi         ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
> +@c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
>  c_addi4spn        000    ........ ... 00 @ciw
> -c_fld             001  ... ... .. ... 00 @cl_d
> -c_lw              010  ... ... .. ... 00 @cl_w
> +fld               001  ... ... .. ... 00 @cl_d
> +lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> -c_fsd             101  ... ... .. ... 00 @cs_d
> -c_sw              110  ... ... .. ... 00 @cs_w
> +fsd               101  ... ... .. ... 00 @cs_d
> +sw                110  ... ... .. ... 00 @cs_w
>  c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
>  # *** RV64C Standard Extension (Quadrant 1) ***
> -c_addi            000 .  .....  ..... 01 @ci
> +addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> -c_li              010 .  .....  ..... 01 @ci
> +addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
>  c_srli            100 . 00 ...  ..... 01 @c_shift
>  c_srai            100 . 01 ...  ..... 01 @c_shift
> -c_andi            100 . 10 ...  ..... 01 @c_andi
> -c_sub             100 0 11 ... 00 ... 01 @cs_2
> -c_xor             100 0 11 ... 01 ... 01 @cs_2
> -c_or              100 0 11 ... 10 ... 01 @cs_2
> -c_and             100 0 11 ... 11 ... 01 @cs_2
> +andi              100 . 10 ...  ..... 01 @c_andi
> +sub               100 0 11 ... 00 ... 01 @cs_2
> +xor               100 0 11 ... 01 ... 01 @cs_2
> +or                100 0 11 ... 10 ... 01 @cs_2
> +and               100 0 11 ... 11 ... 01 @cs_2
>  c_subw            100 1 11 ... 00 ... 01 @cs_2
>  c_addw            100 1 11 ... 01 ... 01 @cs_2
> -c_j               101     ........... 01 @cj
> -c_beqz            110  ... ...  ..... 01 @cb
> -c_bnez            111  ... ...  ..... 01 @cb
> +jal               101     ........... 01 @cj    rd=0  # C.J
> +beq               110  ... ...  ..... 01 @cb_z
> +bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
>  c_slli            000 .  .....  ..... 10 @c_shift2
> -c_fldsp           001 .  .....  ..... 10 @c_ld
> -c_lwsp            010 .  .....  ..... 10 @c_lw
> +fld               001 .  .....  ..... 10 @c_ldsp
> +lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  c_jr_mv           100 0  .....  ..... 10 @cr
>  c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> -c_fsdsp           101   ......  ..... 10 @c_sd
> -c_swsp            110 .  .....  ..... 10 @c_sw
> +fsd               101   ......  ..... 10 @c_sdsp
> +sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:51 PDT (-0700), richard.henderson@linaro.org wrote:
> Special handling for IMM==0 is the only difference between
> RVC shifti and RVI shifti.  This can be handled with !function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 47 -------------------------
>  target/riscv/translate.c                |  6 ++++
>  target/riscv/insn16.decode              | 12 +++----
>  3 files changed, 12 insertions(+), 53 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index dfb46a2348..691b1e2725 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>      return false;
>  }
>
> -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srli(ctx, &arg);
> -}
> -
> -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srai(ctx, &arg);
> -}
>
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
> @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  #endif
>  }
>
> -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_slli(ctx, &arg);
> -}
> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9e016d8e50..a1cd29f80f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,6 +538,12 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> +static int ex_rvc_shifti(int imm)
> +{
> +    /* For RV128 a shamt of 0 means a shift by 64. */
> +    return imm ? imm : 64;
> +}
> +
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index d0cc778bc9..add9cf3923 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -30,7 +30,7 @@
>  %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
>  %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
>
> -%nzuimm_6bit   12:1 2:5
> +%shimm_6bit   12:1 2:5               !function=ex_rvc_shifti
>  %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
>  %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
>  %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
> @@ -94,9 +94,9 @@
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
> -                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
>  @c_shift2       ... . .. ... ..... .. \
> -                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
> +                &shift rd=%rd rs1=%rd shamt=%shimm_6bit
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> @@ -114,8 +114,8 @@ addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> -c_srli            100 . 00 ...  ..... 01 @c_shift
> -c_srai            100 . 01 ...  ..... 01 @c_shift
> +srli              100 . 00 ...  ..... 01 @c_shift
> +srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
>  sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
> @@ -128,7 +128,7 @@ beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
> -c_slli            000 .  .....  ..... 10 @c_shift2
> +slli              000 .  .....  ..... 10 @c_shift2

This is another one where rd=0 is illegal in the compressed ISA, but again we
don't appear to handle these correctly before the cleanups.

>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:51 PDT (-0700), richard.henderson@linaro.org wrote:
> Special handling for IMM==0 is the only difference between
> RVC shifti and RVI shifti.  This can be handled with !function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 47 -------------------------
>  target/riscv/translate.c                |  6 ++++
>  target/riscv/insn16.decode              | 12 +++----
>  3 files changed, 12 insertions(+), 53 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index dfb46a2348..691b1e2725 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>      return false;
>  }
>
> -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srli(ctx, &arg);
> -}
> -
> -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srai(ctx, &arg);
> -}
>
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
> @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  #endif
>  }
>
> -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_slli(ctx, &arg);
> -}
> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9e016d8e50..a1cd29f80f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,6 +538,12 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> +static int ex_rvc_shifti(int imm)
> +{
> +    /* For RV128 a shamt of 0 means a shift by 64. */
> +    return imm ? imm : 64;
> +}
> +
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index d0cc778bc9..add9cf3923 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -30,7 +30,7 @@
>  %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
>  %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
>
> -%nzuimm_6bit   12:1 2:5
> +%shimm_6bit   12:1 2:5               !function=ex_rvc_shifti
>  %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
>  %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
>  %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
> @@ -94,9 +94,9 @@
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
> -                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
>  @c_shift2       ... . .. ... ..... .. \
> -                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
> +                &shift rd=%rd rs1=%rd shamt=%shimm_6bit
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> @@ -114,8 +114,8 @@ addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> -c_srli            100 . 00 ...  ..... 01 @c_shift
> -c_srai            100 . 01 ...  ..... 01 @c_shift
> +srli              100 . 00 ...  ..... 01 @c_shift
> +srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
>  sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
> @@ -128,7 +128,7 @@ beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
> -c_slli            000 .  .....  ..... 10 @c_shift2
> +slli              000 .  .....  ..... 10 @c_shift2

This is another one where rd=0 is illegal in the compressed ISA, but again we
don't appear to handle these correctly before the cleanups.

>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:51 PDT (-0700), richard.henderson@linaro.org wrote:
> Special handling for IMM==0 is the only difference between
> RVC shifti and RVI shifti.  This can be handled with !function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 47 -------------------------
>  target/riscv/translate.c                |  6 ++++
>  target/riscv/insn16.decode              | 12 +++----
>  3 files changed, 12 insertions(+), 53 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index dfb46a2348..691b1e2725 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
>      return false;
>  }
>
> -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srli(ctx, &arg);
> -}
> -
> -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_srai(ctx, &arg);
> -}
>
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
> @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
>  #endif
>  }
>
> -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
> -{
> -    int shamt = a->shamt;
> -    if (shamt == 0) {
> -        /* For RV128 a shamt of 0 means a shift by 64 */
> -        shamt = 64;
> -    }
> -    /* Ensure, that shamt[5] is zero for RV32 */
> -    if (shamt >= TARGET_LONG_BITS) {
> -        return false;
> -    }
> -
> -    arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
> -    return trans_slli(ctx, &arg);
> -}
> -
>  static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9e016d8e50..a1cd29f80f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -538,6 +538,12 @@ static int ex_rvc_register(int reg)
>      return 8 + reg;
>  }
>
> +static int ex_rvc_shifti(int imm)
> +{
> +    /* For RV128 a shamt of 0 means a shift by 64. */
> +    return imm ? imm : 64;
> +}
> +
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index d0cc778bc9..add9cf3923 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -30,7 +30,7 @@
>  %imm_cb        12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
>  %imm_cj        12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
>
> -%nzuimm_6bit   12:1 2:5
> +%shimm_6bit   12:1 2:5               !function=ex_rvc_shifti
>  %uimm_6bit_ld 2:3 12:1 5:2           !function=ex_shift_3
>  %uimm_6bit_lw 2:2 12:1 4:3           !function=ex_shift_2
>  %uimm_6bit_sd 7:3 10:3               !function=ex_shift_3
> @@ -94,9 +94,9 @@
>      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
> -                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%nzuimm_6bit
> +                &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
>  @c_shift2       ... . .. ... ..... .. \
> -                &shift rd=%rd rs1=%rd shamt=%nzuimm_6bit
> +                &shift rd=%rd rs1=%rd shamt=%shimm_6bit
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> @@ -114,8 +114,8 @@ addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> -c_srli            100 . 00 ...  ..... 01 @c_shift
> -c_srai            100 . 01 ...  ..... 01 @c_shift
> +srli              100 . 00 ...  ..... 01 @c_shift
> +srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
>  sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
> @@ -128,7 +128,7 @@ beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
>  # *** RV64C Standard Extension (Quadrant 2) ***
> -c_slli            000 .  .....  ..... 10 @c_shift2
> +slli              000 .  .....  ..... 10 @c_shift2

This is another one where rd=0 is illegal in the compressed ISA, but again we
don't appear to handle these correctly before the cleanups.

>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:52 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates about half of the complicated decode
> bits within insn_trans/trans_rvc.inc.c.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 63 -------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  6 +++
>  target/riscv/insn16.decode              | 29 +++++++++---
>  3 files changed, 29 insertions(+), 69 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index 691b1e2725..43bff97f66 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -18,16 +18,6 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
> -{
> -    if (a->nzuimm == 0) {
> -        /* Reserved in ISA */
> -        return false;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
> -{
> -    if (a->rd == 2) {
> -        /* C.ADDI16SP */
> -        arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
> -        return trans_addi(ctx, &arg);
> -    } else if (a->imm_lui != 0) {
> -        /* C.LUI */
> -        if (a->rd == 0) {
> -            /* Hint: insn is valid but does not affect state */
> -            return true;
> -        }
> -        arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
> -        return trans_lui(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> @@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>      return false;
>  }
>
> -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
> -{
> -    if (a->rd != 0 && a->rs2 == 0) {
> -        /* C.JR */
> -        arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
> -        return trans_jalr(ctx, &arg);
> -    } else if (a->rd != 0 && a->rs2 != 0) {
> -        /* C.MV */
> -        arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
> -        return trans_add(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
> -{
> -    if (a->rd == 0 && a->rs2 == 0) {
> -        /* C.EBREAK */
> -        arg_ebreak arg = { };
> -        return trans_ebreak(ctx, &arg);
> -    } else if (a->rd != 0) {
> -        if (a->rs2 == 0) {
> -            /* C.JALR */
> -            arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
> -            return trans_jalr(ctx, &arg);
> -        } else {
> -            /* C.ADD */
> -            arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -            return trans_add(ctx, &arg);
> -        }
> -    }
> -    return false;
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index d420a4d8b2..caf91f9a05 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -18,6 +18,12 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> +static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> +{
> +    gen_exception_illegal(ctx);
> +    return true;
> +}
> +
>  static bool trans_lui(DisasContext *ctx, arg_lui *a)
>  {
>      if (a->rd != 0) {
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index add9cf3923..3c79edf1c9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -70,7 +70,6 @@
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> -@ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> @@ -86,8 +85,12 @@
>  @c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
>  @c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
>  @c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
> +@c_lui     ... . .....  ..... .. &u      imm=%imm_lui %rd
> +@c_jalr    ... . .....  ..... .. &i      imm=0 rs1=%rd
> +@c_mv      ... . ..... .....  .. &i      imm=0 rs1=%rs2_5 %rd
>
> -@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
> +@c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> +@c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
>      uimm_ldsp=%uimm_6bit_ld %rd
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> @@ -101,7 +104,11 @@
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
> -c_addi4spn        000    ........ ... 00 @ciw
> +{
> +  # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> +  illegal         000  000 000 00 --- 00
> +  addi            000  ... ... .. ... 00 @c_addi4spn
> +}
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> @@ -113,7 +120,10 @@ c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>  addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
> -c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> +{
> +  addi            011 .  00010  ..... 01 @c_addi16sp
> +  lui             011 .  .....  ..... 01 @c_lui
> +}
>  srli              100 . 00 ...  ..... 01 @c_shift
>  srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
> @@ -132,8 +142,15 @@ slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> -c_jr_mv           100 0  .....  ..... 10 @cr
> -c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> +{
> +  jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> +  addi            100 0  .....  ..... 10 @c_mv
> +}
> +{
> +  ebreak          100 1  00000  00000 10
> +  jalr            100 1  .....  00000 10 @c_jalr rd=1  # C.JALR
> +  add             100 1  .....  ..... 10 @cr
> +}
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:52 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates about half of the complicated decode
> bits within insn_trans/trans_rvc.inc.c.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 63 -------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  6 +++
>  target/riscv/insn16.decode              | 29 +++++++++---
>  3 files changed, 29 insertions(+), 69 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index 691b1e2725..43bff97f66 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -18,16 +18,6 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
> -{
> -    if (a->nzuimm == 0) {
> -        /* Reserved in ISA */
> -        return false;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
> -{
> -    if (a->rd == 2) {
> -        /* C.ADDI16SP */
> -        arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
> -        return trans_addi(ctx, &arg);
> -    } else if (a->imm_lui != 0) {
> -        /* C.LUI */
> -        if (a->rd == 0) {
> -            /* Hint: insn is valid but does not affect state */
> -            return true;
> -        }
> -        arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
> -        return trans_lui(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> @@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>      return false;
>  }
>
> -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
> -{
> -    if (a->rd != 0 && a->rs2 == 0) {
> -        /* C.JR */
> -        arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
> -        return trans_jalr(ctx, &arg);
> -    } else if (a->rd != 0 && a->rs2 != 0) {
> -        /* C.MV */
> -        arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
> -        return trans_add(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
> -{
> -    if (a->rd == 0 && a->rs2 == 0) {
> -        /* C.EBREAK */
> -        arg_ebreak arg = { };
> -        return trans_ebreak(ctx, &arg);
> -    } else if (a->rd != 0) {
> -        if (a->rs2 == 0) {
> -            /* C.JALR */
> -            arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
> -            return trans_jalr(ctx, &arg);
> -        } else {
> -            /* C.ADD */
> -            arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -            return trans_add(ctx, &arg);
> -        }
> -    }
> -    return false;
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index d420a4d8b2..caf91f9a05 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -18,6 +18,12 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> +static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> +{
> +    gen_exception_illegal(ctx);
> +    return true;
> +}
> +
>  static bool trans_lui(DisasContext *ctx, arg_lui *a)
>  {
>      if (a->rd != 0) {
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index add9cf3923..3c79edf1c9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -70,7 +70,6 @@
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> -@ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> @@ -86,8 +85,12 @@
>  @c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
>  @c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
>  @c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
> +@c_lui     ... . .....  ..... .. &u      imm=%imm_lui %rd
> +@c_jalr    ... . .....  ..... .. &i      imm=0 rs1=%rd
> +@c_mv      ... . ..... .....  .. &i      imm=0 rs1=%rs2_5 %rd
>
> -@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
> +@c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> +@c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
>      uimm_ldsp=%uimm_6bit_ld %rd
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> @@ -101,7 +104,11 @@
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
> -c_addi4spn        000    ........ ... 00 @ciw
> +{
> +  # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> +  illegal         000  000 000 00 --- 00
> +  addi            000  ... ... .. ... 00 @c_addi4spn
> +}
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> @@ -113,7 +120,10 @@ c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>  addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
> -c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> +{
> +  addi            011 .  00010  ..... 01 @c_addi16sp
> +  lui             011 .  .....  ..... 01 @c_lui
> +}
>  srli              100 . 00 ...  ..... 01 @c_shift
>  srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
> @@ -132,8 +142,15 @@ slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> -c_jr_mv           100 0  .....  ..... 10 @cr
> -c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> +{
> +  jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> +  addi            100 0  .....  ..... 10 @c_mv
> +}
> +{
> +  ebreak          100 1  00000  00000 10
> +  jalr            100 1  .....  00000 10 @c_jalr rd=1  # C.JALR
> +  add             100 1  .....  ..... 10 @cr
> +}
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:52 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates about half of the complicated decode
> bits within insn_trans/trans_rvc.inc.c.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 63 -------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  6 +++
>  target/riscv/insn16.decode              | 29 +++++++++---
>  3 files changed, 29 insertions(+), 69 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> index 691b1e2725..43bff97f66 100644
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ b/target/riscv/insn_trans/trans_rvc.inc.c
> @@ -18,16 +18,6 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
> -{
> -    if (a->nzuimm == 0) {
> -        /* Reserved in ISA */
> -        return false;
> -    }
> -    arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
> -    return trans_addi(ctx, &arg);
> -}
> -
>  static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
>  {
>  #ifdef TARGET_RISCV32
> @@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
>  #endif
>  }
>
> -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
> -{
> -    if (a->rd == 2) {
> -        /* C.ADDI16SP */
> -        arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
> -        return trans_addi(ctx, &arg);
> -    } else if (a->imm_lui != 0) {
> -        /* C.LUI */
> -        if (a->rd == 0) {
> -            /* Hint: insn is valid but does not affect state */
> -            return true;
> -        }
> -        arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
> -        return trans_lui(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -
>  static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
>  {
>  #ifdef TARGET_RISCV64
> @@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
>      return false;
>  }
>
> -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
> -{
> -    if (a->rd != 0 && a->rs2 == 0) {
> -        /* C.JR */
> -        arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
> -        return trans_jalr(ctx, &arg);
> -    } else if (a->rd != 0 && a->rs2 != 0) {
> -        /* C.MV */
> -        arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
> -        return trans_add(ctx, &arg);
> -    }
> -    return false;
> -}
> -
> -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
> -{
> -    if (a->rd == 0 && a->rs2 == 0) {
> -        /* C.EBREAK */
> -        arg_ebreak arg = { };
> -        return trans_ebreak(ctx, &arg);
> -    } else if (a->rd != 0) {
> -        if (a->rs2 == 0) {
> -            /* C.JALR */
> -            arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
> -            return trans_jalr(ctx, &arg);
> -        } else {
> -            /* C.ADD */
> -            arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
> -            return trans_add(ctx, &arg);
> -        }
> -    }
> -    return false;
> -}
> -
>  static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
>  {
>  #ifdef TARGET_RISCV32
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index d420a4d8b2..caf91f9a05 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -18,6 +18,12 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> +static bool trans_illegal(DisasContext *ctx, arg_empty *a)
> +{
> +    gen_exception_illegal(ctx);
> +    return true;
> +}
> +
>  static bool trans_lui(DisasContext *ctx, arg_lui *a)
>  {
>      if (a->rd != 0) {
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index add9cf3923..3c79edf1c9 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -70,7 +70,6 @@
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> -@ciw       ...   ........ ... .. &ciw    nzuimm=%nzuimm_ciw           rd=%rs2_3
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
>  @cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> @@ -86,8 +85,12 @@
>  @c_sdsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
>  @c_swsp    ... . .....  ..... .. &s      imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
>  @c_li      ... . .....  ..... .. &i      imm=%imm_ci rs1=0 %rd
> +@c_lui     ... . .....  ..... .. &u      imm=%imm_lui %rd
> +@c_jalr    ... . .....  ..... .. &i      imm=0 rs1=%rd
> +@c_mv      ... . ..... .....  .. &i      imm=0 rs1=%rs2_5 %rd
>
> -@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
> +@c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> +@c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
>  @c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
>      uimm_ldsp=%uimm_6bit_ld %rd
>  @c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> @@ -101,7 +104,11 @@
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
>  # *** RV64C Standard Extension (Quadrant 0) ***
> -c_addi4spn        000    ........ ... 00 @ciw
> +{
> +  # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> +  illegal         000  000 000 00 --- 00
> +  addi            000  ... ... .. ... 00 @c_addi4spn
> +}
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
>  c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> @@ -113,7 +120,10 @@ c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>  addi              000 .  .....  ..... 01 @ci
>  c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
> -c_addi16sp_lui    011 .  .....  ..... 01 @c_addi16sp_lui # shares opc with C.LUI
> +{
> +  addi            011 .  00010  ..... 01 @c_addi16sp
> +  lui             011 .  .....  ..... 01 @c_lui
> +}
>  srli              100 . 00 ...  ..... 01 @c_shift
>  srai              100 . 01 ...  ..... 01 @c_shift
>  andi              100 . 10 ...  ..... 01 @c_andi
> @@ -132,8 +142,15 @@ slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
>  c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> -c_jr_mv           100 0  .....  ..... 10 @cr
> -c_ebreak_jalr_add 100 1  .....  ..... 10 @cr
> +{
> +  jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> +  addi            100 0  .....  ..... 10 @c_mv
> +}
> +{
> +  ebreak          100 1  00000  00000 10
> +  jalr            100 1  .....  00000 10 @c_jalr rd=1  # C.JALR
> +  add             100 1  .....  ..... 10 @cr
> +}
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
>  c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates all functions in insn_trans/trans_rvc.inc.c,
> so the entire file can be removed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
>  target/riscv/translate.c                |   2 -
>  target/riscv/Makefile.objs              |   9 +-
>  target/riscv/insn16-32.decode           |  28 ++++++
>  target/riscv/insn16-64.decode           |  30 +++++++
>  target/riscv/insn16.decode              |  35 +-------
>  6 files changed, 67 insertions(+), 152 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> deleted file mode 100644
> index 43bff97f66..0000000000
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ /dev/null
> @@ -1,115 +0,0 @@
> -/*
> - * RISC-V translation routines for the RVC Compressed Instruction Set.
> - *
> - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2 or later, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_i arg;
> -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> -    return trans_flw(ctx, &arg);
> -#else
> -    /* C.LD ( RV64C/RV128C-only ) */
> -    arg_i arg;
> -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> -    return trans_ld(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_s arg;
> -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> -    return trans_fsw(ctx, &arg);
> -#else
> -    /* C.SD ( RV64C/RV128C-only ) */
> -    arg_s arg;
> -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> -    return trans_sd(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.JAL */
> -    arg_j tmp;
> -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> -    return trans_jal(ctx, &arg);
> -#else
> -    /* C.ADDIW */
> -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addiw(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_subw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_addw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLWSP */
> -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> -    return trans_flw(ctx, &arg_flw);
> -#else
> -    /* C.LDSP */
> -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> -    return trans_ld(ctx, &arg_ld);
> -#endif
> -    return false;
> -}
> -
> -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSWSP */
> -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> -    return trans_fsw(ctx, &a_fsw);
> -#else
> -    /* C.SDSP */
> -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> -    return trans_sd(ctx, &a_sd);
> -#endif
> -}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a1cd29f80f..50d8f58e4b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>
>  #pragma GCC diagnostic pop
>
> -#include "insn_trans/trans_rvc.inc.c"
> -
>  static void decode_opc(DisasContext *ctx)
>  {
>      /* check for compressed insn */
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index c7a1b063ed..b1c79bc1d1 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
>  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
>  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
> +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> +
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
>            $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
> -target/riscv/decode_insn16.inc.c: \
> -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c
> diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> new file mode 100644
> index 0000000000..0819b17028
> --- /dev/null
> +++ b/target/riscv/insn16-32.decode
> @@ -0,0 +1,28 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV32C Standard Extension (Quadrant 0) ***
> +flw               011  ... ... .. ... 00 @cl_w
> +fsw               111  ... ... .. ... 00 @cs_w
> +
> +# *** RV32C Standard Extension (Quadrant 1) ***
> +jal               001     ........... 01 @cj    rd=1  # C.JAL
> +
> +# *** RV32C Standard Extension (Quadrant 2) ***
> +flw               011 .  .....  ..... 10 @c_lwsp
> +fsw               111 .  .....  ..... 10 @c_swsp
> diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> new file mode 100644
> index 0000000000..055859d29f
> --- /dev/null
> +++ b/target/riscv/insn16-64.decode
> @@ -0,0 +1,30 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV64C Standard Extension (Quadrant 0) ***
> +ld                011  ... ... .. ... 00 @cl_d
> +sd                111  ... ... .. ... 00 @cs_d
> +
> +# *** RV64C Standard Extension (Quadrant 1) ***
> +addiw             001 .  .....  ..... 01 @ci
> +subw              100 1 11 ... 00 ... 01 @cs_2
> +addw              100 1 11 ... 01 ... 01 @cs_2
> +
> +# *** RV64C Standard Extension (Quadrant 2) ***
> +ld                011 .  .....  ..... 10 @c_ldsp
> +sd                111 .  .....  ..... 10 @c_sdsp
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 3c79edf1c9..433c0e8c68 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -50,30 +50,12 @@
>  &u         imm rd       !extern
>  &shift     shamt rs1 rd !extern
>
> -# Argument sets:
> -&cl               rs1 rd
> -&cl_dw     uimm   rs1 rd
> -&ciw       nzuimm     rd
> -&cs               rs1 rs2
> -&cs_dw     uimm   rs1 rs2
> -&cb        imm    rs1
> -&cr               rd  rs2
> -&c_shift   shamt      rd
> -
> -&c_ld      uimm  rd
> -&c_sd      uimm  rs2
> -
> -&caddi16sp_lui  imm_lui imm_addi16sp rd
> -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
>  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
>  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
>  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> @@ -91,10 +73,6 @@
>
>  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
>  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> -    uimm_ldsp=%uimm_6bit_ld %rd
> -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
>                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> @@ -103,7 +81,7 @@
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> -# *** RV64C Standard Extension (Quadrant 0) ***
> +# *** RV32/64C Standard Extension (Quadrant 0) ***
>  {
>    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
>    illegal         000  000 000 00 --- 00
> @@ -111,14 +89,11 @@
>  }
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
> -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
>  fsd               101  ... ... .. ... 00 @cs_d
>  sw                110  ... ... .. ... 00 @cs_w
> -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
> -# *** RV64C Standard Extension (Quadrant 1) ***
> +# *** RV32/64C Standard Extension (Quadrant 1) ***
>  addi              000 .  .....  ..... 01 @ci
> -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  {
>    addi            011 .  00010  ..... 01 @c_addi16sp
> @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
>  or                100 0 11 ... 10 ... 01 @cs_2
>  and               100 0 11 ... 11 ... 01 @cs_2
> -c_subw            100 1 11 ... 00 ... 01 @cs_2
> -c_addw            100 1 11 ... 01 ... 01 @cs_2
>  jal               101     ........... 01 @cj    rd=0  # C.J
>  beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
> -# *** RV64C Standard Extension (Quadrant 2) ***
> +# *** RV32/64C Standard Extension (Quadrant 2) ***
>  slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
> -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  {
>    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
>    addi            100 0  .....  ..... 10 @c_mv
> @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  }
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
> -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates all functions in insn_trans/trans_rvc.inc.c,
> so the entire file can be removed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
>  target/riscv/translate.c                |   2 -
>  target/riscv/Makefile.objs              |   9 +-
>  target/riscv/insn16-32.decode           |  28 ++++++
>  target/riscv/insn16-64.decode           |  30 +++++++
>  target/riscv/insn16.decode              |  35 +-------
>  6 files changed, 67 insertions(+), 152 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> deleted file mode 100644
> index 43bff97f66..0000000000
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ /dev/null
> @@ -1,115 +0,0 @@
> -/*
> - * RISC-V translation routines for the RVC Compressed Instruction Set.
> - *
> - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2 or later, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_i arg;
> -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> -    return trans_flw(ctx, &arg);
> -#else
> -    /* C.LD ( RV64C/RV128C-only ) */
> -    arg_i arg;
> -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> -    return trans_ld(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_s arg;
> -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> -    return trans_fsw(ctx, &arg);
> -#else
> -    /* C.SD ( RV64C/RV128C-only ) */
> -    arg_s arg;
> -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> -    return trans_sd(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.JAL */
> -    arg_j tmp;
> -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> -    return trans_jal(ctx, &arg);
> -#else
> -    /* C.ADDIW */
> -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addiw(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_subw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_addw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLWSP */
> -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> -    return trans_flw(ctx, &arg_flw);
> -#else
> -    /* C.LDSP */
> -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> -    return trans_ld(ctx, &arg_ld);
> -#endif
> -    return false;
> -}
> -
> -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSWSP */
> -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> -    return trans_fsw(ctx, &a_fsw);
> -#else
> -    /* C.SDSP */
> -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> -    return trans_sd(ctx, &a_sd);
> -#endif
> -}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a1cd29f80f..50d8f58e4b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>
>  #pragma GCC diagnostic pop
>
> -#include "insn_trans/trans_rvc.inc.c"
> -
>  static void decode_opc(DisasContext *ctx)
>  {
>      /* check for compressed insn */
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index c7a1b063ed..b1c79bc1d1 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
>  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
>  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
> +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> +
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
>            $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
> -target/riscv/decode_insn16.inc.c: \
> -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c
> diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> new file mode 100644
> index 0000000000..0819b17028
> --- /dev/null
> +++ b/target/riscv/insn16-32.decode
> @@ -0,0 +1,28 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV32C Standard Extension (Quadrant 0) ***
> +flw               011  ... ... .. ... 00 @cl_w
> +fsw               111  ... ... .. ... 00 @cs_w
> +
> +# *** RV32C Standard Extension (Quadrant 1) ***
> +jal               001     ........... 01 @cj    rd=1  # C.JAL
> +
> +# *** RV32C Standard Extension (Quadrant 2) ***
> +flw               011 .  .....  ..... 10 @c_lwsp
> +fsw               111 .  .....  ..... 10 @c_swsp
> diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> new file mode 100644
> index 0000000000..055859d29f
> --- /dev/null
> +++ b/target/riscv/insn16-64.decode
> @@ -0,0 +1,30 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV64C Standard Extension (Quadrant 0) ***
> +ld                011  ... ... .. ... 00 @cl_d
> +sd                111  ... ... .. ... 00 @cs_d
> +
> +# *** RV64C Standard Extension (Quadrant 1) ***
> +addiw             001 .  .....  ..... 01 @ci
> +subw              100 1 11 ... 00 ... 01 @cs_2
> +addw              100 1 11 ... 01 ... 01 @cs_2
> +
> +# *** RV64C Standard Extension (Quadrant 2) ***
> +ld                011 .  .....  ..... 10 @c_ldsp
> +sd                111 .  .....  ..... 10 @c_sdsp
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 3c79edf1c9..433c0e8c68 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -50,30 +50,12 @@
>  &u         imm rd       !extern
>  &shift     shamt rs1 rd !extern
>
> -# Argument sets:
> -&cl               rs1 rd
> -&cl_dw     uimm   rs1 rd
> -&ciw       nzuimm     rd
> -&cs               rs1 rs2
> -&cs_dw     uimm   rs1 rs2
> -&cb        imm    rs1
> -&cr               rd  rs2
> -&c_shift   shamt      rd
> -
> -&c_ld      uimm  rd
> -&c_sd      uimm  rs2
> -
> -&caddi16sp_lui  imm_lui imm_addi16sp rd
> -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
>  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
>  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
>  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> @@ -91,10 +73,6 @@
>
>  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
>  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> -    uimm_ldsp=%uimm_6bit_ld %rd
> -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
>                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> @@ -103,7 +81,7 @@
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> -# *** RV64C Standard Extension (Quadrant 0) ***
> +# *** RV32/64C Standard Extension (Quadrant 0) ***
>  {
>    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
>    illegal         000  000 000 00 --- 00
> @@ -111,14 +89,11 @@
>  }
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
> -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
>  fsd               101  ... ... .. ... 00 @cs_d
>  sw                110  ... ... .. ... 00 @cs_w
> -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
> -# *** RV64C Standard Extension (Quadrant 1) ***
> +# *** RV32/64C Standard Extension (Quadrant 1) ***
>  addi              000 .  .....  ..... 01 @ci
> -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  {
>    addi            011 .  00010  ..... 01 @c_addi16sp
> @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
>  or                100 0 11 ... 10 ... 01 @cs_2
>  and               100 0 11 ... 11 ... 01 @cs_2
> -c_subw            100 1 11 ... 00 ... 01 @cs_2
> -c_addw            100 1 11 ... 01 ... 01 @cs_2
>  jal               101     ........... 01 @cj    rd=0  # C.J
>  beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
> -# *** RV64C Standard Extension (Quadrant 2) ***
> +# *** RV32/64C Standard Extension (Quadrant 2) ***
>  slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
> -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  {
>    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
>    addi            100 0  .....  ..... 10 @c_mv
> @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  }
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
> -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> This eliminates all functions in insn_trans/trans_rvc.inc.c,
> so the entire file can be removed.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
>  target/riscv/translate.c                |   2 -
>  target/riscv/Makefile.objs              |   9 +-
>  target/riscv/insn16-32.decode           |  28 ++++++
>  target/riscv/insn16-64.decode           |  30 +++++++
>  target/riscv/insn16.decode              |  35 +-------
>  6 files changed, 67 insertions(+), 152 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode
>
> diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> deleted file mode 100644
> index 43bff97f66..0000000000
> --- a/target/riscv/insn_trans/trans_rvc.inc.c
> +++ /dev/null
> @@ -1,115 +0,0 @@
> -/*
> - * RISC-V translation routines for the RVC Compressed Instruction Set.
> - *
> - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms and conditions of the GNU General Public License,
> - * version 2 or later, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program.  If not, see <http://www.gnu.org/licenses/>.
> - */
> -
> -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_i arg;
> -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> -    return trans_flw(ctx, &arg);
> -#else
> -    /* C.LD ( RV64C/RV128C-only ) */
> -    arg_i arg;
> -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> -    return trans_ld(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSW ( RV32FC-only ) */
> -    REQUIRE_FPU;
> -    REQUIRE_EXT(ctx, RVF);
> -
> -    arg_s arg;
> -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> -    return trans_fsw(ctx, &arg);
> -#else
> -    /* C.SD ( RV64C/RV128C-only ) */
> -    arg_s arg;
> -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> -    return trans_sd(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.JAL */
> -    arg_j tmp;
> -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> -    return trans_jal(ctx, &arg);
> -#else
> -    /* C.ADDIW */
> -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> -    return trans_addiw(ctx, &arg);
> -#endif
> -}
> -
> -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_subw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> -{
> -#ifdef TARGET_RISCV64
> -    return trans_addw(ctx, a);
> -#else
> -    return false;
> -#endif
> -}
> -
> -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FLWSP */
> -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> -    return trans_flw(ctx, &arg_flw);
> -#else
> -    /* C.LDSP */
> -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> -    return trans_ld(ctx, &arg_ld);
> -#endif
> -    return false;
> -}
> -
> -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> -{
> -#ifdef TARGET_RISCV32
> -    /* C.FSWSP */
> -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> -    return trans_fsw(ctx, &a_fsw);
> -#else
> -    /* C.SDSP */
> -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> -    return trans_sd(ctx, &a_sd);
> -#endif
> -}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a1cd29f80f..50d8f58e4b 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
>
>  #pragma GCC diagnostic pop
>
> -#include "insn_trans/trans_rvc.inc.c"
> -
>  static void decode_opc(DisasContext *ctx)
>  {
>      /* check for compressed insn */
> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index c7a1b063ed..b1c79bc1d1 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
>  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
>  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
>
> +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> +
>  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
>            $(decode32-y), "GEN", $(TARGET_DIR)$@)
>
> -target/riscv/decode_insn16.inc.c: \
> -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
>  	$(call quiet-command, \
>  	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
>
>  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
>  	target/riscv/decode_insn16.inc.c
> diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> new file mode 100644
> index 0000000000..0819b17028
> --- /dev/null
> +++ b/target/riscv/insn16-32.decode
> @@ -0,0 +1,28 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV32C Standard Extension (Quadrant 0) ***
> +flw               011  ... ... .. ... 00 @cl_w
> +fsw               111  ... ... .. ... 00 @cs_w
> +
> +# *** RV32C Standard Extension (Quadrant 1) ***
> +jal               001     ........... 01 @cj    rd=1  # C.JAL
> +
> +# *** RV32C Standard Extension (Quadrant 2) ***
> +flw               011 .  .....  ..... 10 @c_lwsp
> +fsw               111 .  .....  ..... 10 @c_swsp
> diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> new file mode 100644
> index 0000000000..055859d29f
> --- /dev/null
> +++ b/target/riscv/insn16-64.decode
> @@ -0,0 +1,30 @@
> +#
> +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> +#
> +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> +#
> +# This program is free software; you can redistribute it and/or modify it
> +# under the terms and conditions of the GNU General Public License,
> +# version 2 or later, as published by the Free Software Foundation.
> +#
> +# This program is distributed in the hope it will be useful, but WITHOUT
> +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> +# more details.
> +#
> +# You should have received a copy of the GNU General Public License along with
> +# this program.  If not, see <http://www.gnu.org/licenses/>.
> +
> +# *** RV64C Standard Extension (Quadrant 0) ***
> +ld                011  ... ... .. ... 00 @cl_d
> +sd                111  ... ... .. ... 00 @cs_d
> +
> +# *** RV64C Standard Extension (Quadrant 1) ***
> +addiw             001 .  .....  ..... 01 @ci
> +subw              100 1 11 ... 00 ... 01 @cs_2
> +addw              100 1 11 ... 01 ... 01 @cs_2
> +
> +# *** RV64C Standard Extension (Quadrant 2) ***
> +ld                011 .  .....  ..... 10 @c_ldsp
> +sd                111 .  .....  ..... 10 @c_sdsp
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 3c79edf1c9..433c0e8c68 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -50,30 +50,12 @@
>  &u         imm rd       !extern
>  &shift     shamt rs1 rd !extern
>
> -# Argument sets:
> -&cl               rs1 rd
> -&cl_dw     uimm   rs1 rd
> -&ciw       nzuimm     rd
> -&cs               rs1 rs2
> -&cs_dw     uimm   rs1 rs2
> -&cb        imm    rs1
> -&cr               rd  rs2
> -&c_shift   shamt      rd
> -
> -&c_ld      uimm  rd
> -&c_sd      uimm  rs2
> -
> -&caddi16sp_lui  imm_lui imm_addi16sp rd
> -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
>
>  # Formats 16:
>  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
>  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
>  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
>  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
>  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
>  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
>  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> @@ -91,10 +73,6 @@
>
>  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
>  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> -    uimm_ldsp=%uimm_6bit_ld %rd
> -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
>
>  @c_shift        ... . .. ... ..... .. \
>                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> @@ -103,7 +81,7 @@
>
>  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
>
> -# *** RV64C Standard Extension (Quadrant 0) ***
> +# *** RV32/64C Standard Extension (Quadrant 0) ***
>  {
>    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
>    illegal         000  000 000 00 --- 00
> @@ -111,14 +89,11 @@
>  }
>  fld               001  ... ... .. ... 00 @cl_d
>  lw                010  ... ... .. ... 00 @cl_w
> -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
>  fsd               101  ... ... .. ... 00 @cs_d
>  sw                110  ... ... .. ... 00 @cs_w
> -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
>
> -# *** RV64C Standard Extension (Quadrant 1) ***
> +# *** RV32/64C Standard Extension (Quadrant 1) ***
>  addi              000 .  .....  ..... 01 @ci
> -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
>  addi              010 .  .....  ..... 01 @c_li
>  {
>    addi            011 .  00010  ..... 01 @c_addi16sp
> @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
>  xor               100 0 11 ... 01 ... 01 @cs_2
>  or                100 0 11 ... 10 ... 01 @cs_2
>  and               100 0 11 ... 11 ... 01 @cs_2
> -c_subw            100 1 11 ... 00 ... 01 @cs_2
> -c_addw            100 1 11 ... 01 ... 01 @cs_2
>  jal               101     ........... 01 @cj    rd=0  # C.J
>  beq               110  ... ...  ..... 01 @cb_z
>  bne               111  ... ...  ..... 01 @cb_z
>
> -# *** RV64C Standard Extension (Quadrant 2) ***
> +# *** RV32/64C Standard Extension (Quadrant 2) ***
>  slli              000 .  .....  ..... 10 @c_shift2
>  fld               001 .  .....  ..... 10 @c_ldsp
>  lw                010 .  .....  ..... 10 @c_lwsp
> -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  {
>    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
>    addi            100 0  .....  ..... 10 @c_mv
> @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
>  }
>  fsd               101   ......  ..... 10 @c_sdsp
>  sw                110 .  .....  ..... 10 @c_swsp
> -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:54 PDT (-0700), richard.henderson@linaro.org wrote:
> The tcg_gen_fooi_tl functions have some immediate constant
> folding built in, which match up with some of the riscv asm
> builtin macros, like mv and not.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
>  target/riscv/translate.c                | 19 +++++++++++++++++--
>  2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index caf91f9a05..620df5f323 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
>
>  static bool trans_addi(DisasContext *ctx, arg_addi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
>  }
>
>  static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
> @@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
>
>  static bool trans_slti(DisasContext *ctx, arg_slti *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_slt);
> +    return gen_arith_imm_tl(ctx, a, &gen_slt);
>  }
>
>  static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_sltu);
> +    return gen_arith_imm_tl(ctx, a, &gen_sltu);
>  }
>
>  static bool trans_xori(DisasContext *ctx, arg_xori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
>  }
>  static bool trans_ori(DisasContext *ctx, arg_ori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
>  }
>  static bool trans_andi(DisasContext *ctx, arg_andi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
>  }
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
>  {
> @@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
>  #ifdef TARGET_RISCV64
>  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_addw);
> +    return gen_arith_imm_tl(ctx, a, &gen_addw);
>  }
>
>  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 50d8f58e4b..fb66e886bf 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -547,8 +547,23 @@ static int ex_rvc_shifti(int imm)
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> -static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
> -                          void(*func)(TCGv, TCGv, TCGv))
> +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, target_long))
> +{
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +
> +    gen_get_gpr(source1, a->rs1);
> +
> +    (*func)(source1, source1, a->imm);
> +
> +    gen_set_gpr(a->rd, source1);
> +    tcg_temp_free(source1);
> +    return true;
> +}
> +
> +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, TCGv))
>  {
>      TCGv source1, source2;
>      source1 = tcg_temp_new();

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:54 PDT (-0700), richard.henderson@linaro.org wrote:
> The tcg_gen_fooi_tl functions have some immediate constant
> folding built in, which match up with some of the riscv asm
> builtin macros, like mv and not.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
>  target/riscv/translate.c                | 19 +++++++++++++++++--
>  2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index caf91f9a05..620df5f323 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
>
>  static bool trans_addi(DisasContext *ctx, arg_addi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
>  }
>
>  static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
> @@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
>
>  static bool trans_slti(DisasContext *ctx, arg_slti *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_slt);
> +    return gen_arith_imm_tl(ctx, a, &gen_slt);
>  }
>
>  static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_sltu);
> +    return gen_arith_imm_tl(ctx, a, &gen_sltu);
>  }
>
>  static bool trans_xori(DisasContext *ctx, arg_xori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
>  }
>  static bool trans_ori(DisasContext *ctx, arg_ori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
>  }
>  static bool trans_andi(DisasContext *ctx, arg_andi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
>  }
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
>  {
> @@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
>  #ifdef TARGET_RISCV64
>  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_addw);
> +    return gen_arith_imm_tl(ctx, a, &gen_addw);
>  }
>
>  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 50d8f58e4b..fb66e886bf 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -547,8 +547,23 @@ static int ex_rvc_shifti(int imm)
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> -static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
> -                          void(*func)(TCGv, TCGv, TCGv))
> +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, target_long))
> +{
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +
> +    gen_get_gpr(source1, a->rs1);
> +
> +    (*func)(source1, source1, a->imm);
> +
> +    gen_set_gpr(a->rd, source1);
> +    tcg_temp_free(source1);
> +    return true;
> +}
> +
> +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, TCGv))
>  {
>      TCGv source1, source2;
>      source1 = tcg_temp_new();

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:54 PDT (-0700), richard.henderson@linaro.org wrote:
> The tcg_gen_fooi_tl functions have some immediate constant
> folding built in, which match up with some of the riscv asm
> builtin macros, like mv and not.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++-------
>  target/riscv/translate.c                | 19 +++++++++++++++++--
>  2 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index caf91f9a05..620df5f323 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
>
>  static bool trans_addi(DisasContext *ctx, arg_addi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
>  }
>
>  static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
> @@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
>
>  static bool trans_slti(DisasContext *ctx, arg_slti *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_slt);
> +    return gen_arith_imm_tl(ctx, a, &gen_slt);
>  }
>
>  static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_sltu);
> +    return gen_arith_imm_tl(ctx, a, &gen_sltu);
>  }
>
>  static bool trans_xori(DisasContext *ctx, arg_xori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
>  }
>  static bool trans_ori(DisasContext *ctx, arg_ori *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
>  }
>  static bool trans_andi(DisasContext *ctx, arg_andi *a)
>  {
> -    return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
> +    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
>  }
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
>  {
> @@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
>  #ifdef TARGET_RISCV64
>  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
>  {
> -    return gen_arith_imm(ctx, a, &gen_addw);
> +    return gen_arith_imm_tl(ctx, a, &gen_addw);
>  }
>
>  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 50d8f58e4b..fb66e886bf 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -547,8 +547,23 @@ static int ex_rvc_shifti(int imm)
>  /* Include the auto-generated decoder for 32 bit insn */
>  #include "decode_insn32.inc.c"
>
> -static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
> -                          void(*func)(TCGv, TCGv, TCGv))
> +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, target_long))
> +{
> +    TCGv source1;
> +    source1 = tcg_temp_new();
> +
> +    gen_get_gpr(source1, a->rs1);
> +
> +    (*func)(source1, source1, a->imm);
> +
> +    gen_set_gpr(a->rd, source1);
> +    tcg_temp_free(source1);
> +    return true;
> +}
> +
> +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
> +                             void (*func)(TCGv, TCGv, TCGv))
>  {
>      TCGv source1, source2;
>      source1 = tcg_temp_new();

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:55 PDT (-0700), richard.henderson@linaro.org wrote:
> These extra spaces make the "-d op" dump look weird.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/cpu.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d61bce6d55..624528efb5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -29,17 +29,17 @@
>  static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
>  const char * const riscv_int_regnames[] = {
> -  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",
> -  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",
> -  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",
> -  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "
> +  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
> +  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
> +  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
> +  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
>  };
>
>  const char * const riscv_fpr_regnames[] = {
> -  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",
> -  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",
> -  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",
> -  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"
> +  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
> +  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
> +  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
> +  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>  };
>
>  const char * const riscv_excp_names[] = {

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:55 PDT (-0700), richard.henderson@linaro.org wrote:
> These extra spaces make the "-d op" dump look weird.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/cpu.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d61bce6d55..624528efb5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -29,17 +29,17 @@
>  static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
>  const char * const riscv_int_regnames[] = {
> -  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",
> -  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",
> -  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",
> -  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "
> +  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
> +  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
> +  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
> +  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
>  };
>
>  const char * const riscv_fpr_regnames[] = {
> -  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",
> -  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",
> -  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",
> -  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"
> +  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
> +  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
> +  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
> +  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>  };
>
>  const char * const riscv_excp_names[] = {

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:55 PDT (-0700), richard.henderson@linaro.org wrote:
> These extra spaces make the "-d op" dump look weird.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/cpu.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d61bce6d55..624528efb5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -29,17 +29,17 @@
>  static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
>
>  const char * const riscv_int_regnames[] = {
> -  "zero", "ra  ", "sp  ", "gp  ", "tp  ", "t0  ", "t1  ", "t2  ",
> -  "s0  ", "s1  ", "a0  ", "a1  ", "a2  ", "a3  ", "a4  ", "a5  ",
> -  "a6  ", "a7  ", "s2  ", "s3  ", "s4  ", "s5  ", "s6  ", "s7  ",
> -  "s8  ", "s9  ", "s10 ", "s11 ", "t3  ", "t4  ", "t5  ", "t6  "
> +  "zero", "ra", "sp",  "gp",  "tp", "t0", "t1", "t2",
> +  "s0",   "s1", "a0",  "a1",  "a2", "a3", "a4", "a5",
> +  "a6",   "a7", "s2",  "s3",  "s4", "s5", "s6", "s7",
> +  "s8",   "s9", "s10", "s11", "t3", "t4", "t5", "t6"
>  };
>
>  const char * const riscv_fpr_regnames[] = {
> -  "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ",  "ft7 ",
> -  "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ",  "fa5 ",
> -  "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ",  "fs7 ",
> -  "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10",  "ft11"
> +  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
> +  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
> +  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
> +  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
>  };
>
>  const char * const riscv_excp_names[] = {

Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:47 PDT (-0700), richard.henderson@linaro.org wrote:
> There's new support in decodetree for pattern groups.
> I believe that patch 5, or something close to it, was
> posted as an RFC as part of the original pattern group
> patch set, but this cleans that up further.
>
>
> r~
>
>
> Richard Henderson (8):
>   target/riscv: Name the argument sets for all of insn32 formats
>   target/riscv: Use --static-decode for decodetree
>   target/riscv: Merge argument sets for insn32 and insn16
>   target/riscv: Merge argument decode for RVC shifti
>   target/riscv: Use pattern groups in insn16.decode
>   target/riscv: Split RVC32 and RVC64 insns into separate files
>   target/riscv: Split gen_arith_imm into functional and temp
>   target/riscv: Remove spaces from register names
>
>  target/riscv/cpu.c                      |  16 +-
>  target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
>  target/riscv/translate.c                |  40 ++-
>  target/riscv/Makefile.objs              |  15 +-
>  target/riscv/insn16-32.decode           |  28 ++
>  target/riscv/insn16-64.decode           |  30 ++
>  target/riscv/insn16.decode              | 154 ++++++-----
>  target/riscv/insn32.decode              |  10 +-
>  9 files changed, 205 insertions(+), 455 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode

Thanks!  I'm happy taking this as it stands, since all those decode issues I
pointed out aren't regressions in this patch set.  Let me know if you want to
fix those or if you want me to -- as you can probably tell my email queue is a
bit long... :)

I've dropped this on my integration branch, but I probably won't submit a pull
for a week or so.

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:47 PDT (-0700), richard.henderson@linaro.org wrote:
> There's new support in decodetree for pattern groups.
> I believe that patch 5, or something close to it, was
> posted as an RFC as part of the original pattern group
> patch set, but this cleans that up further.
>
>
> r~
>
>
> Richard Henderson (8):
>   target/riscv: Name the argument sets for all of insn32 formats
>   target/riscv: Use --static-decode for decodetree
>   target/riscv: Merge argument sets for insn32 and insn16
>   target/riscv: Merge argument decode for RVC shifti
>   target/riscv: Use pattern groups in insn16.decode
>   target/riscv: Split RVC32 and RVC64 insns into separate files
>   target/riscv: Split gen_arith_imm into functional and temp
>   target/riscv: Remove spaces from register names
>
>  target/riscv/cpu.c                      |  16 +-
>  target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
>  target/riscv/translate.c                |  40 ++-
>  target/riscv/Makefile.objs              |  15 +-
>  target/riscv/insn16-32.decode           |  28 ++
>  target/riscv/insn16-64.decode           |  30 ++
>  target/riscv/insn16.decode              | 154 ++++++-----
>  target/riscv/insn32.decode              |  10 +-
>  9 files changed, 205 insertions(+), 455 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode

Thanks!  I'm happy taking this as it stands, since all those decode issues I
pointed out aren't regressions in this patch set.  Let me know if you want to
fix those or if you want me to -- as you can probably tell my email queue is a
bit long... :)

I've dropped this on my integration branch, but I probably won't submit a pull
for a week or so.

Re: [Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Sun, 31 Mar 2019 20:11:47 PDT (-0700), richard.henderson@linaro.org wrote:
> There's new support in decodetree for pattern groups.
> I believe that patch 5, or something close to it, was
> posted as an RFC as part of the original pattern group
> patch set, but this cleans that up further.
>
>
> r~
>
>
> Richard Henderson (8):
>   target/riscv: Name the argument sets for all of insn32 formats
>   target/riscv: Use --static-decode for decodetree
>   target/riscv: Merge argument sets for insn32 and insn16
>   target/riscv: Merge argument decode for RVC shifti
>   target/riscv: Use pattern groups in insn16.decode
>   target/riscv: Split RVC32 and RVC64 insns into separate files
>   target/riscv: Split gen_arith_imm into functional and temp
>   target/riscv: Remove spaces from register names
>
>  target/riscv/cpu.c                      |  16 +-
>  target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
>  target/riscv/translate.c                |  40 ++-
>  target/riscv/Makefile.objs              |  15 +-
>  target/riscv/insn16-32.decode           |  28 ++
>  target/riscv/insn16-64.decode           |  30 ++
>  target/riscv/insn16.decode              | 154 ++++++-----
>  target/riscv/insn32.decode              |  10 +-
>  9 files changed, 205 insertions(+), 455 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode

Thanks!  I'm happy taking this as it stands, since all those decode issues I
pointed out aren't regressions in this patch set.  Let me know if you want to
fix those or if you want me to -- as you can probably tell my email queue is a
bit long... :)

I've dropped this on my integration branch, but I probably won't submit a pull
for a week or so.

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
> re-introduce the shim to handle that quirk, but since it's not actually a new
> bug I'm OK taking the patch set and fixing that later.

That should be fixable in the decode file, without a shim.
See patch 5, where I introduce trans_illegal, for doing
exactly this for c.addi4spn.


r~

Re: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
> re-introduce the shim to handle that quirk, but since it's not actually a new
> bug I'm OK taking the patch set and fixing that later.

That should be fixable in the decode file, without a shim.
See patch 5, where I introduce trans_illegal, for doing
exactly this for c.addi4spn.


r~

Re: [Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> c.lwsp with rd=0 should be an illegal instruction, but it's not.  We'd need to
> re-introduce the shim to handle that quirk, but since it's not actually a new
> bug I'm OK taking the patch set and fixing that later.

That should be fixable in the decode file, without a shim.
See patch 5, where I introduce trans_illegal, for doing
exactly this for c.addi4spn.


r~

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> 
> Thanks!  I'm happy taking this as it stands, since all those decode issues I
> pointed out aren't regressions in this patch set.  Let me know if you want to
> fix those or if you want me to -- as you can probably tell my email queue is a
> bit long... :)

I'm happy to fix those, if you'll point me at your branch.


r~

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> 
> Thanks!  I'm happy taking this as it stands, since all those decode issues I
> pointed out aren't regressions in this patch set.  Let me know if you want to
> fix those or if you want me to -- as you can probably tell my email queue is a
> bit long... :)

I'm happy to fix those, if you'll point me at your branch.


r~

Re: [Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> 
> Thanks!  I'm happy taking this as it stands, since all those decode issues I
> pointed out aren't regressions in this patch set.  Let me know if you want to
> fix those or if you want me to -- as you can probably tell my email queue is a
> bit long... :)

I'm happy to fix those, if you'll point me at your branch.


r~

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>  # *** RV64C Standard Extension (Quadrant 2) ***
>> -c_slli            000 .  .....  ..... 10 @c_shift2
>> +slli              000 .  .....  ..... 10 @c_shift2
> 
> This is another one where rd=0 is illegal in the compressed ISA, but again we
> don't appear to handle these correctly before the cleanups.

I see "HINT, rd=0" in the 2.2 documentation for this case.


r~

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>  # *** RV64C Standard Extension (Quadrant 2) ***
>> -c_slli            000 .  .....  ..... 10 @c_shift2
>> +slli              000 .  .....  ..... 10 @c_shift2
> 
> This is another one where rd=0 is illegal in the compressed ISA, but again we
> don't appear to handle these correctly before the cleanups.

I see "HINT, rd=0" in the 2.2 documentation for this case.


r~

Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Richard Henderson]

On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>  # *** RV64C Standard Extension (Quadrant 2) ***
>> -c_slli            000 .  .....  ..... 10 @c_shift2
>> +slli              000 .  .....  ..... 10 @c_shift2
> 
> This is another one where rd=0 is illegal in the compressed ISA, but again we
> don't appear to handle these correctly before the cleanups.

I see "HINT, rd=0" in the 2.2 documentation for this case.


r~

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:23:56 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>
>> Thanks!  I'm happy taking this as it stands, since all those decode issues I
>> pointed out aren't regressions in this patch set.  Let me know if you want to
>> fix those or if you want me to -- as you can probably tell my email queue is a
>> bit long... :)
>
> I'm happy to fix those, if you'll point me at your branch.

github.com/palmer-dabbelt/riscv-qemu, for-master branch.  I haven't sent the PR
because I haven't banged on the branch yet, but I don't anticipate any major
problems.

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:23:56 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>
>> Thanks!  I'm happy taking this as it stands, since all those decode issues I
>> pointed out aren't regressions in this patch set.  Let me know if you want to
>> fix those or if you want me to -- as you can probably tell my email queue is a
>> bit long... :)
>
> I'm happy to fix those, if you'll point me at your branch.

github.com/palmer-dabbelt/riscv-qemu, for-master branch.  I haven't sent the PR
because I haven't banged on the branch yet, but I don't anticipate any major
problems.

Re: [Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:23:56 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>
>> Thanks!  I'm happy taking this as it stands, since all those decode issues I
>> pointed out aren't regressions in this patch set.  Let me know if you want to
>> fix those or if you want me to -- as you can probably tell my email queue is a
>> bit long... :)
>
> I'm happy to fix those, if you'll point me at your branch.

github.com/palmer-dabbelt/riscv-qemu, for-master branch.  I haven't sent the PR
because I haven't banged on the branch yet, but I don't anticipate any major
problems.

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:50:41 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>>  # *** RV64C Standard Extension (Quadrant 2) ***
>>> -c_slli            000 .  .....  ..... 10 @c_shift2
>>> +slli              000 .  .....  ..... 10 @c_shift2
>>
>> This is another one where rd=0 is illegal in the compressed ISA, but again we
>> don't appear to handle these correctly before the cleanups.
>
> I see "HINT, rd=0" in the 2.2 documentation for this case.

Looks like you're right -- I was assuming the "rd != 0" to mean that it was an
illegal instruction, but I just confirmed with Andrew that it's legal.  In this
case (and probably the others I mentioned), I think QEMU is correct already.

Re: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:50:41 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>>  # *** RV64C Standard Extension (Quadrant 2) ***
>>> -c_slli            000 .  .....  ..... 10 @c_shift2
>>> +slli              000 .  .....  ..... 10 @c_shift2
>>
>> This is another one where rd=0 is illegal in the compressed ISA, but again we
>> don't appear to handle these correctly before the cleanups.
>
> I see "HINT, rd=0" in the 2.2 documentation for this case.

Looks like you're right -- I was assuming the "rd != 0" to mean that it was an
illegal instruction, but I just confirmed with Andrew that it's legal.  In this
case (and probably the others I mentioned), I think QEMU is correct already.

Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti

[Palmer Dabbelt]

On Thu, 25 Apr 2019 09:50:41 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>>  # *** RV64C Standard Extension (Quadrant 2) ***
>>> -c_slli            000 .  .....  ..... 10 @c_shift2
>>> +slli              000 .  .....  ..... 10 @c_shift2
>>
>> This is another one where rd=0 is illegal in the compressed ISA, but again we
>> don't appear to handle these correctly before the cleanups.
>
> I see "HINT, rd=0" in the 2.2 documentation for this case.

Looks like you're right -- I was assuming the "rd != 0" to mean that it was an
illegal instruction, but I just confirmed with Andrew that it's legal.  In this
case (and probably the others I mentioned), I think QEMU is correct already.

Re: [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Alistair Francis]

On Thu, Apr 25, 2019 at 9:04 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> > This eliminates all functions in insn_trans/trans_rvc.inc.c,
> > so the entire file can be removed.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

You need to remove the line in: target/riscv/translate.c:710
    #include "insn_trans/trans_rvc.inc.c"

otherwise this patch doesn't compile.

Alistair

> > ---
> >  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
> >  target/riscv/translate.c                |   2 -
> >  target/riscv/Makefile.objs              |   9 +-
> >  target/riscv/insn16-32.decode           |  28 ++++++
> >  target/riscv/insn16-64.decode           |  30 +++++++
> >  target/riscv/insn16.decode              |  35 +-------
> >  6 files changed, 67 insertions(+), 152 deletions(-)
> >  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
> >  create mode 100644 target/riscv/insn16-32.decode
> >  create mode 100644 target/riscv/insn16-64.decode
> >
> > diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> > deleted file mode 100644
> > index 43bff97f66..0000000000
> > --- a/target/riscv/insn_trans/trans_rvc.inc.c
> > +++ /dev/null
> > @@ -1,115 +0,0 @@
> > -/*
> > - * RISC-V translation routines for the RVC Compressed Instruction Set.
> > - *
> > - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> > - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > - *
> > - * This program is free software; you can redistribute it and/or modify it
> > - * under the terms and conditions of the GNU General Public License,
> > - * version 2 or later, as published by the Free Software Foundation.
> > - *
> > - * This program is distributed in the hope it will be useful, but WITHOUT
> > - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > - * more details.
> > - *
> > - * You should have received a copy of the GNU General Public License along with
> > - * this program.  If not, see <http://www.gnu.org/licenses/>.
> > - */
> > -
> > -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> > -    return trans_flw(ctx, &arg);
> > -#else
> > -    /* C.LD ( RV64C/RV128C-only ) */
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> > -    return trans_ld(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> > -    return trans_fsw(ctx, &arg);
> > -#else
> > -    /* C.SD ( RV64C/RV128C-only ) */
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> > -    return trans_sd(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.JAL */
> > -    arg_j tmp;
> > -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> > -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> > -    return trans_jal(ctx, &arg);
> > -#else
> > -    /* C.ADDIW */
> > -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> > -    return trans_addiw(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_subw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_addw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLWSP */
> > -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> > -    return trans_flw(ctx, &arg_flw);
> > -#else
> > -    /* C.LDSP */
> > -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> > -    return trans_ld(ctx, &arg_ld);
> > -#endif
> > -    return false;
> > -}
> > -
> > -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSWSP */
> > -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> > -    return trans_fsw(ctx, &a_fsw);
> > -#else
> > -    /* C.SDSP */
> > -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> > -    return trans_sd(ctx, &a_sd);
> > -#endif
> > -}
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index a1cd29f80f..50d8f58e4b 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
> >
> >  #pragma GCC diagnostic pop
> >
> > -#include "insn_trans/trans_rvc.inc.c"
> > -
> >  static void decode_opc(DisasContext *ctx)
> >  {
> >      /* check for compressed insn */
> > diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> > index c7a1b063ed..b1c79bc1d1 100644
> > --- a/target/riscv/Makefile.objs
> > +++ b/target/riscv/Makefile.objs
> > @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
> >  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
> >  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
> >
> > +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> > +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> > +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> > +
> >  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> >            $(decode32-y), "GEN", $(TARGET_DIR)$@)
> >
> > -target/riscv/decode_insn16.inc.c: \
> > -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> > +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> > -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> > +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
> >
> >  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
> >       target/riscv/decode_insn16.inc.c
> > diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> > new file mode 100644
> > index 0000000000..0819b17028
> > --- /dev/null
> > +++ b/target/riscv/insn16-32.decode
> > @@ -0,0 +1,28 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV32C Standard Extension (Quadrant 0) ***
> > +flw               011  ... ... .. ... 00 @cl_w
> > +fsw               111  ... ... .. ... 00 @cs_w
> > +
> > +# *** RV32C Standard Extension (Quadrant 1) ***
> > +jal               001     ........... 01 @cj    rd=1  # C.JAL
> > +
> > +# *** RV32C Standard Extension (Quadrant 2) ***
> > +flw               011 .  .....  ..... 10 @c_lwsp
> > +fsw               111 .  .....  ..... 10 @c_swsp
> > diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> > new file mode 100644
> > index 0000000000..055859d29f
> > --- /dev/null
> > +++ b/target/riscv/insn16-64.decode
> > @@ -0,0 +1,30 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV64C Standard Extension (Quadrant 0) ***
> > +ld                011  ... ... .. ... 00 @cl_d
> > +sd                111  ... ... .. ... 00 @cs_d
> > +
> > +# *** RV64C Standard Extension (Quadrant 1) ***
> > +addiw             001 .  .....  ..... 01 @ci
> > +subw              100 1 11 ... 00 ... 01 @cs_2
> > +addw              100 1 11 ... 01 ... 01 @cs_2
> > +
> > +# *** RV64C Standard Extension (Quadrant 2) ***
> > +ld                011 .  .....  ..... 10 @c_ldsp
> > +sd                111 .  .....  ..... 10 @c_sdsp
> > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> > index 3c79edf1c9..433c0e8c68 100644
> > --- a/target/riscv/insn16.decode
> > +++ b/target/riscv/insn16.decode
> > @@ -50,30 +50,12 @@
> >  &u         imm rd       !extern
> >  &shift     shamt rs1 rd !extern
> >
> > -# Argument sets:
> > -&cl               rs1 rd
> > -&cl_dw     uimm   rs1 rd
> > -&ciw       nzuimm     rd
> > -&cs               rs1 rs2
> > -&cs_dw     uimm   rs1 rs2
> > -&cb        imm    rs1
> > -&cr               rd  rs2
> > -&c_shift   shamt      rd
> > -
> > -&c_ld      uimm  rd
> > -&c_sd      uimm  rs2
> > -
> > -&caddi16sp_lui  imm_lui imm_addi16sp rd
> > -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> > -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
> >
> >  # Formats 16:
> >  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> >  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> >  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> >  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> > -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> > -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> >  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> >  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> >  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> > @@ -91,10 +73,6 @@
> >
> >  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> >  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> > -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> > -    uimm_ldsp=%uimm_6bit_ld %rd
> > -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> > -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
> >
> >  @c_shift        ... . .. ... ..... .. \
> >                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> > @@ -103,7 +81,7 @@
> >
> >  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
> >
> > -# *** RV64C Standard Extension (Quadrant 0) ***
> > +# *** RV32/64C Standard Extension (Quadrant 0) ***
> >  {
> >    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> >    illegal         000  000 000 00 --- 00
> > @@ -111,14 +89,11 @@
> >  }
> >  fld               001  ... ... .. ... 00 @cl_d
> >  lw                010  ... ... .. ... 00 @cl_w
> > -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> >  fsd               101  ... ... .. ... 00 @cs_d
> >  sw                110  ... ... .. ... 00 @cs_w
> > -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
> >
> > -# *** RV64C Standard Extension (Quadrant 1) ***
> > +# *** RV32/64C Standard Extension (Quadrant 1) ***
> >  addi              000 .  .....  ..... 01 @ci
> > -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> >  addi              010 .  .....  ..... 01 @c_li
> >  {
> >    addi            011 .  00010  ..... 01 @c_addi16sp
> > @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
> >  xor               100 0 11 ... 01 ... 01 @cs_2
> >  or                100 0 11 ... 10 ... 01 @cs_2
> >  and               100 0 11 ... 11 ... 01 @cs_2
> > -c_subw            100 1 11 ... 00 ... 01 @cs_2
> > -c_addw            100 1 11 ... 01 ... 01 @cs_2
> >  jal               101     ........... 01 @cj    rd=0  # C.J
> >  beq               110  ... ...  ..... 01 @cb_z
> >  bne               111  ... ...  ..... 01 @cb_z
> >
> > -# *** RV64C Standard Extension (Quadrant 2) ***
> > +# *** RV32/64C Standard Extension (Quadrant 2) ***
> >  slli              000 .  .....  ..... 10 @c_shift2
> >  fld               001 .  .....  ..... 10 @c_ldsp
> >  lw                010 .  .....  ..... 10 @c_lwsp
> > -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  {
> >    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> >    addi            100 0  .....  ..... 10 @c_mv
> > @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  }
> >  fsd               101   ......  ..... 10 @c_sdsp
> >  sw                110 .  .....  ..... 10 @c_swsp
> > -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>

Re: [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Alistair Francis]

On Thu, Apr 25, 2019 at 9:04 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> > This eliminates all functions in insn_trans/trans_rvc.inc.c,
> > so the entire file can be removed.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

You need to remove the line in: target/riscv/translate.c:710
    #include "insn_trans/trans_rvc.inc.c"

otherwise this patch doesn't compile.

Alistair

> > ---
> >  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
> >  target/riscv/translate.c                |   2 -
> >  target/riscv/Makefile.objs              |   9 +-
> >  target/riscv/insn16-32.decode           |  28 ++++++
> >  target/riscv/insn16-64.decode           |  30 +++++++
> >  target/riscv/insn16.decode              |  35 +-------
> >  6 files changed, 67 insertions(+), 152 deletions(-)
> >  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
> >  create mode 100644 target/riscv/insn16-32.decode
> >  create mode 100644 target/riscv/insn16-64.decode
> >
> > diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> > deleted file mode 100644
> > index 43bff97f66..0000000000
> > --- a/target/riscv/insn_trans/trans_rvc.inc.c
> > +++ /dev/null
> > @@ -1,115 +0,0 @@
> > -/*
> > - * RISC-V translation routines for the RVC Compressed Instruction Set.
> > - *
> > - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> > - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > - *
> > - * This program is free software; you can redistribute it and/or modify it
> > - * under the terms and conditions of the GNU General Public License,
> > - * version 2 or later, as published by the Free Software Foundation.
> > - *
> > - * This program is distributed in the hope it will be useful, but WITHOUT
> > - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > - * more details.
> > - *
> > - * You should have received a copy of the GNU General Public License along with
> > - * this program.  If not, see <http://www.gnu.org/licenses/>.
> > - */
> > -
> > -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> > -    return trans_flw(ctx, &arg);
> > -#else
> > -    /* C.LD ( RV64C/RV128C-only ) */
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> > -    return trans_ld(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> > -    return trans_fsw(ctx, &arg);
> > -#else
> > -    /* C.SD ( RV64C/RV128C-only ) */
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> > -    return trans_sd(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.JAL */
> > -    arg_j tmp;
> > -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> > -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> > -    return trans_jal(ctx, &arg);
> > -#else
> > -    /* C.ADDIW */
> > -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> > -    return trans_addiw(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_subw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_addw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLWSP */
> > -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> > -    return trans_flw(ctx, &arg_flw);
> > -#else
> > -    /* C.LDSP */
> > -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> > -    return trans_ld(ctx, &arg_ld);
> > -#endif
> > -    return false;
> > -}
> > -
> > -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSWSP */
> > -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> > -    return trans_fsw(ctx, &a_fsw);
> > -#else
> > -    /* C.SDSP */
> > -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> > -    return trans_sd(ctx, &a_sd);
> > -#endif
> > -}
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index a1cd29f80f..50d8f58e4b 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
> >
> >  #pragma GCC diagnostic pop
> >
> > -#include "insn_trans/trans_rvc.inc.c"
> > -
> >  static void decode_opc(DisasContext *ctx)
> >  {
> >      /* check for compressed insn */
> > diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> > index c7a1b063ed..b1c79bc1d1 100644
> > --- a/target/riscv/Makefile.objs
> > +++ b/target/riscv/Makefile.objs
> > @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
> >  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
> >  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
> >
> > +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> > +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> > +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> > +
> >  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> >            $(decode32-y), "GEN", $(TARGET_DIR)$@)
> >
> > -target/riscv/decode_insn16.inc.c: \
> > -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> > +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> > -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> > +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
> >
> >  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
> >       target/riscv/decode_insn16.inc.c
> > diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> > new file mode 100644
> > index 0000000000..0819b17028
> > --- /dev/null
> > +++ b/target/riscv/insn16-32.decode
> > @@ -0,0 +1,28 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV32C Standard Extension (Quadrant 0) ***
> > +flw               011  ... ... .. ... 00 @cl_w
> > +fsw               111  ... ... .. ... 00 @cs_w
> > +
> > +# *** RV32C Standard Extension (Quadrant 1) ***
> > +jal               001     ........... 01 @cj    rd=1  # C.JAL
> > +
> > +# *** RV32C Standard Extension (Quadrant 2) ***
> > +flw               011 .  .....  ..... 10 @c_lwsp
> > +fsw               111 .  .....  ..... 10 @c_swsp
> > diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> > new file mode 100644
> > index 0000000000..055859d29f
> > --- /dev/null
> > +++ b/target/riscv/insn16-64.decode
> > @@ -0,0 +1,30 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV64C Standard Extension (Quadrant 0) ***
> > +ld                011  ... ... .. ... 00 @cl_d
> > +sd                111  ... ... .. ... 00 @cs_d
> > +
> > +# *** RV64C Standard Extension (Quadrant 1) ***
> > +addiw             001 .  .....  ..... 01 @ci
> > +subw              100 1 11 ... 00 ... 01 @cs_2
> > +addw              100 1 11 ... 01 ... 01 @cs_2
> > +
> > +# *** RV64C Standard Extension (Quadrant 2) ***
> > +ld                011 .  .....  ..... 10 @c_ldsp
> > +sd                111 .  .....  ..... 10 @c_sdsp
> > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> > index 3c79edf1c9..433c0e8c68 100644
> > --- a/target/riscv/insn16.decode
> > +++ b/target/riscv/insn16.decode
> > @@ -50,30 +50,12 @@
> >  &u         imm rd       !extern
> >  &shift     shamt rs1 rd !extern
> >
> > -# Argument sets:
> > -&cl               rs1 rd
> > -&cl_dw     uimm   rs1 rd
> > -&ciw       nzuimm     rd
> > -&cs               rs1 rs2
> > -&cs_dw     uimm   rs1 rs2
> > -&cb        imm    rs1
> > -&cr               rd  rs2
> > -&c_shift   shamt      rd
> > -
> > -&c_ld      uimm  rd
> > -&c_sd      uimm  rs2
> > -
> > -&caddi16sp_lui  imm_lui imm_addi16sp rd
> > -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> > -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
> >
> >  # Formats 16:
> >  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> >  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> >  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> >  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> > -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> > -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> >  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> >  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> >  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> > @@ -91,10 +73,6 @@
> >
> >  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> >  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> > -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> > -    uimm_ldsp=%uimm_6bit_ld %rd
> > -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> > -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
> >
> >  @c_shift        ... . .. ... ..... .. \
> >                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> > @@ -103,7 +81,7 @@
> >
> >  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
> >
> > -# *** RV64C Standard Extension (Quadrant 0) ***
> > +# *** RV32/64C Standard Extension (Quadrant 0) ***
> >  {
> >    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> >    illegal         000  000 000 00 --- 00
> > @@ -111,14 +89,11 @@
> >  }
> >  fld               001  ... ... .. ... 00 @cl_d
> >  lw                010  ... ... .. ... 00 @cl_w
> > -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> >  fsd               101  ... ... .. ... 00 @cs_d
> >  sw                110  ... ... .. ... 00 @cs_w
> > -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
> >
> > -# *** RV64C Standard Extension (Quadrant 1) ***
> > +# *** RV32/64C Standard Extension (Quadrant 1) ***
> >  addi              000 .  .....  ..... 01 @ci
> > -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> >  addi              010 .  .....  ..... 01 @c_li
> >  {
> >    addi            011 .  00010  ..... 01 @c_addi16sp
> > @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
> >  xor               100 0 11 ... 01 ... 01 @cs_2
> >  or                100 0 11 ... 10 ... 01 @cs_2
> >  and               100 0 11 ... 11 ... 01 @cs_2
> > -c_subw            100 1 11 ... 00 ... 01 @cs_2
> > -c_addw            100 1 11 ... 01 ... 01 @cs_2
> >  jal               101     ........... 01 @cj    rd=0  # C.J
> >  beq               110  ... ...  ..... 01 @cb_z
> >  bne               111  ... ...  ..... 01 @cb_z
> >
> > -# *** RV64C Standard Extension (Quadrant 2) ***
> > +# *** RV32/64C Standard Extension (Quadrant 2) ***
> >  slli              000 .  .....  ..... 10 @c_shift2
> >  fld               001 .  .....  ..... 10 @c_ldsp
> >  lw                010 .  .....  ..... 10 @c_lwsp
> > -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  {
> >    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> >    addi            100 0  .....  ..... 10 @c_mv
> > @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  }
> >  fsd               101   ......  ..... 10 @c_sdsp
> >  sw                110 .  .....  ..... 10 @c_swsp
> > -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>

Re: [Qemu-riscv] [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files

[Alistair Francis]

On Thu, Apr 25, 2019 at 9:04 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Sun, 31 Mar 2019 20:11:53 PDT (-0700), richard.henderson@linaro.org wrote:
> > This eliminates all functions in insn_trans/trans_rvc.inc.c,
> > so the entire file can be removed.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

You need to remove the line in: target/riscv/translate.c:710
    #include "insn_trans/trans_rvc.inc.c"

otherwise this patch doesn't compile.

Alistair

> > ---
> >  target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------
> >  target/riscv/translate.c                |   2 -
> >  target/riscv/Makefile.objs              |   9 +-
> >  target/riscv/insn16-32.decode           |  28 ++++++
> >  target/riscv/insn16-64.decode           |  30 +++++++
> >  target/riscv/insn16.decode              |  35 +-------
> >  6 files changed, 67 insertions(+), 152 deletions(-)
> >  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
> >  create mode 100644 target/riscv/insn16-32.decode
> >  create mode 100644 target/riscv/insn16-64.decode
> >
> > diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
> > deleted file mode 100644
> > index 43bff97f66..0000000000
> > --- a/target/riscv/insn_trans/trans_rvc.inc.c
> > +++ /dev/null
> > @@ -1,115 +0,0 @@
> > -/*
> > - * RISC-V translation routines for the RVC Compressed Instruction Set.
> > - *
> > - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
> > - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > - *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > - *
> > - * This program is free software; you can redistribute it and/or modify it
> > - * under the terms and conditions of the GNU General Public License,
> > - * version 2 or later, as published by the Free Software Foundation.
> > - *
> > - * This program is distributed in the hope it will be useful, but WITHOUT
> > - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > - * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > - * more details.
> > - *
> > - * You should have received a copy of the GNU General Public License along with
> > - * this program.  If not, see <http://www.gnu.org/licenses/>.
> > - */
> > -
> > -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_w(&arg, ctx->opcode);
> > -    return trans_flw(ctx, &arg);
> > -#else
> > -    /* C.LD ( RV64C/RV128C-only ) */
> > -    arg_i arg;
> > -    decode_insn16_extract_cl_d(&arg, ctx->opcode);
> > -    return trans_ld(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSW ( RV32FC-only ) */
> > -    REQUIRE_FPU;
> > -    REQUIRE_EXT(ctx, RVF);
> > -
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_w(&arg, ctx->opcode);
> > -    return trans_fsw(ctx, &arg);
> > -#else
> > -    /* C.SD ( RV64C/RV128C-only ) */
> > -    arg_s arg;
> > -    decode_insn16_extract_cs_d(&arg, ctx->opcode);
> > -    return trans_sd(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.JAL */
> > -    arg_j tmp;
> > -    decode_insn16_extract_cj(&tmp, ctx->opcode);
> > -    arg_jal arg = { .rd = 1, .imm = tmp.imm };
> > -    return trans_jal(ctx, &arg);
> > -#else
> > -    /* C.ADDIW */
> > -    arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
> > -    return trans_addiw(ctx, &arg);
> > -#endif
> > -}
> > -
> > -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_subw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
> > -{
> > -#ifdef TARGET_RISCV64
> > -    return trans_addw(ctx, a);
> > -#else
> > -    return false;
> > -#endif
> > -}
> > -
> > -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FLWSP */
> > -    arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
> > -    return trans_flw(ctx, &arg_flw);
> > -#else
> > -    /* C.LDSP */
> > -    arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
> > -    return trans_ld(ctx, &arg_ld);
> > -#endif
> > -    return false;
> > -}
> > -
> > -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
> > -{
> > -#ifdef TARGET_RISCV32
> > -    /* C.FSWSP */
> > -    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
> > -    return trans_fsw(ctx, &a_fsw);
> > -#else
> > -    /* C.SDSP */
> > -    arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
> > -    return trans_sd(ctx, &a_sd);
> > -#endif
> > -}
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index a1cd29f80f..50d8f58e4b 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
> >
> >  #pragma GCC diagnostic pop
> >
> > -#include "insn_trans/trans_rvc.inc.c"
> > -
> >  static void decode_opc(DisasContext *ctx)
> >  {
> >      /* check for compressed insn */
> > diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> > index c7a1b063ed..b1c79bc1d1 100644
> > --- a/target/riscv/Makefile.objs
> > +++ b/target/riscv/Makefile.objs
> > @@ -5,16 +5,19 @@ DECODETREE = $(SRC_PATH)/scripts/decodetree.py
> >  decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
> >  decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
> >
> > +decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
> > +decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
> > +decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
> > +
> >  target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
> >            $(decode32-y), "GEN", $(TARGET_DIR)$@)
> >
> > -target/riscv/decode_insn16.inc.c: \
> > -  $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
> > +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
> >       $(call quiet-command, \
> >         $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
> > -          --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@)
> > +          --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
> >
> >  target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
> >       target/riscv/decode_insn16.inc.c
> > diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
> > new file mode 100644
> > index 0000000000..0819b17028
> > --- /dev/null
> > +++ b/target/riscv/insn16-32.decode
> > @@ -0,0 +1,28 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV32C Standard Extension (Quadrant 0) ***
> > +flw               011  ... ... .. ... 00 @cl_w
> > +fsw               111  ... ... .. ... 00 @cs_w
> > +
> > +# *** RV32C Standard Extension (Quadrant 1) ***
> > +jal               001     ........... 01 @cj    rd=1  # C.JAL
> > +
> > +# *** RV32C Standard Extension (Quadrant 2) ***
> > +flw               011 .  .....  ..... 10 @c_lwsp
> > +fsw               111 .  .....  ..... 10 @c_swsp
> > diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
> > new file mode 100644
> > index 0000000000..055859d29f
> > --- /dev/null
> > +++ b/target/riscv/insn16-64.decode
> > @@ -0,0 +1,30 @@
> > +#
> > +# RISC-V translation routines for the RVXI Base Integer Instruction Set.
> > +#
> > +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
> > +#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
> > +#
> > +# This program is free software; you can redistribute it and/or modify it
> > +# under the terms and conditions of the GNU General Public License,
> > +# version 2 or later, as published by the Free Software Foundation.
> > +#
> > +# This program is distributed in the hope it will be useful, but WITHOUT
> > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > +# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > +# more details.
> > +#
> > +# You should have received a copy of the GNU General Public License along with
> > +# this program.  If not, see <http://www.gnu.org/licenses/>.
> > +
> > +# *** RV64C Standard Extension (Quadrant 0) ***
> > +ld                011  ... ... .. ... 00 @cl_d
> > +sd                111  ... ... .. ... 00 @cs_d
> > +
> > +# *** RV64C Standard Extension (Quadrant 1) ***
> > +addiw             001 .  .....  ..... 01 @ci
> > +subw              100 1 11 ... 00 ... 01 @cs_2
> > +addw              100 1 11 ... 01 ... 01 @cs_2
> > +
> > +# *** RV64C Standard Extension (Quadrant 2) ***
> > +ld                011 .  .....  ..... 10 @c_ldsp
> > +sd                111 .  .....  ..... 10 @c_sdsp
> > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> > index 3c79edf1c9..433c0e8c68 100644
> > --- a/target/riscv/insn16.decode
> > +++ b/target/riscv/insn16.decode
> > @@ -50,30 +50,12 @@
> >  &u         imm rd       !extern
> >  &shift     shamt rs1 rd !extern
> >
> > -# Argument sets:
> > -&cl               rs1 rd
> > -&cl_dw     uimm   rs1 rd
> > -&ciw       nzuimm     rd
> > -&cs               rs1 rs2
> > -&cs_dw     uimm   rs1 rs2
> > -&cb        imm    rs1
> > -&cr               rd  rs2
> > -&c_shift   shamt      rd
> > -
> > -&c_ld      uimm  rd
> > -&c_sd      uimm  rs2
> > -
> > -&caddi16sp_lui  imm_lui imm_addi16sp rd
> > -&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
> > -&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2
> >
> >  # Formats 16:
> >  @cr        ....  ..... .....  .. &r      rs2=%rs2_5       rs1=%rd     %rd
> >  @ci        ... . ..... .....  .. &i      imm=%imm_ci      rs1=%rd     %rd
> >  @cl_d      ... ... ... .. ... .. &i      imm=%uimm_cl_d   rs1=%rs1_3  rd=%rs2_3
> >  @cl_w      ... ... ... .. ... .. &i      imm=%uimm_cl_w   rs1=%rs1_3  rd=%rs2_3
> > -@cl        ... ... ... .. ... .. &cl                      rs1=%rs1_3  rd=%rs2_3
> > -@cs        ... ... ... .. ... .. &cs                      rs1=%rs1_3  rs2=%rs2_3
> >  @cs_2      ... ... ... .. ... .. &r      rs2=%rs2_3       rs1=%rs1_3  rd=%rs1_3
> >  @cs_d      ... ... ... .. ... .. &s      imm=%uimm_cl_d   rs1=%rs1_3  rs2=%rs2_3
> >  @cs_w      ... ... ... .. ... .. &s      imm=%uimm_cl_w   rs1=%rs1_3  rs2=%rs2_3
> > @@ -91,10 +73,6 @@
> >
> >  @c_addi4spn     ... .  ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
> >  @c_addi16sp     ... .  ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
> > -@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
> > -    uimm_ldsp=%uimm_6bit_ld %rd
> > -@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
> > -    uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
> >
> >  @c_shift        ... . .. ... ..... .. \
> >                  &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
> > @@ -103,7 +81,7 @@
> >
> >  @c_andi         ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
> >
> > -# *** RV64C Standard Extension (Quadrant 0) ***
> > +# *** RV32/64C Standard Extension (Quadrant 0) ***
> >  {
> >    # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
> >    illegal         000  000 000 00 --- 00
> > @@ -111,14 +89,11 @@
> >  }
> >  fld               001  ... ... .. ... 00 @cl_d
> >  lw                010  ... ... .. ... 00 @cl_w
> > -c_flw_ld          011  --- ... -- ... 00 @cl    #Note: Must parse uimm manually
> >  fsd               101  ... ... .. ... 00 @cs_d
> >  sw                110  ... ... .. ... 00 @cs_w
> > -c_fsw_sd          111  --- ... -- ... 00 @cs    #Note: Must parse uimm manually
> >
> > -# *** RV64C Standard Extension (Quadrant 1) ***
> > +# *** RV32/64C Standard Extension (Quadrant 1) ***
> >  addi              000 .  .....  ..... 01 @ci
> > -c_jal_addiw       001 .  .....  ..... 01 @ci #Note: parse rd and/or imm manually
> >  addi              010 .  .....  ..... 01 @c_li
> >  {
> >    addi            011 .  00010  ..... 01 @c_addi16sp
> > @@ -131,17 +106,14 @@ sub               100 0 11 ... 00 ... 01 @cs_2
> >  xor               100 0 11 ... 01 ... 01 @cs_2
> >  or                100 0 11 ... 10 ... 01 @cs_2
> >  and               100 0 11 ... 11 ... 01 @cs_2
> > -c_subw            100 1 11 ... 00 ... 01 @cs_2
> > -c_addw            100 1 11 ... 01 ... 01 @cs_2
> >  jal               101     ........... 01 @cj    rd=0  # C.J
> >  beq               110  ... ...  ..... 01 @cb_z
> >  bne               111  ... ...  ..... 01 @cb_z
> >
> > -# *** RV64C Standard Extension (Quadrant 2) ***
> > +# *** RV32/64C Standard Extension (Quadrant 2) ***
> >  slli              000 .  .....  ..... 10 @c_shift2
> >  fld               001 .  .....  ..... 10 @c_ldsp
> >  lw                010 .  .....  ..... 10 @c_lwsp
> > -c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  {
> >    jalr            100 0  .....  00000 10 @c_jalr rd=0  # C.JR
> >    addi            100 0  .....  ..... 10 @c_mv
> > @@ -153,4 +125,3 @@ c_flwsp_ldsp      011 .  .....  ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
> >  }
> >  fsd               101   ......  ..... 10 @c_sdsp
> >  sw                110 .  .....  ..... 10 @c_swsp
> > -c_fswsp_sdsp      111 .  .....  ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>