From: Will Deacon <will.deacon@arm.com>
To: Frank Li <frank.li@nxp.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
Aisheng Dong <aisheng.dong@nxp.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"lznuaa@gmail.com" <lznuaa@gmail.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH V4 2/4] drivers/perf: imx_ddr: Add ddr performance counter support
Date: Thu, 4 Apr 2019 12:17:14 +0100 [thread overview]
Message-ID: <20190404111714.GA26392@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <1550253761-26841-2-git-send-email-Frank.Li@nxp.com>
Hi Frank,
On Fri, Feb 15, 2019 at 06:03:11PM +0000, Frank Li wrote:
> Add ddr performance monitor support for iMX8QXP
>
> There are 4 counters for ddr perfomance events.
> counter 0 is dedicated for cycles.
> you choose any up to 3 no cycles events.
>
> for example:
>
> perf stat -a -e ddr0/read-access/,ddr0/write-access/,ddr0/precharge/ ls
> perf stat -a -e ddr0/cycles/,ddr0/read-access/,ddr0/write-access/ ls
Could you elaborate a bit on DDR_CAP_AXI_ID, please? Specifically, how
does the COUNTER_DPCR1 register work and what happens if I specify two
simultaneous events with different values in config1? I'm a little wary
of taking raw user input and throwing it straight into a device register!
Will
WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will.deacon@arm.com>
To: Frank Li <frank.li@nxp.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
Aisheng Dong <aisheng.dong@nxp.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"lznuaa@gmail.com" <lznuaa@gmail.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH V4 2/4] drivers/perf: imx_ddr: Add ddr performance counter support
Date: Thu, 4 Apr 2019 12:17:14 +0100 [thread overview]
Message-ID: <20190404111714.GA26392@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <1550253761-26841-2-git-send-email-Frank.Li@nxp.com>
Hi Frank,
On Fri, Feb 15, 2019 at 06:03:11PM +0000, Frank Li wrote:
> Add ddr performance monitor support for iMX8QXP
>
> There are 4 counters for ddr perfomance events.
> counter 0 is dedicated for cycles.
> you choose any up to 3 no cycles events.
>
> for example:
>
> perf stat -a -e ddr0/read-access/,ddr0/write-access/,ddr0/precharge/ ls
> perf stat -a -e ddr0/cycles/,ddr0/read-access/,ddr0/write-access/ ls
Could you elaborate a bit on DDR_CAP_AXI_ID, please? Specifically, how
does the COUNTER_DPCR1 register work and what happens if I specify two
simultaneous events with different values in config1? I'm a little wary
of taking raw user input and throwing it straight into a device register!
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-04-04 11:17 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-15 18:03 [PATCH V4 1/4] dt-bindings: perf: imx8-ddr: add imx8qxp ddr performance monitor Frank Li
2019-02-15 18:03 ` Frank Li
2019-02-15 18:03 ` [PATCH V4 2/4] drivers/perf: imx_ddr: Add ddr performance counter support Frank Li
2019-02-15 18:03 ` Frank Li
2019-02-22 19:45 ` Zhi Li
2019-02-22 19:45 ` Zhi Li
2019-02-28 21:39 ` Zhi Li
2019-02-28 21:39 ` Zhi Li
2019-03-12 21:49 ` Zhi Li
2019-03-12 21:49 ` Zhi Li
2019-04-04 11:17 ` Will Deacon [this message]
2019-04-04 11:17 ` Will Deacon
2019-04-05 14:34 ` Zhi Li
2019-04-05 14:34 ` Zhi Li
2019-04-05 14:38 ` Will Deacon
2019-04-05 14:38 ` Will Deacon
2019-04-05 14:58 ` Zhi Li
2019-04-05 14:58 ` Zhi Li
2019-04-05 15:03 ` Will Deacon
2019-04-05 15:03 ` Will Deacon
2019-04-08 19:10 ` Zhi Li
2019-04-08 19:10 ` Zhi Li
2019-04-16 13:51 ` Will Deacon
2019-04-16 13:51 ` Will Deacon
2019-04-16 20:41 ` Zhi Li
2019-04-16 20:41 ` Zhi Li
2019-02-15 18:03 ` [PATCH V4 3/4] arm64: dts: imx8qxp: added ddr performance monitor nodes Frank Li
2019-02-15 18:03 ` Frank Li
2019-02-18 17:38 ` Fabio Estevam
2019-02-18 17:38 ` Fabio Estevam
2019-02-15 18:03 ` [PATCH V4 4/4] MAINTAINERS: Added imx DDR performonitor driver maintainer information Frank Li
2019-02-15 18:03 ` Frank Li
2019-02-15 20:01 ` Uwe Kleine-König
2019-02-15 20:01 ` Uwe Kleine-König
2019-02-15 21:13 ` Zhi Li
2019-02-15 21:44 ` Uwe Kleine-König
2019-02-15 21:44 ` Uwe Kleine-König
2019-02-18 1:22 ` Shawn Guo
2019-02-18 1:22 ` Shawn Guo
2019-02-20 6:28 ` Aisheng Dong
2019-02-20 6:28 ` Aisheng Dong
2019-02-18 16:56 ` [PATCH V4 1/4] dt-bindings: perf: imx8-ddr: add imx8qxp ddr performance monitor Rob Herring
2019-02-18 16:56 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190404111714.GA26392@fuggles.cambridge.arm.com \
--to=will.deacon@arm.com \
--cc=aisheng.dong@nxp.com \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=frank.li@nxp.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=lznuaa@gmail.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.