* [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base
@ 2019-04-05 12:38 Chris Wilson
2019-04-05 13:11 ` Tvrtko Ursulin
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Chris Wilson @ 2019-04-05 12:38 UTC (permalink / raw)
To: intel-gfx
The PDP registers are an oddity inside the set of context saved
registers in that they take the engine as a parameter to the macro and
not the mmio_base as the others do. Make it accept the engine->mmio_base
for consistency in programming the context registers.
add/remove: 0/0 grow/shrink: 2/1 up/down: 3/-32 (-29)
Function old new delta
emit_ppgtt_update 324 326 +2
capture 5102 5103 +1
execlists_init_reg_state.isra 1128 1096 -32
And similar savings later!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_context.c | 9 +++++----
drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++++++++------
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++----------
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f8c94405670b..66b6852cb4d2 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1028,6 +1028,7 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
struct intel_engine_cs *engine = rq->engine;
+ u32 base = engine->mmio_base;
u32 *cs;
int i;
@@ -1040,9 +1041,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
*cs++ = MI_LOAD_REGISTER_IMM(2);
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, 0));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
*cs++ = upper_32_bits(pd_daddr);
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
*cs++ = lower_32_bits(pd_daddr);
*cs++ = MI_NOOP;
@@ -1056,9 +1057,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
for (i = GEN8_3LVL_PDPES; i--; ) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
*cs++ = upper_32_bits(pd_daddr);
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
*cs++ = lower_32_bits(pd_daddr);
}
*cs++ = MI_NOOP;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index c65d45bc63ee..43b68fdc8967 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1215,20 +1215,23 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
- if (IS_GEN(dev_priv, 6))
+ if (IS_GEN(dev_priv, 6)) {
ee->vm_info.pp_dir_base =
ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
- else if (IS_GEN(dev_priv, 7))
+ } else if (IS_GEN(dev_priv, 7)) {
ee->vm_info.pp_dir_base =
- ENGINE_READ(engine, RING_PP_DIR_BASE);
- else if (INTEL_GEN(dev_priv) >= 8)
+ ENGINE_READ(engine, RING_PP_DIR_BASE);
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ u32 base = engine->mmio_base;
+
for (i = 0; i < 4; i++) {
ee->vm_info.pdp[i] =
- I915_READ(GEN8_RING_PDP_UDW(engine, i));
+ I915_READ(GEN8_RING_PDP_UDW(base, i));
ee->vm_info.pdp[i] <<= 32;
ee->vm_info.pdp[i] |=
- I915_READ(GEN8_RING_PDP_LDW(engine, i));
+ I915_READ(GEN8_RING_PDP_LDW(base, i));
}
+ }
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00e03560c4e7..c18caa76f27c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -439,8 +439,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
#define PP_DIR_DCLV_2G 0xffffffff
-#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
-#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
+#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
+#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
#define GEN8_RPCS_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b662a054f228..6931dbb2888c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1451,10 +1451,11 @@ static int emit_pdps(struct i915_request *rq)
*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
for (i = GEN8_3LVL_PDPES; i--; ) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
+ u32 base = engine->mmio_base;
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
*cs++ = upper_32_bits(pd_daddr);
- *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
+ *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
*cs++ = lower_32_bits(pd_daddr);
}
*cs++ = MI_NOOP;
@@ -2729,14 +2730,14 @@ static void execlists_init_reg_state(u32 *regs,
CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
/* PDP values well be assigned later if needed */
- CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
- CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
- CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
- CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
- CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
- CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
- CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
- CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
+ CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
+ CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
+ CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
+ CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
+ CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
+ CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
+ CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
+ CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
if (i915_vm_is_4lvl(&ppgtt->vm)) {
/* 64b PPGTT (48bit canonical)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base
2019-04-05 12:38 [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base Chris Wilson
@ 2019-04-05 13:11 ` Tvrtko Ursulin
2019-04-05 14:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-04-06 12:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Tvrtko Ursulin @ 2019-04-05 13:11 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 05/04/2019 13:38, Chris Wilson wrote:
> The PDP registers are an oddity inside the set of context saved
> registers in that they take the engine as a parameter to the macro and
> not the mmio_base as the others do. Make it accept the engine->mmio_base
> for consistency in programming the context registers.
>
> add/remove: 0/0 grow/shrink: 2/1 up/down: 3/-32 (-29)
> Function old new delta
> emit_ppgtt_update 324 326 +2
> capture 5102 5103 +1
> execlists_init_reg_state.isra 1128 1096 -32
>
> And similar savings later!
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 9 +++++----
> drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++----------
> 4 files changed, 27 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f8c94405670b..66b6852cb4d2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -1028,6 +1028,7 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
> {
> struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> struct intel_engine_cs *engine = rq->engine;
> + u32 base = engine->mmio_base;
> u32 *cs;
> int i;
>
> @@ -1040,9 +1041,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
>
> *cs++ = MI_LOAD_REGISTER_IMM(2);
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, 0));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
> *cs++ = lower_32_bits(pd_daddr);
>
> *cs++ = MI_NOOP;
> @@ -1056,9 +1057,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
> for (i = GEN8_3LVL_PDPES; i--; ) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
> *cs++ = lower_32_bits(pd_daddr);
> }
> *cs++ = MI_NOOP;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c65d45bc63ee..43b68fdc8967 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1215,20 +1215,23 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>
> ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>
> - if (IS_GEN(dev_priv, 6))
> + if (IS_GEN(dev_priv, 6)) {
> ee->vm_info.pp_dir_base =
> ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
> - else if (IS_GEN(dev_priv, 7))
> + } else if (IS_GEN(dev_priv, 7)) {
> ee->vm_info.pp_dir_base =
> - ENGINE_READ(engine, RING_PP_DIR_BASE);
> - else if (INTEL_GEN(dev_priv) >= 8)
> + ENGINE_READ(engine, RING_PP_DIR_BASE);
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> + u32 base = engine->mmio_base;
> +
> for (i = 0; i < 4; i++) {
> ee->vm_info.pdp[i] =
> - I915_READ(GEN8_RING_PDP_UDW(engine, i));
> + I915_READ(GEN8_RING_PDP_UDW(base, i));
> ee->vm_info.pdp[i] <<= 32;
> ee->vm_info.pdp[i] |=
> - I915_READ(GEN8_RING_PDP_LDW(engine, i));
> + I915_READ(GEN8_RING_PDP_LDW(base, i));
> }
> + }
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00e03560c4e7..c18caa76f27c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -439,8 +439,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
> #define PP_DIR_DCLV_2G 0xffffffff
>
> -#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
> -#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
> +#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
> +#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>
> #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
> #define GEN8_RPCS_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index b662a054f228..6931dbb2888c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1451,10 +1451,11 @@ static int emit_pdps(struct i915_request *rq)
> *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
> for (i = GEN8_3LVL_PDPES; i--; ) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
> + u32 base = engine->mmio_base;
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
> *cs++ = lower_32_bits(pd_daddr);
> }
> *cs++ = MI_NOOP;
> @@ -2729,14 +2730,14 @@ static void execlists_init_reg_state(u32 *regs,
>
> CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
> /* PDP values well be assigned later if needed */
> - CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
> - CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
> - CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
> - CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
> - CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
> - CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
> - CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
> - CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
> + CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
> + CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
> + CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
> + CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
> + CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
> + CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
> + CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
> + CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
>
> if (i915_vm_is_4lvl(&ppgtt->vm)) {
> /* 64b PPGTT (48bit canonical)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Make RING_PDP relative to engine->mmio_base
2019-04-05 12:38 [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base Chris Wilson
2019-04-05 13:11 ` Tvrtko Ursulin
@ 2019-04-05 14:32 ` Patchwork
2019-04-06 12:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2019-04-05 14:32 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Make RING_PDP relative to engine->mmio_base
URL : https://patchwork.freedesktop.org/series/59060/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5880 -> Patchwork_12698
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59060/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12698 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
* igt@kms_psr@primary_page_flip:
- fi-skl-lmem: NOTRUN -> SKIP [fdo#109271] +37
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (46 -> 41)
------------------------------
Additional (3): fi-bsw-kefka fi-skl-lmem fi-bsw-n3050
Missing (8): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-bdw-5557u fi-skl-gvtdvm fi-bsw-cyan fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5880 -> Patchwork_12698
CI_DRM_5880: 10ec600ac87dc6da25d2784720d8fd029033d3ef @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4931: 019f892e5d1a0a9643cb726c47ce2d99c14b444f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12698: acfd6b2c9939087cb17fea76931ba36b52aaa0e5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
acfd6b2c9939 drm/i915: Make RING_PDP relative to engine->mmio_base
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12698/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Make RING_PDP relative to engine->mmio_base
2019-04-05 12:38 [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base Chris Wilson
2019-04-05 13:11 ` Tvrtko Ursulin
2019-04-05 14:32 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-04-06 12:08 ` Patchwork
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2019-04-06 12:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Make RING_PDP relative to engine->mmio_base
URL : https://patchwork.freedesktop.org/series/59060/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5880_full -> Patchwork_12698_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12698_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12698_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12698_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-glk: PASS -> DMESG-WARN
#### Warnings ####
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-iclb: SKIP [fdo#109280] -> INCOMPLETE
Known issues
------------
Here are the changes found in Patchwork_12698_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_pread@stolen-normal:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +75
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> FAIL [fdo#108686]
* igt@gem_userptr_blits@coherency-unsync:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@i915_pm_rps@min-max-config-loaded:
- shard-iclb: NOTRUN -> FAIL [fdo#108059]
* igt@i915_selftest@live_contexts:
- shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
- shard-iclb: NOTRUN -> SKIP [fdo#109278]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_color@pipe-a-degamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> SKIP [fdo#109279]
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +4
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: NOTRUN -> SKIP [fdo#109349]
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: PASS -> DMESG-WARN [fdo#109593]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: PASS -> DMESG-WARN [fdo#108566]
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +8
* igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary:
- shard-iclb: NOTRUN -> FAIL [fdo#109247] +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#109247] +16
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815] +1
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr@primary_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +2
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_psr@psr2_suspend:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* igt@kms_universal_plane@universal-plane-pipe-a-sanity:
- shard-snb: PASS -> SKIP [fdo#109271]
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-iclb: PASS -> FAIL [fdo#104894]
* igt@runner@aborted:
- shard-iclb: NOTRUN -> FAIL [fdo#109593]
* igt@v3d_mmap@mmap-bad-handle:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +21
#### Possible fixes ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: INCOMPLETE [fdo#109801] -> PASS
* igt@i915_selftest@live_requests:
- shard-iclb: INCOMPLETE [fdo#109644] -> PASS
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-iclb: FAIL [fdo#103355] -> PASS +1
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: FAIL [fdo#109247] -> PASS +17
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@kms_psr@no_drrs:
- shard-iclb: FAIL [fdo#108341] -> PASS
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +1
* igt@kms_vblank@pipe-b-query-idle:
- shard-snb: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@runner@aborted:
- shard-glk: ( 2 FAIL ) [fdo#109373] / [k.org#202321] -> ( 3 FAIL ) [fdo#109373] / [k.org#202321]
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5880 -> Patchwork_12698
CI_DRM_5880: 10ec600ac87dc6da25d2784720d8fd029033d3ef @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4931: 019f892e5d1a0a9643cb726c47ce2d99c14b444f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12698: acfd6b2c9939087cb17fea76931ba36b52aaa0e5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12698/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-04-06 12:08 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-05 12:38 [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base Chris Wilson
2019-04-05 13:11 ` Tvrtko Ursulin
2019-04-05 14:32 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-04-06 12:08 ` ✗ Fi.CI.IGT: failure " Patchwork
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