* [RFT 1/2] drm/i915: Prepare for larger CSB status FIFO size
@ 2019-04-05 20:46 Chris Wilson
2019-04-05 20:46 ` [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2019-04-05 20:46 UTC (permalink / raw)
To: intel-gfx
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Make csb entry count variable in preparation for larger
CSB status FIFO size found on gen11+ hardware.
v2: adapt to hwsp access only (Chris)
non continuous mmio (Daniele)
v3: entries (Chris), fix macro for checkpatch
v4: num_entries (Chris)
v5: consistency on num_entries
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 29 +++++++++--------------
drivers/gpu/drm/i915/intel_engine_types.h | 5 ++++
drivers/gpu/drm/i915/intel_lrc.c | 7 ++++--
drivers/gpu/drm/i915/intel_lrc.h | 13 +++++-----
4 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d0427c2e3997..a9262df24289 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1381,40 +1381,33 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
if (HAS_EXECLISTS(dev_priv)) {
const u32 *hws =
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
+ const u8 num_entries = execlists->csb_size;
unsigned int idx;
u8 read, write;
- drm_printf(m, "\tExeclist status: 0x%08x %08x\n",
+ drm_printf(m, "\tExeclist status: 0x%08x %08x, entries %u\n",
ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
- ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
+ num_entries);
read = execlists->csb_head;
write = READ_ONCE(*execlists->csb_write);
- drm_printf(m, "\tExeclist CSB read %d, write %d [mmio:%d], tasklet queued? %s (%s)\n",
+ drm_printf(m, "\tExeclist CSB read %d, write %d, tasklet queued? %s (%s)\n",
read, write,
- GEN8_CSB_WRITE_PTR(ENGINE_READ(engine, RING_CONTEXT_STATUS_PTR)),
yesno(test_bit(TASKLET_STATE_SCHED,
&engine->execlists.tasklet.state)),
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
- if (read >= GEN8_CSB_ENTRIES)
+ if (read >= num_entries)
read = 0;
- if (write >= GEN8_CSB_ENTRIES)
+ if (write >= num_entries)
write = 0;
if (read > write)
- write += GEN8_CSB_ENTRIES;
+ write += num_entries;
while (read < write) {
- idx = ++read % GEN8_CSB_ENTRIES;
- drm_printf(m, "\tExeclist CSB[%d]: 0x%08x [mmio:0x%08x], context: %d [mmio:%d]\n",
- idx,
- hws[idx * 2],
- ENGINE_READ_IDX(engine,
- RING_CONTEXT_STATUS_BUF_LO,
- idx),
- hws[idx * 2 + 1],
- ENGINE_READ_IDX(engine,
- RING_CONTEXT_STATUS_BUF_HI,
- idx));
+ idx = ++read % num_entries;
+ drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
+ idx, hws[idx * 2], hws[idx * 2 + 1]);
}
rcu_read_lock();
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h
index 6c6d8a9aca94..1f970c76b6a6 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -246,6 +246,11 @@ struct intel_engine_execlists {
*/
u32 preempt_complete_status;
+ /**
+ * @csb_size: context status buffer FIFO size
+ */
+ u8 csb_size;
+
/**
* @csb_head: context status buffer head
*/
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6931dbb2888c..687b55d9133d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -895,7 +895,7 @@ invalidate_csb_entries(const u32 *first, const u32 *last)
static void reset_csb_pointers(struct intel_engine_execlists *execlists)
{
- const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+ const unsigned int reset_value = execlists->csb_size - 1;
/*
* After a reset, the HW starts writing into CSB entry [0]. We
@@ -994,6 +994,7 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
const u32 * const buf = execlists->csb_status;
+ const u8 num_entries = execlists->csb_size;
u8 head, tail;
lockdep_assert_held(&engine->timeline.lock);
@@ -1029,7 +1030,7 @@ static void process_csb(struct intel_engine_cs *engine)
unsigned int status;
unsigned int count;
- if (++head == GEN8_CSB_ENTRIES)
+ if (++head == num_entries)
head = 0;
/*
@@ -2452,6 +2453,8 @@ static int logical_ring_init(struct intel_engine_cs *engine)
execlists->csb_write =
&engine->status_page.addr[intel_hws_csb_write_index(i915)];
+ execlists->csb_size = GEN8_CSB_ENTRIES;
+
reset_csb_pointers(execlists);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 92642ab91472..67a55e75d734 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -36,12 +36,10 @@
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
-#define RING_CONTEXT_STATUS_BUF_BASE(base) _MMIO((base) + 0x370)
-#define RING_CONTEXT_STATUS_BUF_LO(base, i) _MMIO((base) + 0x370 + (i) * 8)
-#define RING_CONTEXT_STATUS_BUF_HI(base, i) _MMIO((base) + 0x370 + (i) * 8 + 4)
#define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
#define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
#define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
+
#define EL_CTRL_LOAD (1 << 0)
/* The docs specify that the write pointer wraps around after 5h, "After status
@@ -55,10 +53,11 @@
#define GEN8_CSB_PTR_MASK 0x7
#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
-#define GEN8_CSB_WRITE_PTR(csb_status) \
- (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
-#define GEN8_CSB_READ_PTR(csb_status) \
- (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
+
+#define GEN11_CSB_ENTRIES 12
+#define GEN11_CSB_PTR_MASK 0xf
+#define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8)
+#define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0)
enum {
INTEL_CONTEXT_SCHEDULE_IN = 0,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO
2019-04-05 20:46 [RFT 1/2] drm/i915: Prepare for larger CSB status FIFO size Chris Wilson
@ 2019-04-05 20:46 ` Chris Wilson
2019-04-05 20:51 ` Chris Wilson
2019-04-05 21:22 ` ✓ Fi.CI.BAT: success for series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size Patchwork
2019-04-06 19:48 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2019-04-05 20:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Now when we can support variable csb fifo sizes, disable legacy mode.
By disabling legacy we hope to get better hw testing coverage by
assuming everyone else have switched over.
v2: rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_lrc.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 687b55d9133d..d1bb8c95ac71 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1825,17 +1825,9 @@ static void enable_execlists(struct intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
- /*
- * Make sure we're not enabling the new 12-deep CSB
- * FIFO as that requires a slightly updated handling
- * in the ctx switch irq. Since we're currently only
- * using only 2 elements of the enhanced execlists the
- * deeper FIFO it's not needed and it's not worth adding
- * more statements to the irq handler to support it.
- */
if (INTEL_GEN(dev_priv) >= 11)
I915_WRITE(RING_MODE_GEN7(engine),
- _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+ _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
else
I915_WRITE(RING_MODE_GEN7(engine),
_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
@@ -2453,7 +2445,10 @@ static int logical_ring_init(struct intel_engine_cs *engine)
execlists->csb_write =
&engine->status_page.addr[intel_hws_csb_write_index(i915)];
- execlists->csb_size = GEN8_CSB_ENTRIES;
+ if (INTEL_GEN(engine->i915) < 11)
+ execlists->csb_size = GEN8_CSB_ENTRIES;
+ else
+ execlists->csb_size = GEN11_CSB_ENTRIES;
reset_csb_pointers(execlists);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO
2019-04-05 20:46 ` [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO Chris Wilson
@ 2019-04-05 20:51 ` Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2019-04-05 20:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Quoting Chris Wilson (2019-04-05 21:46:57)
> From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> Now when we can support variable csb fifo sizes, disable legacy mode.
> By disabling legacy we hope to get better hw testing coverage by
> assuming everyone else have switched over.
There should be no advantage here until we transition to a larger
submission queue -- but just maybe this helps with say
https://bugs.freedesktop.org/show_bug.cgi?id=110338
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size
2019-04-05 20:46 [RFT 1/2] drm/i915: Prepare for larger CSB status FIFO size Chris Wilson
2019-04-05 20:46 ` [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO Chris Wilson
@ 2019-04-05 21:22 ` Patchwork
2019-04-06 19:48 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-04-05 21:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size
URL : https://patchwork.freedesktop.org/series/59083/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5881 -> Patchwork_12709
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59083/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12709 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u2: PASS -> DMESG-WARN [fdo#109638]
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (49 -> 42)
------------------------------
Missing (7): fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-icl-y fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5881 -> Patchwork_12709
CI_DRM_5881: b070175c76da1440a747fd023ee6253e573055f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4931: 019f892e5d1a0a9643cb726c47ce2d99c14b444f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12709: 67953c59b94a3c8906d81089ef18e23a6db9a543 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
67953c59b94a drm/i915/icl: Switch to using 12 deep CSB status FIFO
2d8ac6ad28d3 drm/i915: Prepare for larger CSB status FIFO size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12709/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size
2019-04-05 20:46 [RFT 1/2] drm/i915: Prepare for larger CSB status FIFO size Chris Wilson
2019-04-05 20:46 ` [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO Chris Wilson
2019-04-05 21:22 ` ✓ Fi.CI.BAT: success for series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size Patchwork
@ 2019-04-06 19:48 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2019-04-06 19:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size
URL : https://patchwork.freedesktop.org/series/59083/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5881_full -> Patchwork_12709_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12709_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12709_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12709_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-glk: PASS -> DMESG-WARN
Known issues
------------
Here are the changes found in Patchwork_12709_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@preempt-other-chain-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +3
* igt@gem_exec_store@cachelines-bsd1:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +80
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: PASS -> INCOMPLETE [fdo#109801]
* igt@gem_softpin@noreloc-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@gem_tiled_pread_pwrite:
- shard-iclb: PASS -> TIMEOUT [fdo#109673]
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> INCOMPLETE [fdo#108686]
* igt@i915_pm_rpm@pm-tiling:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] +1
* igt@kms_atomic_transition@4x-modeset-transitions-nonblocking-fencing:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#110222]
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-oldfb-render-f:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-c:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@extended-pageflip-hang-oldfb-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_ccs@pipe-c-missing-ccs-buffer:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +36
* igt@kms_chamelium@dp-crc-single:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +1
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-iclb: PASS -> FAIL [fdo#103355]
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@basic:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-iclb: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +3
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +22
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-iclb: PASS -> FAIL [fdo#109247] +4
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +79
* igt@kms_lease@atomic_implicit_crtc:
- shard-skl: NOTRUN -> FAIL [fdo#110279]
- shard-apl: NOTRUN -> FAIL [fdo#110279]
* igt@kms_lease@setcrtc_implicit_plane:
- shard-skl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- shard-skl: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@read-crc-pipe-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-kbl: PASS -> FAIL [fdo#108590]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215]
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-apl: PASS -> FAIL [fdo#104894] +1
* igt@perf@short-reads:
- shard-kbl: NOTRUN -> FAIL [fdo#103183]
#### Possible fixes ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: INCOMPLETE [fdo#109801] -> PASS
* igt@i915_pm_rpm@universal-planes-dpms:
- shard-iclb: INCOMPLETE [fdo#107713] / [fdo#108840] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-iclb: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: FAIL [fdo#103355] -> PASS +1
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: DMESG-WARN [fdo#109593] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: FAIL [fdo#103375] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +11
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS +1
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1
* igt@kms_psr@primary_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-modeset-hang:
- shard-apl: FAIL [fdo#104894] -> PASS
* igt@perf@oa-exponents:
- shard-glk: FAIL [fdo#105483] -> PASS
#### Warnings ####
* igt@runner@aborted:
- shard-glk: FAIL [fdo#109373] / [k.org#202321] -> ( 2 FAIL ) [fdo#109373] / [k.org#202321]
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105483]: https://bugs.freedesktop.org/show_bug.cgi?id=105483
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5881 -> Patchwork_12709
CI_DRM_5881: b070175c76da1440a747fd023ee6253e573055f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4931: 019f892e5d1a0a9643cb726c47ce2d99c14b444f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12709: 67953c59b94a3c8906d81089ef18e23a6db9a543 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12709/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-04-06 19:48 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-05 20:46 [RFT 1/2] drm/i915: Prepare for larger CSB status FIFO size Chris Wilson
2019-04-05 20:46 ` [RFT 2/2] drm/i915/icl: Switch to using 12 deep CSB status FIFO Chris Wilson
2019-04-05 20:51 ` Chris Wilson
2019-04-05 21:22 ` ✓ Fi.CI.BAT: success for series starting with [RFT,1/2] drm/i915: Prepare for larger CSB status FIFO size Patchwork
2019-04-06 19:48 ` ✗ Fi.CI.IGT: failure " Patchwork
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