Re: [PATCH 2/2] drm/i915: Simplify some icl pll calculations

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: Simplify some icl pll calculations
Date: Mon, 8 Apr 2019 19:06:01 +0300	[thread overview]
Message-ID: <20190408160601.GH3888@intel.com> (raw)
In-Reply-To: <155473855386.26510.399775695436410433@skylake-alporthouse-com>

On Mon, Apr 08, 2019 at 04:49:13PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-08 16:27:02)
> > -       /*
> > -        * Adjust the original formula to delay the division by 2^22 in order to
> > -        * minimize possible rounding errors.
> > -        */
> > -       tmp = (u64)m1 * m2_int * ref_clock +
> > -             (((u64)m1 * m2_frac * ref_clock) >> 22);
> > -       tmp = div_u64(tmp, 5 * div1 * div2);
> > -
> > -       return tmp;
> > +       return div_u64(mul_u32_u32(ref_clock * m1, m2),
> > +                      (5 * div1 * div2) << 22);
> 
> You say the denominator here is a u64, so do you not need to cast
> (u64)(5 * d1 * d2) to ensure it doesn't overflow the shift?

It should fit into u32. The maximum value should be
<= (5*0xf*0x7)<<22 based on the number of bits available
for div1/2.

-- 
Ville Syrjälä
Intel
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