* [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
@ 2019-04-12 20:24 Chris Wilson
2019-04-12 20:24 ` [PATCH 2/2] drm/i915: Verify workarounds immediately after application Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Chris Wilson @ 2019-04-12 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Start weaning ourselves off the implicit I915_WRITE macro madness and
start using the explicit intel_uncore mmio access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 65 +++++++++----------
drivers/gpu/drm/i915/intel_workarounds.h | 6 +-
.../drm/i915/selftests/intel_workarounds.c | 5 +-
3 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a04dbc58ec1c..60738332fc29 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -729,9 +729,9 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
static void
-wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
+wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
u32 mcr_slice_subslice_mask;
/*
@@ -747,14 +747,15 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
* something more complex that requires checking the range of every
* MMIO read).
*/
- if (INTEL_GEN(dev_priv) >= 10 &&
+ if (INTEL_GEN(i915) >= 10 &&
is_power_of_2(sseu->slice_mask)) {
/*
* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
* enabled subslice, no need to redirect MCR packet
*/
u32 slice = fls(sseu->slice_mask);
- u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
+ u32 fuse3 =
+ intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
u8 ss_mask = sseu->subslice_mask[slice];
u8 enabled_mask = (ss_mask | ss_mask >>
@@ -768,7 +769,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
}
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(i915) >= 11)
mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
GEN11_MCR_SUBSLICE_MASK;
else
@@ -788,7 +789,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN8_MCR_SELECTOR,
mcr_slice_subslice_mask,
- intel_calculate_mcr_s_ss_select(dev_priv));
+ intel_calculate_mcr_s_ss_select(i915));
}
static void
@@ -897,15 +898,14 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915)
}
static enum forcewake_domains
-wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
- const struct i915_wa_list *wal)
+wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
{
enum forcewake_domains fw = 0;
struct i915_wa *wa;
unsigned int i;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- fw |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
+ fw |= intel_uncore_forcewake_for_reg(uncore,
wa->reg,
FW_REG_READ |
FW_REG_WRITE);
@@ -914,7 +914,7 @@ wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
}
static void
-wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
+wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
{
enum forcewake_domains fw;
unsigned long flags;
@@ -924,27 +924,22 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
if (!wal->count)
return;
- fw = wal_get_fw_for_rmw(dev_priv, wal);
+ fw = wal_get_fw_for_rmw(uncore, wal);
- spin_lock_irqsave(&dev_priv->uncore.lock, flags);
- intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
+ spin_lock_irqsave(&uncore->lock, flags);
+ intel_uncore_forcewake_get__locked(uncore, fw);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
- u32 val = I915_READ_FW(wa->reg);
-
- val &= ~wa->mask;
- val |= wa->val;
-
- I915_WRITE_FW(wa->reg, val);
+ intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
}
- intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
+ intel_uncore_forcewake_put__locked(uncore, fw);
+ spin_unlock_irqrestore(&uncore->lock, flags);
}
-void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv)
+void intel_gt_apply_workarounds(struct drm_i915_private *i915)
{
- wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
+ wa_list_apply(&i915->uncore, &i915->gt_wa_list);
}
static bool
@@ -961,7 +956,7 @@ wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
return true;
}
-static bool wa_list_verify(struct drm_i915_private *dev_priv,
+static bool wa_list_verify(struct intel_uncore *uncore,
const struct i915_wa_list *wal,
const char *from)
{
@@ -970,15 +965,17 @@ static bool wa_list_verify(struct drm_i915_private *dev_priv,
bool ok = true;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
+ ok &= wa_verify(wa,
+ intel_uncore_read(uncore, wa->reg),
+ wal->name, from);
return ok;
}
-bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
+bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
const char *from)
{
- return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+ return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
}
static void
@@ -1088,8 +1085,8 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
const struct i915_wa_list *wal = &engine->whitelist;
+ struct intel_uncore *uncore = engine->uncore;
const u32 base = engine->mmio_base;
struct i915_wa *wa;
unsigned int i;
@@ -1098,13 +1095,15 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
return;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
- i915_mmio_reg_offset(wa->reg));
+ intel_uncore_write(uncore,
+ RING_FORCE_TO_NONPRIV(base, i),
+ i915_mmio_reg_offset(wa->reg));
/* And clear the rest just in case of garbage */
for (; i < RING_MAX_NONPRIV_SLOTS; i++)
- I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
- i915_mmio_reg_offset(RING_NOPID(base)));
+ intel_uncore_write(uncore,
+ RING_FORCE_TO_NONPRIV(base, i),
+ i915_mmio_reg_offset(RING_NOPID(base)));
}
static void
@@ -1253,7 +1252,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
{
- wa_list_apply(engine->i915, &engine->wa_list);
+ wa_list_apply(engine->uncore, &engine->wa_list);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h b/drivers/gpu/drm/i915/intel_workarounds.h
index a1bf51c611a9..34eee5ec511e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -20,9 +20,9 @@ static inline void intel_wa_list_free(struct i915_wa_list *wal)
void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
int intel_engine_emit_ctx_wa(struct i915_request *rq);
-void intel_gt_init_workarounds(struct drm_i915_private *dev_priv);
-void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv);
-bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
+void intel_gt_init_workarounds(struct drm_i915_private *i915);
+void intel_gt_apply_workarounds(struct drm_i915_private *i915);
+bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
const char *from);
void intel_engine_init_whitelist(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index 3baed59008d7..567b6f8dae86 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -750,10 +750,11 @@ static bool verify_gt_engine_wa(struct drm_i915_private *i915,
enum intel_engine_id id;
bool ok = true;
- ok &= wa_list_verify(i915, &lists->gt_wa_list, str);
+ ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
for_each_engine(engine, i915, id)
- ok &= wa_list_verify(i915, &lists->engine[id].wa_list, str);
+ ok &= wa_list_verify(engine->uncore,
+ &lists->engine[id].wa_list, str);
return ok;
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Verify workarounds immediately after application
2019-04-12 20:24 [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Chris Wilson
@ 2019-04-12 20:24 ` Chris Wilson
2019-04-12 20:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-04-12 20:24 UTC (permalink / raw)
To: intel-gfx
Immediately after writing the workaround, verify that it stuck in the
register.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 +++++++++++++-----------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 60738332fc29..92c60ae5a298 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -913,6 +913,20 @@ wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
return fw;
}
+static bool
+wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
+{
+ if ((cur ^ wa->val) & wa->mask) {
+ DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
+ name, from, i915_mmio_reg_offset(wa->reg), cur,
+ cur & wa->mask, wa->val, wa->mask);
+
+ return false;
+ }
+
+ return true;
+}
+
static void
wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
{
@@ -931,6 +945,10 @@ wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
+
+ wa_verify(wa,
+ intel_uncore_read_fw(uncore, wa->reg),
+ wal->name, "applictation");
}
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -942,20 +960,6 @@ void intel_gt_apply_workarounds(struct drm_i915_private *i915)
wa_list_apply(&i915->uncore, &i915->gt_wa_list);
}
-static bool
-wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
-{
- if ((cur ^ wa->val) & wa->mask) {
- DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
- name, from, i915_mmio_reg_offset(wa->reg), cur,
- cur & wa->mask, wa->val, wa->mask);
-
- return false;
- }
-
- return true;
-}
-
static bool wa_list_verify(struct intel_uncore *uncore,
const struct i915_wa_list *wal,
const char *from)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
2019-04-12 20:24 [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Chris Wilson
2019-04-12 20:24 ` [PATCH 2/2] drm/i915: Verify workarounds immediately after application Chris Wilson
@ 2019-04-12 20:52 ` Patchwork
2019-04-12 21:45 ` [PATCH 1/2] " Daniele Ceraolo Spurio
2019-04-13 0:49 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-04-12 20:52 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
URL : https://patchwork.freedesktop.org/series/59421/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5924 -> Patchwork_12785
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59421/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12785 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
- fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
#### Possible fixes ####
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (47 -> 41)
------------------------------
Missing (6): fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5924 -> Patchwork_12785
CI_DRM_5924: 1f6d0d97a9eff3abfe9201a735e96ef2d634d6d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12785: e338c7b598c6887e59c0f0b2d1e7f25a06a7eecb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e338c7b598c6 drm/i915: Verify workarounds immediately after application
8c6437df53c0 drm/i915: Teach intel_workarounds to use uncore mmio access
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12785/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
2019-04-12 20:24 [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Chris Wilson
2019-04-12 20:24 ` [PATCH 2/2] drm/i915: Verify workarounds immediately after application Chris Wilson
2019-04-12 20:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Patchwork
@ 2019-04-12 21:45 ` Daniele Ceraolo Spurio
2019-04-12 21:48 ` Chris Wilson
2019-04-13 0:49 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
3 siblings, 1 reply; 6+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-04-12 21:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Paulo Zanoni
On 4/12/19 1:24 PM, Chris Wilson wrote:
> Start weaning ourselves off the implicit I915_WRITE macro madness and
> start using the explicit intel_uncore mmio access.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 65 +++++++++----------
> drivers/gpu/drm/i915/intel_workarounds.h | 6 +-
> .../drm/i915/selftests/intel_workarounds.c | 5 +-
> 3 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index a04dbc58ec1c..60738332fc29 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -729,9 +729,9 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> }
>
> static void
> -wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
> +wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> - const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> + const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
> u32 mcr_slice_subslice_mask;
>
> /*
> @@ -747,14 +747,15 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
> * something more complex that requires checking the range of every
> * MMIO read).
> */
> - if (INTEL_GEN(dev_priv) >= 10 &&
> + if (INTEL_GEN(i915) >= 10 &&
> is_power_of_2(sseu->slice_mask)) {
> /*
> * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> * enabled subslice, no need to redirect MCR packet
> */
> u32 slice = fls(sseu->slice_mask);
> - u32 fuse3 = I915_READ(GEN10_MIRROR_FUSE3);
> + u32 fuse3 =
> + intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
> u8 ss_mask = sseu->subslice_mask[slice];
>
> u8 enabled_mask = (ss_mask | ss_mask >>
> @@ -768,7 +769,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
> WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
> }
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(i915) >= 11)
> mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
> GEN11_MCR_SUBSLICE_MASK;
> else
> @@ -788,7 +789,7 @@ wa_init_mcr(struct drm_i915_private *dev_priv, struct i915_wa_list *wal)
> wa_write_masked_or(wal,
> GEN8_MCR_SELECTOR,
> mcr_slice_subslice_mask,
> - intel_calculate_mcr_s_ss_select(dev_priv));
> + intel_calculate_mcr_s_ss_select(i915));
> }
>
> static void
> @@ -897,15 +898,14 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915)
> }
>
> static enum forcewake_domains
> -wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
> - const struct i915_wa_list *wal)
> +wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
> {
> enum forcewake_domains fw = 0;
> struct i915_wa *wa;
> unsigned int i;
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> - fw |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> + fw |= intel_uncore_forcewake_for_reg(uncore,
> wa->reg,
> FW_REG_READ |
> FW_REG_WRITE);
> @@ -914,7 +914,7 @@ wal_get_fw_for_rmw(struct drm_i915_private *dev_priv,
> }
>
> static void
> -wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> +wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal)
> {
> enum forcewake_domains fw;
> unsigned long flags;
> @@ -924,27 +924,22 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> if (!wal->count)
> return;
>
> - fw = wal_get_fw_for_rmw(dev_priv, wal);
> + fw = wal_get_fw_for_rmw(uncore, wal);
>
> - spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> - intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
> + spin_lock_irqsave(&uncore->lock, flags);
> + intel_uncore_forcewake_get__locked(uncore, fw);
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
nitpick: brackets not needed anymore here.
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> - u32 val = I915_READ_FW(wa->reg);
> -
> - val &= ~wa->mask;
> - val |= wa->val;
> -
> - I915_WRITE_FW(wa->reg, val);
> + intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val);
> }
>
> - intel_uncore_forcewake_put__locked(&dev_priv->uncore, fw);
> - spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
> + intel_uncore_forcewake_put__locked(uncore, fw);
> + spin_unlock_irqrestore(&uncore->lock, flags);
> }
>
> -void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv)
> +void intel_gt_apply_workarounds(struct drm_i915_private *i915)
> {
> - wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
> + wa_list_apply(&i915->uncore, &i915->gt_wa_list);
> }
>
> static bool
> @@ -961,7 +956,7 @@ wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
> return true;
> }
>
> -static bool wa_list_verify(struct drm_i915_private *dev_priv,
> +static bool wa_list_verify(struct intel_uncore *uncore,
> const struct i915_wa_list *wal,
> const char *from)
> {
> @@ -970,15 +965,17 @@ static bool wa_list_verify(struct drm_i915_private *dev_priv,
> bool ok = true;
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> - ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
> + ok &= wa_verify(wa,
> + intel_uncore_read(uncore, wa->reg),
> + wal->name, from);
>
> return ok;
> }
>
> -bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
> +bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
> const char *from)
> {
> - return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
> + return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
> }
>
> static void
> @@ -1088,8 +1085,8 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> {
> - struct drm_i915_private *dev_priv = engine->i915;
> const struct i915_wa_list *wal = &engine->whitelist;
> + struct intel_uncore *uncore = engine->uncore;
> const u32 base = engine->mmio_base;
> struct i915_wa *wa;
> unsigned int i;
> @@ -1098,13 +1095,15 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> return;
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> - I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
> - i915_mmio_reg_offset(wa->reg));
> + intel_uncore_write(uncore,
> + RING_FORCE_TO_NONPRIV(base, i),
> + i915_mmio_reg_offset(wa->reg));
>
> /* And clear the rest just in case of garbage */
> for (; i < RING_MAX_NONPRIV_SLOTS; i++)
> - I915_WRITE(RING_FORCE_TO_NONPRIV(base, i),
> - i915_mmio_reg_offset(RING_NOPID(base)));
> + intel_uncore_write(uncore,
> + RING_FORCE_TO_NONPRIV(base, i),
> + i915_mmio_reg_offset(RING_NOPID(base)));
> }
>
> static void
> @@ -1253,7 +1252,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>
> void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
> {
> - wa_list_apply(engine->i915, &engine->wa_list);
> + wa_list_apply(engine->uncore, &engine->wa_list);
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.h b/drivers/gpu/drm/i915/intel_workarounds.h
> index a1bf51c611a9..34eee5ec511e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.h
> +++ b/drivers/gpu/drm/i915/intel_workarounds.h
> @@ -20,9 +20,9 @@ static inline void intel_wa_list_free(struct i915_wa_list *wal)
> void intel_engine_init_ctx_wa(struct intel_engine_cs *engine);
> int intel_engine_emit_ctx_wa(struct i915_request *rq);
>
> -void intel_gt_init_workarounds(struct drm_i915_private *dev_priv);
> -void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv);
> -bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
> +void intel_gt_init_workarounds(struct drm_i915_private *i915);
> +void intel_gt_apply_workarounds(struct drm_i915_private *i915);
> +bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
> const char *from);
>
> void intel_engine_init_whitelist(struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> index 3baed59008d7..567b6f8dae86 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> @@ -750,10 +750,11 @@ static bool verify_gt_engine_wa(struct drm_i915_private *i915,
> enum intel_engine_id id;
> bool ok = true;
>
> - ok &= wa_list_verify(i915, &lists->gt_wa_list, str);
> + ok &= wa_list_verify(&i915->uncore, &lists->gt_wa_list, str);
>
> for_each_engine(engine, i915, id)
> - ok &= wa_list_verify(i915, &lists->engine[id].wa_list, str);
> + ok &= wa_list_verify(engine->uncore,
> + &lists->engine[id].wa_list, str);
>
> return ok;
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
2019-04-12 21:45 ` [PATCH 1/2] " Daniele Ceraolo Spurio
@ 2019-04-12 21:48 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-04-12 21:48 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Paulo Zanoni
Quoting Daniele Ceraolo Spurio (2019-04-12 22:45:29)
>
>
> On 4/12/19 1:24 PM, Chris Wilson wrote:
> > @@ -924,27 +924,22 @@ wa_list_apply(struct drm_i915_private *dev_priv, const struct i915_wa_list *wal)
> > if (!wal->count)
> > return;
> >
> > - fw = wal_get_fw_for_rmw(dev_priv, wal);
> > + fw = wal_get_fw_for_rmw(uncore, wal);
> >
> > - spin_lock_irqsave(&dev_priv->uncore.lock, flags);
> > - intel_uncore_forcewake_get__locked(&dev_priv->uncore, fw);
> > + spin_lock_irqsave(&uncore->lock, flags);
> > + intel_uncore_forcewake_get__locked(uncore, fw);
> >
> > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>
> nitpick: brackets not needed anymore here.
Just saving a bit of churn with the next patch.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
2019-04-12 20:24 [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Chris Wilson
` (2 preceding siblings ...)
2019-04-12 21:45 ` [PATCH 1/2] " Daniele Ceraolo Spurio
@ 2019-04-13 0:49 ` Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-04-13 0:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access
URL : https://patchwork.freedesktop.org/series/59421/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5924_full -> Patchwork_12785_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_12785_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12785_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12785_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-a:
- shard-iclb: PASS -> DMESG-WARN +95
Known issues
------------
Here are the changes found in Patchwork_12785_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#108566] +1
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +82
* igt@gem_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +4
* igt@gem_pwrite@huge-cpu-fbr:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> FAIL [fdo#108686]
* igt@i915_pm_rpm@cursor-dpms:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@i915_pm_rpm@legacy-planes:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@i915_selftest@live_requests:
- shard-iclb: PASS -> DMESG-WARN [fdo#109644]
* igt@kms_atomic_transition@3x-modeset-transitions-fencing:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +1
* igt@kms_busy@basic-modeset-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: PASS -> DMESG-WARN [fdo#110222] +5
* igt@kms_busy@extended-modeset-hang-oldfb-render-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274] +3
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +25
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#109507]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +6
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-iclb: PASS -> FAIL [fdo#109247] +12
* igt@kms_lease@page_flip_implicit_plane:
- shard-apl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr@primary_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +4
* igt@kms_psr@psr2_dpms:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +4
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> SKIP [fdo#109291]
* igt@tools_test@tools_test:
- shard-glk: PASS -> SKIP [fdo#109271]
#### Possible fixes ####
* igt@i915_pm_rpm@gem-execbuf-stress:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +5
* igt@kms_cursor_edge_walk@pipe-a-128x128-top-edge:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-snb: SKIP [fdo#109271] -> PASS +2
* igt@kms_cursor_legacy@pipe-c-single-bo:
- shard-kbl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +11
* igt@kms_flip@flip-vs-expired-vblank:
- shard-apl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +13
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_vblank@invalid:
- shard-kbl: DMESG-FAIL [fdo#103558] / [fdo#105602] -> PASS
#### Warnings ####
* igt@kms_lease@setcrtc_implicit_plane:
- shard-kbl: DMESG-FAIL [fdo#103558] / [fdo#105602] -> FAIL [fdo#110281]
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109644]: https://bugs.freedesktop.org/show_bug.cgi?id=109644
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5924 -> Patchwork_12785
CI_DRM_5924: 1f6d0d97a9eff3abfe9201a735e96ef2d634d6d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12785: e338c7b598c6887e59c0f0b2d1e7f25a06a7eecb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12785/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-04-13 0:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-12 20:24 [PATCH 1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Chris Wilson
2019-04-12 20:24 ` [PATCH 2/2] drm/i915: Verify workarounds immediately after application Chris Wilson
2019-04-12 20:52 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Teach intel_workarounds to use uncore mmio access Patchwork
2019-04-12 21:45 ` [PATCH 1/2] " Daniele Ceraolo Spurio
2019-04-12 21:48 ` Chris Wilson
2019-04-13 0:49 ` ✗ Fi.CI.IGT: failure for series starting with [1/2] " Patchwork
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