* [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support
@ 2019-04-09 21:39 Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 1/6] cpu: Add support for orfp64a32 spec Stafford Horne
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
Hello,
This is basically a resend, but properly including binutils list.
Changes from v1:
- Rebased
- Note Andrey is working on doing his FSF copyright assignment for binutils, sim
This is a set of patches to the OpenRISC assembler and simulator to support
64-bit floating point operations on 32-bit cores using register pairs, see
orfpx64a32 [0].
The original patches were written by Andrey Bacherov and I have made some
updates to get the simulator working and to match ABI updates from GCC 9. The
main GCC 9 ABI change is to have r16 and above pair with an n+2 register rather
than n+1. This is done because openrisc callee saved registers are r14-r30
(even). If a 64-bit value was stored in {r16,r17}, it would always need to be
spilled across function calls as r17 is volatile. Therefore, values of 64-bits
and greater are stored in even reg pairs, such as {r16,r18}.
Example of orfpx64a32 operations:
lf.add.d r4, r6, r8 ; {r3,r4} <= {r5,r6} + {r7,r8}
lf.add.d r16, r20, r24 ; {r16,r18} <= {r20,r22} + {r24,r26}
These binutil patches have been used along with the GCC FPU patches [1] on the
OpenRISC GCC 9 toolchain to test single and double precision floating point
support. The main 'real' implementation of this hardware is Andrey's
or1k_marocchino [2] core implementation which we have been using along with
simulators for verification.
This whole patch series can be found on my github repo [3] as well.
[0] https://openrisc.io/proposals/orfpx64a32
[1] git at github.com:stffrdhrn/gcc.git or1k-fpu-1
[2] https://github.com/openrisc/or1k_marocchino
[3] git@github.com:stffrdhrn/binutils-gdb.git orfpx64a32-2
Stafford Horne (6):
cpu: Add support for orfp64a32 spec
opcodes: Regenerate opcodes for orfp64a32 spec
sim/or1k: Regenerate sim for orfp64a32 spec
sim/common: Wire in df/di conversion
sim/or1k: Add test for 64-bit fpu operations
sim/common: Fix issue with wrong byte order on BE targets
cpu/or1k.cpu | 15 +-
cpu/or1kcommon.cpu | 103 ++++--
cpu/or1korfpx.cpu | 113 +++++--
opcodes/or1k-asm.c | 19 +-
opcodes/or1k-desc.c | 227 +++++++++++--
opcodes/or1k-desc.h | 330 +++++++++----------
opcodes/or1k-dis.c | 19 +-
opcodes/or1k-ibld.c | 114 ++++++-
opcodes/or1k-opc.c | 166 ++++++++--
opcodes/or1k-opc.h | 21 +-
opcodes/or1k-opinst.c | 51 +++
sim/common/cgen-accfp.c | 24 ++
sim/common/cgen-ops.h | 8 +-
sim/or1k/cpu.c | 60 +++-
sim/or1k/cpu.h | 115 ++++++-
sim/or1k/decode.c | 302 ++++++++++++++----
sim/or1k/decode.h | 16 +-
sim/or1k/model.c | 510 ++++++++++++++++++++++++++++++
sim/or1k/sem-switch.c | 296 +++++++++++++++++
sim/or1k/sem.c | 326 +++++++++++++++++++
sim/testsuite/sim/or1k/fpu64a32.S | 172 ++++++++++
21 files changed, 2637 insertions(+), 370 deletions(-)
create mode 100644 sim/testsuite/sim/or1k/fpu64a32.S
--
2.19.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 1/6] cpu: Add support for orfp64a32 spec
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes " Stafford Horne
` (4 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs. The functionality is being added to the OpenRISC spec
as per architecture proposal 14[0].
This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.
[0] https://openrisc.io/proposals/orfpx64a32
cpu/ChangeLog:
yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org>
Stafford Horne <shorne@gmail.com>
* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
(ORFPX-MACHS): Removed pmacro.
* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
and add comments.
(h-fdr): Update comment to indicate or64.
(reg-pair-offset): New hardware for 64-bit or32 register pair.
(h-fd32r): New hardware for 64-bit fpu registers.
(h-i64r): New hardware for 64-bit int registers.
* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
(rDDF, rADF, rBDF): Update operand comment to indicate or64.
(rDD32F, rAD32F, rBD32F, rDDI, rADI): New operands.
(float-regreg-insn): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(float-setflag-insn): Update single precision generator to MACH
ORFPX32-MACHS. Fix double instructions from single to double
precision. Add generator for or32 64-bit instructions.
(float-cust-insn cust-num): Update single precision generator to MACH
ORFPX32-MACHS. Add generator for or32 64-bit instructions.
(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
ORFPX32-MACHS.
(lf-rem-d): Fix operation from mod to rem.
(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
(lf-itof-d): Fix operands from single to double.
(lf-ftoi-d): Update operand mode from DI to WI.
---
cpu/or1k.cpu | 15 +++---
cpu/or1kcommon.cpu | 103 +++++++++++++++++++++++++++++++++--------
cpu/or1korfpx.cpu | 113 +++++++++++++++++++++++++++++++++++++--------
3 files changed, 186 insertions(+), 45 deletions(-)
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index 3a932bcb90..e1ae1b8c88 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -1,8 +1,9 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg at opencores.org
; Modified by Julius Baxter, juliusbaxter at gmail.com
; Modified by Peter Gavin, pgavin at gmail.com
+; Modified by Andrey Bacherov, avbacherov at opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -42,12 +43,12 @@
(base-insn-bitsize 32)
)
-(define-pmacro OR32-MACHS or32,or32nd)
-(define-pmacro OR64-MACHS or64,or64nd)
-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro OR32-MACHS or32,or32nd)
+(define-pmacro OR64-MACHS or64,or64nd)
+(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
+(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
(define-attr
(for model)
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
index c0e4f316ad..06bfe29ce8 100644
--- a/cpu/or1kcommon.cpu
+++ b/cpu/or1kcommon.cpu
@@ -1,7 +1,8 @@
; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed for OR32 by Johan Rydberg, jrydberg at opencores.org
; Modified by Julius Baxter, juliusbaxter at gmail.com
+; Modified by Andrey Bacherov, avbacherov at opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -71,6 +72,38 @@
(fp 2))
)
+;
+; Hardware: [S]pecial [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-spr) (comment "special purpose registers")
+ (attrs VIRTUAL (MACH ORBIS-MACHS))
+ (type register UWI (#x20000))
+ (get (index) (c-call UWI "@cpu at _h_spr_get_raw" index))
+ (set (index newval) (c-call VOID "@cpu at _h_spr_set_raw" index newval))
+)
+
+(define-pmacro spr-shift 11)
+(define-pmacro (spr-address spr-group spr-index)
+ (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
+ (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+
+;
+; Hardware: [G]enepral [P]urpose [R]egisters
+;
+(define-hardware
+ (name h-gpr) (comment "general registers")
+ (attrs (MACH ORBIS-MACHS))
+ (type register UWI (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
+ (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
+ )
+
+;
+; Hardware: virtual registerts for FPU (single precision)
+; mapped to GPRs
+;
(define-hardware
(name h-fsr)
(comment "floating point registers (single, virtual)")
@@ -81,8 +114,13 @@
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
+;
+; Hardware: virtual registerts for FPU (double precision)
+; mapped to GPRs
+;
(define-hardware
- (name h-fdr) (comment "floating point registers (double, virtual)")
+ (name h-fdr)
+ (comment "or64 floating point registers (double, virtual)")
(attrs VIRTUAL (MACH ORFPX64-MACHS))
(type register DF (32))
(indices keyword "" REG-INDICES)
@@ -90,27 +128,56 @@
(set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
)
-(define-hardware
- (name h-spr) (comment "special purpose registers")
- (attrs VIRTUAL (MACH ORBIS-MACHS))
- (type register UWI (#x20000))
- (get (index) (c-call UWI "@cpu at _h_spr_get_raw" index))
- (set (index newval) (c-call VOID "@cpu at _h_spr_set_raw" index newval))
+;
+; Register pairs are offset by 2 for registers r16 and above. This is to
+; be able to allow registers to be call saved in GCC across function calls.
+;
+(define-pmacro (reg-pair-offset index)
+ (if (gt index 15) 2 1)
)
-(define-pmacro spr-shift 11)
-(define-pmacro (spr-address spr-group spr-index)
- (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
- (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
+;
+; Hardware: vrtual registers for double precision floating point
+; operands on 32-bit machines
+; mapped to GPRs
+;
+(define-hardware
+ (name h-fd32r)
+ (comment "or32 floating point registers (double, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DF (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (join DF SI
+ (reg h-gpr index)
+ (reg h-gpr (add index (reg-pair-offset index)))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr index) (subword SI newval 0))
+ (set (reg h-gpr (add index (reg-pair-offset index)))
+ (subword SI newval 1))))
+)
+;
+; Hardware: vrtual 64-bit integer registers for conversions
+; float64 <-> int64 on 32-bit machines
+; mapped to GPRs
+;
(define-hardware
- (name h-gpr) (comment "general registers")
- (attrs (MACH ORBIS-MACHS))
- (type register UWI (32))
+ (name h-i64r)
+ (comment "or32 double word registers (int64, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DI (32))
(indices keyword "" REG-INDICES)
- (get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
- (set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
- )
+ (get (index) (join DI SI
+ (reg h-gpr index)
+ (reg h-gpr (add index (reg-pair-offset index)))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr index) (subword SI newval 0))
+ (set (reg h-gpr (add index (reg-pair-offset index)))
+ (subword SI newval 1))))
+)
+
(define-normal-enum
except-number
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index 1a128a97b2..2f5c248b3d 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -1,6 +1,7 @@
; OpenRISC 1000 architecture. -*- Scheme -*-
-; Copyright 2000-2014 Free Software Foundation, Inc.
+; Copyright 2000-2019 Free Software Foundation, Inc.
; Contributed by Peter Gavin, pgavin at gmail.com
+; Modified by Andrey Bacherov, avbacherov at opencores.org
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@@ -58,19 +59,28 @@
)
)
-(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
-(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
-(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
+(dnop rDSF "destination register (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r1)
+(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
+(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
+
+(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
+(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
+
+(dnop rDD32F "or32 destination register (double floating point mode)" ((MACH ORFPX64A32-MACHS)) h-fd32r f-r1)
+(dnop rAD32F "or32 source register A (double floating point mode)" ((MACH ORFPX64A32-MACHS)) h-fd32r f-r2)
+(dnop rBD32F "or32 source register B (double floating point mode)" ((MACH ORFPX64A32-MACHS)) h-fd32r f-r3)
+
+(dnop rDDI "or32 destination register (double integer mode)" ((MACH ORFPX64A32-MACHS)) h-i64r f-r1)
+(dnop rADI "or32 source register A (double integer mode)" ((MACH ORFPX64A32-MACHS)) h-i64r f-r2)
+
-(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
-(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
-(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
(define-pmacro (float-regreg-insn mnemonic)
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf." mnemonic ".s reg/reg/reg")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
(set SF rDSF (mnemonic SF rASF rBSF))
@@ -84,6 +94,14 @@
(set DF rDDF (mnemonic DF rADF rBDF))
()
)
+ (dni (.sym lf- mnemonic -d32)
+ (.str "lf." mnemonic ".d reg/reg/reg")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf." mnemonic ".d $rDD32F,$rAD32F,$rBD32F")
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
+ (set DF rDD32F (mnemonic DF rAD32F rBD32F))
+ ()
+ )
)
)
@@ -94,18 +112,28 @@
(dni lf-rem-s
"lf.rem.s reg/reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.rem.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
(set SF rDSF (rem SF rASF rBSF))
()
)
+
(dni lf-rem-d
"lf.rem.d reg/reg/reg"
((MACH ORFPX64-MACHS))
"lf.rem.d $rDDF,$rADF,$rBDF"
(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
- (set DF rDDF (mod DF rADF rBDF))
+ (set DF rDDF (rem DF rADF rBDF))
+ ()
+ )
+
+(dni lf-rem-d32
+ "lf.rem.d reg/reg/reg"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.rem.d $rDD32F,$rAD32F,$rBD32F"
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
+ (set DF rDD32F (rem DF rAD32F rBD32F))
()
)
@@ -120,24 +148,34 @@
(dni lf-itof-s
"lf.itof.s reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.itof.s $rDSF,$rA"
(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
()
)
+
(dni lf-itof-d
"lf.itof.d reg/reg"
((MACH ORFPX64-MACHS))
- "lf.itof.d $rDSF,$rA"
- (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
+ "lf.itof.d $rDDF,$rA"
+ (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
(set DF rDDF (float DF (get-rounding-mode) rA))
()
)
+(dni lf-itof-d32
+ "lf.itof.d reg/reg"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.itof.d $rDD32F,$rADI"
+ (+ OPC_FLOAT rDD32F rADI (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
+ (set DF rDD32F (float DF (get-rounding-mode) rADI))
+ ()
+ )
+
(dni lf-ftoi-s
"lf.ftoi.s reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.ftoi.s $rD,$rASF"
(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
@@ -149,7 +187,16 @@
((MACH ORFPX64-MACHS))
"lf.ftoi.d $rD,$rADF"
(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
- (set DI rD (fix DI (get-rounding-mode) rADF))
+ (set WI rD (fix WI (get-rounding-mode) rADF))
+ ()
+ )
+
+(dni lf-ftoi-d32
+ "lf.ftoi.d reg/reg"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.ftoi.d $rDDI,$rAD32F"
+ (+ OPC_FLOAT rDDI rAD32F (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
+ (set DI rDDI (fix DI (get-rounding-mode) rAD32F))
()
)
@@ -157,7 +204,7 @@
(begin
(dni (.sym lf- mnemonic -s)
(.str "lf.sf" mnemonic ".s reg/reg")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
(set BI sys-sr-f (mnemonic SF rASF rBSF))
@@ -166,11 +213,19 @@
(dni (.sym lf- mnemonic -d)
(.str "lf.sf" mnemonic ".d reg/reg")
((MACH ORFPX64-MACHS))
- (.str "lf.sf" mnemonic ".d $rASF,$rBSF")
- (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+ (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
+ (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
(set BI sys-sr-f (mnemonic DF rADF rBDF))
()
)
+ (dni (.sym lf- mnemonic -d32)
+ (.str "lf.sf" mnemonic ".d reg/reg")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
+ (+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+ (set BI sys-sr-f (mnemonic DF rAD32F rBD32F))
+ ()
+ )
)
)
@@ -183,12 +238,13 @@
(dni lf-madd-s
"lf.madd.s reg/reg/reg"
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
"lf.madd.s $rDSF,$rASF,$rBSF"
(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
()
)
+
(dni lf-madd-d
"lf.madd.d reg/reg/reg"
((MACH ORFPX64-MACHS))
@@ -198,11 +254,20 @@
()
)
+(dni lf-madd-d32
+ "lf.madd.d reg/reg/reg"
+ ((MACH ORFPX64A32-MACHS))
+ "lf.madd.d $rDD32F,$rAD32F,$rBD32F"
+ (+ OPC_FLOAT rDD32F rAD32F rBD32F (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
+ (set DF rDD32F (add DF (mul DF rAD32F rBD32F) rDD32F))
+ ()
+ )
+
(define-pmacro (float-cust-insn cust-num)
(begin
(dni (.sym "lf-cust" cust-num "-s")
(.str "lf.cust" cust-num ".s")
- ((MACH ORFPX-MACHS))
+ ((MACH ORFPX32-MACHS))
(.str "lf.cust" cust-num ".s $rASF,$rBSF")
(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
(nop)
@@ -216,6 +281,14 @@
(nop)
()
)
+ (dni (.sym "lf-cust" cust-num "-d32")
+ (.str "lf.cust" cust-num ".d")
+ ((MACH ORFPX64A32-MACHS))
+ (.str "lf.cust" cust-num ".d")
+ (+ OPC_FLOAT (f-resv-25-5 0) rAD32F rBD32F (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
+ (nop)
+ ()
+ )
)
)
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes for orfp64a32 spec
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 1/6] cpu: Add support for orfp64a32 spec Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-11 8:45 ` Nick Clifton
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim " Stafford Horne
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
opcodes/ChangeLog:
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
---
opcodes/or1k-asm.c | 19 ++-
opcodes/or1k-desc.c | 227 ++++++++++++++++++++++++++---
opcodes/or1k-desc.h | 330 +++++++++++++++++++++---------------------
opcodes/or1k-dis.c | 19 ++-
opcodes/or1k-ibld.c | 114 +++++++++++++--
opcodes/or1k-opc.c | 166 ++++++++++++++++++---
opcodes/or1k-opc.h | 21 +--
opcodes/or1k-opinst.c | 51 +++++++
8 files changed, 716 insertions(+), 231 deletions(-)
diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c
index 7d058d03f5..f1e20e4ebc 100644
--- a/opcodes/or1k-asm.c
+++ b/opcodes/or1k-asm.c
@@ -466,8 +466,14 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r2);
break;
+ case OR1K_OPERAND_RAD32F :
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fd32r, & fields->f_r2);
+ break;
case OR1K_OPERAND_RADF :
- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2);
+ break;
+ case OR1K_OPERAND_RADI :
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_i64r, & fields->f_r2);
break;
case OR1K_OPERAND_RASF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r2);
@@ -475,8 +481,11 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r3);
break;
+ case OR1K_OPERAND_RBD32F :
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fd32r, & fields->f_r3);
+ break;
case OR1K_OPERAND_RBDF :
- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3);
break;
case OR1K_OPERAND_RBSF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r3);
@@ -484,9 +493,15 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_gpr, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDD32F :
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fd32r, & fields->f_r1);
+ break;
case OR1K_OPERAND_RDDF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDDI :
+ errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_i64r, & fields->f_r1);
+ break;
case OR1K_OPERAND_RDSF :
errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fsr, & fields->f_r1);
break;
diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c
index 486b0f2626..9835d012cd 100644
--- a/opcodes/or1k-desc.c
+++ b/opcodes/or1k-desc.c
@@ -134,6 +134,52 @@ static const CGEN_MACH or1k_cgen_mach_table[] = {
{ 0, 0, 0, 0 }
};
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
+{
+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+ { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD or1k_cgen_opval_h_gpr =
+{
+ & or1k_cgen_opval_h_gpr_entries[0],
+ 35,
+ 0, 0, 0, 0, ""
+};
+
static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fsr_entries[] =
{
{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
@@ -226,7 +272,7 @@ CGEN_KEYWORD or1k_cgen_opval_h_fdr =
0, 0, 0, 0, ""
};
-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fd32r_entries[] =
{
{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
@@ -265,9 +311,55 @@ static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_gpr_entries[] =
{ "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
};
-CGEN_KEYWORD or1k_cgen_opval_h_gpr =
+CGEN_KEYWORD or1k_cgen_opval_h_fd32r =
{
- & or1k_cgen_opval_h_gpr_entries[0],
+ & or1k_cgen_opval_h_fd32r_entries[0],
+ 35,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_i64r_entries[] =
+{
+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+ { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+ { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+ { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+ { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+ { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+ { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+ { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+ { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+ { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+ { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+ { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+ { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+ { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+ { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+ { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+ { "lr", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD or1k_cgen_opval_h_i64r =
+{
+ & or1k_cgen_opval_h_i64r_entries[0],
35,
0, 0, 0, 0, ""
};
@@ -285,10 +377,12 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
- { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
- { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_gpr, { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+ { "h-fd32r", HW_H_FD32R, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fd32r, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+ { "h-i64r", HW_H_I64R, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_i64r, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
{ "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
{ "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
@@ -1124,18 +1218,38 @@ const CGEN_OPERAND or1k_cgen_operand_table[] =
{ "rBSF", OR1K_OPERAND_RBSF, HW_H_FSR, 15, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rDDF: destination register (double floating point mode) */
+/* rDDF: or64 destination register (double floating point mode) */
{ "rDDF", OR1K_OPERAND_RDDF, HW_H_FDR, 25, 5,
{ 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rADF: source register A (double floating point mode) */
- { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rADF: or64 source register A (double floating point mode) */
+ { "rADF", OR1K_OPERAND_RADF, HW_H_FDR, 20, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
-/* rBDF: source register B (double floating point mode) */
- { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 25, 5,
- { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+/* rBDF: or64 source register B (double floating point mode) */
+ { "rBDF", OR1K_OPERAND_RBDF, HW_H_FDR, 15, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } } },
+/* rDD32F: or32 destination register (double floating point mode) */
+ { "rDD32F", OR1K_OPERAND_RDD32F, HW_H_FD32R, 25, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rAD32F: or32 source register A (double floating point mode) */
+ { "rAD32F", OR1K_OPERAND_RAD32F, HW_H_FD32R, 20, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rBD32F: or32 source register B (double floating point mode) */
+ { "rBD32F", OR1K_OPERAND_RBD32F, HW_H_FD32R, 15, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R3] } },
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rDDI: or32 destination register (double integer mode) */
+ { "rDDI", OR1K_OPERAND_RDDI, HW_H_I64R, 25, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R1] } },
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
+/* rADI: or32 source register A (double integer mode) */
+ { "rADI", OR1K_OPERAND_RADI, HW_H_I64R, 20, 5,
+ { 0, { (const PTR) &or1k_cgen_ifld_table[OR1K_F_R2] } },
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
@@ -1656,6 +1770,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_ADD_D, "lf-add-d", "lf.add.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_ADD_D32, "lf-add-d32", "lf.add.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sub.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_SUB_S, "lf-sub-s", "lf.sub.s", 32,
@@ -1666,6 +1785,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_SUB_D, "lf-sub-d", "lf.sub.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_SUB_D32, "lf-sub-d32", "lf.sub.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.mul.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_MUL_S, "lf-mul-s", "lf.mul.s", 32,
@@ -1676,6 +1800,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_MUL_D, "lf-mul-d", "lf.mul.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_MUL_D32, "lf-mul-d32", "lf.mul.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.div.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_DIV_S, "lf-div-s", "lf.div.s", 32,
@@ -1686,6 +1815,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_DIV_D, "lf-div-d", "lf.div.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_DIV_D32, "lf-div-d32", "lf.div.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.rem.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_REM_S, "lf-rem-s", "lf.rem.s", 32,
@@ -1696,16 +1830,26 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_REM_D, "lf-rem-d", "lf.rem.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_REM_D32, "lf-rem-d32", "lf.rem.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.itof.s $rDSF,$rA */
{
OR1K_INSN_LF_ITOF_S, "lf-itof-s", "lf.itof.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.itof.d $rDSF,$rA */
+/* lf.itof.d $rDDF,$rA */
{
OR1K_INSN_LF_ITOF_D, "lf-itof-d", "lf.itof.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.itof.d $rDD32F,$rADI */
+ {
+ OR1K_INSN_LF_ITOF_D32, "lf-itof-d32", "lf.itof.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.ftoi.s $rD,$rASF */
{
OR1K_INSN_LF_FTOI_S, "lf-ftoi-s", "lf.ftoi.s", 32,
@@ -1716,66 +1860,101 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_FTOI_D, "lf-ftoi-d", "lf.ftoi.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.ftoi.d $rDDI,$rAD32F */
+ {
+ OR1K_INSN_LF_FTOI_D32, "lf-ftoi-d32", "lf.ftoi.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfeq.s $rASF,$rBSF */
{
OR1K_INSN_LF_EQ_S, "lf-eq-s", "lf.sfeq.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfeq.d $rASF,$rBSF */
+/* lf.sfeq.d $rADF,$rBDF */
{
OR1K_INSN_LF_EQ_D, "lf-eq-d", "lf.sfeq.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfeq.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_EQ_D32, "lf-eq-d32", "lf.sfeq.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfne.s $rASF,$rBSF */
{
OR1K_INSN_LF_NE_S, "lf-ne-s", "lf.sfne.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfne.d $rASF,$rBSF */
+/* lf.sfne.d $rADF,$rBDF */
{
OR1K_INSN_LF_NE_D, "lf-ne-d", "lf.sfne.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfne.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_NE_D32, "lf-ne-d32", "lf.sfne.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfge.s $rASF,$rBSF */
{
OR1K_INSN_LF_GE_S, "lf-ge-s", "lf.sfge.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfge.d $rASF,$rBSF */
+/* lf.sfge.d $rADF,$rBDF */
{
OR1K_INSN_LF_GE_D, "lf-ge-d", "lf.sfge.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfge.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_GE_D32, "lf-ge-d32", "lf.sfge.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfgt.s $rASF,$rBSF */
{
OR1K_INSN_LF_GT_S, "lf-gt-s", "lf.sfgt.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfgt.d $rASF,$rBSF */
+/* lf.sfgt.d $rADF,$rBDF */
{
OR1K_INSN_LF_GT_D, "lf-gt-d", "lf.sfgt.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfgt.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_GT_D32, "lf-gt-d32", "lf.sfgt.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sflt.s $rASF,$rBSF */
{
OR1K_INSN_LF_LT_S, "lf-lt-s", "lf.sflt.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sflt.d $rASF,$rBSF */
+/* lf.sflt.d $rADF,$rBDF */
{
OR1K_INSN_LF_LT_D, "lf-lt-d", "lf.sflt.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sflt.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_LT_D32, "lf-lt-d32", "lf.sflt.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.sfle.s $rASF,$rBSF */
{
OR1K_INSN_LF_LE_S, "lf-le-s", "lf.sfle.s", 32,
{ 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
-/* lf.sfle.d $rASF,$rBSF */
+/* lf.sfle.d $rADF,$rBDF */
{
OR1K_INSN_LF_LE_D, "lf-le-d", "lf.sfle.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.sfle.d $rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_LE_D32, "lf-le-d32", "lf.sfle.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.madd.s $rDSF,$rASF,$rBSF */
{
OR1K_INSN_LF_MADD_S, "lf-madd-s", "lf.madd.s", 32,
@@ -1786,6 +1965,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_MADD_D, "lf-madd-d", "lf.madd.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ OR1K_INSN_LF_MADD_D32, "lf-madd-d32", "lf.madd.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
/* lf.cust1.s $rASF,$rBSF */
{
OR1K_INSN_LF_CUST1_S, "lf-cust1-s", "lf.cust1.s", 32,
@@ -1796,6 +1980,11 @@ static const CGEN_IBASE or1k_cgen_insn_table[MAX_INSNS] =
OR1K_INSN_LF_CUST1_D, "lf-cust1-d", "lf.cust1.d", 32,
{ 0, { { { (1<<MACH_OR64)|(1<<MACH_OR64ND), 0 } } } }
},
+/* lf.cust1.d */
+ {
+ OR1K_INSN_LF_CUST1_D32, "lf-cust1-d32", "lf.cust1.d", 32,
+ { 0, { { { (1<<MACH_OR32)|(1<<MACH_OR32ND), 0 } } } }
+ },
};
#undef OP
diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h
index ade9241a93..de1f094a38 100644
--- a/opcodes/or1k-desc.h
+++ b/opcodes/or1k-desc.h
@@ -429,166 +429,167 @@ typedef enum cgen_hw_attr {
/* Enum declaration for or1k hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_PC, HW_H_FSR, HW_H_FDR
- , HW_H_SPR, HW_H_GPR, HW_H_SYS_VR, HW_H_SYS_UPR
- , HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR, HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR
- , HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR, HW_H_SYS_PCCFGR, HW_H_SYS_NPC
- , HW_H_SYS_SR, HW_H_SYS_PPC, HW_H_SYS_FPCSR, HW_H_SYS_EPCR0
- , HW_H_SYS_EPCR1, HW_H_SYS_EPCR2, HW_H_SYS_EPCR3, HW_H_SYS_EPCR4
- , HW_H_SYS_EPCR5, HW_H_SYS_EPCR6, HW_H_SYS_EPCR7, HW_H_SYS_EPCR8
- , HW_H_SYS_EPCR9, HW_H_SYS_EPCR10, HW_H_SYS_EPCR11, HW_H_SYS_EPCR12
- , HW_H_SYS_EPCR13, HW_H_SYS_EPCR14, HW_H_SYS_EPCR15, HW_H_SYS_EEAR0
- , HW_H_SYS_EEAR1, HW_H_SYS_EEAR2, HW_H_SYS_EEAR3, HW_H_SYS_EEAR4
- , HW_H_SYS_EEAR5, HW_H_SYS_EEAR6, HW_H_SYS_EEAR7, HW_H_SYS_EEAR8
- , HW_H_SYS_EEAR9, HW_H_SYS_EEAR10, HW_H_SYS_EEAR11, HW_H_SYS_EEAR12
- , HW_H_SYS_EEAR13, HW_H_SYS_EEAR14, HW_H_SYS_EEAR15, HW_H_SYS_ESR0
- , HW_H_SYS_ESR1, HW_H_SYS_ESR2, HW_H_SYS_ESR3, HW_H_SYS_ESR4
- , HW_H_SYS_ESR5, HW_H_SYS_ESR6, HW_H_SYS_ESR7, HW_H_SYS_ESR8
- , HW_H_SYS_ESR9, HW_H_SYS_ESR10, HW_H_SYS_ESR11, HW_H_SYS_ESR12
- , HW_H_SYS_ESR13, HW_H_SYS_ESR14, HW_H_SYS_ESR15, HW_H_SYS_GPR0
- , HW_H_SYS_GPR1, HW_H_SYS_GPR2, HW_H_SYS_GPR3, HW_H_SYS_GPR4
- , HW_H_SYS_GPR5, HW_H_SYS_GPR6, HW_H_SYS_GPR7, HW_H_SYS_GPR8
- , HW_H_SYS_GPR9, HW_H_SYS_GPR10, HW_H_SYS_GPR11, HW_H_SYS_GPR12
- , HW_H_SYS_GPR13, HW_H_SYS_GPR14, HW_H_SYS_GPR15, HW_H_SYS_GPR16
- , HW_H_SYS_GPR17, HW_H_SYS_GPR18, HW_H_SYS_GPR19, HW_H_SYS_GPR20
- , HW_H_SYS_GPR21, HW_H_SYS_GPR22, HW_H_SYS_GPR23, HW_H_SYS_GPR24
- , HW_H_SYS_GPR25, HW_H_SYS_GPR26, HW_H_SYS_GPR27, HW_H_SYS_GPR28
- , HW_H_SYS_GPR29, HW_H_SYS_GPR30, HW_H_SYS_GPR31, HW_H_SYS_GPR32
- , HW_H_SYS_GPR33, HW_H_SYS_GPR34, HW_H_SYS_GPR35, HW_H_SYS_GPR36
- , HW_H_SYS_GPR37, HW_H_SYS_GPR38, HW_H_SYS_GPR39, HW_H_SYS_GPR40
- , HW_H_SYS_GPR41, HW_H_SYS_GPR42, HW_H_SYS_GPR43, HW_H_SYS_GPR44
- , HW_H_SYS_GPR45, HW_H_SYS_GPR46, HW_H_SYS_GPR47, HW_H_SYS_GPR48
- , HW_H_SYS_GPR49, HW_H_SYS_GPR50, HW_H_SYS_GPR51, HW_H_SYS_GPR52
- , HW_H_SYS_GPR53, HW_H_SYS_GPR54, HW_H_SYS_GPR55, HW_H_SYS_GPR56
- , HW_H_SYS_GPR57, HW_H_SYS_GPR58, HW_H_SYS_GPR59, HW_H_SYS_GPR60
- , HW_H_SYS_GPR61, HW_H_SYS_GPR62, HW_H_SYS_GPR63, HW_H_SYS_GPR64
- , HW_H_SYS_GPR65, HW_H_SYS_GPR66, HW_H_SYS_GPR67, HW_H_SYS_GPR68
- , HW_H_SYS_GPR69, HW_H_SYS_GPR70, HW_H_SYS_GPR71, HW_H_SYS_GPR72
- , HW_H_SYS_GPR73, HW_H_SYS_GPR74, HW_H_SYS_GPR75, HW_H_SYS_GPR76
- , HW_H_SYS_GPR77, HW_H_SYS_GPR78, HW_H_SYS_GPR79, HW_H_SYS_GPR80
- , HW_H_SYS_GPR81, HW_H_SYS_GPR82, HW_H_SYS_GPR83, HW_H_SYS_GPR84
- , HW_H_SYS_GPR85, HW_H_SYS_GPR86, HW_H_SYS_GPR87, HW_H_SYS_GPR88
- , HW_H_SYS_GPR89, HW_H_SYS_GPR90, HW_H_SYS_GPR91, HW_H_SYS_GPR92
- , HW_H_SYS_GPR93, HW_H_SYS_GPR94, HW_H_SYS_GPR95, HW_H_SYS_GPR96
- , HW_H_SYS_GPR97, HW_H_SYS_GPR98, HW_H_SYS_GPR99, HW_H_SYS_GPR100
- , HW_H_SYS_GPR101, HW_H_SYS_GPR102, HW_H_SYS_GPR103, HW_H_SYS_GPR104
- , HW_H_SYS_GPR105, HW_H_SYS_GPR106, HW_H_SYS_GPR107, HW_H_SYS_GPR108
- , HW_H_SYS_GPR109, HW_H_SYS_GPR110, HW_H_SYS_GPR111, HW_H_SYS_GPR112
- , HW_H_SYS_GPR113, HW_H_SYS_GPR114, HW_H_SYS_GPR115, HW_H_SYS_GPR116
- , HW_H_SYS_GPR117, HW_H_SYS_GPR118, HW_H_SYS_GPR119, HW_H_SYS_GPR120
- , HW_H_SYS_GPR121, HW_H_SYS_GPR122, HW_H_SYS_GPR123, HW_H_SYS_GPR124
- , HW_H_SYS_GPR125, HW_H_SYS_GPR126, HW_H_SYS_GPR127, HW_H_SYS_GPR128
- , HW_H_SYS_GPR129, HW_H_SYS_GPR130, HW_H_SYS_GPR131, HW_H_SYS_GPR132
- , HW_H_SYS_GPR133, HW_H_SYS_GPR134, HW_H_SYS_GPR135, HW_H_SYS_GPR136
- , HW_H_SYS_GPR137, HW_H_SYS_GPR138, HW_H_SYS_GPR139, HW_H_SYS_GPR140
- , HW_H_SYS_GPR141, HW_H_SYS_GPR142, HW_H_SYS_GPR143, HW_H_SYS_GPR144
- , HW_H_SYS_GPR145, HW_H_SYS_GPR146, HW_H_SYS_GPR147, HW_H_SYS_GPR148
- , HW_H_SYS_GPR149, HW_H_SYS_GPR150, HW_H_SYS_GPR151, HW_H_SYS_GPR152
- , HW_H_SYS_GPR153, HW_H_SYS_GPR154, HW_H_SYS_GPR155, HW_H_SYS_GPR156
- , HW_H_SYS_GPR157, HW_H_SYS_GPR158, HW_H_SYS_GPR159, HW_H_SYS_GPR160
- , HW_H_SYS_GPR161, HW_H_SYS_GPR162, HW_H_SYS_GPR163, HW_H_SYS_GPR164
- , HW_H_SYS_GPR165, HW_H_SYS_GPR166, HW_H_SYS_GPR167, HW_H_SYS_GPR168
- , HW_H_SYS_GPR169, HW_H_SYS_GPR170, HW_H_SYS_GPR171, HW_H_SYS_GPR172
- , HW_H_SYS_GPR173, HW_H_SYS_GPR174, HW_H_SYS_GPR175, HW_H_SYS_GPR176
- , HW_H_SYS_GPR177, HW_H_SYS_GPR178, HW_H_SYS_GPR179, HW_H_SYS_GPR180
- , HW_H_SYS_GPR181, HW_H_SYS_GPR182, HW_H_SYS_GPR183, HW_H_SYS_GPR184
- , HW_H_SYS_GPR185, HW_H_SYS_GPR186, HW_H_SYS_GPR187, HW_H_SYS_GPR188
- , HW_H_SYS_GPR189, HW_H_SYS_GPR190, HW_H_SYS_GPR191, HW_H_SYS_GPR192
- , HW_H_SYS_GPR193, HW_H_SYS_GPR194, HW_H_SYS_GPR195, HW_H_SYS_GPR196
- , HW_H_SYS_GPR197, HW_H_SYS_GPR198, HW_H_SYS_GPR199, HW_H_SYS_GPR200
- , HW_H_SYS_GPR201, HW_H_SYS_GPR202, HW_H_SYS_GPR203, HW_H_SYS_GPR204
- , HW_H_SYS_GPR205, HW_H_SYS_GPR206, HW_H_SYS_GPR207, HW_H_SYS_GPR208
- , HW_H_SYS_GPR209, HW_H_SYS_GPR210, HW_H_SYS_GPR211, HW_H_SYS_GPR212
- , HW_H_SYS_GPR213, HW_H_SYS_GPR214, HW_H_SYS_GPR215, HW_H_SYS_GPR216
- , HW_H_SYS_GPR217, HW_H_SYS_GPR218, HW_H_SYS_GPR219, HW_H_SYS_GPR220
- , HW_H_SYS_GPR221, HW_H_SYS_GPR222, HW_H_SYS_GPR223, HW_H_SYS_GPR224
- , HW_H_SYS_GPR225, HW_H_SYS_GPR226, HW_H_SYS_GPR227, HW_H_SYS_GPR228
- , HW_H_SYS_GPR229, HW_H_SYS_GPR230, HW_H_SYS_GPR231, HW_H_SYS_GPR232
- , HW_H_SYS_GPR233, HW_H_SYS_GPR234, HW_H_SYS_GPR235, HW_H_SYS_GPR236
- , HW_H_SYS_GPR237, HW_H_SYS_GPR238, HW_H_SYS_GPR239, HW_H_SYS_GPR240
- , HW_H_SYS_GPR241, HW_H_SYS_GPR242, HW_H_SYS_GPR243, HW_H_SYS_GPR244
- , HW_H_SYS_GPR245, HW_H_SYS_GPR246, HW_H_SYS_GPR247, HW_H_SYS_GPR248
- , HW_H_SYS_GPR249, HW_H_SYS_GPR250, HW_H_SYS_GPR251, HW_H_SYS_GPR252
- , HW_H_SYS_GPR253, HW_H_SYS_GPR254, HW_H_SYS_GPR255, HW_H_SYS_GPR256
- , HW_H_SYS_GPR257, HW_H_SYS_GPR258, HW_H_SYS_GPR259, HW_H_SYS_GPR260
- , HW_H_SYS_GPR261, HW_H_SYS_GPR262, HW_H_SYS_GPR263, HW_H_SYS_GPR264
- , HW_H_SYS_GPR265, HW_H_SYS_GPR266, HW_H_SYS_GPR267, HW_H_SYS_GPR268
- , HW_H_SYS_GPR269, HW_H_SYS_GPR270, HW_H_SYS_GPR271, HW_H_SYS_GPR272
- , HW_H_SYS_GPR273, HW_H_SYS_GPR274, HW_H_SYS_GPR275, HW_H_SYS_GPR276
- , HW_H_SYS_GPR277, HW_H_SYS_GPR278, HW_H_SYS_GPR279, HW_H_SYS_GPR280
- , HW_H_SYS_GPR281, HW_H_SYS_GPR282, HW_H_SYS_GPR283, HW_H_SYS_GPR284
- , HW_H_SYS_GPR285, HW_H_SYS_GPR286, HW_H_SYS_GPR287, HW_H_SYS_GPR288
- , HW_H_SYS_GPR289, HW_H_SYS_GPR290, HW_H_SYS_GPR291, HW_H_SYS_GPR292
- , HW_H_SYS_GPR293, HW_H_SYS_GPR294, HW_H_SYS_GPR295, HW_H_SYS_GPR296
- , HW_H_SYS_GPR297, HW_H_SYS_GPR298, HW_H_SYS_GPR299, HW_H_SYS_GPR300
- , HW_H_SYS_GPR301, HW_H_SYS_GPR302, HW_H_SYS_GPR303, HW_H_SYS_GPR304
- , HW_H_SYS_GPR305, HW_H_SYS_GPR306, HW_H_SYS_GPR307, HW_H_SYS_GPR308
- , HW_H_SYS_GPR309, HW_H_SYS_GPR310, HW_H_SYS_GPR311, HW_H_SYS_GPR312
- , HW_H_SYS_GPR313, HW_H_SYS_GPR314, HW_H_SYS_GPR315, HW_H_SYS_GPR316
- , HW_H_SYS_GPR317, HW_H_SYS_GPR318, HW_H_SYS_GPR319, HW_H_SYS_GPR320
- , HW_H_SYS_GPR321, HW_H_SYS_GPR322, HW_H_SYS_GPR323, HW_H_SYS_GPR324
- , HW_H_SYS_GPR325, HW_H_SYS_GPR326, HW_H_SYS_GPR327, HW_H_SYS_GPR328
- , HW_H_SYS_GPR329, HW_H_SYS_GPR330, HW_H_SYS_GPR331, HW_H_SYS_GPR332
- , HW_H_SYS_GPR333, HW_H_SYS_GPR334, HW_H_SYS_GPR335, HW_H_SYS_GPR336
- , HW_H_SYS_GPR337, HW_H_SYS_GPR338, HW_H_SYS_GPR339, HW_H_SYS_GPR340
- , HW_H_SYS_GPR341, HW_H_SYS_GPR342, HW_H_SYS_GPR343, HW_H_SYS_GPR344
- , HW_H_SYS_GPR345, HW_H_SYS_GPR346, HW_H_SYS_GPR347, HW_H_SYS_GPR348
- , HW_H_SYS_GPR349, HW_H_SYS_GPR350, HW_H_SYS_GPR351, HW_H_SYS_GPR352
- , HW_H_SYS_GPR353, HW_H_SYS_GPR354, HW_H_SYS_GPR355, HW_H_SYS_GPR356
- , HW_H_SYS_GPR357, HW_H_SYS_GPR358, HW_H_SYS_GPR359, HW_H_SYS_GPR360
- , HW_H_SYS_GPR361, HW_H_SYS_GPR362, HW_H_SYS_GPR363, HW_H_SYS_GPR364
- , HW_H_SYS_GPR365, HW_H_SYS_GPR366, HW_H_SYS_GPR367, HW_H_SYS_GPR368
- , HW_H_SYS_GPR369, HW_H_SYS_GPR370, HW_H_SYS_GPR371, HW_H_SYS_GPR372
- , HW_H_SYS_GPR373, HW_H_SYS_GPR374, HW_H_SYS_GPR375, HW_H_SYS_GPR376
- , HW_H_SYS_GPR377, HW_H_SYS_GPR378, HW_H_SYS_GPR379, HW_H_SYS_GPR380
- , HW_H_SYS_GPR381, HW_H_SYS_GPR382, HW_H_SYS_GPR383, HW_H_SYS_GPR384
- , HW_H_SYS_GPR385, HW_H_SYS_GPR386, HW_H_SYS_GPR387, HW_H_SYS_GPR388
- , HW_H_SYS_GPR389, HW_H_SYS_GPR390, HW_H_SYS_GPR391, HW_H_SYS_GPR392
- , HW_H_SYS_GPR393, HW_H_SYS_GPR394, HW_H_SYS_GPR395, HW_H_SYS_GPR396
- , HW_H_SYS_GPR397, HW_H_SYS_GPR398, HW_H_SYS_GPR399, HW_H_SYS_GPR400
- , HW_H_SYS_GPR401, HW_H_SYS_GPR402, HW_H_SYS_GPR403, HW_H_SYS_GPR404
- , HW_H_SYS_GPR405, HW_H_SYS_GPR406, HW_H_SYS_GPR407, HW_H_SYS_GPR408
- , HW_H_SYS_GPR409, HW_H_SYS_GPR410, HW_H_SYS_GPR411, HW_H_SYS_GPR412
- , HW_H_SYS_GPR413, HW_H_SYS_GPR414, HW_H_SYS_GPR415, HW_H_SYS_GPR416
- , HW_H_SYS_GPR417, HW_H_SYS_GPR418, HW_H_SYS_GPR419, HW_H_SYS_GPR420
- , HW_H_SYS_GPR421, HW_H_SYS_GPR422, HW_H_SYS_GPR423, HW_H_SYS_GPR424
- , HW_H_SYS_GPR425, HW_H_SYS_GPR426, HW_H_SYS_GPR427, HW_H_SYS_GPR428
- , HW_H_SYS_GPR429, HW_H_SYS_GPR430, HW_H_SYS_GPR431, HW_H_SYS_GPR432
- , HW_H_SYS_GPR433, HW_H_SYS_GPR434, HW_H_SYS_GPR435, HW_H_SYS_GPR436
- , HW_H_SYS_GPR437, HW_H_SYS_GPR438, HW_H_SYS_GPR439, HW_H_SYS_GPR440
- , HW_H_SYS_GPR441, HW_H_SYS_GPR442, HW_H_SYS_GPR443, HW_H_SYS_GPR444
- , HW_H_SYS_GPR445, HW_H_SYS_GPR446, HW_H_SYS_GPR447, HW_H_SYS_GPR448
- , HW_H_SYS_GPR449, HW_H_SYS_GPR450, HW_H_SYS_GPR451, HW_H_SYS_GPR452
- , HW_H_SYS_GPR453, HW_H_SYS_GPR454, HW_H_SYS_GPR455, HW_H_SYS_GPR456
- , HW_H_SYS_GPR457, HW_H_SYS_GPR458, HW_H_SYS_GPR459, HW_H_SYS_GPR460
- , HW_H_SYS_GPR461, HW_H_SYS_GPR462, HW_H_SYS_GPR463, HW_H_SYS_GPR464
- , HW_H_SYS_GPR465, HW_H_SYS_GPR466, HW_H_SYS_GPR467, HW_H_SYS_GPR468
- , HW_H_SYS_GPR469, HW_H_SYS_GPR470, HW_H_SYS_GPR471, HW_H_SYS_GPR472
- , HW_H_SYS_GPR473, HW_H_SYS_GPR474, HW_H_SYS_GPR475, HW_H_SYS_GPR476
- , HW_H_SYS_GPR477, HW_H_SYS_GPR478, HW_H_SYS_GPR479, HW_H_SYS_GPR480
- , HW_H_SYS_GPR481, HW_H_SYS_GPR482, HW_H_SYS_GPR483, HW_H_SYS_GPR484
- , HW_H_SYS_GPR485, HW_H_SYS_GPR486, HW_H_SYS_GPR487, HW_H_SYS_GPR488
- , HW_H_SYS_GPR489, HW_H_SYS_GPR490, HW_H_SYS_GPR491, HW_H_SYS_GPR492
- , HW_H_SYS_GPR493, HW_H_SYS_GPR494, HW_H_SYS_GPR495, HW_H_SYS_GPR496
- , HW_H_SYS_GPR497, HW_H_SYS_GPR498, HW_H_SYS_GPR499, HW_H_SYS_GPR500
- , HW_H_SYS_GPR501, HW_H_SYS_GPR502, HW_H_SYS_GPR503, HW_H_SYS_GPR504
- , HW_H_SYS_GPR505, HW_H_SYS_GPR506, HW_H_SYS_GPR507, HW_H_SYS_GPR508
- , HW_H_SYS_GPR509, HW_H_SYS_GPR510, HW_H_SYS_GPR511, HW_H_MAC_MACLO
- , HW_H_MAC_MACHI, HW_H_TICK_TTMR, HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG
- , HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP, HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP
- , HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP, HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP
- , HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP, HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP
- , HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR, HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S
- , HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S, HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S
- , HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM, HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE
- , HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE, HW_H_SYS_SR_DME, HW_H_SYS_SR_IME
- , HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE, HW_H_SYS_SR_F, HW_H_SYS_SR_CY
- , HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE, HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH
- , HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA, HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE
- , HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF, HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF
- , HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF, HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF
- , HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF, HW_H_SIMM16, HW_H_UIMM16
- , HW_H_UIMM6, HW_H_ATOMIC_RESERVE, HW_H_ATOMIC_ADDRESS, HW_MAX
+ , HW_H_IADDR, HW_H_PC, HW_H_SPR, HW_H_GPR
+ , HW_H_FSR, HW_H_FDR, HW_H_FD32R, HW_H_I64R
+ , HW_H_SYS_VR, HW_H_SYS_UPR, HW_H_SYS_CPUCFGR, HW_H_SYS_DMMUCFGR
+ , HW_H_SYS_IMMUCFGR, HW_H_SYS_DCCFGR, HW_H_SYS_ICCFGR, HW_H_SYS_DCFGR
+ , HW_H_SYS_PCCFGR, HW_H_SYS_NPC, HW_H_SYS_SR, HW_H_SYS_PPC
+ , HW_H_SYS_FPCSR, HW_H_SYS_EPCR0, HW_H_SYS_EPCR1, HW_H_SYS_EPCR2
+ , HW_H_SYS_EPCR3, HW_H_SYS_EPCR4, HW_H_SYS_EPCR5, HW_H_SYS_EPCR6
+ , HW_H_SYS_EPCR7, HW_H_SYS_EPCR8, HW_H_SYS_EPCR9, HW_H_SYS_EPCR10
+ , HW_H_SYS_EPCR11, HW_H_SYS_EPCR12, HW_H_SYS_EPCR13, HW_H_SYS_EPCR14
+ , HW_H_SYS_EPCR15, HW_H_SYS_EEAR0, HW_H_SYS_EEAR1, HW_H_SYS_EEAR2
+ , HW_H_SYS_EEAR3, HW_H_SYS_EEAR4, HW_H_SYS_EEAR5, HW_H_SYS_EEAR6
+ , HW_H_SYS_EEAR7, HW_H_SYS_EEAR8, HW_H_SYS_EEAR9, HW_H_SYS_EEAR10
+ , HW_H_SYS_EEAR11, HW_H_SYS_EEAR12, HW_H_SYS_EEAR13, HW_H_SYS_EEAR14
+ , HW_H_SYS_EEAR15, HW_H_SYS_ESR0, HW_H_SYS_ESR1, HW_H_SYS_ESR2
+ , HW_H_SYS_ESR3, HW_H_SYS_ESR4, HW_H_SYS_ESR5, HW_H_SYS_ESR6
+ , HW_H_SYS_ESR7, HW_H_SYS_ESR8, HW_H_SYS_ESR9, HW_H_SYS_ESR10
+ , HW_H_SYS_ESR11, HW_H_SYS_ESR12, HW_H_SYS_ESR13, HW_H_SYS_ESR14
+ , HW_H_SYS_ESR15, HW_H_SYS_GPR0, HW_H_SYS_GPR1, HW_H_SYS_GPR2
+ , HW_H_SYS_GPR3, HW_H_SYS_GPR4, HW_H_SYS_GPR5, HW_H_SYS_GPR6
+ , HW_H_SYS_GPR7, HW_H_SYS_GPR8, HW_H_SYS_GPR9, HW_H_SYS_GPR10
+ , HW_H_SYS_GPR11, HW_H_SYS_GPR12, HW_H_SYS_GPR13, HW_H_SYS_GPR14
+ , HW_H_SYS_GPR15, HW_H_SYS_GPR16, HW_H_SYS_GPR17, HW_H_SYS_GPR18
+ , HW_H_SYS_GPR19, HW_H_SYS_GPR20, HW_H_SYS_GPR21, HW_H_SYS_GPR22
+ , HW_H_SYS_GPR23, HW_H_SYS_GPR24, HW_H_SYS_GPR25, HW_H_SYS_GPR26
+ , HW_H_SYS_GPR27, HW_H_SYS_GPR28, HW_H_SYS_GPR29, HW_H_SYS_GPR30
+ , HW_H_SYS_GPR31, HW_H_SYS_GPR32, HW_H_SYS_GPR33, HW_H_SYS_GPR34
+ , HW_H_SYS_GPR35, HW_H_SYS_GPR36, HW_H_SYS_GPR37, HW_H_SYS_GPR38
+ , HW_H_SYS_GPR39, HW_H_SYS_GPR40, HW_H_SYS_GPR41, HW_H_SYS_GPR42
+ , HW_H_SYS_GPR43, HW_H_SYS_GPR44, HW_H_SYS_GPR45, HW_H_SYS_GPR46
+ , HW_H_SYS_GPR47, HW_H_SYS_GPR48, HW_H_SYS_GPR49, HW_H_SYS_GPR50
+ , HW_H_SYS_GPR51, HW_H_SYS_GPR52, HW_H_SYS_GPR53, HW_H_SYS_GPR54
+ , HW_H_SYS_GPR55, HW_H_SYS_GPR56, HW_H_SYS_GPR57, HW_H_SYS_GPR58
+ , HW_H_SYS_GPR59, HW_H_SYS_GPR60, HW_H_SYS_GPR61, HW_H_SYS_GPR62
+ , HW_H_SYS_GPR63, HW_H_SYS_GPR64, HW_H_SYS_GPR65, HW_H_SYS_GPR66
+ , HW_H_SYS_GPR67, HW_H_SYS_GPR68, HW_H_SYS_GPR69, HW_H_SYS_GPR70
+ , HW_H_SYS_GPR71, HW_H_SYS_GPR72, HW_H_SYS_GPR73, HW_H_SYS_GPR74
+ , HW_H_SYS_GPR75, HW_H_SYS_GPR76, HW_H_SYS_GPR77, HW_H_SYS_GPR78
+ , HW_H_SYS_GPR79, HW_H_SYS_GPR80, HW_H_SYS_GPR81, HW_H_SYS_GPR82
+ , HW_H_SYS_GPR83, HW_H_SYS_GPR84, HW_H_SYS_GPR85, HW_H_SYS_GPR86
+ , HW_H_SYS_GPR87, HW_H_SYS_GPR88, HW_H_SYS_GPR89, HW_H_SYS_GPR90
+ , HW_H_SYS_GPR91, HW_H_SYS_GPR92, HW_H_SYS_GPR93, HW_H_SYS_GPR94
+ , HW_H_SYS_GPR95, HW_H_SYS_GPR96, HW_H_SYS_GPR97, HW_H_SYS_GPR98
+ , HW_H_SYS_GPR99, HW_H_SYS_GPR100, HW_H_SYS_GPR101, HW_H_SYS_GPR102
+ , HW_H_SYS_GPR103, HW_H_SYS_GPR104, HW_H_SYS_GPR105, HW_H_SYS_GPR106
+ , HW_H_SYS_GPR107, HW_H_SYS_GPR108, HW_H_SYS_GPR109, HW_H_SYS_GPR110
+ , HW_H_SYS_GPR111, HW_H_SYS_GPR112, HW_H_SYS_GPR113, HW_H_SYS_GPR114
+ , HW_H_SYS_GPR115, HW_H_SYS_GPR116, HW_H_SYS_GPR117, HW_H_SYS_GPR118
+ , HW_H_SYS_GPR119, HW_H_SYS_GPR120, HW_H_SYS_GPR121, HW_H_SYS_GPR122
+ , HW_H_SYS_GPR123, HW_H_SYS_GPR124, HW_H_SYS_GPR125, HW_H_SYS_GPR126
+ , HW_H_SYS_GPR127, HW_H_SYS_GPR128, HW_H_SYS_GPR129, HW_H_SYS_GPR130
+ , HW_H_SYS_GPR131, HW_H_SYS_GPR132, HW_H_SYS_GPR133, HW_H_SYS_GPR134
+ , HW_H_SYS_GPR135, HW_H_SYS_GPR136, HW_H_SYS_GPR137, HW_H_SYS_GPR138
+ , HW_H_SYS_GPR139, HW_H_SYS_GPR140, HW_H_SYS_GPR141, HW_H_SYS_GPR142
+ , HW_H_SYS_GPR143, HW_H_SYS_GPR144, HW_H_SYS_GPR145, HW_H_SYS_GPR146
+ , HW_H_SYS_GPR147, HW_H_SYS_GPR148, HW_H_SYS_GPR149, HW_H_SYS_GPR150
+ , HW_H_SYS_GPR151, HW_H_SYS_GPR152, HW_H_SYS_GPR153, HW_H_SYS_GPR154
+ , HW_H_SYS_GPR155, HW_H_SYS_GPR156, HW_H_SYS_GPR157, HW_H_SYS_GPR158
+ , HW_H_SYS_GPR159, HW_H_SYS_GPR160, HW_H_SYS_GPR161, HW_H_SYS_GPR162
+ , HW_H_SYS_GPR163, HW_H_SYS_GPR164, HW_H_SYS_GPR165, HW_H_SYS_GPR166
+ , HW_H_SYS_GPR167, HW_H_SYS_GPR168, HW_H_SYS_GPR169, HW_H_SYS_GPR170
+ , HW_H_SYS_GPR171, HW_H_SYS_GPR172, HW_H_SYS_GPR173, HW_H_SYS_GPR174
+ , HW_H_SYS_GPR175, HW_H_SYS_GPR176, HW_H_SYS_GPR177, HW_H_SYS_GPR178
+ , HW_H_SYS_GPR179, HW_H_SYS_GPR180, HW_H_SYS_GPR181, HW_H_SYS_GPR182
+ , HW_H_SYS_GPR183, HW_H_SYS_GPR184, HW_H_SYS_GPR185, HW_H_SYS_GPR186
+ , HW_H_SYS_GPR187, HW_H_SYS_GPR188, HW_H_SYS_GPR189, HW_H_SYS_GPR190
+ , HW_H_SYS_GPR191, HW_H_SYS_GPR192, HW_H_SYS_GPR193, HW_H_SYS_GPR194
+ , HW_H_SYS_GPR195, HW_H_SYS_GPR196, HW_H_SYS_GPR197, HW_H_SYS_GPR198
+ , HW_H_SYS_GPR199, HW_H_SYS_GPR200, HW_H_SYS_GPR201, HW_H_SYS_GPR202
+ , HW_H_SYS_GPR203, HW_H_SYS_GPR204, HW_H_SYS_GPR205, HW_H_SYS_GPR206
+ , HW_H_SYS_GPR207, HW_H_SYS_GPR208, HW_H_SYS_GPR209, HW_H_SYS_GPR210
+ , HW_H_SYS_GPR211, HW_H_SYS_GPR212, HW_H_SYS_GPR213, HW_H_SYS_GPR214
+ , HW_H_SYS_GPR215, HW_H_SYS_GPR216, HW_H_SYS_GPR217, HW_H_SYS_GPR218
+ , HW_H_SYS_GPR219, HW_H_SYS_GPR220, HW_H_SYS_GPR221, HW_H_SYS_GPR222
+ , HW_H_SYS_GPR223, HW_H_SYS_GPR224, HW_H_SYS_GPR225, HW_H_SYS_GPR226
+ , HW_H_SYS_GPR227, HW_H_SYS_GPR228, HW_H_SYS_GPR229, HW_H_SYS_GPR230
+ , HW_H_SYS_GPR231, HW_H_SYS_GPR232, HW_H_SYS_GPR233, HW_H_SYS_GPR234
+ , HW_H_SYS_GPR235, HW_H_SYS_GPR236, HW_H_SYS_GPR237, HW_H_SYS_GPR238
+ , HW_H_SYS_GPR239, HW_H_SYS_GPR240, HW_H_SYS_GPR241, HW_H_SYS_GPR242
+ , HW_H_SYS_GPR243, HW_H_SYS_GPR244, HW_H_SYS_GPR245, HW_H_SYS_GPR246
+ , HW_H_SYS_GPR247, HW_H_SYS_GPR248, HW_H_SYS_GPR249, HW_H_SYS_GPR250
+ , HW_H_SYS_GPR251, HW_H_SYS_GPR252, HW_H_SYS_GPR253, HW_H_SYS_GPR254
+ , HW_H_SYS_GPR255, HW_H_SYS_GPR256, HW_H_SYS_GPR257, HW_H_SYS_GPR258
+ , HW_H_SYS_GPR259, HW_H_SYS_GPR260, HW_H_SYS_GPR261, HW_H_SYS_GPR262
+ , HW_H_SYS_GPR263, HW_H_SYS_GPR264, HW_H_SYS_GPR265, HW_H_SYS_GPR266
+ , HW_H_SYS_GPR267, HW_H_SYS_GPR268, HW_H_SYS_GPR269, HW_H_SYS_GPR270
+ , HW_H_SYS_GPR271, HW_H_SYS_GPR272, HW_H_SYS_GPR273, HW_H_SYS_GPR274
+ , HW_H_SYS_GPR275, HW_H_SYS_GPR276, HW_H_SYS_GPR277, HW_H_SYS_GPR278
+ , HW_H_SYS_GPR279, HW_H_SYS_GPR280, HW_H_SYS_GPR281, HW_H_SYS_GPR282
+ , HW_H_SYS_GPR283, HW_H_SYS_GPR284, HW_H_SYS_GPR285, HW_H_SYS_GPR286
+ , HW_H_SYS_GPR287, HW_H_SYS_GPR288, HW_H_SYS_GPR289, HW_H_SYS_GPR290
+ , HW_H_SYS_GPR291, HW_H_SYS_GPR292, HW_H_SYS_GPR293, HW_H_SYS_GPR294
+ , HW_H_SYS_GPR295, HW_H_SYS_GPR296, HW_H_SYS_GPR297, HW_H_SYS_GPR298
+ , HW_H_SYS_GPR299, HW_H_SYS_GPR300, HW_H_SYS_GPR301, HW_H_SYS_GPR302
+ , HW_H_SYS_GPR303, HW_H_SYS_GPR304, HW_H_SYS_GPR305, HW_H_SYS_GPR306
+ , HW_H_SYS_GPR307, HW_H_SYS_GPR308, HW_H_SYS_GPR309, HW_H_SYS_GPR310
+ , HW_H_SYS_GPR311, HW_H_SYS_GPR312, HW_H_SYS_GPR313, HW_H_SYS_GPR314
+ , HW_H_SYS_GPR315, HW_H_SYS_GPR316, HW_H_SYS_GPR317, HW_H_SYS_GPR318
+ , HW_H_SYS_GPR319, HW_H_SYS_GPR320, HW_H_SYS_GPR321, HW_H_SYS_GPR322
+ , HW_H_SYS_GPR323, HW_H_SYS_GPR324, HW_H_SYS_GPR325, HW_H_SYS_GPR326
+ , HW_H_SYS_GPR327, HW_H_SYS_GPR328, HW_H_SYS_GPR329, HW_H_SYS_GPR330
+ , HW_H_SYS_GPR331, HW_H_SYS_GPR332, HW_H_SYS_GPR333, HW_H_SYS_GPR334
+ , HW_H_SYS_GPR335, HW_H_SYS_GPR336, HW_H_SYS_GPR337, HW_H_SYS_GPR338
+ , HW_H_SYS_GPR339, HW_H_SYS_GPR340, HW_H_SYS_GPR341, HW_H_SYS_GPR342
+ , HW_H_SYS_GPR343, HW_H_SYS_GPR344, HW_H_SYS_GPR345, HW_H_SYS_GPR346
+ , HW_H_SYS_GPR347, HW_H_SYS_GPR348, HW_H_SYS_GPR349, HW_H_SYS_GPR350
+ , HW_H_SYS_GPR351, HW_H_SYS_GPR352, HW_H_SYS_GPR353, HW_H_SYS_GPR354
+ , HW_H_SYS_GPR355, HW_H_SYS_GPR356, HW_H_SYS_GPR357, HW_H_SYS_GPR358
+ , HW_H_SYS_GPR359, HW_H_SYS_GPR360, HW_H_SYS_GPR361, HW_H_SYS_GPR362
+ , HW_H_SYS_GPR363, HW_H_SYS_GPR364, HW_H_SYS_GPR365, HW_H_SYS_GPR366
+ , HW_H_SYS_GPR367, HW_H_SYS_GPR368, HW_H_SYS_GPR369, HW_H_SYS_GPR370
+ , HW_H_SYS_GPR371, HW_H_SYS_GPR372, HW_H_SYS_GPR373, HW_H_SYS_GPR374
+ , HW_H_SYS_GPR375, HW_H_SYS_GPR376, HW_H_SYS_GPR377, HW_H_SYS_GPR378
+ , HW_H_SYS_GPR379, HW_H_SYS_GPR380, HW_H_SYS_GPR381, HW_H_SYS_GPR382
+ , HW_H_SYS_GPR383, HW_H_SYS_GPR384, HW_H_SYS_GPR385, HW_H_SYS_GPR386
+ , HW_H_SYS_GPR387, HW_H_SYS_GPR388, HW_H_SYS_GPR389, HW_H_SYS_GPR390
+ , HW_H_SYS_GPR391, HW_H_SYS_GPR392, HW_H_SYS_GPR393, HW_H_SYS_GPR394
+ , HW_H_SYS_GPR395, HW_H_SYS_GPR396, HW_H_SYS_GPR397, HW_H_SYS_GPR398
+ , HW_H_SYS_GPR399, HW_H_SYS_GPR400, HW_H_SYS_GPR401, HW_H_SYS_GPR402
+ , HW_H_SYS_GPR403, HW_H_SYS_GPR404, HW_H_SYS_GPR405, HW_H_SYS_GPR406
+ , HW_H_SYS_GPR407, HW_H_SYS_GPR408, HW_H_SYS_GPR409, HW_H_SYS_GPR410
+ , HW_H_SYS_GPR411, HW_H_SYS_GPR412, HW_H_SYS_GPR413, HW_H_SYS_GPR414
+ , HW_H_SYS_GPR415, HW_H_SYS_GPR416, HW_H_SYS_GPR417, HW_H_SYS_GPR418
+ , HW_H_SYS_GPR419, HW_H_SYS_GPR420, HW_H_SYS_GPR421, HW_H_SYS_GPR422
+ , HW_H_SYS_GPR423, HW_H_SYS_GPR424, HW_H_SYS_GPR425, HW_H_SYS_GPR426
+ , HW_H_SYS_GPR427, HW_H_SYS_GPR428, HW_H_SYS_GPR429, HW_H_SYS_GPR430
+ , HW_H_SYS_GPR431, HW_H_SYS_GPR432, HW_H_SYS_GPR433, HW_H_SYS_GPR434
+ , HW_H_SYS_GPR435, HW_H_SYS_GPR436, HW_H_SYS_GPR437, HW_H_SYS_GPR438
+ , HW_H_SYS_GPR439, HW_H_SYS_GPR440, HW_H_SYS_GPR441, HW_H_SYS_GPR442
+ , HW_H_SYS_GPR443, HW_H_SYS_GPR444, HW_H_SYS_GPR445, HW_H_SYS_GPR446
+ , HW_H_SYS_GPR447, HW_H_SYS_GPR448, HW_H_SYS_GPR449, HW_H_SYS_GPR450
+ , HW_H_SYS_GPR451, HW_H_SYS_GPR452, HW_H_SYS_GPR453, HW_H_SYS_GPR454
+ , HW_H_SYS_GPR455, HW_H_SYS_GPR456, HW_H_SYS_GPR457, HW_H_SYS_GPR458
+ , HW_H_SYS_GPR459, HW_H_SYS_GPR460, HW_H_SYS_GPR461, HW_H_SYS_GPR462
+ , HW_H_SYS_GPR463, HW_H_SYS_GPR464, HW_H_SYS_GPR465, HW_H_SYS_GPR466
+ , HW_H_SYS_GPR467, HW_H_SYS_GPR468, HW_H_SYS_GPR469, HW_H_SYS_GPR470
+ , HW_H_SYS_GPR471, HW_H_SYS_GPR472, HW_H_SYS_GPR473, HW_H_SYS_GPR474
+ , HW_H_SYS_GPR475, HW_H_SYS_GPR476, HW_H_SYS_GPR477, HW_H_SYS_GPR478
+ , HW_H_SYS_GPR479, HW_H_SYS_GPR480, HW_H_SYS_GPR481, HW_H_SYS_GPR482
+ , HW_H_SYS_GPR483, HW_H_SYS_GPR484, HW_H_SYS_GPR485, HW_H_SYS_GPR486
+ , HW_H_SYS_GPR487, HW_H_SYS_GPR488, HW_H_SYS_GPR489, HW_H_SYS_GPR490
+ , HW_H_SYS_GPR491, HW_H_SYS_GPR492, HW_H_SYS_GPR493, HW_H_SYS_GPR494
+ , HW_H_SYS_GPR495, HW_H_SYS_GPR496, HW_H_SYS_GPR497, HW_H_SYS_GPR498
+ , HW_H_SYS_GPR499, HW_H_SYS_GPR500, HW_H_SYS_GPR501, HW_H_SYS_GPR502
+ , HW_H_SYS_GPR503, HW_H_SYS_GPR504, HW_H_SYS_GPR505, HW_H_SYS_GPR506
+ , HW_H_SYS_GPR507, HW_H_SYS_GPR508, HW_H_SYS_GPR509, HW_H_SYS_GPR510
+ , HW_H_SYS_GPR511, HW_H_MAC_MACLO, HW_H_MAC_MACHI, HW_H_TICK_TTMR
+ , HW_H_SYS_VR_REV, HW_H_SYS_VR_CFG, HW_H_SYS_VR_VER, HW_H_SYS_UPR_UP
+ , HW_H_SYS_UPR_DCP, HW_H_SYS_UPR_ICP, HW_H_SYS_UPR_DMP, HW_H_SYS_UPR_MP
+ , HW_H_SYS_UPR_IMP, HW_H_SYS_UPR_DUP, HW_H_SYS_UPR_PCUP, HW_H_SYS_UPR_PICP
+ , HW_H_SYS_UPR_PMP, HW_H_SYS_UPR_TTP, HW_H_SYS_UPR_CUP, HW_H_SYS_CPUCFGR_NSGR
+ , HW_H_SYS_CPUCFGR_CGF, HW_H_SYS_CPUCFGR_OB32S, HW_H_SYS_CPUCFGR_OB64S, HW_H_SYS_CPUCFGR_OF32S
+ , HW_H_SYS_CPUCFGR_OF64S, HW_H_SYS_CPUCFGR_OV64S, HW_H_SYS_CPUCFGR_ND, HW_H_SYS_SR_SM
+ , HW_H_SYS_SR_TEE, HW_H_SYS_SR_IEE, HW_H_SYS_SR_DCE, HW_H_SYS_SR_ICE
+ , HW_H_SYS_SR_DME, HW_H_SYS_SR_IME, HW_H_SYS_SR_LEE, HW_H_SYS_SR_CE
+ , HW_H_SYS_SR_F, HW_H_SYS_SR_CY, HW_H_SYS_SR_OV, HW_H_SYS_SR_OVE
+ , HW_H_SYS_SR_DSX, HW_H_SYS_SR_EPH, HW_H_SYS_SR_FO, HW_H_SYS_SR_SUMRA
+ , HW_H_SYS_SR_CID, HW_H_SYS_FPCSR_FPEE, HW_H_SYS_FPCSR_RM, HW_H_SYS_FPCSR_OVF
+ , HW_H_SYS_FPCSR_UNF, HW_H_SYS_FPCSR_SNF, HW_H_SYS_FPCSR_QNF, HW_H_SYS_FPCSR_ZF
+ , HW_H_SYS_FPCSR_IXF, HW_H_SYS_FPCSR_IVF, HW_H_SYS_FPCSR_INF, HW_H_SYS_FPCSR_DZF
+ , HW_H_SIMM16, HW_H_UIMM16, HW_H_UIMM6, HW_H_ATOMIC_RESERVE
+ , HW_H_ATOMIC_ADDRESS, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@@ -626,11 +627,12 @@ typedef enum cgen_operand_type {
, OR1K_OPERAND_DISP26, OR1K_OPERAND_DISP21, OR1K_OPERAND_SIMM16, OR1K_OPERAND_UIMM16
, OR1K_OPERAND_SIMM16_SPLIT, OR1K_OPERAND_UIMM16_SPLIT, OR1K_OPERAND_RDSF, OR1K_OPERAND_RASF
, OR1K_OPERAND_RBSF, OR1K_OPERAND_RDDF, OR1K_OPERAND_RADF, OR1K_OPERAND_RBDF
- , OR1K_OPERAND_MAX
+ , OR1K_OPERAND_RDD32F, OR1K_OPERAND_RAD32F, OR1K_OPERAND_RBD32F, OR1K_OPERAND_RDDI
+ , OR1K_OPERAND_RADI, OR1K_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 32
+#define MAX_OPERANDS 37
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 10
@@ -678,9 +680,11 @@ extern const CGEN_ATTR_TABLE or1k_cgen_insn_attr_table[];
/* Hardware decls. */
+extern CGEN_KEYWORD or1k_cgen_opval_h_gpr;
extern CGEN_KEYWORD or1k_cgen_opval_h_fsr;
extern CGEN_KEYWORD or1k_cgen_opval_h_fdr;
-extern CGEN_KEYWORD or1k_cgen_opval_h_gpr;
+extern CGEN_KEYWORD or1k_cgen_opval_h_fd32r;
+extern CGEN_KEYWORD or1k_cgen_opval_h_i64r;
extern const CGEN_HW_ENTRY or1k_cgen_hw_table[];
diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
index f14c56fec4..c7a80ba4c9 100644
--- a/opcodes/or1k-dis.c
+++ b/opcodes/or1k-dis.c
@@ -99,8 +99,14 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r2, 0);
break;
+ case OR1K_OPERAND_RAD32F :
+ print_keyword (cd, info, & or1k_cgen_opval_h_fd32r, fields->f_r2, 0);
+ break;
case OR1K_OPERAND_RADF :
- print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r2, 0);
+ break;
+ case OR1K_OPERAND_RADI :
+ print_keyword (cd, info, & or1k_cgen_opval_h_i64r, fields->f_r2, 0);
break;
case OR1K_OPERAND_RASF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r2, 0);
@@ -108,8 +114,11 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r3, 0);
break;
+ case OR1K_OPERAND_RBD32F :
+ print_keyword (cd, info, & or1k_cgen_opval_h_fd32r, fields->f_r3, 0);
+ break;
case OR1K_OPERAND_RBDF :
- print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
+ print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r3, 0);
break;
case OR1K_OPERAND_RBSF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r3, 0);
@@ -117,9 +126,15 @@ or1k_cgen_print_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
print_keyword (cd, info, & or1k_cgen_opval_h_gpr, fields->f_r1, 0);
break;
+ case OR1K_OPERAND_RDD32F :
+ print_keyword (cd, info, & or1k_cgen_opval_h_fd32r, fields->f_r1, 0);
+ break;
case OR1K_OPERAND_RDDF :
print_keyword (cd, info, & or1k_cgen_opval_h_fdr, fields->f_r1, 0);
break;
+ case OR1K_OPERAND_RDDI :
+ print_keyword (cd, info, & or1k_cgen_opval_h_i64r, fields->f_r1, 0);
+ break;
case OR1K_OPERAND_RDSF :
print_keyword (cd, info, & or1k_cgen_opval_h_fsr, fields->f_r1, 0);
break;
diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c
index 964ec33ee8..f60540e7de 100644
--- a/opcodes/or1k-ibld.c
+++ b/opcodes/or1k-ibld.c
@@ -590,8 +590,14 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RAD32F :
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
+ break;
case OR1K_OPERAND_RADF :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
+ break;
+ case OR1K_OPERAND_RADI :
+ errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
break;
case OR1K_OPERAND_RASF :
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
@@ -599,8 +605,11 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RBD32F :
+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
+ break;
case OR1K_OPERAND_RBDF :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
break;
case OR1K_OPERAND_RBSF :
errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
@@ -608,9 +617,15 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RDD32F :
+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ break;
case OR1K_OPERAND_RDDF :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
+ case OR1K_OPERAND_RDDI :
+ errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
+ break;
case OR1K_OPERAND_RDSF :
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
break;
@@ -714,8 +729,14 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RA :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
break;
+ case OR1K_OPERAND_RAD32F :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
+ break;
case OR1K_OPERAND_RADF :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
+ break;
+ case OR1K_OPERAND_RADI :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
break;
case OR1K_OPERAND_RASF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
@@ -723,8 +744,11 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RB :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
break;
+ case OR1K_OPERAND_RBD32F :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
+ break;
case OR1K_OPERAND_RBDF :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
break;
case OR1K_OPERAND_RBSF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
@@ -732,9 +756,15 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd,
case OR1K_OPERAND_RD :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDD32F :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ break;
case OR1K_OPERAND_RDDF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
+ case OR1K_OPERAND_RDDI :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
+ break;
case OR1K_OPERAND_RDSF :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
break;
@@ -813,8 +843,14 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
value = fields->f_r2;
break;
+ case OR1K_OPERAND_RAD32F :
+ value = fields->f_r2;
+ break;
case OR1K_OPERAND_RADF :
- value = fields->f_r1;
+ value = fields->f_r2;
+ break;
+ case OR1K_OPERAND_RADI :
+ value = fields->f_r2;
break;
case OR1K_OPERAND_RASF :
value = fields->f_r2;
@@ -822,8 +858,11 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
value = fields->f_r3;
break;
+ case OR1K_OPERAND_RBD32F :
+ value = fields->f_r3;
+ break;
case OR1K_OPERAND_RBDF :
- value = fields->f_r1;
+ value = fields->f_r3;
break;
case OR1K_OPERAND_RBSF :
value = fields->f_r3;
@@ -831,9 +870,15 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDD32F :
+ value = fields->f_r1;
+ break;
case OR1K_OPERAND_RDDF :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDDI :
+ value = fields->f_r1;
+ break;
case OR1K_OPERAND_RDSF :
value = fields->f_r1;
break;
@@ -882,8 +927,14 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
value = fields->f_r2;
break;
+ case OR1K_OPERAND_RAD32F :
+ value = fields->f_r2;
+ break;
case OR1K_OPERAND_RADF :
- value = fields->f_r1;
+ value = fields->f_r2;
+ break;
+ case OR1K_OPERAND_RADI :
+ value = fields->f_r2;
break;
case OR1K_OPERAND_RASF :
value = fields->f_r2;
@@ -891,8 +942,11 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
value = fields->f_r3;
break;
+ case OR1K_OPERAND_RBD32F :
+ value = fields->f_r3;
+ break;
case OR1K_OPERAND_RBDF :
- value = fields->f_r1;
+ value = fields->f_r3;
break;
case OR1K_OPERAND_RBSF :
value = fields->f_r3;
@@ -900,9 +954,15 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDD32F :
+ value = fields->f_r1;
+ break;
case OR1K_OPERAND_RDDF :
value = fields->f_r1;
break;
+ case OR1K_OPERAND_RDDI :
+ value = fields->f_r1;
+ break;
case OR1K_OPERAND_RDSF :
value = fields->f_r1;
break;
@@ -958,8 +1018,14 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
fields->f_r2 = value;
break;
+ case OR1K_OPERAND_RAD32F :
+ fields->f_r2 = value;
+ break;
case OR1K_OPERAND_RADF :
- fields->f_r1 = value;
+ fields->f_r2 = value;
+ break;
+ case OR1K_OPERAND_RADI :
+ fields->f_r2 = value;
break;
case OR1K_OPERAND_RASF :
fields->f_r2 = value;
@@ -967,8 +1033,11 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
fields->f_r3 = value;
break;
+ case OR1K_OPERAND_RBD32F :
+ fields->f_r3 = value;
+ break;
case OR1K_OPERAND_RBDF :
- fields->f_r1 = value;
+ fields->f_r3 = value;
break;
case OR1K_OPERAND_RBSF :
fields->f_r3 = value;
@@ -976,9 +1045,15 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDD32F :
+ fields->f_r1 = value;
+ break;
case OR1K_OPERAND_RDDF :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDDI :
+ fields->f_r1 = value;
+ break;
case OR1K_OPERAND_RDSF :
fields->f_r1 = value;
break;
@@ -1024,8 +1099,14 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RA :
fields->f_r2 = value;
break;
+ case OR1K_OPERAND_RAD32F :
+ fields->f_r2 = value;
+ break;
case OR1K_OPERAND_RADF :
- fields->f_r1 = value;
+ fields->f_r2 = value;
+ break;
+ case OR1K_OPERAND_RADI :
+ fields->f_r2 = value;
break;
case OR1K_OPERAND_RASF :
fields->f_r2 = value;
@@ -1033,8 +1114,11 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RB :
fields->f_r3 = value;
break;
+ case OR1K_OPERAND_RBD32F :
+ fields->f_r3 = value;
+ break;
case OR1K_OPERAND_RBDF :
- fields->f_r1 = value;
+ fields->f_r3 = value;
break;
case OR1K_OPERAND_RBSF :
fields->f_r3 = value;
@@ -1042,9 +1126,15 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case OR1K_OPERAND_RD :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDD32F :
+ fields->f_r1 = value;
+ break;
case OR1K_OPERAND_RDDF :
fields->f_r1 = value;
break;
+ case OR1K_OPERAND_RDDI :
+ fields->f_r1 = value;
+ break;
case OR1K_OPERAND_RDSF :
fields->f_r1 = value;
break;
diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c
index 36aed256d6..f7b3caec5d 100644
--- a/opcodes/or1k-opc.c
+++ b/opcodes/or1k-opc.c
@@ -149,31 +149,59 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = {
};
static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = {
32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
+static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = {
32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R1) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_eq_s ATTRIBUTE_UNUSED = {
32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
+static const CGEN_IFMT ifmt_lf_eq_d ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_eq_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = {
32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R1) }, { F (F_R1) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } }
};
#undef F
@@ -791,6 +819,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000010 }
},
+/* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000010 }
+ },
/* lf.sub.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -803,6 +837,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000011 }
},
+/* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000011 }
+ },
/* lf.mul.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -815,6 +855,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000012 }
},
+/* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000012 }
+ },
/* lf.div.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -827,6 +873,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000013 }
},
+/* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000013 }
+ },
/* lf.rem.s $rDSF,$rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -839,17 +891,29 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000016 }
},
+/* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000016 }
+ },
/* lf.itof.s $rDSF,$rA */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } },
& ifmt_lf_itof_s, { 0xc8000004 }
},
-/* lf.itof.d $rDSF,$rA */
+/* lf.itof.d $rDDF,$rA */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } },
- & ifmt_lf_itof_s, { 0xc8000014 }
+ { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } },
+ & ifmt_lf_itof_d, { 0xc8000014 }
+ },
+/* lf.itof.d $rDD32F,$rADI */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RADI), 0 } },
+ & ifmt_lf_itof_d32, { 0xc8000014 }
},
/* lf.ftoi.s $rD,$rASF */
{
@@ -863,17 +927,29 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } },
& ifmt_lf_ftoi_d, { 0xc8000015 }
},
+/* lf.ftoi.d $rDDI,$rAD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDDI), ',', OP (RAD32F), 0 } },
+ & ifmt_lf_ftoi_d32, { 0xc8000015 }
+ },
/* lf.sfeq.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc8000008 }
},
-/* lf.sfeq.d $rASF,$rBSF */
+/* lf.sfeq.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000018 }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc8000018 }
+ },
+/* lf.sfeq.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc8000018 }
},
/* lf.sfne.s $rASF,$rBSF */
{
@@ -881,11 +957,17 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc8000009 }
},
-/* lf.sfne.d $rASF,$rBSF */
+/* lf.sfne.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc8000019 }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc8000019 }
+ },
+/* lf.sfne.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc8000019 }
},
/* lf.sfge.s $rASF,$rBSF */
{
@@ -893,11 +975,17 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc800000b }
},
-/* lf.sfge.d $rASF,$rBSF */
+/* lf.sfge.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001b }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc800001b }
+ },
+/* lf.sfge.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc800001b }
},
/* lf.sfgt.s $rASF,$rBSF */
{
@@ -905,11 +993,17 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc800000a }
},
-/* lf.sfgt.d $rASF,$rBSF */
+/* lf.sfgt.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001a }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc800001a }
+ },
+/* lf.sfgt.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc800001a }
},
/* lf.sflt.s $rASF,$rBSF */
{
@@ -917,11 +1011,17 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc800000c }
},
-/* lf.sflt.d $rASF,$rBSF */
+/* lf.sflt.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001c }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc800001c }
+ },
+/* lf.sflt.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc800001c }
},
/* lf.sfle.s $rASF,$rBSF */
{
@@ -929,11 +1029,17 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
& ifmt_lf_eq_s, { 0xc800000d }
},
-/* lf.sfle.d $rASF,$rBSF */
+/* lf.sfle.d $rADF,$rBDF */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } },
- & ifmt_lf_eq_s, { 0xc800001d }
+ { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } },
+ & ifmt_lf_eq_d, { 0xc800001d }
+ },
+/* lf.sfle.d $rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_eq_d32, { 0xc800001d }
},
/* lf.madd.s $rDSF,$rASF,$rBSF */
{
@@ -947,6 +1053,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } },
& ifmt_lf_add_d, { 0xc8000017 }
},
+/* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (RDD32F), ',', OP (RAD32F), ',', OP (RBD32F), 0 } },
+ & ifmt_lf_add_d32, { 0xc8000017 }
+ },
/* lf.cust1.s $rASF,$rBSF */
{
{ 0, 0, 0, 0 },
@@ -959,6 +1071,12 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, 0 } },
& ifmt_lf_cust1_d, { 0xc80000e0 }
},
+/* lf.cust1.d */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_lf_cust1_d32, { 0xc80000e0 }
+ },
};
#undef A
diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h
index 78ed425332..54fc31fabc 100644
--- a/opcodes/or1k-opc.h
+++ b/opcodes/or1k-opc.h
@@ -65,21 +65,24 @@ typedef enum cgen_insn_type {
, OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1
, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5
, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S
- , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S
- , OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S
- , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S
- , OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S
- , OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S
- , OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S
- , OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S
- , OR1K_INSN_LF_CUST1_D
+ , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D
+ , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32
+ , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S
+ , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D
+ , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32
+ , OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_EQ_D32, OR1K_INSN_LF_NE_S
+ , OR1K_INSN_LF_NE_D, OR1K_INSN_LF_NE_D32, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GE_D
+ , OR1K_INSN_LF_GE_D32, OR1K_INSN_LF_GT_S, OR1K_INSN_LF_GT_D, OR1K_INSN_LF_GT_D32
+ , OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LT_D32, OR1K_INSN_LF_LE_S
+ , OR1K_INSN_LF_LE_D, OR1K_INSN_LF_LE_D32, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_MADD_D
+ , OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D, OR1K_INSN_LF_CUST1_D32
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID OR1K_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D + 1)
+#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D32 + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c
index 6b18dab986..ff7593ac74 100644
--- a/opcodes/or1k-opinst.c
+++ b/opcodes/or1k-opinst.c
@@ -461,6 +461,13 @@ static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 },
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
@@ -475,6 +482,13 @@ static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 },
+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
@@ -489,6 +503,13 @@ static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 },
+ { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_eq_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
@@ -503,6 +524,13 @@ static const CGEN_OPINST sfmt_lf_eq_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_eq_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = {
{ INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 },
{ INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 },
@@ -519,6 +547,14 @@ static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = {
{ END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
+static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = {
+ { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 },
+ { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 },
+ { INPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
#undef OP_ENT
#undef INPUT
#undef OUTPUT
@@ -629,32 +665,47 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = {
& sfmt_l_msync_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_add_s_ops[0],
& sfmt_lf_add_d_ops[0],
+ & sfmt_lf_add_d32_ops[0],
& sfmt_lf_itof_s_ops[0],
& sfmt_lf_itof_d_ops[0],
+ & sfmt_lf_itof_d32_ops[0],
& sfmt_lf_ftoi_s_ops[0],
& sfmt_lf_ftoi_d_ops[0],
+ & sfmt_lf_ftoi_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_eq_s_ops[0],
& sfmt_lf_eq_d_ops[0],
+ & sfmt_lf_eq_d32_ops[0],
& sfmt_lf_madd_s_ops[0],
& sfmt_lf_madd_d_ops[0],
+ & sfmt_lf_madd_d32_ops[0],
+ & sfmt_l_msync_ops[0],
& sfmt_l_msync_ops[0],
& sfmt_l_msync_ops[0],
};
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim for orfp64a32 spec
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 1/6] cpu: Add support for orfp64a32 spec Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes " Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-13 21:40 ` Andrew Burgess
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion Stafford Horne
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
sim/ChangeLog:
* or1k/cpu.c: Regenerate.
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate.
---
sim/or1k/cpu.c | 60 +++--
sim/or1k/cpu.h | 115 +++++++++-
sim/or1k/decode.c | 302 +++++++++++++++++++------
sim/or1k/decode.h | 16 +-
sim/or1k/model.c | 510 ++++++++++++++++++++++++++++++++++++++++++
sim/or1k/sem-switch.c | 296 ++++++++++++++++++++++++
sim/or1k/sem.c | 326 +++++++++++++++++++++++++++
7 files changed, 1537 insertions(+), 88 deletions(-)
diff --git a/sim/or1k/cpu.c b/sim/or1k/cpu.c
index f93b51276e..a0ee763813 100644
--- a/sim/or1k/cpu.c
+++ b/sim/or1k/cpu.c
@@ -44,6 +44,38 @@ or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
SET_H_PC (newval);
}
+/* Get the value of h-spr. */
+
+USI
+or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SPR (regno);
+}
+
+/* Set a value for h-spr. */
+
+void
+or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_SPR (regno, newval);
+}
+
+/* Get the value of h-gpr. */
+
+USI
+or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GPR (regno);
+}
+
+/* Set a value for h-gpr. */
+
+void
+or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+{
+ SET_H_GPR (regno, newval);
+}
+
/* Get the value of h-fsr. */
SF
@@ -60,36 +92,36 @@ or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
SET_H_FSR (regno, newval);
}
-/* Get the value of h-spr. */
+/* Get the value of h-fd32r. */
-USI
-or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
+DF
+or1k32bf_h_fd32r_get (SIM_CPU *current_cpu, UINT regno)
{
- return GET_H_SPR (regno);
+ return GET_H_FD32R (regno);
}
-/* Set a value for h-spr. */
+/* Set a value for h-fd32r. */
void
-or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+or1k32bf_h_fd32r_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
- SET_H_SPR (regno, newval);
+ SET_H_FD32R (regno, newval);
}
-/* Get the value of h-gpr. */
+/* Get the value of h-i64r. */
-USI
-or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+DI
+or1k32bf_h_i64r_get (SIM_CPU *current_cpu, UINT regno)
{
- return GET_H_GPR (regno);
+ return GET_H_I64R (regno);
}
-/* Set a value for h-gpr. */
+/* Set a value for h-i64r. */
void
-or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
+or1k32bf_h_i64r_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
- SET_H_GPR (regno, newval);
+ SET_H_I64R (regno, newval);
}
/* Get the value of h-sys-vr. */
diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
index 199c93bce3..7a16c3f6ec 100644
--- a/sim/or1k/cpu.h
+++ b/sim/or1k/cpu.h
@@ -73,15 +73,31 @@ SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))),
/* Virtual regs. */
+#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
+#define SET_H_SPR(index, x) \
+do { \
+or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
+;} while (0)
#define GET_H_FSR(index) SUBWORDSISF (TRUNCSISI (GET_H_GPR (index)))
#define SET_H_FSR(index, x) \
do { \
SET_H_GPR ((index), ZEXTSISI (SUBWORDSFSI ((x))));\
;} while (0)
-#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
-#define SET_H_SPR(index, x) \
+#define GET_H_FD32R(index) JOINSIDF (GET_H_GPR (index), GET_H_GPR (((index) + (((((index) > (15))) ? (2) : (1))))))
+#define SET_H_FD32R(index, x) \
do { \
-or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
+{\
+SET_H_GPR ((index), SUBWORDDFSI ((x), 0));\
+SET_H_GPR ((((index)) + ((((((index)) > (15))) ? (2) : (1)))), SUBWORDDFSI ((x), 1));\
+}\
+;} while (0)
+#define GET_H_I64R(index) JOINSIDI (GET_H_GPR (index), GET_H_GPR (((index) + (((((index) > (15))) ? (2) : (1))))))
+#define SET_H_I64R(index, x) \
+do { \
+{\
+SET_H_GPR ((index), SUBWORDDISI ((x), 0));\
+SET_H_GPR ((((index)) + ((((((index)) > (15))) ? (2) : (1)))), SUBWORDDISI ((x), 1));\
+}\
;} while (0)
#define GET_H_SYS_VR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR))
#define SET_H_SYS_VR(x) \
@@ -3227,12 +3243,16 @@ or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_
/* Cover fns for register access. */
USI or1k32bf_h_pc_get (SIM_CPU *);
void or1k32bf_h_pc_set (SIM_CPU *, USI);
-SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
-void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
+SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
+void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
+DF or1k32bf_h_fd32r_get (SIM_CPU *, UINT);
+void or1k32bf_h_fd32r_set (SIM_CPU *, UINT, DF);
+DI or1k32bf_h_i64r_get (SIM_CPU *, UINT);
+void or1k32bf_h_i64r_set (SIM_CPU *, UINT, DI);
USI or1k32bf_h_sys_vr_get (SIM_CPU *);
void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_upr_get (SIM_CPU *);
@@ -4978,6 +4998,23 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_ADD_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ADD_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_ITOF_S_VARS \
UINT f_opcode; \
UINT f_r1; \
@@ -4995,6 +5032,23 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_ITOF_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_ITOF_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_FTOI_S_VARS \
UINT f_opcode; \
UINT f_r1; \
@@ -5012,6 +5066,23 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_FTOI_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_FTOI_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_EQ_S_VARS \
UINT f_opcode; \
UINT f_r1; \
@@ -5029,6 +5100,23 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_EQ_D32_VARS \
+ UINT f_opcode; \
+ UINT f_r1; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_EQ_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
#define EXTRACT_IFMT_LF_CUST1_S_VARS \
UINT f_opcode; \
UINT f_resv_25_5; \
@@ -5046,6 +5134,23 @@ struct scache {
f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+#define EXTRACT_IFMT_LF_CUST1_D32_VARS \
+ UINT f_opcode; \
+ UINT f_resv_25_5; \
+ UINT f_r2; \
+ UINT f_r3; \
+ UINT f_resv_10_3; \
+ UINT f_op_7_8; \
+ unsigned int length;
+#define EXTRACT_IFMT_LF_CUST1_D32_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
+ f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
+
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {
diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c
index 153e00f82f..d619910aa7 100644
--- a/sim/or1k/decode.c
+++ b/sim/or1k/decode.c
@@ -144,20 +144,35 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_REM_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_SFMT_LF_ADD_S },
+ { OR1K_INSN_LF_REM_D32, OR1K32BF_INSN_LF_REM_D32, OR1K32BF_SFMT_LF_ADD_D32 },
{ OR1K_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_S },
+ { OR1K_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_SFMT_LF_ITOF_D32 },
{ OR1K_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_SFMT_LF_FTOI_S },
+ { OR1K_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_SFMT_LF_FTOI_D32 },
{ OR1K_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_EQ_D32, OR1K32BF_INSN_LF_EQ_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_NE_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_NE_D32, OR1K32BF_INSN_LF_NE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_GE_D32, OR1K32BF_INSN_LF_GE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_GT_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_GT_D32, OR1K32BF_INSN_LF_GT_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_LT_D32, OR1K32BF_INSN_LF_LT_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
+ { OR1K_INSN_LF_LE_D32, OR1K32BF_INSN_LF_LE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
{ OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
+ { OR1K_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_SFMT_LF_MADD_D32 },
{ OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_LF_CUST1_D32, OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_SFMT_L_MSYNC },
};
static const struct insn_sem or1k32bf_insn_sem_invalid =
@@ -235,7 +250,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_WORD insn = base_insn;
{
- unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 2) & (1 << 4)) | ((insn >> 0) & (15 << 0)));
+ unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 0) & (31 << 0)));
switch (val)
{
case 0 : /* fall through */
@@ -1083,22 +1098,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1484 : /* fall through */
case 1485 : /* fall through */
case 1486 : /* fall through */
- case 1487 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
- { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
- { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
+ case 1487 : /* fall through */
case 1488 : /* fall through */
case 1489 : /* fall through */
case 1490 : /* fall through */
@@ -1116,14 +1116,22 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1502 : /* fall through */
case 1503 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
+ { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1 :
if ((entire_insn & 0xfc00ffc0) == 0xb8000040)
{ itype = OR1K32BF_INSN_L_SRLI; goto extract_sfmt_l_slli; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
+ case 2 :
+ if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
+ { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
if ((entire_insn & 0xfc00ffc0) == 0xb80000c0)
{ itype = OR1K32BF_INSN_L_RORI; goto extract_sfmt_l_slli; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -1258,9 +1266,21 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_MSBU; goto extract_sfmt_l_macu; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1600 :
- if ((entire_insn & 0xfc0007ff) == 0xc8000000)
- { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ {
+ unsigned int val = (((insn >> 5) & (7 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000000)
+ { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 7 :
+ if ((entire_insn & 0xffe007ff) == 0xc80000e0)
+ { itype = OR1K32BF_INSN_LF_CUST1_D32; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 1601 :
if ((entire_insn & 0xfc0007ff) == 0xc8000001)
{ itype = OR1K32BF_INSN_LF_SUB_S; goto extract_sfmt_lf_add_s; }
@@ -1314,8 +1334,72 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_LF_LE_S; goto extract_sfmt_lf_eq_s; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1616 :
- if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
+ {
+ unsigned int val = (((insn >> 6) & (3 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000010)
+ { itype = OR1K32BF_INSN_LF_ADD_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xffe007ff) == 0xc80000d0)
+ { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1617 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000011)
+ { itype = OR1K32BF_INSN_LF_SUB_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1618 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000012)
+ { itype = OR1K32BF_INSN_LF_MUL_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1619 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000013)
+ { itype = OR1K32BF_INSN_LF_DIV_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1620 :
+ if ((entire_insn & 0xfc00ffff) == 0xc8000014)
+ { itype = OR1K32BF_INSN_LF_ITOF_D32; goto extract_sfmt_lf_itof_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1621 :
+ if ((entire_insn & 0xfc00ffff) == 0xc8000015)
+ { itype = OR1K32BF_INSN_LF_FTOI_D32; goto extract_sfmt_lf_ftoi_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1622 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000016)
+ { itype = OR1K32BF_INSN_LF_REM_D32; goto extract_sfmt_lf_add_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1623 :
+ if ((entire_insn & 0xfc0007ff) == 0xc8000017)
+ { itype = OR1K32BF_INSN_LF_MADD_D32; goto extract_sfmt_lf_madd_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1624 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000018)
+ { itype = OR1K32BF_INSN_LF_EQ_D32; goto extract_sfmt_lf_eq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1625 :
+ if ((entire_insn & 0xffe007ff) == 0xc8000019)
+ { itype = OR1K32BF_INSN_LF_NE_D32; goto extract_sfmt_lf_eq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1626 :
+ if ((entire_insn & 0xffe007ff) == 0xc800001a)
+ { itype = OR1K32BF_INSN_LF_GT_D32; goto extract_sfmt_lf_eq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1627 :
+ if ((entire_insn & 0xffe007ff) == 0xc800001b)
+ { itype = OR1K32BF_INSN_LF_GE_D32; goto extract_sfmt_lf_eq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1628 :
+ if ((entire_insn & 0xffe007ff) == 0xc800001c)
+ { itype = OR1K32BF_INSN_LF_LT_D32; goto extract_sfmt_lf_eq_d32; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1629 :
+ if ((entire_insn & 0xffe007ff) == 0xc800001d)
+ { itype = OR1K32BF_INSN_LF_LE_D32; goto extract_sfmt_lf_eq_d32; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1632 : /* fall through */
case 1633 : /* fall through */
@@ -1479,7 +1563,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1800 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
@@ -1487,9 +1571,17 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_SLL; goto extract_sfmt_l_sll; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
+ if ((entire_insn & 0xfc0007ff) == 0xe0000048)
+ { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
if ((entire_insn & 0xfc0007ff) == 0xe0000088)
{ itype = OR1K32BF_INSN_L_SRA; goto extract_sfmt_l_sll; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
+ { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@@ -1507,7 +1599,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1804 :
{
- unsigned int val = (((insn >> 7) & (1 << 0)));
+ unsigned int val = (((insn >> 6) & (3 << 0)));
switch (val)
{
case 0 :
@@ -1515,22 +1607,34 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{ itype = OR1K32BF_INSN_L_EXTHS; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004c)
+ { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
if ((entire_insn & 0xfc00ffff) == 0xe000008c)
{ itype = OR1K32BF_INSN_L_EXTHZ; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 3 :
+ if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
+ { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 1805 :
{
- unsigned int val = (((insn >> 8) & (3 << 0)));
+ unsigned int val = (((insn >> 7) & (3 << 1)) | ((insn >> 6) & (1 << 0)));
switch (val)
{
case 0 :
if ((entire_insn & 0xfc00ffff) == 0xe000000d)
{ itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 3 :
+ case 1 :
+ if ((entire_insn & 0xfc00ffff) == 0xe000004d)
+ { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
if ((entire_insn & 0xffe007ff) == 0xe000030d)
{ itype = OR1K32BF_INSN_L_MULDU; goto extract_sfmt_l_muld; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
@@ -1557,42 +1661,6 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
- case 1816 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc0007ff) == 0xe0000048)
- { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
- { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
- case 1820 :
- {
- unsigned int val = (((insn >> 7) & (1 << 0)));
- switch (val)
- {
- case 0 :
- if ((entire_insn & 0xfc00ffff) == 0xe000004c)
- { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 1 :
- if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
- { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- }
- }
- case 1821 :
- if ((entire_insn & 0xfc00ffff) == 0xe000004d)
- { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
- itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1824 :
{
unsigned int val = (((insn >> 21) & (15 << 0)));
@@ -2682,6 +2750,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_add_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2702,6 +2793,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_itof_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_d32", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2722,6 +2833,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_ftoi_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ UINT f_r1;
+ UINT f_r2;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_d32", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2742,6 +2873,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r3) = f_r3;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_eq_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
+
#undef FLD
return idesc;
}
@@ -2765,6 +2916,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lf_madd_d32:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ UINT f_r1;
+ UINT f_r2;
+ UINT f_r3;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
#undef FLD
return idesc;
}
diff --git a/sim/or1k/decode.h b/sim/or1k/decode.h
index 8650bdfa0e..76c2c667ac 100644
--- a/sim/or1k/decode.h
+++ b/sim/or1k/decode.h
@@ -60,10 +60,14 @@ typedef enum or1k32bf_insn_type {
, OR1K32BF_INSN_L_MACU, OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MSBU, OR1K32BF_INSN_L_CUST1
, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5
, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S
- , OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S
- , OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S
- , OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S
- , OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX
+ , OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_MUL_S
+ , OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_REM_S
+ , OR1K32BF_INSN_LF_REM_D32, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_FTOI_S
+ , OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_D32, OR1K32BF_INSN_LF_NE_S
+ , OR1K32BF_INSN_LF_NE_D32, OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_D32, OR1K32BF_INSN_LF_GT_S
+ , OR1K32BF_INSN_LF_GT_D32, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_D32, OR1K32BF_INSN_LF_LE_S
+ , OR1K32BF_INSN_LF_LE_D32, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_CUST1_S
+ , OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_INSN__MAX
} OR1K32BF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family or1k32bf. */
@@ -80,7 +84,9 @@ typedef enum or1k32bf_sfmt_type {
, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_MULI
, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_MACU, OR1K32BF_SFMT_LF_ADD_S
- , OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_LF_ADD_D32, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_D32, OR1K32BF_SFMT_LF_FTOI_S
+ , OR1K32BF_SFMT_LF_FTOI_D32, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_D32, OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_LF_MADD_D32
} OR1K32BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/model.c b/sim/or1k/model.c
index 461ba4bb00..44da5b9019 100644
--- a/sim/or1k/model.c
+++ b/sim/or1k/model.c
@@ -1602,6 +1602,22 @@ model_or1200_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1618,6 +1634,22 @@ model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1634,6 +1666,22 @@ model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1650,6 +1698,22 @@ model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1666,6 +1730,22 @@ model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1682,6 +1762,22 @@ model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1698,6 +1794,22 @@ model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1714,6 +1826,22 @@ model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_eq_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1730,6 +1858,22 @@ model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_ne_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1746,6 +1890,22 @@ model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_ge_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1762,6 +1922,22 @@ model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_gt_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1778,6 +1954,22 @@ model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_lt_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1794,6 +1986,22 @@ model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_le_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1810,6 +2018,22 @@ model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -1826,6 +2050,22 @@ model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3394,6 +3634,22 @@ model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3410,6 +3666,22 @@ model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3426,6 +3698,22 @@ model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3442,6 +3730,22 @@ model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3458,6 +3762,22 @@ model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3474,6 +3794,22 @@ model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3490,6 +3826,22 @@ model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3506,6 +3858,22 @@ model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_eq_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3522,6 +3890,22 @@ model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_ne_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3538,6 +3922,22 @@ model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_ge_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3554,6 +3954,22 @@ model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_gt_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3570,6 +3986,22 @@ model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_lt_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3586,6 +4018,22 @@ model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_le_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3602,6 +4050,22 @@ model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
static int
model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
{
@@ -3618,6 +4082,22 @@ model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
+static int
+model_or1200nd_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
/* We assume UNIT_NONE == 0 because the tables don't always terminate
entries with it. */
@@ -3728,20 +4208,35 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_CUST7, model_or1200_l_cust7, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CUST8, model_or1200_l_cust8, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ADD_S, model_or1200_lf_add_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_D32, model_or1200_lf_add_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_SUB_S, model_or1200_lf_sub_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_D32, model_or1200_lf_sub_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MUL_S, model_or1200_lf_mul_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_D32, model_or1200_lf_mul_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_DIV_S, model_or1200_lf_div_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_D32, model_or1200_lf_div_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_REM_S, model_or1200_lf_rem_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_D32, model_or1200_lf_rem_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ITOF_S, model_or1200_lf_itof_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_D32, model_or1200_lf_itof_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_FTOI_S, model_or1200_lf_ftoi_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_D32, model_or1200_lf_ftoi_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_EQ_S, model_or1200_lf_eq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_EQ_D32, model_or1200_lf_eq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_NE_S, model_or1200_lf_ne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_NE_D32, model_or1200_lf_ne_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_GE_S, model_or1200_lf_ge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GE_D32, model_or1200_lf_ge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_GT_S, model_or1200_lf_gt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GT_D32, model_or1200_lf_gt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_LT_S, model_or1200_lf_lt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LT_D32, model_or1200_lf_lt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_LE_S, model_or1200_lf_le_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LE_D32, model_or1200_lf_le_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MADD_S, model_or1200_lf_madd_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_D32, model_or1200_lf_madd_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_CUST1_S, model_or1200_lf_cust1_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_D32, model_or1200_lf_cust1_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
};
/* Model timing data for `or1200nd'. */
@@ -3851,20 +4346,35 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_CUST7, model_or1200nd_l_cust7, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CUST8, model_or1200nd_l_cust8, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ADD_S, model_or1200nd_lf_add_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ADD_D32, model_or1200nd_lf_add_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_SUB_S, model_or1200nd_lf_sub_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_SUB_D32, model_or1200nd_lf_sub_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MUL_S, model_or1200nd_lf_mul_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MUL_D32, model_or1200nd_lf_mul_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_DIV_S, model_or1200nd_lf_div_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_DIV_D32, model_or1200nd_lf_div_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_REM_S, model_or1200nd_lf_rem_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_REM_D32, model_or1200nd_lf_rem_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_ITOF_S, model_or1200nd_lf_itof_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_ITOF_D32, model_or1200nd_lf_itof_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_FTOI_S, model_or1200nd_lf_ftoi_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_FTOI_D32, model_or1200nd_lf_ftoi_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_EQ_S, model_or1200nd_lf_eq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_EQ_D32, model_or1200nd_lf_eq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_NE_S, model_or1200nd_lf_ne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_NE_D32, model_or1200nd_lf_ne_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_GE_S, model_or1200nd_lf_ge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GE_D32, model_or1200nd_lf_ge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_GT_S, model_or1200nd_lf_gt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_GT_D32, model_or1200nd_lf_gt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_LT_S, model_or1200nd_lf_lt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LT_D32, model_or1200nd_lf_lt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_LE_S, model_or1200nd_lf_le_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_LE_D32, model_or1200nd_lf_le_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_MADD_S, model_or1200nd_lf_madd_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_MADD_D32, model_or1200nd_lf_madd_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_LF_CUST1_S, model_or1200nd_lf_cust1_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_LF_CUST1_D32, model_or1200nd_lf_cust1_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
};
#endif /* WITH_PROFILE_MODEL_P */
diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
index e250e45c60..203f619253 100644
--- a/sim/or1k/sem-switch.c
+++ b/sim/or1k/sem-switch.c
@@ -136,20 +136,35 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
{ OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
{ OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
+ { OR1K32BF_INSN_LF_ADD_D32, && case_sem_INSN_LF_ADD_D32 },
{ OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
+ { OR1K32BF_INSN_LF_SUB_D32, && case_sem_INSN_LF_SUB_D32 },
{ OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
+ { OR1K32BF_INSN_LF_MUL_D32, && case_sem_INSN_LF_MUL_D32 },
{ OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
+ { OR1K32BF_INSN_LF_DIV_D32, && case_sem_INSN_LF_DIV_D32 },
{ OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
+ { OR1K32BF_INSN_LF_REM_D32, && case_sem_INSN_LF_REM_D32 },
{ OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
+ { OR1K32BF_INSN_LF_ITOF_D32, && case_sem_INSN_LF_ITOF_D32 },
{ OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
+ { OR1K32BF_INSN_LF_FTOI_D32, && case_sem_INSN_LF_FTOI_D32 },
{ OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S },
+ { OR1K32BF_INSN_LF_EQ_D32, && case_sem_INSN_LF_EQ_D32 },
{ OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S },
+ { OR1K32BF_INSN_LF_NE_D32, && case_sem_INSN_LF_NE_D32 },
{ OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S },
+ { OR1K32BF_INSN_LF_GE_D32, && case_sem_INSN_LF_GE_D32 },
{ OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S },
+ { OR1K32BF_INSN_LF_GT_D32, && case_sem_INSN_LF_GT_D32 },
{ OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S },
+ { OR1K32BF_INSN_LF_LT_D32, && case_sem_INSN_LF_LT_D32 },
{ OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S },
+ { OR1K32BF_INSN_LF_LE_D32, && case_sem_INSN_LF_LE_D32 },
{ OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
+ { OR1K32BF_INSN_LF_MADD_D32, && case_sem_INSN_LF_MADD_D32 },
{ OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
+ { OR1K32BF_INSN_LF_CUST1_D32, && case_sem_INSN_LF_CUST1_D32 },
{ 0, 0 }
};
int i;
@@ -2646,6 +2661,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ADD_D32) : /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2665,6 +2699,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_SUB_D32) : /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2684,6 +2737,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MUL_D32) : /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2703,6 +2775,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_DIV_D32) : /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2722,6 +2813,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_REM_D32) : /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2741,6 +2851,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_ITOF_D32) : /* lf.itof.d $rDD32F,$rADI */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_r2)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2760,6 +2889,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_FTOI_D32) : /* lf.ftoi.d $rDDI,$rAD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_r2)));
+ SET_H_I64R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2779,6 +2927,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_EQ_D32) : /* lf.sfeq.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2798,6 +2965,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_NE_D32) : /* lf.sfne.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2817,6 +3003,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_GE_D32) : /* lf.sfge.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2836,6 +3041,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_GT_D32) : /* lf.sfgt.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2855,6 +3079,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_LT_D32) : /* lf.sflt.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2874,6 +3117,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_LE_D32) : /* lf.sfle.d $rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2893,6 +3155,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_MADD_D32) : /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3))), GET_H_FD32R (FLD (f_r1)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
#undef FLD
}
NEXT (vpc);
@@ -2908,6 +3189,21 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
((void) 0); /*nop*/
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LF_CUST1_D32) : /* lf.cust1.d */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
#undef FLD
}
NEXT (vpc);
diff --git a/sim/or1k/sem.c b/sim/or1k/sem.c
index 15ef24c079..7cfa998dbd 100644
--- a/sim/or1k/sem.c
+++ b/sim/or1k/sem.c
@@ -2694,6 +2694,27 @@ SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-add-d32: lf.add.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_add_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-sub-s: lf.sub.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2715,6 +2736,27 @@ SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-sub-d32: lf.sub.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_sub_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-mul-s: lf.mul.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2736,6 +2778,27 @@ SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-mul-d32: lf.mul.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_mul_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-div-s: lf.div.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2757,6 +2820,27 @@ SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-div-d32: lf.div.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_div_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-rem-s: lf.rem.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2778,6 +2862,27 @@ SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-rem-d32: lf.rem.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_rem_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-itof-s: lf.itof.s $rDSF,$rA */
static SEM_PC
@@ -2799,6 +2904,27 @@ SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-itof-d32: lf.itof.d $rDD32F,$rADI */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_itof_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_r2)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-ftoi-s: lf.ftoi.s $rD,$rASF */
static SEM_PC
@@ -2820,6 +2946,27 @@ SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-ftoi-d32: lf.ftoi.d $rDDI,$rAD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ftoi_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_slli.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_r2)));
+ SET_H_I64R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-eq-s: lf.sfeq.s $rASF,$rBSF */
static SEM_PC
@@ -2841,6 +2988,27 @@ SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-eq-d32: lf.sfeq.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_eq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-ne-s: lf.sfne.s $rASF,$rBSF */
static SEM_PC
@@ -2862,6 +3030,27 @@ SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-ne-d32: lf.sfne.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ne_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-ge-s: lf.sfge.s $rASF,$rBSF */
static SEM_PC
@@ -2883,6 +3072,27 @@ SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-ge-d32: lf.sfge.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_ge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-gt-s: lf.sfgt.s $rASF,$rBSF */
static SEM_PC
@@ -2904,6 +3114,27 @@ SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-gt-d32: lf.sfgt.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_gt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-lt-s: lf.sflt.s $rASF,$rBSF */
static SEM_PC
@@ -2925,6 +3156,27 @@ SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-lt-d32: lf.sflt.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_lt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-le-s: lf.sfle.s $rASF,$rBSF */
static SEM_PC
@@ -2946,6 +3198,27 @@ SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-le-d32: lf.sfle.d $rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_le_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-madd-s: lf.madd.s $rDSF,$rASF,$rBSF */
static SEM_PC
@@ -2967,6 +3240,27 @@ SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-madd-d32: lf.madd.d $rDD32F,$rAD32F,$rBD32F */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_madd_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sll.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3))), GET_H_FD32R (FLD (f_r1)));
+ SET_H_FD32R (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
/* lf-cust1-s: lf.cust1.s $rASF,$rBSF */
static SEM_PC
@@ -2984,6 +3278,23 @@ SEM_FN_NAME (or1k32bf,lf_cust1_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
+/* lf-cust1-d32: lf.cust1.d */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,lf_cust1_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
/* Table of all semantic fns. */
static const struct sem_fn_desc sem_fns[] = {
@@ -3091,20 +3402,35 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_CUST7, SEM_FN_NAME (or1k32bf,l_cust7) },
{ OR1K32BF_INSN_L_CUST8, SEM_FN_NAME (or1k32bf,l_cust8) },
{ OR1K32BF_INSN_LF_ADD_S, SEM_FN_NAME (or1k32bf,lf_add_s) },
+ { OR1K32BF_INSN_LF_ADD_D32, SEM_FN_NAME (or1k32bf,lf_add_d32) },
{ OR1K32BF_INSN_LF_SUB_S, SEM_FN_NAME (or1k32bf,lf_sub_s) },
+ { OR1K32BF_INSN_LF_SUB_D32, SEM_FN_NAME (or1k32bf,lf_sub_d32) },
{ OR1K32BF_INSN_LF_MUL_S, SEM_FN_NAME (or1k32bf,lf_mul_s) },
+ { OR1K32BF_INSN_LF_MUL_D32, SEM_FN_NAME (or1k32bf,lf_mul_d32) },
{ OR1K32BF_INSN_LF_DIV_S, SEM_FN_NAME (or1k32bf,lf_div_s) },
+ { OR1K32BF_INSN_LF_DIV_D32, SEM_FN_NAME (or1k32bf,lf_div_d32) },
{ OR1K32BF_INSN_LF_REM_S, SEM_FN_NAME (or1k32bf,lf_rem_s) },
+ { OR1K32BF_INSN_LF_REM_D32, SEM_FN_NAME (or1k32bf,lf_rem_d32) },
{ OR1K32BF_INSN_LF_ITOF_S, SEM_FN_NAME (or1k32bf,lf_itof_s) },
+ { OR1K32BF_INSN_LF_ITOF_D32, SEM_FN_NAME (or1k32bf,lf_itof_d32) },
{ OR1K32BF_INSN_LF_FTOI_S, SEM_FN_NAME (or1k32bf,lf_ftoi_s) },
+ { OR1K32BF_INSN_LF_FTOI_D32, SEM_FN_NAME (or1k32bf,lf_ftoi_d32) },
{ OR1K32BF_INSN_LF_EQ_S, SEM_FN_NAME (or1k32bf,lf_eq_s) },
+ { OR1K32BF_INSN_LF_EQ_D32, SEM_FN_NAME (or1k32bf,lf_eq_d32) },
{ OR1K32BF_INSN_LF_NE_S, SEM_FN_NAME (or1k32bf,lf_ne_s) },
+ { OR1K32BF_INSN_LF_NE_D32, SEM_FN_NAME (or1k32bf,lf_ne_d32) },
{ OR1K32BF_INSN_LF_GE_S, SEM_FN_NAME (or1k32bf,lf_ge_s) },
+ { OR1K32BF_INSN_LF_GE_D32, SEM_FN_NAME (or1k32bf,lf_ge_d32) },
{ OR1K32BF_INSN_LF_GT_S, SEM_FN_NAME (or1k32bf,lf_gt_s) },
+ { OR1K32BF_INSN_LF_GT_D32, SEM_FN_NAME (or1k32bf,lf_gt_d32) },
{ OR1K32BF_INSN_LF_LT_S, SEM_FN_NAME (or1k32bf,lf_lt_s) },
+ { OR1K32BF_INSN_LF_LT_D32, SEM_FN_NAME (or1k32bf,lf_lt_d32) },
{ OR1K32BF_INSN_LF_LE_S, SEM_FN_NAME (or1k32bf,lf_le_s) },
+ { OR1K32BF_INSN_LF_LE_D32, SEM_FN_NAME (or1k32bf,lf_le_d32) },
{ OR1K32BF_INSN_LF_MADD_S, SEM_FN_NAME (or1k32bf,lf_madd_s) },
+ { OR1K32BF_INSN_LF_MADD_D32, SEM_FN_NAME (or1k32bf,lf_madd_d32) },
{ OR1K32BF_INSN_LF_CUST1_S, SEM_FN_NAME (or1k32bf,lf_cust1_s) },
+ { OR1K32BF_INSN_LF_CUST1_D32, SEM_FN_NAME (or1k32bf,lf_cust1_d32) },
{ 0, 0 }
};
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
` (2 preceding siblings ...)
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim " Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-13 21:59 ` Andrew Burgess
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets Stafford Horne
5 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
Up until now these have not been used in any CGEN targets, add them as
they are now used by OpenRISC.
sim/common/ChangeLog:
* cgen-accfp.c (floatdidf, fixdfdi): New functions.
(cgen_init_accurate_fpu): Add floatdidf and fixdfdi.
---
sim/common/cgen-accfp.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index 5d600c6e41..51f5a29fe2 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -349,6 +349,17 @@ floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
return res;
}
+static DF
+floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
+{
+ sim_fpu ans;
+ unsigned64 res;
+
+ sim_fpu_i64to (&ans, x, sim_fpu_round_near);
+ sim_fpu_to64 (&res, &ans);
+ return res;
+}
+
static SF
ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
{
@@ -382,6 +393,17 @@ fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
return res;
}
+static DI
+fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
+{
+ sim_fpu op1;
+ unsigned64 res;
+
+ sim_fpu_64to (&op1, x);
+ sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
+ return res;
+}
+
static USI
ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
{
@@ -739,8 +761,10 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
o->ftruncdfsf = ftruncdfsf;
o->floatsisf = floatsisf;
o->floatsidf = floatsidf;
+ o->floatdidf = floatdidf;
o->ufloatsisf = ufloatsisf;
o->fixsfsi = fixsfsi;
o->fixdfsi = fixdfsi;
+ o->fixdfdi = fixdfdi;
o->ufixsfsi = ufixsfsi;
}
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
` (3 preceding siblings ...)
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-13 21:36 ` Andrew Burgess
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets Stafford Horne
5 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
This is a very basic test but it ensure the machine is wired up
correctly and that the assembler works.
sim/testsuite/sim/or1k/ChangeLog:
* fpu64a32.S: New file.
---
sim/testsuite/sim/or1k/fpu64a32.S | 172 ++++++++++++++++++++++++++++++
1 file changed, 172 insertions(+)
create mode 100644 sim/testsuite/sim/or1k/fpu64a32.S
diff --git a/sim/testsuite/sim/or1k/fpu64a32.S b/sim/testsuite/sim/or1k/fpu64a32.S
new file mode 100644
index 0000000000..6c40170854
--- /dev/null
+++ b/sim/testsuite/sim/or1k/fpu64a32.S
@@ -0,0 +1,172 @@
+/* Tests some basic fpu instructions.
+
+ Copyright (C) 2017-2019 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+# mach: or1k
+# output: report(0x400921f9);\n
+# output: report(0xf01b866e);\n
+# output: report(0x4005bf09);\n
+# output: report(0x95aaf790);\n
+# output: report(0x00000000);\n
+# output: report(0x00001234);\n
+# output: \n
+# output: report(0x40b23400);\n
+# output: report(0x00000000);\n
+# output: report(0x40b23400);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40177081);\n
+# output: report(0xc2e33eff);\n
+# output: report(0x400921f9);\n
+# output: report(0xf01b866e);\n
+# output: \n
+# output: report(0x40211456);\n
+# output: report(0x587dfabf);\n
+# output: report(0x400921f9);\n
+# output: report(0xf01b866d);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: \n
+# output: WARNING: ignoring fpu error caught in fast mode.\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .exception_vectors
+
+ /* Floating point exception. */
+ .org 0xd00
+
+ /* The handling is a bit dubious at present. We just patch the
+ instruction with l.nop and restart. This will go wrong in branch
+ delay slots. But we don't have those in this test. */
+ l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
+ PUSH r2
+ PUSH r3
+ /* Save the address of the instruction that caused the problem. */
+ MOVE_FROM_SPR r2, SPR_EPCR_BASE
+ LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
+ l.sw -4(r2), r3
+ POP r3
+ POP r2
+ l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
+ l.rfe
+
+ .section .data
+ .align 4
+ .type pi, @object
+ .size pi, 8
+anchor:
+pi:
+ .double 3.14159
+
+ .type e, @object
+ .size e, 8
+e:
+ .double 2.71828
+
+ .type large, @object
+ .size large, 8
+large:
+ .long 0
+ .long 0x1234
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ /* Test lf.itof.d int to double conversion. Setting up:
+ * r11 pointer to data
+ * r12,r13 pi as double
+ * r14,r15 e as double
+ * r16,r17 a long long
+ */
+ l.ori r11, r0, ha(anchor)
+ l.addi r11, r11, lo(anchor)
+ l.lwz r12, 0(r11)
+ l.lwz r13, 4(r11)
+
+ l.lwz r14, 8(r11)
+ l.lwz r15, 12(r11)
+
+ l.lwz r16, 16(r11)
+ l.lwz r18, 20(r11)
+
+ /* Output to ensure we loaded it correctly. */
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ REPORT_REG_TO_CONSOLE r14
+ REPORT_REG_TO_CONSOLE r15
+
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Convert the big long to a double. */
+ lf.itof.d r16, r16
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+
+ /* Convert the double back to a long, it should match before. */
+ lf.ftoi.d r16, r16
+ lf.itof.d r16, r16
+
+ REPORT_REG_TO_CONSOLE r16
+ REPORT_REG_TO_CONSOLE r18
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Add and subtract some double values. */
+ lf.add.d r12, r12, r14
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ lf.sub.d r12, r12, r14
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Multiply and divide double values. */
+ lf.mul.d r12, r12, r14
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+
+ lf.div.d r12, r12, r14
+ REPORT_REG_TO_CONSOLE r12
+ REPORT_REG_TO_CONSOLE r13
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Test lf.sfge.s set flag if r6 >= r10. */
+ lf.sfge.d r12, r14
+ MOVE_FROM_SPR r2, SPR_SR
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
+ PRINT_NEWLINE_TO_CONSOLE
+
+ /* Test raising an exception by dividing by 0. */
+ MOVE_FROM_SPR r2, SPR_FPCSR
+ l.ori r2, r2, 0x1
+ MOVE_TO_SPR SPR_FPCSR, r2
+div0: lf.div.d r2, r12, r0
+ REPORT_EXCEPTION div0
+ PRINT_NEWLINE_TO_CONSOLE
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
` (4 preceding siblings ...)
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations Stafford Horne
@ 2019-04-09 21:39 ` Stafford Horne
2019-04-11 22:27 ` Andrew Burgess
5 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-09 21:39 UTC (permalink / raw)
To: openrisc
Currently only the OpenRISC sim uses this JOINSIDF() function to compose a
double float from 2 registers. The old code doesn't seem to work as the
work order gets swapped when running on a x86_64 host. This change
fixes that, but I am not sure if its the best thing to do.
On mips they do similar reg pair floating point operations composing
doubles from 2 32-bit registers in sim/mips/cp1.c value_fpr().
sim/common/ChangeLog:
* cgen-ops.h (JOINSIDF): Fix big endian check.
---
sim/common/cgen-ops.h | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
index 841552066f..d718394723 100644
--- a/sim/common/cgen-ops.h
+++ b/sim/common/cgen-ops.h
@@ -431,12 +431,8 @@ JOINSIDI (SI x0, SI x1)
SEMOPS_INLINE DF
JOINSIDF (SI x0, SI x1)
{
- union { SI in[2]; DF out; } x;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- x.in[0] = x0, x.in[1] = x1;
- else
- x.in[1] = x0, x.in[0] = x1;
- return x.out;
+ /* Making doubles is the same as making long longs. */
+ return MAKEDI (x0, x1);
}
SEMOPS_INLINE XF
--
2.19.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes for orfp64a32 spec
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes " Stafford Horne
@ 2019-04-11 8:45 ` Nick Clifton
0 siblings, 0 replies; 15+ messages in thread
From: Nick Clifton @ 2019-04-11 8:45 UTC (permalink / raw)
To: openrisc
Hi Stafford,
> opcodes/ChangeLog:
>
> * or1k-asm.c: Regenerated.
> * or1k-desc.c: Regenerated.
> * or1k-desc.h: Regenerated.
> * or1k-dis.c: Regenerated.
> * or1k-ibld.c: Regenerated.
> * or1k-opc.c: Regenerated.
> * or1k-opc.h: Regenerated.
> * or1k-opinst.c: Regenerated.
This part of your patch series is approved. Please commit whenever you are ready.
Cheers
Nick
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets Stafford Horne
@ 2019-04-11 22:27 ` Andrew Burgess
2019-04-12 20:21 ` Stafford Horne
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Burgess @ 2019-04-11 22:27 UTC (permalink / raw)
To: openrisc
* Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:25 +0900]:
> Currently only the OpenRISC sim uses this JOINSIDF() function to compose a
> double float from 2 registers. The old code doesn't seem to work as the
> work order gets swapped when running on a x86_64 host. This change
> fixes that, but I am not sure if its the best thing to do.
>
> On mips they do similar reg pair floating point operations composing
> doubles from 2 32-bit registers in sim/mips/cp1.c value_fpr().
>
> sim/common/ChangeLog:
>
> * cgen-ops.h (JOINSIDF): Fix big endian check.
> ---
> sim/common/cgen-ops.h | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
> index 841552066f..d718394723 100644
> --- a/sim/common/cgen-ops.h
> +++ b/sim/common/cgen-ops.h
> @@ -431,12 +431,8 @@ JOINSIDI (SI x0, SI x1)
> SEMOPS_INLINE DF
> JOINSIDF (SI x0, SI x1)
> {
> - union { SI in[2]; DF out; } x;
> - if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
I think this is the problem with the existing code, we're using memory
on the HOST to perform packing / unpacking, and so its the byte
ordering of the HOST that we care about here, not the target.
If I change the above line to instead be:
if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
then everything works fine.
On inspection I believe all of the uses of CURRENT_TARGET_BYTE_ORDER
in this file should be similarly replaced.
I've attached a patch for this change. If you agree I'll go ahead and
push it.
Thanks,
Andrew
--
[PATCH] sim: Use host not target byte order for merging and splitting values
When using writes to memory through a struct to merge and extract
multi-word value, it is the endianness of the host, not the target
that affects which order the component words need to be written into
the structure.
Of the 5 functions adjusted here 4 of them are unused. The 5th,
JOINSIDF will soon be used by the or1k target.
For or1k, simulated on x86-64, this change fixes this function so that
the correct bytes are now returned.
sim/common/ChangeLog:
* cgen-ops.h (SUBWORDXFSI): Compare HOST_BYTE_ORDER not
CURRENT_TARGET_BYTE_ORDER.
(SUBWORDTFSI): Likewise.
(JOINSIDF): Likewise.
(JOINSIXF): Likewise.
(JOINSITF): Likewise.
---
sim/common/ChangeLog | 9 +++++++++
sim/common/cgen-ops.h | 10 +++++-----
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
index 841552066f4..6fecb862a8a 100644
--- a/sim/common/cgen-ops.h
+++ b/sim/common/cgen-ops.h
@@ -404,7 +404,7 @@ SUBWORDXFSI (XF in, int word)
/* Note: typedef struct { SI parts[3]; } XF; */
union { XF in; SI out[3]; } x;
x.in = in;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
return x.out[word];
else
return x.out[2 - word];
@@ -416,7 +416,7 @@ SUBWORDTFSI (TF in, int word)
/* Note: typedef struct { SI parts[4]; } TF; */
union { TF in; SI out[4]; } x;
x.in = in;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
return x.out[word];
else
return x.out[3 - word];
@@ -432,7 +432,7 @@ SEMOPS_INLINE DF
JOINSIDF (SI x0, SI x1)
{
union { SI in[2]; DF out; } x;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
x.in[0] = x0, x.in[1] = x1;
else
x.in[1] = x0, x.in[0] = x1;
@@ -443,7 +443,7 @@ SEMOPS_INLINE XF
JOINSIXF (SI x0, SI x1, SI x2)
{
union { SI in[3]; XF out; } x;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
x.in[0] = x0, x.in[1] = x1, x.in[2] = x2;
else
x.in[2] = x0, x.in[1] = x1, x.in[0] = x2;
@@ -454,7 +454,7 @@ SEMOPS_INLINE TF
JOINSITF (SI x0, SI x1, SI x2, SI x3)
{
union { SI in[4]; TF out; } x;
- if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
x.in[0] = x0, x.in[1] = x1, x.in[2] = x2, x.in[3] = x3;
else
x.in[3] = x0, x.in[2] = x1, x.in[1] = x2, x.in[0] = x3;
--
2.14.5
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets
2019-04-11 22:27 ` Andrew Burgess
@ 2019-04-12 20:21 ` Stafford Horne
2019-04-13 21:30 ` Andrew Burgess
0 siblings, 1 reply; 15+ messages in thread
From: Stafford Horne @ 2019-04-12 20:21 UTC (permalink / raw)
To: openrisc
Hi Andrew,
On Thu, Apr 11, 2019 at 11:27:49PM +0100, Andrew Burgess wrote:
> * Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:25 +0900]:
>
> > Currently only the OpenRISC sim uses this JOINSIDF() function to compose a
> > double float from 2 registers. The old code doesn't seem to work as the
> > work order gets swapped when running on a x86_64 host. This change
> > fixes that, but I am not sure if its the best thing to do.
> >
> > On mips they do similar reg pair floating point operations composing
> > doubles from 2 32-bit registers in sim/mips/cp1.c value_fpr().
> >
> > sim/common/ChangeLog:
> >
> > * cgen-ops.h (JOINSIDF): Fix big endian check.
> > ---
> > sim/common/cgen-ops.h | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
> > index 841552066f..d718394723 100644
> > --- a/sim/common/cgen-ops.h
> > +++ b/sim/common/cgen-ops.h
> > @@ -431,12 +431,8 @@ JOINSIDI (SI x0, SI x1)
> > SEMOPS_INLINE DF
> > JOINSIDF (SI x0, SI x1)
> > {
> > - union { SI in[2]; DF out; } x;
> > - if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
>
> I think this is the problem with the existing code, we're using memory
> on the HOST to perform packing / unpacking, and so its the byte
> ordering of the HOST that we care about here, not the target.
>
> If I change the above line to instead be:
>
> if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
>
> then everything works fine.
>
> On inspection I believe all of the uses of CURRENT_TARGET_BYTE_ORDER
> in this file should be similarly replaced.
>
> I've attached a patch for this change. If you agree I'll go ahead and
> push it.
I tested this with the or1k testsuite and it does seem to work fine, thank you.
Please go ahead.
I thought I had tried this fix as well, I guess not.
-Stafford
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets
2019-04-12 20:21 ` Stafford Horne
@ 2019-04-13 21:30 ` Andrew Burgess
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Burgess @ 2019-04-13 21:30 UTC (permalink / raw)
To: openrisc
* Stafford Horne <shorne@gmail.com> [2019-04-13 05:21:45 +0900]:
> Hi Andrew,
>
> On Thu, Apr 11, 2019 at 11:27:49PM +0100, Andrew Burgess wrote:
> > * Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:25 +0900]:
> >
> > > Currently only the OpenRISC sim uses this JOINSIDF() function to compose a
> > > double float from 2 registers. The old code doesn't seem to work as the
> > > work order gets swapped when running on a x86_64 host. This change
> > > fixes that, but I am not sure if its the best thing to do.
> > >
> > > On mips they do similar reg pair floating point operations composing
> > > doubles from 2 32-bit registers in sim/mips/cp1.c value_fpr().
> > >
> > > sim/common/ChangeLog:
> > >
> > > * cgen-ops.h (JOINSIDF): Fix big endian check.
> > > ---
> > > sim/common/cgen-ops.h | 8 ++------
> > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/sim/common/cgen-ops.h b/sim/common/cgen-ops.h
> > > index 841552066f..d718394723 100644
> > > --- a/sim/common/cgen-ops.h
> > > +++ b/sim/common/cgen-ops.h
> > > @@ -431,12 +431,8 @@ JOINSIDI (SI x0, SI x1)
> > > SEMOPS_INLINE DF
> > > JOINSIDF (SI x0, SI x1)
> > > {
> > > - union { SI in[2]; DF out; } x;
> > > - if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
> >
> > I think this is the problem with the existing code, we're using memory
> > on the HOST to perform packing / unpacking, and so its the byte
> > ordering of the HOST that we care about here, not the target.
> >
> > If I change the above line to instead be:
> >
> > if (HOST_BYTE_ORDER == BFD_ENDIAN_BIG)
> >
> > then everything works fine.
> >
> > On inspection I believe all of the uses of CURRENT_TARGET_BYTE_ORDER
> > in this file should be similarly replaced.
> >
> > I've attached a patch for this change. If you agree I'll go ahead and
> > push it.
>
> I tested this with the or1k testsuite and it does seem to work fine, thank you.
> Please go ahead.
>
> I thought I had tried this fix as well, I guess not.
Thanks for testing this.
I've pushed this patch now.
Andrew
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations Stafford Horne
@ 2019-04-13 21:36 ` Andrew Burgess
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Burgess @ 2019-04-13 21:36 UTC (permalink / raw)
To: openrisc
* Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:24 +0900]:
> This is a very basic test but it ensure the machine is wired up
> correctly and that the assembler works.
>
> sim/testsuite/sim/or1k/ChangeLog:
>
> * fpu64a32.S: New file.
This is fine.
Thanks,
Andrew
> ---
> sim/testsuite/sim/or1k/fpu64a32.S | 172 ++++++++++++++++++++++++++++++
> 1 file changed, 172 insertions(+)
> create mode 100644 sim/testsuite/sim/or1k/fpu64a32.S
>
> diff --git a/sim/testsuite/sim/or1k/fpu64a32.S b/sim/testsuite/sim/or1k/fpu64a32.S
> new file mode 100644
> index 0000000000..6c40170854
> --- /dev/null
> +++ b/sim/testsuite/sim/or1k/fpu64a32.S
> @@ -0,0 +1,172 @@
> +/* Tests some basic fpu instructions.
> +
> + Copyright (C) 2017-2019 Free Software Foundation, Inc.
> +
> + This program is free software; you can redistribute it and/or modify
> + it under the terms of the GNU General Public License as published by
> + the Free Software Foundation; either version 3 of the License, or
> + (at your option) any later version.
> +
> + This program is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + GNU General Public License for more details.
> +
> + You should have received a copy of the GNU General Public License
> + along with this program. If not, see <http://www.gnu.org/licenses/>. */
> +
> +# mach: or1k
> +# output: report(0x400921f9);\n
> +# output: report(0xf01b866e);\n
> +# output: report(0x4005bf09);\n
> +# output: report(0x95aaf790);\n
> +# output: report(0x00000000);\n
> +# output: report(0x00001234);\n
> +# output: \n
> +# output: report(0x40b23400);\n
> +# output: report(0x00000000);\n
> +# output: report(0x40b23400);\n
> +# output: report(0x00000000);\n
> +# output: \n
> +# output: report(0x40177081);\n
> +# output: report(0xc2e33eff);\n
> +# output: report(0x400921f9);\n
> +# output: report(0xf01b866e);\n
> +# output: \n
> +# output: report(0x40211456);\n
> +# output: report(0x587dfabf);\n
> +# output: report(0x400921f9);\n
> +# output: report(0xf01b866d);\n
> +# output: \n
> +# output: report(0x00000001);\n
> +# output: \n
> +# output: WARNING: ignoring fpu error caught in fast mode.\n
> +# output: report(0x00000000);\n
> +# output: \n
> +# output: exit(0)\n
> +
> +#include "or1k-asm-test-helpers.h"
> +
> + STANDARD_TEST_ENVIRONMENT
> +
> + .section .exception_vectors
> +
> + /* Floating point exception. */
> + .org 0xd00
> +
> + /* The handling is a bit dubious at present. We just patch the
> + instruction with l.nop and restart. This will go wrong in branch
> + delay slots. But we don't have those in this test. */
> + l.addi r1, r1, -EXCEPTION_STACK_SKIP_SIZE
> + PUSH r2
> + PUSH r3
> + /* Save the address of the instruction that caused the problem. */
> + MOVE_FROM_SPR r2, SPR_EPCR_BASE
> + LOAD_IMMEDIATE r3, 0x15000000 /* Opcode for l.nop */
> + l.sw -4(r2), r3
> + POP r3
> + POP r2
> + l.addi r1, r1, EXCEPTION_STACK_SKIP_SIZE
> + l.rfe
> +
> + .section .data
> + .align 4
> + .type pi, @object
> + .size pi, 8
> +anchor:
> +pi:
> + .double 3.14159
> +
> + .type e, @object
> + .size e, 8
> +e:
> + .double 2.71828
> +
> + .type large, @object
> + .size large, 8
> +large:
> + .long 0
> + .long 0x1234
> +
> + .section .text
> +start_tests:
> + PUSH LINK_REGISTER_R9
> +
> + /* Test lf.itof.d int to double conversion. Setting up:
> + * r11 pointer to data
> + * r12,r13 pi as double
> + * r14,r15 e as double
> + * r16,r17 a long long
> + */
> + l.ori r11, r0, ha(anchor)
> + l.addi r11, r11, lo(anchor)
> + l.lwz r12, 0(r11)
> + l.lwz r13, 4(r11)
> +
> + l.lwz r14, 8(r11)
> + l.lwz r15, 12(r11)
> +
> + l.lwz r16, 16(r11)
> + l.lwz r18, 20(r11)
> +
> + /* Output to ensure we loaded it correctly. */
> + REPORT_REG_TO_CONSOLE r12
> + REPORT_REG_TO_CONSOLE r13
> +
> + REPORT_REG_TO_CONSOLE r14
> + REPORT_REG_TO_CONSOLE r15
> +
> + REPORT_REG_TO_CONSOLE r16
> + REPORT_REG_TO_CONSOLE r18
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + /* Convert the big long to a double. */
> + lf.itof.d r16, r16
> + REPORT_REG_TO_CONSOLE r16
> + REPORT_REG_TO_CONSOLE r18
> +
> + /* Convert the double back to a long, it should match before. */
> + lf.ftoi.d r16, r16
> + lf.itof.d r16, r16
> +
> + REPORT_REG_TO_CONSOLE r16
> + REPORT_REG_TO_CONSOLE r18
> +
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + /* Add and subtract some double values. */
> + lf.add.d r12, r12, r14
> + REPORT_REG_TO_CONSOLE r12
> + REPORT_REG_TO_CONSOLE r13
> +
> + lf.sub.d r12, r12, r14
> + REPORT_REG_TO_CONSOLE r12
> + REPORT_REG_TO_CONSOLE r13
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + /* Multiply and divide double values. */
> + lf.mul.d r12, r12, r14
> + REPORT_REG_TO_CONSOLE r12
> + REPORT_REG_TO_CONSOLE r13
> +
> + lf.div.d r12, r12, r14
> + REPORT_REG_TO_CONSOLE r12
> + REPORT_REG_TO_CONSOLE r13
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + /* Test lf.sfge.s set flag if r6 >= r10. */
> + lf.sfge.d r12, r14
> + MOVE_FROM_SPR r2, SPR_SR
> + REPORT_BIT_TO_CONSOLE r2, SPR_SR_F
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + /* Test raising an exception by dividing by 0. */
> + MOVE_FROM_SPR r2, SPR_FPCSR
> + l.ori r2, r2, 0x1
> + MOVE_TO_SPR SPR_FPCSR, r2
> +div0: lf.div.d r2, r12, r0
> + REPORT_EXCEPTION div0
> + PRINT_NEWLINE_TO_CONSOLE
> +
> + POP LINK_REGISTER_R9
> + RETURN_TO_LINK_REGISTER_R9
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim for orfp64a32 spec
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim " Stafford Horne
@ 2019-04-13 21:40 ` Andrew Burgess
2019-04-14 6:44 ` Stafford Horne
0 siblings, 1 reply; 15+ messages in thread
From: Andrew Burgess @ 2019-04-13 21:40 UTC (permalink / raw)
To: openrisc
* Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:22 +0900]:
> sim/ChangeLog:
>
> * or1k/cpu.c: Regenerate.
> * or1k/cpu.h: Regenerate.
> * or1k/decode.c: Regenerate.
> * or1k/decode.h: Regenerate.
> * or1k/model.c: Regenerate.
> * or1k/sem-switch.c: Regenerate.
> * or1k/sem.c: Regenerate.
Kind-of hard to argue with that :)
This is fine with me,
Thanks,
Andrew
> ---
> sim/or1k/cpu.c | 60 +++--
> sim/or1k/cpu.h | 115 +++++++++-
> sim/or1k/decode.c | 302 +++++++++++++++++++------
> sim/or1k/decode.h | 16 +-
> sim/or1k/model.c | 510 ++++++++++++++++++++++++++++++++++++++++++
> sim/or1k/sem-switch.c | 296 ++++++++++++++++++++++++
> sim/or1k/sem.c | 326 +++++++++++++++++++++++++++
> 7 files changed, 1537 insertions(+), 88 deletions(-)
>
> diff --git a/sim/or1k/cpu.c b/sim/or1k/cpu.c
> index f93b51276e..a0ee763813 100644
> --- a/sim/or1k/cpu.c
> +++ b/sim/or1k/cpu.c
> @@ -44,6 +44,38 @@ or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
> SET_H_PC (newval);
> }
>
> +/* Get the value of h-spr. */
> +
> +USI
> +or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
> +{
> + return GET_H_SPR (regno);
> +}
> +
> +/* Set a value for h-spr. */
> +
> +void
> +or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
> +{
> + SET_H_SPR (regno, newval);
> +}
> +
> +/* Get the value of h-gpr. */
> +
> +USI
> +or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
> +{
> + return GET_H_GPR (regno);
> +}
> +
> +/* Set a value for h-gpr. */
> +
> +void
> +or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
> +{
> + SET_H_GPR (regno, newval);
> +}
> +
> /* Get the value of h-fsr. */
>
> SF
> @@ -60,36 +92,36 @@ or1k32bf_h_fsr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
> SET_H_FSR (regno, newval);
> }
>
> -/* Get the value of h-spr. */
> +/* Get the value of h-fd32r. */
>
> -USI
> -or1k32bf_h_spr_get (SIM_CPU *current_cpu, UINT regno)
> +DF
> +or1k32bf_h_fd32r_get (SIM_CPU *current_cpu, UINT regno)
> {
> - return GET_H_SPR (regno);
> + return GET_H_FD32R (regno);
> }
>
> -/* Set a value for h-spr. */
> +/* Set a value for h-fd32r. */
>
> void
> -or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
> +or1k32bf_h_fd32r_set (SIM_CPU *current_cpu, UINT regno, DF newval)
> {
> - SET_H_SPR (regno, newval);
> + SET_H_FD32R (regno, newval);
> }
>
> -/* Get the value of h-gpr. */
> +/* Get the value of h-i64r. */
>
> -USI
> -or1k32bf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
> +DI
> +or1k32bf_h_i64r_get (SIM_CPU *current_cpu, UINT regno)
> {
> - return GET_H_GPR (regno);
> + return GET_H_I64R (regno);
> }
>
> -/* Set a value for h-gpr. */
> +/* Set a value for h-i64r. */
>
> void
> -or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
> +or1k32bf_h_i64r_set (SIM_CPU *current_cpu, UINT regno, DI newval)
> {
> - SET_H_GPR (regno, newval);
> + SET_H_I64R (regno, newval);
> }
>
> /* Get the value of h-sys-vr. */
> diff --git a/sim/or1k/cpu.h b/sim/or1k/cpu.h
> index 199c93bce3..7a16c3f6ec 100644
> --- a/sim/or1k/cpu.h
> +++ b/sim/or1k/cpu.h
> @@ -73,15 +73,31 @@ SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))),
>
> /* Virtual regs. */
>
> +#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
> +#define SET_H_SPR(index, x) \
> +do { \
> +or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
> +;} while (0)
> #define GET_H_FSR(index) SUBWORDSISF (TRUNCSISI (GET_H_GPR (index)))
> #define SET_H_FSR(index, x) \
> do { \
> SET_H_GPR ((index), ZEXTSISI (SUBWORDSFSI ((x))));\
> ;} while (0)
> -#define GET_H_SPR(index) or1k32bf_h_spr_get_raw (current_cpu, index)
> -#define SET_H_SPR(index, x) \
> +#define GET_H_FD32R(index) JOINSIDF (GET_H_GPR (index), GET_H_GPR (((index) + (((((index) > (15))) ? (2) : (1))))))
> +#define SET_H_FD32R(index, x) \
> do { \
> -or1k32bf_h_spr_set_raw (current_cpu, (index), (x));\
> +{\
> +SET_H_GPR ((index), SUBWORDDFSI ((x), 0));\
> +SET_H_GPR ((((index)) + ((((((index)) > (15))) ? (2) : (1)))), SUBWORDDFSI ((x), 1));\
> +}\
> +;} while (0)
> +#define GET_H_I64R(index) JOINSIDI (GET_H_GPR (index), GET_H_GPR (((index) + (((((index) > (15))) ? (2) : (1))))))
> +#define SET_H_I64R(index, x) \
> +do { \
> +{\
> +SET_H_GPR ((index), SUBWORDDISI ((x), 0));\
> +SET_H_GPR ((((index)) + ((((((index)) > (15))) ? (2) : (1)))), SUBWORDDISI ((x), 1));\
> +}\
> ;} while (0)
> #define GET_H_SYS_VR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR))
> #define SET_H_SYS_VR(x) \
> @@ -3227,12 +3243,16 @@ or1k32bf_h_spr_field_set_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_
> /* Cover fns for register access. */
> USI or1k32bf_h_pc_get (SIM_CPU *);
> void or1k32bf_h_pc_set (SIM_CPU *, USI);
> -SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
> -void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
> USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
> void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
> USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
> void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
> +SF or1k32bf_h_fsr_get (SIM_CPU *, UINT);
> +void or1k32bf_h_fsr_set (SIM_CPU *, UINT, SF);
> +DF or1k32bf_h_fd32r_get (SIM_CPU *, UINT);
> +void or1k32bf_h_fd32r_set (SIM_CPU *, UINT, DF);
> +DI or1k32bf_h_i64r_get (SIM_CPU *, UINT);
> +void or1k32bf_h_i64r_set (SIM_CPU *, UINT, DI);
> USI or1k32bf_h_sys_vr_get (SIM_CPU *);
> void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
> USI or1k32bf_h_sys_upr_get (SIM_CPU *);
> @@ -4978,6 +4998,23 @@ struct scache {
> f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
>
> +#define EXTRACT_IFMT_LF_ADD_D32_VARS \
> + UINT f_opcode; \
> + UINT f_r1; \
> + UINT f_r2; \
> + UINT f_r3; \
> + UINT f_resv_10_3; \
> + UINT f_op_7_8; \
> + unsigned int length;
> +#define EXTRACT_IFMT_LF_ADD_D32_CODE \
> + length = 4; \
> + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
> + f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> + f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
> +
> #define EXTRACT_IFMT_LF_ITOF_S_VARS \
> UINT f_opcode; \
> UINT f_r1; \
> @@ -4995,6 +5032,23 @@ struct scache {
> f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
>
> +#define EXTRACT_IFMT_LF_ITOF_D32_VARS \
> + UINT f_opcode; \
> + UINT f_r1; \
> + UINT f_r2; \
> + UINT f_r3; \
> + UINT f_resv_10_3; \
> + UINT f_op_7_8; \
> + unsigned int length;
> +#define EXTRACT_IFMT_LF_ITOF_D32_CODE \
> + length = 4; \
> + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
> + f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> + f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
> +
> #define EXTRACT_IFMT_LF_FTOI_S_VARS \
> UINT f_opcode; \
> UINT f_r1; \
> @@ -5012,6 +5066,23 @@ struct scache {
> f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
>
> +#define EXTRACT_IFMT_LF_FTOI_D32_VARS \
> + UINT f_opcode; \
> + UINT f_r1; \
> + UINT f_r2; \
> + UINT f_r3; \
> + UINT f_resv_10_3; \
> + UINT f_op_7_8; \
> + unsigned int length;
> +#define EXTRACT_IFMT_LF_FTOI_D32_CODE \
> + length = 4; \
> + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
> + f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> + f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
> +
> #define EXTRACT_IFMT_LF_EQ_S_VARS \
> UINT f_opcode; \
> UINT f_r1; \
> @@ -5029,6 +5100,23 @@ struct scache {
> f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
>
> +#define EXTRACT_IFMT_LF_EQ_D32_VARS \
> + UINT f_opcode; \
> + UINT f_r1; \
> + UINT f_r2; \
> + UINT f_r3; \
> + UINT f_resv_10_3; \
> + UINT f_op_7_8; \
> + unsigned int length;
> +#define EXTRACT_IFMT_LF_EQ_D32_CODE \
> + length = 4; \
> + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
> + f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> + f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
> +
> #define EXTRACT_IFMT_LF_CUST1_S_VARS \
> UINT f_opcode; \
> UINT f_resv_25_5; \
> @@ -5046,6 +5134,23 @@ struct scache {
> f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
>
> +#define EXTRACT_IFMT_LF_CUST1_D32_VARS \
> + UINT f_opcode; \
> + UINT f_resv_25_5; \
> + UINT f_r2; \
> + UINT f_r3; \
> + UINT f_resv_10_3; \
> + UINT f_op_7_8; \
> + unsigned int length;
> +#define EXTRACT_IFMT_LF_CUST1_D32_CODE \
> + length = 4; \
> + f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
> + f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
> + f_resv_10_3 = EXTRACT_LSB0_UINT (insn, 32, 10, 3); \
> + f_op_7_8 = EXTRACT_LSB0_UINT (insn, 32, 7, 8); \
> +
> /* Collection of various things for the trace handler to use. */
>
> typedef struct trace_record {
> diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c
> index 153e00f82f..d619910aa7 100644
> --- a/sim/or1k/decode.c
> +++ b/sim/or1k/decode.c
> @@ -144,20 +144,35 @@ static const struct insn_sem or1k32bf_insn_sem[] =
> { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_MSYNC },
> { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_MSYNC },
> { OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
> + { OR1K_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_SFMT_LF_ADD_D32 },
> { OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
> + { OR1K_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_SFMT_LF_ADD_D32 },
> { OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
> + { OR1K_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_SFMT_LF_ADD_D32 },
> { OR1K_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_SFMT_LF_ADD_S },
> + { OR1K_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_SFMT_LF_ADD_D32 },
> { OR1K_INSN_LF_REM_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_SFMT_LF_ADD_S },
> + { OR1K_INSN_LF_REM_D32, OR1K32BF_INSN_LF_REM_D32, OR1K32BF_SFMT_LF_ADD_D32 },
> { OR1K_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_S },
> + { OR1K_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_SFMT_LF_ITOF_D32 },
> { OR1K_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_SFMT_LF_FTOI_S },
> + { OR1K_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_SFMT_LF_FTOI_D32 },
> { OR1K_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_EQ_D32, OR1K32BF_INSN_LF_EQ_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_NE_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_NE_D32, OR1K32BF_INSN_LF_NE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_GE_D32, OR1K32BF_INSN_LF_GE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_GT_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_GT_D32, OR1K32BF_INSN_LF_GT_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_LT_D32, OR1K32BF_INSN_LF_LT_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
> + { OR1K_INSN_LF_LE_D32, OR1K32BF_INSN_LF_LE_D32, OR1K32BF_SFMT_LF_EQ_D32 },
> { OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
> + { OR1K_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_SFMT_LF_MADD_D32 },
> { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_MSYNC },
> + { OR1K_INSN_LF_CUST1_D32, OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_SFMT_L_MSYNC },
> };
>
> static const struct insn_sem or1k32bf_insn_sem_invalid =
> @@ -235,7 +250,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> CGEN_INSN_WORD insn = base_insn;
>
> {
> - unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 2) & (1 << 4)) | ((insn >> 0) & (15 << 0)));
> + unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 0) & (31 << 0)));
> switch (val)
> {
> case 0 : /* fall through */
> @@ -1083,22 +1098,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> case 1484 : /* fall through */
> case 1485 : /* fall through */
> case 1486 : /* fall through */
> - case 1487 :
> - {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> - switch (val)
> - {
> - case 0 :
> - if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
> - { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - case 1 :
> - if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
> - { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - }
> - }
> + case 1487 : /* fall through */
> case 1488 : /* fall through */
> case 1489 : /* fall through */
> case 1490 : /* fall through */
> @@ -1116,14 +1116,22 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> case 1502 : /* fall through */
> case 1503 :
> {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> + unsigned int val = (((insn >> 6) & (3 << 0)));
> switch (val)
> {
> case 0 :
> + if ((entire_insn & 0xfc00ffc0) == 0xb8000000)
> + { itype = OR1K32BF_INSN_L_SLLI; goto extract_sfmt_l_slli; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1 :
> if ((entire_insn & 0xfc00ffc0) == 0xb8000040)
> { itype = OR1K32BF_INSN_L_SRLI; goto extract_sfmt_l_slli; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - case 1 :
> + case 2 :
> + if ((entire_insn & 0xfc00ffc0) == 0xb8000080)
> + { itype = OR1K32BF_INSN_L_SRAI; goto extract_sfmt_l_slli; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 3 :
> if ((entire_insn & 0xfc00ffc0) == 0xb80000c0)
> { itype = OR1K32BF_INSN_L_RORI; goto extract_sfmt_l_slli; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> @@ -1258,9 +1266,21 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> { itype = OR1K32BF_INSN_L_MSBU; goto extract_sfmt_l_macu; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1600 :
> - if ((entire_insn & 0xfc0007ff) == 0xc8000000)
> - { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + {
> + unsigned int val = (((insn >> 5) & (7 << 0)));
> + switch (val)
> + {
> + case 0 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000000)
> + { itype = OR1K32BF_INSN_LF_ADD_S; goto extract_sfmt_lf_add_s; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 7 :
> + if ((entire_insn & 0xffe007ff) == 0xc80000e0)
> + { itype = OR1K32BF_INSN_LF_CUST1_D32; goto extract_sfmt_l_msync; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + }
> + }
> case 1601 :
> if ((entire_insn & 0xfc0007ff) == 0xc8000001)
> { itype = OR1K32BF_INSN_LF_SUB_S; goto extract_sfmt_lf_add_s; }
> @@ -1314,8 +1334,72 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> { itype = OR1K32BF_INSN_LF_LE_S; goto extract_sfmt_lf_eq_s; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1616 :
> - if ((entire_insn & 0xffe007ff) == 0xc80000d0)
> - { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
> + {
> + unsigned int val = (((insn >> 6) & (3 << 0)));
> + switch (val)
> + {
> + case 0 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000010)
> + { itype = OR1K32BF_INSN_LF_ADD_D32; goto extract_sfmt_lf_add_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 3 :
> + if ((entire_insn & 0xffe007ff) == 0xc80000d0)
> + { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + }
> + }
> + case 1617 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000011)
> + { itype = OR1K32BF_INSN_LF_SUB_D32; goto extract_sfmt_lf_add_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1618 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000012)
> + { itype = OR1K32BF_INSN_LF_MUL_D32; goto extract_sfmt_lf_add_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1619 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000013)
> + { itype = OR1K32BF_INSN_LF_DIV_D32; goto extract_sfmt_lf_add_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1620 :
> + if ((entire_insn & 0xfc00ffff) == 0xc8000014)
> + { itype = OR1K32BF_INSN_LF_ITOF_D32; goto extract_sfmt_lf_itof_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1621 :
> + if ((entire_insn & 0xfc00ffff) == 0xc8000015)
> + { itype = OR1K32BF_INSN_LF_FTOI_D32; goto extract_sfmt_lf_ftoi_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1622 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000016)
> + { itype = OR1K32BF_INSN_LF_REM_D32; goto extract_sfmt_lf_add_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1623 :
> + if ((entire_insn & 0xfc0007ff) == 0xc8000017)
> + { itype = OR1K32BF_INSN_LF_MADD_D32; goto extract_sfmt_lf_madd_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1624 :
> + if ((entire_insn & 0xffe007ff) == 0xc8000018)
> + { itype = OR1K32BF_INSN_LF_EQ_D32; goto extract_sfmt_lf_eq_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1625 :
> + if ((entire_insn & 0xffe007ff) == 0xc8000019)
> + { itype = OR1K32BF_INSN_LF_NE_D32; goto extract_sfmt_lf_eq_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1626 :
> + if ((entire_insn & 0xffe007ff) == 0xc800001a)
> + { itype = OR1K32BF_INSN_LF_GT_D32; goto extract_sfmt_lf_eq_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1627 :
> + if ((entire_insn & 0xffe007ff) == 0xc800001b)
> + { itype = OR1K32BF_INSN_LF_GE_D32; goto extract_sfmt_lf_eq_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1628 :
> + if ((entire_insn & 0xffe007ff) == 0xc800001c)
> + { itype = OR1K32BF_INSN_LF_LT_D32; goto extract_sfmt_lf_eq_d32; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 1629 :
> + if ((entire_insn & 0xffe007ff) == 0xc800001d)
> + { itype = OR1K32BF_INSN_LF_LE_D32; goto extract_sfmt_lf_eq_d32; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1632 : /* fall through */
> case 1633 : /* fall through */
> @@ -1479,7 +1563,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1800 :
> {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> + unsigned int val = (((insn >> 6) & (3 << 0)));
> switch (val)
> {
> case 0 :
> @@ -1487,9 +1571,17 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> { itype = OR1K32BF_INSN_L_SLL; goto extract_sfmt_l_sll; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1 :
> + if ((entire_insn & 0xfc0007ff) == 0xe0000048)
> + { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 2 :
> if ((entire_insn & 0xfc0007ff) == 0xe0000088)
> { itype = OR1K32BF_INSN_L_SRA; goto extract_sfmt_l_sll; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 3 :
> + if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
> + { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> }
> }
> @@ -1507,7 +1599,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1804 :
> {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> + unsigned int val = (((insn >> 6) & (3 << 0)));
> switch (val)
> {
> case 0 :
> @@ -1515,22 +1607,34 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> { itype = OR1K32BF_INSN_L_EXTHS; goto extract_sfmt_l_exths; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1 :
> + if ((entire_insn & 0xfc00ffff) == 0xe000004c)
> + { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 2 :
> if ((entire_insn & 0xfc00ffff) == 0xe000008c)
> { itype = OR1K32BF_INSN_L_EXTHZ; goto extract_sfmt_l_exths; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 3 :
> + if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
> + { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> }
> }
> case 1805 :
> {
> - unsigned int val = (((insn >> 8) & (3 << 0)));
> + unsigned int val = (((insn >> 7) & (3 << 1)) | ((insn >> 6) & (1 << 0)));
> switch (val)
> {
> case 0 :
> if ((entire_insn & 0xfc00ffff) == 0xe000000d)
> { itype = OR1K32BF_INSN_L_EXTWS; goto extract_sfmt_l_exths; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - case 3 :
> + case 1 :
> + if ((entire_insn & 0xfc00ffff) == 0xe000004d)
> + { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
> + itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> + case 6 :
> if ((entire_insn & 0xffe007ff) == 0xe000030d)
> { itype = OR1K32BF_INSN_L_MULDU; goto extract_sfmt_l_muld; }
> itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> @@ -1557,42 +1661,6 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> }
> }
> - case 1816 :
> - {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> - switch (val)
> - {
> - case 0 :
> - if ((entire_insn & 0xfc0007ff) == 0xe0000048)
> - { itype = OR1K32BF_INSN_L_SRL; goto extract_sfmt_l_sll; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - case 1 :
> - if ((entire_insn & 0xfc0007ff) == 0xe00000c8)
> - { itype = OR1K32BF_INSN_L_ROR; goto extract_sfmt_l_sll; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - }
> - }
> - case 1820 :
> - {
> - unsigned int val = (((insn >> 7) & (1 << 0)));
> - switch (val)
> - {
> - case 0 :
> - if ((entire_insn & 0xfc00ffff) == 0xe000004c)
> - { itype = OR1K32BF_INSN_L_EXTBS; goto extract_sfmt_l_exths; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - case 1 :
> - if ((entire_insn & 0xfc00ffff) == 0xe00000cc)
> - { itype = OR1K32BF_INSN_L_EXTBZ; goto extract_sfmt_l_exths; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> - }
> - }
> - case 1821 :
> - if ((entire_insn & 0xfc00ffff) == 0xe000004d)
> - { itype = OR1K32BF_INSN_L_EXTWZ; goto extract_sfmt_l_exths; }
> - itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
> case 1824 :
> {
> unsigned int val = (((insn >> 21) & (15 << 0)));
> @@ -2682,6 +2750,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> FLD (f_r1) = f_r1;
> TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
>
> +#undef FLD
> + return idesc;
> + }
> +
> + extract_sfmt_lf_add_d32:
> + {
> + const IDESC *idesc = &or1k32bf_insn_data[itype];
> + CGEN_INSN_WORD insn = entire_insn;
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + UINT f_r1;
> + UINT f_r2;
> + UINT f_r3;
> +
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
> +
> + /* Record the fields for the semantic handler. */
> + FLD (f_r2) = f_r2;
> + FLD (f_r3) = f_r3;
> + FLD (f_r1) = f_r1;
> + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_add_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
> +
> #undef FLD
> return idesc;
> }
> @@ -2702,6 +2793,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> FLD (f_r1) = f_r1;
> TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
>
> +#undef FLD
> + return idesc;
> + }
> +
> + extract_sfmt_lf_itof_d32:
> + {
> + const IDESC *idesc = &or1k32bf_insn_data[itype];
> + CGEN_INSN_WORD insn = entire_insn;
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + UINT f_r1;
> + UINT f_r2;
> +
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
> +
> + /* Record the fields for the semantic handler. */
> + FLD (f_r2) = f_r2;
> + FLD (f_r1) = f_r1;
> + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_itof_d32", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
> +
> #undef FLD
> return idesc;
> }
> @@ -2722,6 +2833,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> FLD (f_r1) = f_r1;
> TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_s", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
>
> +#undef FLD
> + return idesc;
> + }
> +
> + extract_sfmt_lf_ftoi_d32:
> + {
> + const IDESC *idesc = &or1k32bf_insn_data[itype];
> + CGEN_INSN_WORD insn = entire_insn;
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + UINT f_r1;
> + UINT f_r2;
> +
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
> +
> + /* Record the fields for the semantic handler. */
> + FLD (f_r2) = f_r2;
> + FLD (f_r1) = f_r1;
> + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_ftoi_d32", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, (char *) 0));
> +
> #undef FLD
> return idesc;
> }
> @@ -2742,6 +2873,26 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> FLD (f_r3) = f_r3;
> TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
>
> +#undef FLD
> + return idesc;
> + }
> +
> + extract_sfmt_lf_eq_d32:
> + {
> + const IDESC *idesc = &or1k32bf_insn_data[itype];
> + CGEN_INSN_WORD insn = entire_insn;
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + UINT f_r2;
> + UINT f_r3;
> +
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
> +
> + /* Record the fields for the semantic handler. */
> + FLD (f_r2) = f_r2;
> + FLD (f_r3) = f_r3;
> + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_eq_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
> +
> #undef FLD
> return idesc;
> }
> @@ -2765,6 +2916,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
> FLD (f_r1) = f_r1;
> TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_s", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
>
> +#undef FLD
> + return idesc;
> + }
> +
> + extract_sfmt_lf_madd_d32:
> + {
> + const IDESC *idesc = &or1k32bf_insn_data[itype];
> + CGEN_INSN_WORD insn = entire_insn;
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + UINT f_r1;
> + UINT f_r2;
> + UINT f_r3;
> +
> + f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
> + f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
> + f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
> +
> + /* Record the fields for the semantic handler. */
> + FLD (f_r2) = f_r2;
> + FLD (f_r3) = f_r3;
> + FLD (f_r1) = f_r1;
> + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lf_madd_d32", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_r1 0x%x", 'x', f_r1, (char *) 0));
> +
> #undef FLD
> return idesc;
> }
> diff --git a/sim/or1k/decode.h b/sim/or1k/decode.h
> index 8650bdfa0e..76c2c667ac 100644
> --- a/sim/or1k/decode.h
> +++ b/sim/or1k/decode.h
> @@ -60,10 +60,14 @@ typedef enum or1k32bf_insn_type {
> , OR1K32BF_INSN_L_MACU, OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MSBU, OR1K32BF_INSN_L_CUST1
> , OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5
> , OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S
> - , OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S
> - , OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S
> - , OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S
> - , OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX
> + , OR1K32BF_INSN_LF_ADD_D32, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_D32, OR1K32BF_INSN_LF_MUL_S
> + , OR1K32BF_INSN_LF_MUL_D32, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_DIV_D32, OR1K32BF_INSN_LF_REM_S
> + , OR1K32BF_INSN_LF_REM_D32, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_ITOF_D32, OR1K32BF_INSN_LF_FTOI_S
> + , OR1K32BF_INSN_LF_FTOI_D32, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_EQ_D32, OR1K32BF_INSN_LF_NE_S
> + , OR1K32BF_INSN_LF_NE_D32, OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GE_D32, OR1K32BF_INSN_LF_GT_S
> + , OR1K32BF_INSN_LF_GT_D32, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_D32, OR1K32BF_INSN_LF_LE_S
> + , OR1K32BF_INSN_LF_LE_D32, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_D32, OR1K32BF_INSN_LF_CUST1_S
> + , OR1K32BF_INSN_LF_CUST1_D32, OR1K32BF_INSN__MAX
> } OR1K32BF_INSN_TYPE;
>
> /* Enum declaration for semantic formats in cpu family or1k32bf. */
> @@ -80,7 +84,9 @@ typedef enum or1k32bf_sfmt_type {
> , OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_MULI
> , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
> , OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_MACU, OR1K32BF_SFMT_LF_ADD_S
> - , OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
> + , OR1K32BF_SFMT_LF_ADD_D32, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_ITOF_D32, OR1K32BF_SFMT_LF_FTOI_S
> + , OR1K32BF_SFMT_LF_FTOI_D32, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_EQ_D32, OR1K32BF_SFMT_LF_MADD_S
> + , OR1K32BF_SFMT_LF_MADD_D32
> } OR1K32BF_SFMT_TYPE;
>
> /* Function unit handlers (user written). */
> diff --git a/sim/or1k/model.c b/sim/or1k/model.c
> index 461ba4bb00..44da5b9019 100644
> --- a/sim/or1k/model.c
> +++ b/sim/or1k/model.c
> @@ -1602,6 +1602,22 @@ model_or1200_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1618,6 +1634,22 @@ model_or1200_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1634,6 +1666,22 @@ model_or1200_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1650,6 +1698,22 @@ model_or1200_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1666,6 +1730,22 @@ model_or1200_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1682,6 +1762,22 @@ model_or1200_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1698,6 +1794,22 @@ model_or1200_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1714,6 +1826,22 @@ model_or1200_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_eq_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1730,6 +1858,22 @@ model_or1200_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_ne_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1746,6 +1890,22 @@ model_or1200_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_ge_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1762,6 +1922,22 @@ model_or1200_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_gt_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1778,6 +1954,22 @@ model_or1200_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_lt_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1794,6 +1986,22 @@ model_or1200_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_le_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1810,6 +2018,22 @@ model_or1200_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -1826,6 +2050,22 @@ model_or1200_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_empty.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_l_j (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3394,6 +3634,22 @@ model_or1200nd_lf_add_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_add_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3410,6 +3666,22 @@ model_or1200nd_lf_sub_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_sub_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3426,6 +3698,22 @@ model_or1200nd_lf_mul_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_mul_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3442,6 +3730,22 @@ model_or1200nd_lf_div_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_div_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3458,6 +3762,22 @@ model_or1200nd_lf_rem_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_rem_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3474,6 +3794,22 @@ model_or1200nd_lf_itof_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_itof_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3490,6 +3826,22 @@ model_or1200nd_lf_ftoi_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_ftoi_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3506,6 +3858,22 @@ model_or1200nd_lf_eq_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_eq_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3522,6 +3890,22 @@ model_or1200nd_lf_ne_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_ne_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3538,6 +3922,22 @@ model_or1200nd_lf_ge_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_ge_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3554,6 +3954,22 @@ model_or1200nd_lf_gt_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_gt_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3570,6 +3986,22 @@ model_or1200nd_lf_lt_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_lt_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3586,6 +4018,22 @@ model_or1200nd_lf_le_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_le_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3602,6 +4050,22 @@ model_or1200nd_lf_madd_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_madd_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> static int
> model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
> {
> @@ -3618,6 +4082,22 @@ model_or1200nd_lf_cust1_s (SIM_CPU *current_cpu, void *sem_arg)
> #undef FLD
> }
>
> +static int
> +model_or1200nd_lf_cust1_d32 (SIM_CPU *current_cpu, void *sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_empty.f
> + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
> + const IDESC * UNUSED idesc = abuf->idesc;
> + int cycles = 0;
> + {
> + int referenced = 0;
> + int UNUSED insn_referenced = abuf->written;
> + cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
> + }
> + return cycles;
> +#undef FLD
> +}
> +
> /* We assume UNIT_NONE == 0 because the tables don't always terminate
> entries with it. */
>
> @@ -3728,20 +4208,35 @@ static const INSN_TIMING or1200_timing[] = {
> { OR1K32BF_INSN_L_CUST7, model_or1200_l_cust7, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_L_CUST8, model_or1200_l_cust8, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_ADD_S, model_or1200_lf_add_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_ADD_D32, model_or1200_lf_add_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_SUB_S, model_or1200_lf_sub_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_SUB_D32, model_or1200_lf_sub_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_MUL_S, model_or1200_lf_mul_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_MUL_D32, model_or1200_lf_mul_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_DIV_S, model_or1200_lf_div_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_DIV_D32, model_or1200_lf_div_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_REM_S, model_or1200_lf_rem_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_REM_D32, model_or1200_lf_rem_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_ITOF_S, model_or1200_lf_itof_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_ITOF_D32, model_or1200_lf_itof_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_FTOI_S, model_or1200_lf_ftoi_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_FTOI_D32, model_or1200_lf_ftoi_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_EQ_S, model_or1200_lf_eq_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_EQ_D32, model_or1200_lf_eq_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_NE_S, model_or1200_lf_ne_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_NE_D32, model_or1200_lf_ne_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_GE_S, model_or1200_lf_ge_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_GE_D32, model_or1200_lf_ge_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_GT_S, model_or1200_lf_gt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_GT_D32, model_or1200_lf_gt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_LT_S, model_or1200_lf_lt_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_LT_D32, model_or1200_lf_lt_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_LE_S, model_or1200_lf_le_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_LE_D32, model_or1200_lf_le_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_MADD_S, model_or1200_lf_madd_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_MADD_D32, model_or1200_lf_madd_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_CUST1_S, model_or1200_lf_cust1_s, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_CUST1_D32, model_or1200_lf_cust1_d32, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
> };
>
> /* Model timing data for `or1200nd'. */
> @@ -3851,20 +4346,35 @@ static const INSN_TIMING or1200nd_timing[] = {
> { OR1K32BF_INSN_L_CUST7, model_or1200nd_l_cust7, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_L_CUST8, model_or1200nd_l_cust8, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_ADD_S, model_or1200nd_lf_add_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_ADD_D32, model_or1200nd_lf_add_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_SUB_S, model_or1200nd_lf_sub_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_SUB_D32, model_or1200nd_lf_sub_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_MUL_S, model_or1200nd_lf_mul_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_MUL_D32, model_or1200nd_lf_mul_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_DIV_S, model_or1200nd_lf_div_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_DIV_D32, model_or1200nd_lf_div_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_REM_S, model_or1200nd_lf_rem_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_REM_D32, model_or1200nd_lf_rem_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_ITOF_S, model_or1200nd_lf_itof_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_ITOF_D32, model_or1200nd_lf_itof_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_FTOI_S, model_or1200nd_lf_ftoi_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_FTOI_D32, model_or1200nd_lf_ftoi_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_EQ_S, model_or1200nd_lf_eq_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_EQ_D32, model_or1200nd_lf_eq_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_NE_S, model_or1200nd_lf_ne_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_NE_D32, model_or1200nd_lf_ne_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_GE_S, model_or1200nd_lf_ge_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_GE_D32, model_or1200nd_lf_ge_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_GT_S, model_or1200nd_lf_gt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_GT_D32, model_or1200nd_lf_gt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_LT_S, model_or1200nd_lf_lt_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_LT_D32, model_or1200nd_lf_lt_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_LE_S, model_or1200nd_lf_le_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_LE_D32, model_or1200nd_lf_le_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_MADD_S, model_or1200nd_lf_madd_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_MADD_D32, model_or1200nd_lf_madd_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> { OR1K32BF_INSN_LF_CUST1_S, model_or1200nd_lf_cust1_s, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> + { OR1K32BF_INSN_LF_CUST1_D32, model_or1200nd_lf_cust1_d32, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
> };
>
> #endif /* WITH_PROFILE_MODEL_P */
> diff --git a/sim/or1k/sem-switch.c b/sim/or1k/sem-switch.c
> index e250e45c60..203f619253 100644
> --- a/sim/or1k/sem-switch.c
> +++ b/sim/or1k/sem-switch.c
> @@ -136,20 +136,35 @@ This file is part of the GNU simulators.
> { OR1K32BF_INSN_L_CUST7, && case_sem_INSN_L_CUST7 },
> { OR1K32BF_INSN_L_CUST8, && case_sem_INSN_L_CUST8 },
> { OR1K32BF_INSN_LF_ADD_S, && case_sem_INSN_LF_ADD_S },
> + { OR1K32BF_INSN_LF_ADD_D32, && case_sem_INSN_LF_ADD_D32 },
> { OR1K32BF_INSN_LF_SUB_S, && case_sem_INSN_LF_SUB_S },
> + { OR1K32BF_INSN_LF_SUB_D32, && case_sem_INSN_LF_SUB_D32 },
> { OR1K32BF_INSN_LF_MUL_S, && case_sem_INSN_LF_MUL_S },
> + { OR1K32BF_INSN_LF_MUL_D32, && case_sem_INSN_LF_MUL_D32 },
> { OR1K32BF_INSN_LF_DIV_S, && case_sem_INSN_LF_DIV_S },
> + { OR1K32BF_INSN_LF_DIV_D32, && case_sem_INSN_LF_DIV_D32 },
> { OR1K32BF_INSN_LF_REM_S, && case_sem_INSN_LF_REM_S },
> + { OR1K32BF_INSN_LF_REM_D32, && case_sem_INSN_LF_REM_D32 },
> { OR1K32BF_INSN_LF_ITOF_S, && case_sem_INSN_LF_ITOF_S },
> + { OR1K32BF_INSN_LF_ITOF_D32, && case_sem_INSN_LF_ITOF_D32 },
> { OR1K32BF_INSN_LF_FTOI_S, && case_sem_INSN_LF_FTOI_S },
> + { OR1K32BF_INSN_LF_FTOI_D32, && case_sem_INSN_LF_FTOI_D32 },
> { OR1K32BF_INSN_LF_EQ_S, && case_sem_INSN_LF_EQ_S },
> + { OR1K32BF_INSN_LF_EQ_D32, && case_sem_INSN_LF_EQ_D32 },
> { OR1K32BF_INSN_LF_NE_S, && case_sem_INSN_LF_NE_S },
> + { OR1K32BF_INSN_LF_NE_D32, && case_sem_INSN_LF_NE_D32 },
> { OR1K32BF_INSN_LF_GE_S, && case_sem_INSN_LF_GE_S },
> + { OR1K32BF_INSN_LF_GE_D32, && case_sem_INSN_LF_GE_D32 },
> { OR1K32BF_INSN_LF_GT_S, && case_sem_INSN_LF_GT_S },
> + { OR1K32BF_INSN_LF_GT_D32, && case_sem_INSN_LF_GT_D32 },
> { OR1K32BF_INSN_LF_LT_S, && case_sem_INSN_LF_LT_S },
> + { OR1K32BF_INSN_LF_LT_D32, && case_sem_INSN_LF_LT_D32 },
> { OR1K32BF_INSN_LF_LE_S, && case_sem_INSN_LF_LE_S },
> + { OR1K32BF_INSN_LF_LE_D32, && case_sem_INSN_LF_LE_D32 },
> { OR1K32BF_INSN_LF_MADD_S, && case_sem_INSN_LF_MADD_S },
> + { OR1K32BF_INSN_LF_MADD_D32, && case_sem_INSN_LF_MADD_D32 },
> { OR1K32BF_INSN_LF_CUST1_S, && case_sem_INSN_LF_CUST1_S },
> + { OR1K32BF_INSN_LF_CUST1_D32, && case_sem_INSN_LF_CUST1_D32 },
> { 0, 0 }
> };
> int i;
> @@ -2646,6 +2661,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_ADD_D32) : /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2665,6 +2699,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_SUB_D32) : /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2684,6 +2737,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_MUL_D32) : /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2703,6 +2775,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_DIV_D32) : /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2722,6 +2813,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_REM_D32) : /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2741,6 +2851,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_ITOF_D32) : /* lf.itof.d $rDD32F,$rADI */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_r2)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2760,6 +2889,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_FTOI_D32) : /* lf.ftoi.d $rDDI,$rAD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_r2)));
> + SET_H_I64R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2779,6 +2927,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_EQ_D32) : /* lf.sfeq.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2798,6 +2965,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_NE_D32) : /* lf.sfne.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2817,6 +3003,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_GE_D32) : /* lf.sfge.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2836,6 +3041,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_GT_D32) : /* lf.sfgt.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2855,6 +3079,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_LT_D32) : /* lf.sflt.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2874,6 +3117,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_LE_D32) : /* lf.sfle.d $rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2893,6 +3155,25 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
> CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
> }
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_MADD_D32) : /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3))), GET_H_FD32R (FLD (f_r1)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> #undef FLD
> }
> NEXT (vpc);
> @@ -2908,6 +3189,21 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
>
> ((void) 0); /*nop*/
>
> +#undef FLD
> +}
> + NEXT (vpc);
> +
> + CASE (sem, INSN_LF_CUST1_D32) : /* lf.cust1.d */
> +{
> + SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> +#define FLD(f) abuf->fields.sfmt_empty.f
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> +((void) 0); /*nop*/
> +
> #undef FLD
> }
> NEXT (vpc);
> diff --git a/sim/or1k/sem.c b/sim/or1k/sem.c
> index 15ef24c079..7cfa998dbd 100644
> --- a/sim/or1k/sem.c
> +++ b/sim/or1k/sem.c
> @@ -2694,6 +2694,27 @@ SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-add-d32: lf.add.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_add_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-sub-s: lf.sub.s $rDSF,$rASF,$rBSF */
>
> static SEM_PC
> @@ -2715,6 +2736,27 @@ SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-sub-d32: lf.sub.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_sub_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-mul-s: lf.mul.s $rDSF,$rASF,$rBSF */
>
> static SEM_PC
> @@ -2736,6 +2778,27 @@ SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-mul-d32: lf.mul.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_mul_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-div-s: lf.div.s $rDSF,$rASF,$rBSF */
>
> static SEM_PC
> @@ -2757,6 +2820,27 @@ SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-div-d32: lf.div.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_div_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-rem-s: lf.rem.s $rDSF,$rASF,$rBSF */
>
> static SEM_PC
> @@ -2778,6 +2862,27 @@ SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-rem-d32: lf.rem.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_rem_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->remdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-itof-s: lf.itof.s $rDSF,$rA */
>
> static SEM_PC
> @@ -2799,6 +2904,27 @@ SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-itof-d32: lf.itof.d $rDD32F,$rADI */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_itof_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_I64R (FLD (f_r2)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-ftoi-s: lf.ftoi.s $rD,$rASF */
>
> static SEM_PC
> @@ -2820,6 +2946,27 @@ SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-ftoi-d32: lf.ftoi.d $rDDI,$rAD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_ftoi_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_slli.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FD32R (FLD (f_r2)));
> + SET_H_I64R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "i64r", 'D', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-eq-s: lf.sfeq.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2841,6 +2988,27 @@ SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-eq-d32: lf.sfeq.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_eq_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-ne-s: lf.sfne.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2862,6 +3030,27 @@ SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-ne-d32: lf.sfne.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_ne_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-ge-s: lf.sfge.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2883,6 +3072,27 @@ SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-ge-d32: lf.sfge.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_ge_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-gt-s: lf.sfgt.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2904,6 +3114,27 @@ SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-gt-d32: lf.sfgt.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_gt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-lt-s: lf.sflt.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2925,6 +3156,27 @@ SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-lt-d32: lf.sflt.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_lt_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-le-s: lf.sfle.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2946,6 +3198,27 @@ SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-le-d32: lf.sfle.d $rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_le_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3)));
> + SET_H_SYS_SR_F (opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-madd-s: lf.madd.s $rDSF,$rASF,$rBSF */
>
> static SEM_PC
> @@ -2967,6 +3240,27 @@ SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-madd-d32: lf.madd.d $rDD32F,$rAD32F,$rBD32F */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_madd_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_l_sll.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> + {
> + DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FD32R (FLD (f_r2)), GET_H_FD32R (FLD (f_r3))), GET_H_FD32R (FLD (f_r1)));
> + SET_H_FD32R (FLD (f_r1), opval);
> + CGEN_TRACE_RESULT (current_cpu, abuf, "fd32r", 'f', opval);
> + }
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* lf-cust1-s: lf.cust1.s $rASF,$rBSF */
>
> static SEM_PC
> @@ -2984,6 +3278,23 @@ SEM_FN_NAME (or1k32bf,lf_cust1_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> #undef FLD
> }
>
> +/* lf-cust1-d32: lf.cust1.d */
> +
> +static SEM_PC
> +SEM_FN_NAME (or1k32bf,lf_cust1_d32) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
> +{
> +#define FLD(f) abuf->fields.sfmt_empty.f
> + ARGBUF *abuf = SEM_ARGBUF (sem_arg);
> + int UNUSED written = 0;
> + IADDR UNUSED pc = abuf->addr;
> + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
> +
> +((void) 0); /*nop*/
> +
> + return vpc;
> +#undef FLD
> +}
> +
> /* Table of all semantic fns. */
>
> static const struct sem_fn_desc sem_fns[] = {
> @@ -3091,20 +3402,35 @@ static const struct sem_fn_desc sem_fns[] = {
> { OR1K32BF_INSN_L_CUST7, SEM_FN_NAME (or1k32bf,l_cust7) },
> { OR1K32BF_INSN_L_CUST8, SEM_FN_NAME (or1k32bf,l_cust8) },
> { OR1K32BF_INSN_LF_ADD_S, SEM_FN_NAME (or1k32bf,lf_add_s) },
> + { OR1K32BF_INSN_LF_ADD_D32, SEM_FN_NAME (or1k32bf,lf_add_d32) },
> { OR1K32BF_INSN_LF_SUB_S, SEM_FN_NAME (or1k32bf,lf_sub_s) },
> + { OR1K32BF_INSN_LF_SUB_D32, SEM_FN_NAME (or1k32bf,lf_sub_d32) },
> { OR1K32BF_INSN_LF_MUL_S, SEM_FN_NAME (or1k32bf,lf_mul_s) },
> + { OR1K32BF_INSN_LF_MUL_D32, SEM_FN_NAME (or1k32bf,lf_mul_d32) },
> { OR1K32BF_INSN_LF_DIV_S, SEM_FN_NAME (or1k32bf,lf_div_s) },
> + { OR1K32BF_INSN_LF_DIV_D32, SEM_FN_NAME (or1k32bf,lf_div_d32) },
> { OR1K32BF_INSN_LF_REM_S, SEM_FN_NAME (or1k32bf,lf_rem_s) },
> + { OR1K32BF_INSN_LF_REM_D32, SEM_FN_NAME (or1k32bf,lf_rem_d32) },
> { OR1K32BF_INSN_LF_ITOF_S, SEM_FN_NAME (or1k32bf,lf_itof_s) },
> + { OR1K32BF_INSN_LF_ITOF_D32, SEM_FN_NAME (or1k32bf,lf_itof_d32) },
> { OR1K32BF_INSN_LF_FTOI_S, SEM_FN_NAME (or1k32bf,lf_ftoi_s) },
> + { OR1K32BF_INSN_LF_FTOI_D32, SEM_FN_NAME (or1k32bf,lf_ftoi_d32) },
> { OR1K32BF_INSN_LF_EQ_S, SEM_FN_NAME (or1k32bf,lf_eq_s) },
> + { OR1K32BF_INSN_LF_EQ_D32, SEM_FN_NAME (or1k32bf,lf_eq_d32) },
> { OR1K32BF_INSN_LF_NE_S, SEM_FN_NAME (or1k32bf,lf_ne_s) },
> + { OR1K32BF_INSN_LF_NE_D32, SEM_FN_NAME (or1k32bf,lf_ne_d32) },
> { OR1K32BF_INSN_LF_GE_S, SEM_FN_NAME (or1k32bf,lf_ge_s) },
> + { OR1K32BF_INSN_LF_GE_D32, SEM_FN_NAME (or1k32bf,lf_ge_d32) },
> { OR1K32BF_INSN_LF_GT_S, SEM_FN_NAME (or1k32bf,lf_gt_s) },
> + { OR1K32BF_INSN_LF_GT_D32, SEM_FN_NAME (or1k32bf,lf_gt_d32) },
> { OR1K32BF_INSN_LF_LT_S, SEM_FN_NAME (or1k32bf,lf_lt_s) },
> + { OR1K32BF_INSN_LF_LT_D32, SEM_FN_NAME (or1k32bf,lf_lt_d32) },
> { OR1K32BF_INSN_LF_LE_S, SEM_FN_NAME (or1k32bf,lf_le_s) },
> + { OR1K32BF_INSN_LF_LE_D32, SEM_FN_NAME (or1k32bf,lf_le_d32) },
> { OR1K32BF_INSN_LF_MADD_S, SEM_FN_NAME (or1k32bf,lf_madd_s) },
> + { OR1K32BF_INSN_LF_MADD_D32, SEM_FN_NAME (or1k32bf,lf_madd_d32) },
> { OR1K32BF_INSN_LF_CUST1_S, SEM_FN_NAME (or1k32bf,lf_cust1_s) },
> + { OR1K32BF_INSN_LF_CUST1_D32, SEM_FN_NAME (or1k32bf,lf_cust1_d32) },
> { 0, 0 }
> };
>
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion Stafford Horne
@ 2019-04-13 21:59 ` Andrew Burgess
0 siblings, 0 replies; 15+ messages in thread
From: Andrew Burgess @ 2019-04-13 21:59 UTC (permalink / raw)
To: openrisc
* Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:23 +0900]:
> Up until now these have not been used in any CGEN targets, add them as
> they are now used by OpenRISC.
>
> sim/common/ChangeLog:
>
> * cgen-accfp.c (floatdidf, fixdfdi): New functions.
> (cgen_init_accurate_fpu): Add floatdidf and fixdfdi.
This is fine.
thanks,
Andrew
> ---
> sim/common/cgen-accfp.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
> index 5d600c6e41..51f5a29fe2 100644
> --- a/sim/common/cgen-accfp.c
> +++ b/sim/common/cgen-accfp.c
> @@ -349,6 +349,17 @@ floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
> return res;
> }
>
> +static DF
> +floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
> +{
> + sim_fpu ans;
> + unsigned64 res;
> +
> + sim_fpu_i64to (&ans, x, sim_fpu_round_near);
> + sim_fpu_to64 (&res, &ans);
> + return res;
> +}
> +
> static SF
> ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
> {
> @@ -382,6 +393,17 @@ fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
> return res;
> }
>
> +static DI
> +fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
> +{
> + sim_fpu op1;
> + unsigned64 res;
> +
> + sim_fpu_64to (&op1, x);
> + sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
> + return res;
> +}
> +
> static USI
> ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
> {
> @@ -739,8 +761,10 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
> o->ftruncdfsf = ftruncdfsf;
> o->floatsisf = floatsisf;
> o->floatsidf = floatsidf;
> + o->floatdidf = floatdidf;
> o->ufloatsisf = ufloatsisf;
> o->fixsfsi = fixsfsi;
> o->fixdfsi = fixdfsi;
> + o->fixdfdi = fixdfdi;
> o->ufixsfsi = ufixsfsi;
> }
> --
> 2.19.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim for orfp64a32 spec
2019-04-13 21:40 ` Andrew Burgess
@ 2019-04-14 6:44 ` Stafford Horne
0 siblings, 0 replies; 15+ messages in thread
From: Stafford Horne @ 2019-04-14 6:44 UTC (permalink / raw)
To: openrisc
On Sat, Apr 13, 2019 at 10:40:02PM +0100, Andrew Burgess wrote:
> * Stafford Horne <shorne@gmail.com> [2019-04-10 06:39:22 +0900]:
>
> > sim/ChangeLog:
> >
> > * or1k/cpu.c: Regenerate.
> > * or1k/cpu.h: Regenerate.
> > * or1k/decode.c: Regenerate.
> > * or1k/decode.h: Regenerate.
> > * or1k/model.c: Regenerate.
> > * or1k/sem-switch.c: Regenerate.
> > * or1k/sem.c: Regenerate.
>
> Kind-of hard to argue with that :)
>
> This is fine with me,
Thanks, actually after some recent reviews of the spec that this is implementing
we may be having a revision to how we encode some of these instructions.
Thread for those interested:
- https://lists.librecores.org/pipermail/openrisc/2019-April/001958.html
I will have to make some revisions on this and will submit the series again in a
few weeks.
-Stafford
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-04-14 6:44 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-09 21:39 [OpenRISC] [PATCH v2 0/6] OpenRISC orfpx64a32 support Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 1/6] cpu: Add support for orfp64a32 spec Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 2/6] opcodes: Regenerate opcodes " Stafford Horne
2019-04-11 8:45 ` Nick Clifton
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 3/6] sim/or1k: Regenerate sim " Stafford Horne
2019-04-13 21:40 ` Andrew Burgess
2019-04-14 6:44 ` Stafford Horne
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 4/6] sim/common: Wire in df/di conversion Stafford Horne
2019-04-13 21:59 ` Andrew Burgess
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 5/6] sim/or1k: Add test for 64-bit fpu operations Stafford Horne
2019-04-13 21:36 ` Andrew Burgess
2019-04-09 21:39 ` [OpenRISC] [PATCH v2 6/6] sim/common: Fix issue with wrong byte order on BE targets Stafford Horne
2019-04-11 22:27 ` Andrew Burgess
2019-04-12 20:21 ` Stafford Horne
2019-04-13 21:30 ` Andrew Burgess
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