* [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
This is the second part of vector instruction support for s390x. It is
based on the series soon to land upstream:
[PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
Part 1: Vector Support Instructions
Part 2: Vector Integer Instructions
Part 3: Vector String Instructions
Part 4: Vector Floating-Point Instructions
The current state can be found at (kept updated):
https://github.com/davidhildenbrand/qemu/tree/vx
With the current state I can boot Linux kernel + user space compiled with
SIMD support. This allows to boot distributions compiled exclusively for
z13, requiring SIMD support. Also, it is now possible to build a complete
kernel using rpmbuild as quite some issues have been sorted out.
In this part, all Vector Integer Instructions introduced with the
"Vector Facility" are added. Some instructions part of the Vector Extension
Facilities are also added.
v1 -> v2:
- Many suggestions and fixes as outlined by Richard H.
-- Mostly avoid oom helpers for 128-bit add/sub variants
-- New vector helpers are not considered for now
David Hildenbrand (41):
tcg: Implement tcg_gen_gvec_3i()
s390x/tcg: Implement VECTOR ADD
s390x/tcg: Implement VECTOR ADD COMPUTE CARRY
s390x/tcg: Implement VECTOR ADD WITH CARRY
s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY
s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT)
s390x/tcg: Implement VECTOR AVERAGE
s390x/tcg: Implement VECTOR AVERAGE LOGICAL
s390x/tcg: Implement VECTOR CHECKSUM
s390x/tcg: Implement VECTOR ELEMENT COMPARE *
s390x/tcg: Implement VECTOR COMPARE *
s390x/tcg: Implement VECTOR COUNT LEADING ZEROS
s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS
s390x/tcg: Implement VECTOR EXCLUSIVE OR
s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)
s390x/tcg: Implement VECTOR LOAD COMPLEMENT
s390x/tcg: Implement VECTOR LOAD POSITIVE
s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)
s390x/tcg: Implement VECTOR MULTIPLY AND ADD *
s390x/tcg: Implement VECTOR MULTIPLY *
s390x/tcg: Implement VECTOR NAND
s390x/tcg: Implement VECTOR NOR
s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR
s390x/tcg: Implement VECTOR OR
s390x/tcg: Implement VECTOR OR WITH COMPLEMENT
s390x/tcg: Implement VECTOR POPULATION COUNT
s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL
s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
s390x/tcg: Implement VECTOR ELEMENT SHIFT
s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)
s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE
s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC
s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *
s390x/tcg: Implement VECTOR SUBTRACT
s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW
INDICATION
s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD
s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD
s390x/tcg: Implement VECTOR SUM ACROSS WORD
s390x/tcg: Implement VECTOR TEST UNDER MASK
target/s390x/Makefile.objs | 2 +-
target/s390x/cc_helper.c | 17 +
target/s390x/helper.c | 1 +
target/s390x/helper.h | 86 ++
target/s390x/insn-data.def | 137 +++
target/s390x/internal.h | 1 +
target/s390x/translate.c | 2 +
target/s390x/translate_vx.inc.c | 1473 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 716 +++++++++++++++
tcg/tcg-op-gvec.c | 139 +++
tcg/tcg-op-gvec.h | 24 +
11 files changed, 2597 insertions(+), 1 deletion(-)
create mode 100644 target/s390x/vec_int_helper.c
--
2.20.1
^ permalink raw reply [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
This is the second part of vector instruction support for s390x. It is
based on the series soon to land upstream:
[PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
Part 1: Vector Support Instructions
Part 2: Vector Integer Instructions
Part 3: Vector String Instructions
Part 4: Vector Floating-Point Instructions
The current state can be found at (kept updated):
https://github.com/davidhildenbrand/qemu/tree/vx
With the current state I can boot Linux kernel + user space compiled with
SIMD support. This allows to boot distributions compiled exclusively for
z13, requiring SIMD support. Also, it is now possible to build a complete
kernel using rpmbuild as quite some issues have been sorted out.
In this part, all Vector Integer Instructions introduced with the
"Vector Facility" are added. Some instructions part of the Vector Extension
Facilities are also added.
v1 -> v2:
- Many suggestions and fixes as outlined by Richard H.
-- Mostly avoid oom helpers for 128-bit add/sub variants
-- New vector helpers are not considered for now
David Hildenbrand (41):
tcg: Implement tcg_gen_gvec_3i()
s390x/tcg: Implement VECTOR ADD
s390x/tcg: Implement VECTOR ADD COMPUTE CARRY
s390x/tcg: Implement VECTOR ADD WITH CARRY
s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY
s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT)
s390x/tcg: Implement VECTOR AVERAGE
s390x/tcg: Implement VECTOR AVERAGE LOGICAL
s390x/tcg: Implement VECTOR CHECKSUM
s390x/tcg: Implement VECTOR ELEMENT COMPARE *
s390x/tcg: Implement VECTOR COMPARE *
s390x/tcg: Implement VECTOR COUNT LEADING ZEROS
s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS
s390x/tcg: Implement VECTOR EXCLUSIVE OR
s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)
s390x/tcg: Implement VECTOR LOAD COMPLEMENT
s390x/tcg: Implement VECTOR LOAD POSITIVE
s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)
s390x/tcg: Implement VECTOR MULTIPLY AND ADD *
s390x/tcg: Implement VECTOR MULTIPLY *
s390x/tcg: Implement VECTOR NAND
s390x/tcg: Implement VECTOR NOR
s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR
s390x/tcg: Implement VECTOR OR
s390x/tcg: Implement VECTOR OR WITH COMPLEMENT
s390x/tcg: Implement VECTOR POPULATION COUNT
s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL
s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
s390x/tcg: Implement VECTOR ELEMENT SHIFT
s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)
s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE
s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC
s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *
s390x/tcg: Implement VECTOR SUBTRACT
s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION
s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW
INDICATION
s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD
s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD
s390x/tcg: Implement VECTOR SUM ACROSS WORD
s390x/tcg: Implement VECTOR TEST UNDER MASK
target/s390x/Makefile.objs | 2 +-
target/s390x/cc_helper.c | 17 +
target/s390x/helper.c | 1 +
target/s390x/helper.h | 86 ++
target/s390x/insn-data.def | 137 +++
target/s390x/internal.h | 1 +
target/s390x/translate.c | 2 +
target/s390x/translate_vx.inc.c | 1473 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 716 +++++++++++++++
tcg/tcg-op-gvec.c | 139 +++
tcg/tcg-op-gvec.h | 24 +
11 files changed, 2597 insertions(+), 1 deletion(-)
create mode 100644 target/s390x/vec_int_helper.c
--
2.20.1
^ permalink raw reply [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.h | 24 ++++++++
2 files changed, 163 insertions(+)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 0996ef0812..f831adb4e7 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -663,6 +663,29 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i32(t0);
}
+static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int32_t c, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1, c);
+ tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -770,6 +793,29 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i64(t0);
}
+static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int64_t c, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1, c);
+ tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -883,6 +929,35 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/*
+ * Expand OPSZ bytes worth of three-vector operands and an immediate operand
+ * using host vectors.
+ */
+static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t tysz,
+ TCGType type, int64_t c, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec,
+ int64_t))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ }
+ fni(vece, t2, t0, t1, c);
+ tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+}
+
/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t cofs, uint32_t oprsz,
@@ -1174,6 +1249,70 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
}
}
+/* Expand a vector operation with three vectors and an immediate. */
+void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen3i *g)
+{
+ TCGType type;
+ uint32_t some;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ type = 0;
+ if (g->fniv) {
+ type = choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64);
+ }
+ switch (type) {
+ case TCG_TYPE_V256:
+ /*
+ * Recall that ARM SVE allows vector sizes that are not a
+ * power of 2, but always a multiple of 16. The intent is
+ * that e.g. size == 80 would be expanded with 2x32 + 1x16.
+ */
+ some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
+ c, g->load_dest, g->fniv);
+ if (some == oprsz) {
+ break;
+ }
+ dofs += some;
+ aofs += some;
+ bofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ /* fallthru */
+ case TCG_TYPE_V128:
+ expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
+ c, g->load_dest, g->fniv);
+ break;
+ case TCG_TYPE_V64:
+ expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
+ c, g->load_dest, g->fniv);
+ break;
+
+ case 0:
+ if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
+ return;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
/* Expand a vector four-operand operation. */
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 850da32ded..c093243c4c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -164,6 +164,27 @@ typedef struct {
bool load_dest;
} GVecGen3;
+typedef struct {
+ /*
+ * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
+ * non-NULL.
+ */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
+ /* Expand out-of-line helper w/descriptor, data in descriptor. */
+ gen_helper_gvec_3 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen3i;
+
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
@@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen3i *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.h | 24 ++++++++
2 files changed, 163 insertions(+)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 0996ef0812..f831adb4e7 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -663,6 +663,29 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i32(t0);
}
+static void expand_3i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int32_t c, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1, c);
+ tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -770,6 +793,29 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
tcg_temp_free_i64(t0);
}
+static void expand_3i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, int64_t c, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1, c);
+ tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t cofs, uint32_t oprsz, bool write_aofs,
@@ -883,6 +929,35 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/*
+ * Expand OPSZ bytes worth of three-vector operands and an immediate operand
+ * using host vectors.
+ */
+static void expand_3i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t tysz,
+ TCGType type, int64_t c, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec,
+ int64_t))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ }
+ fni(vece, t2, t0, t1, c);
+ tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+}
+
/* Expand OPSZ bytes worth of four-operand operations using host vectors. */
static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t cofs, uint32_t oprsz,
@@ -1174,6 +1249,70 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
}
}
+/* Expand a vector operation with three vectors and an immediate. */
+void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen3i *g)
+{
+ TCGType type;
+ uint32_t some;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ type = 0;
+ if (g->fniv) {
+ type = choose_vector_type(g->opc, g->vece, oprsz, g->prefer_i64);
+ }
+ switch (type) {
+ case TCG_TYPE_V256:
+ /*
+ * Recall that ARM SVE allows vector sizes that are not a
+ * power of 2, but always a multiple of 16. The intent is
+ * that e.g. size == 80 would be expanded with 2x32 + 1x16.
+ */
+ some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_3i_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
+ c, g->load_dest, g->fniv);
+ if (some == oprsz) {
+ break;
+ }
+ dofs += some;
+ aofs += some;
+ bofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ /* fallthru */
+ case TCG_TYPE_V128:
+ expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
+ c, g->load_dest, g->fniv);
+ break;
+ case TCG_TYPE_V64:
+ expand_3i_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
+ c, g->load_dest, g->fniv);
+ break;
+
+ case 0:
+ if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_3i_i64(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_3i_i32(dofs, aofs, bofs, oprsz, c, g->load_dest, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, c, g->fno);
+ return;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
/* Expand a vector four-operand operation. */
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *g)
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 850da32ded..c093243c4c 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -164,6 +164,27 @@ typedef struct {
bool load_dest;
} GVecGen3;
+typedef struct {
+ /*
+ * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
+ * non-NULL.
+ */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
+ /* Expand out-of-line helper w/descriptor, data in descriptor. */
+ gen_helper_gvec_3 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen3i;
+
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
@@ -193,6 +214,9 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
+void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen3i *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 02/41] s390x/tcg: Implement VECTOR ADD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Introduce two types of fancy new helpers that will be reused a couple of
times
1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3
parameters, simplifying parameter passing
2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations
using two 64 bit values per vector.
Luckily, for VECTOR ADD we already have everything we need.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 5 ++++
target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 71fa9b8d6c..74a0ccc770 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1054,6 +1054,11 @@
/* VECTOR UNPACK LOGICAL LOW */
F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
+/* === Vector Integer Instructions === */
+
+/* VECTOR ADD */
+ F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
+
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 76f9a5d939..2f84ea0511 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -157,6 +157,41 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16)
+
+/*
+ * Helper to carry out a 128 bit vector computation using 2 i64 values per
+ * vector.
+ */
+typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
+static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+}
static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
{
@@ -933,3 +968,20 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_va(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(add, es, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 02/41] s390x/tcg: Implement VECTOR ADD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Introduce two types of fancy new helpers that will be reused a couple of
times
1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3
parameters, simplifying parameter passing
2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations
using two 64 bit values per vector.
Luckily, for VECTOR ADD we already have everything we need.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 5 ++++
target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 71fa9b8d6c..74a0ccc770 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1054,6 +1054,11 @@
/* VECTOR UNPACK LOGICAL LOW */
F(0xe7d4, VUPLL, VRR_a, V, 0, 0, 0, 0, vup, 0, IF_VEC)
+/* === Vector Integer Instructions === */
+
+/* VECTOR ADD */
+ F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
+
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
E(0xb250, CSP, RRE, Z, r1_32u, ra2, r1_P, 0, csp, 0, MO_TEUL, IF_PRIV)
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 76f9a5d939..2f84ea0511 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -157,6 +157,41 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16)
+
+/*
+ * Helper to carry out a 128 bit vector computation using 2 i64 values per
+ * vector.
+ */
+typedef void (*gen_gvec128_3_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
+static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+}
static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
{
@@ -933,3 +968,20 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_va(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(add, es, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 03/41] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
128-bit handling courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 +
target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 74a0ccc770..f0e62b9aa8 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1058,6 +1058,8 @@
/* VECTOR ADD */
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
+/* VECTOR ADD COMPUTE CARRY */
+ F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 2f84ea0511..312c5f67be 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -136,6 +136,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
tcg_temp_free_i64(tmp);
}
+#define gen_gvec_3(v1, v2, v3, gen) \
+ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, gen)
#define gen_gvec_3_ool(v1, v2, v3, data, fn) \
tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, data, fn)
@@ -985,3 +988,94 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
+{
+ const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
+ TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ /* Calculate the carry into the MSB, ignoring the old MSBs */
+ tcg_gen_andc_i64(t1, a, msb_mask);
+ tcg_gen_andc_i64(t2, b, msb_mask);
+ tcg_gen_add_i64(t1, t1, t2);
+ /* Calculate the MSB without any carry into it */
+ tcg_gen_xor_i64(t3, a, b);
+ /* Calculate the carry out of the MSB in the MSB bit position */
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_and_i64(t1, t1, t3);
+ tcg_gen_or_i64(d, d, t1);
+ /* Isolate and shift the carry into position */
+ tcg_gen_and_i64(d, d, msb_mask);
+ tcg_gen_shri_i64(d, d, msb_bit_nr);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_8);
+}
+
+static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_16);
+}
+
+static void gen_acc32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_32);
+}
+
+static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_add_i64(t, a, b);
+ tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_acc8_i64, },
+ { .fni8 = gen_acc16_i64, },
+ { .fni8 = gen_acc32_i64, },
+ { .fni8 = gen_acc_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_acc2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 03/41] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
128-bit handling courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 +
target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 74a0ccc770..f0e62b9aa8 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1058,6 +1058,8 @@
/* VECTOR ADD */
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
+/* VECTOR ADD COMPUTE CARRY */
+ F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 2f84ea0511..312c5f67be 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -136,6 +136,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
tcg_temp_free_i64(tmp);
}
+#define gen_gvec_3(v1, v2, v3, gen) \
+ tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), 16, 16, gen)
#define gen_gvec_3_ool(v1, v2, v3, data, fn) \
tcg_gen_gvec_3_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, data, fn)
@@ -985,3 +988,94 @@ static DisasJumpType op_va(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es)
+{
+ const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1;
+ TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr));
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ /* Calculate the carry into the MSB, ignoring the old MSBs */
+ tcg_gen_andc_i64(t1, a, msb_mask);
+ tcg_gen_andc_i64(t2, b, msb_mask);
+ tcg_gen_add_i64(t1, t1, t2);
+ /* Calculate the MSB without any carry into it */
+ tcg_gen_xor_i64(t3, a, b);
+ /* Calculate the carry out of the MSB in the MSB bit position */
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_and_i64(t1, t1, t3);
+ tcg_gen_or_i64(d, d, t1);
+ /* Isolate and shift the carry into position */
+ tcg_gen_and_i64(d, d, msb_mask);
+ tcg_gen_shri_i64(d, d, msb_bit_nr);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_8);
+}
+
+static void gen_acc16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_16);
+}
+
+static void gen_acc32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ gen_acc(d, a, b, ES_32);
+}
+
+static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_add_i64(t, a, b);
+ tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_acc8_i64, },
+ { .fni8 = gen_acc16_i64, },
+ { .fni8 = gen_acc32_i64, },
+ { .fni8 = gen_acc_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_acc2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 04/41] s390x/tcg: Implement VECTOR ADD WITH CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Only slightly ugly, perform two additions. At least it is only supported
for 128 bit elements.
Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 63 +++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f0e62b9aa8..38d1e22a6d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1060,6 +1060,8 @@
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
/* VECTOR ADD COMPUTE CARRY */
F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
+/* VECTOR ADD WITH CARRY */
+ F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 312c5f67be..c70f380209 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -196,6 +196,41 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
tcg_temp_free_i64(bl);
}
+typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh,
+ TCGv_i64 cl, TCGv_i64 ch);
+static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b, uint8_t c)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+ TCGv_i64 ch = tcg_temp_new_i64();
+ TCGv_i64 cl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ read_vec_element_i64(ch, c, 0, ES_64);
+ read_vec_element_i64(cl, c, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh, cl, ch);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(ch);
+ tcg_temp_free_i64(cl);
+}
+
static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
{
switch (es) {
@@ -1079,3 +1114,31 @@ static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_const_i64(0);
+
+ /* extract the carry only */
+ tcg_gen_extract_i64(tl, cl, 0, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_gen_add2_i64(dl, dh, dl, dh, tl, th);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+}
+
+static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_ac2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 04/41] s390x/tcg: Implement VECTOR ADD WITH CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Only slightly ugly, perform two additions. At least it is only supported
for 128 bit elements.
Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 63 +++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f0e62b9aa8..38d1e22a6d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1060,6 +1060,8 @@
F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC)
/* VECTOR ADD COMPUTE CARRY */
F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
+/* VECTOR ADD WITH CARRY */
+ F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 312c5f67be..c70f380209 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -196,6 +196,41 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn, uint8_t d, uint8_t a,
tcg_temp_free_i64(bl);
}
+typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh,
+ TCGv_i64 cl, TCGv_i64 ch);
+static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
+ uint8_t b, uint8_t c)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 dl = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 al = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+ TCGv_i64 bl = tcg_temp_new_i64();
+ TCGv_i64 ch = tcg_temp_new_i64();
+ TCGv_i64 cl = tcg_temp_new_i64();
+
+ read_vec_element_i64(ah, a, 0, ES_64);
+ read_vec_element_i64(al, a, 1, ES_64);
+ read_vec_element_i64(bh, b, 0, ES_64);
+ read_vec_element_i64(bl, b, 1, ES_64);
+ read_vec_element_i64(ch, c, 0, ES_64);
+ read_vec_element_i64(cl, c, 1, ES_64);
+ fn(dl, dh, al, ah, bl, bh, cl, ch);
+ write_vec_element_i64(dh, d, 0, ES_64);
+ write_vec_element_i64(dl, d, 1, ES_64);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(dl);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(ch);
+ tcg_temp_free_i64(cl);
+}
+
static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
{
switch (es) {
@@ -1079,3 +1114,31 @@ static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_const_i64(0);
+
+ /* extract the carry only */
+ tcg_gen_extract_i64(tl, cl, 0, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_gen_add2_i64(dl, dh, dl, dh, tl, th);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+}
+
+static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_ac2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only.
Courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 38d1e22a6d..a531b21908 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1062,6 +1062,8 @@
F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
/* VECTOR ADD WITH CARRY */
F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
+/* VECTOR ADD WITH CARRY COMPUTE CARRY */
+ F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index c70f380209..6fb93d9aa9 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1142,3 +1142,35 @@ static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_add2_i64(tl, th, tl, zero, al, zero);
+ tcg_gen_add2_i64(tl, th, tl, th, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_accc2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only.
Courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 38d1e22a6d..a531b21908 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1062,6 +1062,8 @@
F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC)
/* VECTOR ADD WITH CARRY */
F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
+/* VECTOR ADD WITH CARRY COMPUTE CARRY */
+ F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index c70f380209..6fb93d9aa9 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1142,3 +1142,35 @@ static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_add2_i64(tl, th, tl, zero, al, zero);
+ tcg_gen_add2_i64(tl, th, tl, th, bl, zero);
+ tcg_gen_add2_i64(tl, th, th, zero, ah, zero);
+ tcg_gen_add2_i64(tl, dl, tl, th, bh, zero);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_accc2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 06/41] s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Easy, as we can reuse existing gvec helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a531b21908..456d5597ca 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1064,6 +1064,10 @@
F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
/* VECTOR ADD WITH CARRY COMPUTE CARRY */
F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
+/* VECTOR AND */
+ F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
+/* VECTOR AND WITH COMPLEMENT */
+ F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6fb93d9aa9..9ee7978c77 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1174,3 +1174,17 @@ static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(and, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(andc, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 06/41] s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Easy, as we can reuse existing gvec helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a531b21908..456d5597ca 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1064,6 +1064,10 @@
F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC)
/* VECTOR ADD WITH CARRY COMPUTE CARRY */
F(0xe7b9, VACCC, VRR_d, V, 0, 0, 0, 0, vaccc, 0, IF_VEC)
+/* VECTOR AND */
+ F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
+/* VECTOR AND WITH COMPLEMENT */
+ F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6fb93d9aa9..9ee7978c77 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1174,3 +1174,17 @@ static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(and, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(andc, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 07/41] s390x/tcg: Implement VECTOR AVERAGE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via
ool helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/Makefile.objs | 2 +-
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 64 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 32 +++++++++++++++++
5 files changed, 103 insertions(+), 1 deletion(-)
create mode 100644 target/s390x/vec_int_helper.c
diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs
index 68eeee3d2f..993ac93ed6 100644
--- a/target/s390x/Makefile.objs
+++ b/target/s390x/Makefile.objs
@@ -1,7 +1,7 @@
obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
-obj-$(CONFIG_TCG) += vec_helper.o
+obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
obj-$(CONFIG_SOFTMMU) += sigp.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 0b494a2fd2..add1d332e5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -145,6 +145,10 @@ DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
+/* === Vector Integer Instructions === */
+DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
DEF_HELPER_4(diag, void, env, i32, i32, i32)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 456d5597ca..6f8b42e327 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1068,6 +1068,8 @@
F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
/* VECTOR AND WITH COMPLEMENT */
F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
+/* VECTOR AVERAGE */
+ F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9ee7978c77..5108025506 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -256,6 +256,17 @@ static void zero_vec(uint8_t reg)
tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
}
+static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ uint64_t b)
+{
+ TCGv_i64 bl = tcg_const_i64(b);
+ TCGv_i64 bh = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(bh);
+}
+
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
@@ -1188,3 +1199,56 @@ static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
get_field(s->fields, v2), get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+
+ /* extending the sign by one bit is sufficient */
+ tcg_gen_extract_i64(ah, al, 63, 1);
+ tcg_gen_extract_i64(bh, bl, 63, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(bh);
+}
+
+static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavg8, },
+ { .fno = gen_helper_gvec_vavg16, },
+ { .fni4 = gen_avg_i32, },
+ { .fni8 = gen_avg_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
new file mode 100644
index 0000000000..d964655bb8
--- /dev/null
+++ b/target/s390x/vec_int_helper.c
@@ -0,0 +1,32 @@
+/*
+ * QEMU TCG support -- s390x vector integer instruction support
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "vec.h"
+#include "exec/helper-proto.h"
+
+#define DEF_VAVG(BITS) \
+void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
+ } \
+}
+DEF_VAVG(8)
+DEF_VAVG(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 07/41] s390x/tcg: Implement VECTOR AVERAGE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via
ool helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/Makefile.objs | 2 +-
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 64 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 32 +++++++++++++++++
5 files changed, 103 insertions(+), 1 deletion(-)
create mode 100644 target/s390x/vec_int_helper.c
diff --git a/target/s390x/Makefile.objs b/target/s390x/Makefile.objs
index 68eeee3d2f..993ac93ed6 100644
--- a/target/s390x/Makefile.objs
+++ b/target/s390x/Makefile.objs
@@ -1,7 +1,7 @@
obj-y += cpu.o cpu_models.o cpu_features.o gdbstub.o interrupt.o helper.o
obj-$(CONFIG_TCG) += translate.o cc_helper.o excp_helper.o fpu_helper.o
obj-$(CONFIG_TCG) += int_helper.o mem_helper.o misc_helper.o crypto_helper.o
-obj-$(CONFIG_TCG) += vec_helper.o
+obj-$(CONFIG_TCG) += vec_helper.o vec_int_helper.o
obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o arch_dump.o mmu_helper.o diag.o
obj-$(CONFIG_SOFTMMU) += sigp.o
obj-$(CONFIG_KVM) += kvm.o
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 0b494a2fd2..add1d332e5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -145,6 +145,10 @@ DEF_HELPER_5(gvec_vpkls_cc64, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
+/* === Vector Integer Instructions === */
+DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
DEF_HELPER_4(diag, void, env, i32, i32, i32)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 456d5597ca..6f8b42e327 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1068,6 +1068,8 @@
F(0xe768, VN, VRR_c, V, 0, 0, 0, 0, vn, 0, IF_VEC)
/* VECTOR AND WITH COMPLEMENT */
F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
+/* VECTOR AVERAGE */
+ F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 9ee7978c77..5108025506 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -256,6 +256,17 @@ static void zero_vec(uint8_t reg)
tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
}
+static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ uint64_t b)
+{
+ TCGv_i64 bl = tcg_const_i64(b);
+ TCGv_i64 bh = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ tcg_temp_free_i64(bl);
+ tcg_temp_free_i64(bh);
+}
+
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
@@ -1188,3 +1199,56 @@ static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
get_field(s->fields, v2), get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 ah = tcg_temp_new_i64();
+ TCGv_i64 bh = tcg_temp_new_i64();
+
+ /* extending the sign by one bit is sufficient */
+ tcg_gen_extract_i64(ah, al, 63, 1);
+ tcg_gen_extract_i64(bh, bl, 63, 1);
+ tcg_gen_add2_i64(dl, dh, al, ah, bl, bh);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(bh);
+}
+
+static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavg8, },
+ { .fno = gen_helper_gvec_vavg16, },
+ { .fni4 = gen_avg_i32, },
+ { .fni8 = gen_avg_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
new file mode 100644
index 0000000000..d964655bb8
--- /dev/null
+++ b/target/s390x/vec_int_helper.c
@@ -0,0 +1,32 @@
+/*
+ * QEMU TCG support -- s390x vector integer instruction support
+ *
+ * Copyright (C) 2019 Red Hat Inc
+ *
+ * Authors:
+ * David Hildenbrand <david@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "vec.h"
+#include "exec/helper-proto.h"
+
+#define DEF_VAVG(BITS) \
+void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
+ } \
+}
+DEF_VAVG(8)
+DEF_VAVG(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 08/41] s390x/tcg: Implement VECTOR AVERAGE LOGICAL
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR AVERAGE but without sign extension.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 48 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 16 +++++++++++
4 files changed, 68 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index add1d332e5..21921397fe 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -148,6 +148,8 @@ DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
/* === Vector Integer Instructions === */
DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 6f8b42e327..9889dc0b01 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1070,6 +1070,8 @@
F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
/* VECTOR AVERAGE */
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
+/* VECTOR AVERAGE LOGICAL */
+ F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5108025506..7e8418e585 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1252,3 +1252,51 @@ static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavgl8, },
+ { .fno = gen_helper_gvec_vavgl16, },
+ { .fni4 = gen_avgl_i32, },
+ { .fni8 = gen_avgl_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index d964655bb8..8f97d3f466 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -30,3 +30,19 @@ void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VAVG(8)
DEF_VAVG(16)
+
+#define DEF_VAVGL(BITS) \
+void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
+ } \
+}
+DEF_VAVGL(8)
+DEF_VAVGL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 08/41] s390x/tcg: Implement VECTOR AVERAGE LOGICAL
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR AVERAGE but without sign extension.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 48 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 16 +++++++++++
4 files changed, 68 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index add1d332e5..21921397fe 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -148,6 +148,8 @@ DEF_HELPER_FLAGS_4(vstl, TCG_CALL_NO_WG, void, env, cptr, i64, i64)
/* === Vector Integer Instructions === */
DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 6f8b42e327..9889dc0b01 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1070,6 +1070,8 @@
F(0xe769, VNC, VRR_c, V, 0, 0, 0, 0, vnc, 0, IF_VEC)
/* VECTOR AVERAGE */
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
+/* VECTOR AVERAGE LOGICAL */
+ F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5108025506..7e8418e585 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1252,3 +1252,51 @@ static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_add_i64(t0, t0, t1);
+ tcg_gen_addi_i64(t0, t0, 1);
+ tcg_gen_shri_i64(t0, t0, 1);
+ tcg_gen_extrl_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl)
+{
+ TCGv_i64 dh = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_add2_i64(dl, dh, al, zero, bl, zero);
+ gen_addi2_i64(dl, dh, dl, dh, 1);
+ tcg_gen_extract2_i64(dl, dl, dh, 1);
+
+ tcg_temp_free_i64(dh);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vavgl8, },
+ { .fno = gen_helper_gvec_vavgl16, },
+ { .fni4 = gen_avgl_i32, },
+ { .fni8 = gen_avgl_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index d964655bb8..8f97d3f466 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -30,3 +30,19 @@ void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VAVG(8)
DEF_VAVG(16)
+
+#define DEF_VAVGL(BITS) \
+void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a + b + 1) >> 1); \
+ } \
+}
+DEF_VAVGL(8)
+DEF_VAVGL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 09/41] s390x/tcg: Implement VECTOR CHECKSUM
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Time to introduce read_vec_element_i32 and write_vec_element_i32.
Take proper care of properly adding the carry. We can perform both
additions including the carry via tcg_gen_add2_i32().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 +
target/s390x/translate_vx.inc.c | 65 +++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 9889dc0b01..64459465c5 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1072,6 +1072,8 @@
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
/* VECTOR AVERAGE LOGICAL */
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
+/* VECTOR CHECKSUM */
+ F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7e8418e585..0f90f981b6 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -90,6 +90,33 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
}
}
+static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_ld8u_i32(dst, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i32(dst, cpu_env, offs);
+ break;
+ case ES_8 | MO_SIGN:
+ tcg_gen_ld8s_i32(dst, cpu_env, offs);
+ break;
+ case ES_16 | MO_SIGN:
+ tcg_gen_ld16s_i32(dst, cpu_env, offs);
+ break;
+ case ES_32:
+ case ES_32 | MO_SIGN:
+ tcg_gen_ld_i32(dst, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
TCGMemOp memop)
{
@@ -113,6 +140,25 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_st8_i32(src, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_st16_i32(src, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_st_i32(src, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
uint8_t es)
@@ -1300,3 +1346,22 @@ static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 sum = tcg_temp_new_i32();
+ int i;
+
+ read_vec_element_i32(sum, get_field(s->fields, v3), 1, ES_32);
+ for (i = 0; i < 4; i++) {
+ read_vec_element_i32(tmp, get_field(s->fields, v2), i, ES_32);
+ tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
+ }
+ zero_vec(get_field(s->fields, v1));
+ write_vec_element_i32(sum, get_field(s->fields, v1), 1, ES_32);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(sum);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 09/41] s390x/tcg: Implement VECTOR CHECKSUM
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Time to introduce read_vec_element_i32 and write_vec_element_i32.
Take proper care of properly adding the carry. We can perform both
additions including the carry via tcg_gen_add2_i32().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 +
target/s390x/translate_vx.inc.c | 65 +++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 9889dc0b01..64459465c5 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1072,6 +1072,8 @@
F(0xe7f2, VAVG, VRR_c, V, 0, 0, 0, 0, vavg, 0, IF_VEC)
/* VECTOR AVERAGE LOGICAL */
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
+/* VECTOR CHECKSUM */
+ F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7e8418e585..0f90f981b6 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -90,6 +90,33 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
}
}
+static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_ld8u_i32(dst, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_ld16u_i32(dst, cpu_env, offs);
+ break;
+ case ES_8 | MO_SIGN:
+ tcg_gen_ld8s_i32(dst, cpu_env, offs);
+ break;
+ case ES_16 | MO_SIGN:
+ tcg_gen_ld16s_i32(dst, cpu_env, offs);
+ break;
+ case ES_32:
+ case ES_32 | MO_SIGN:
+ tcg_gen_ld_i32(dst, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
TCGMemOp memop)
{
@@ -113,6 +140,25 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr,
}
}
+static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr,
+ TCGMemOp memop)
+{
+ const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
+
+ switch (memop) {
+ case ES_8:
+ tcg_gen_st8_i32(src, cpu_env, offs);
+ break;
+ case ES_16:
+ tcg_gen_st16_i32(src, cpu_env, offs);
+ break;
+ case ES_32:
+ tcg_gen_st_i32(src, cpu_env, offs);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
uint8_t es)
@@ -1300,3 +1346,22 @@ static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 sum = tcg_temp_new_i32();
+ int i;
+
+ read_vec_element_i32(sum, get_field(s->fields, v3), 1, ES_32);
+ for (i = 0; i < 4; i++) {
+ read_vec_element_i32(tmp, get_field(s->fields, v2), i, ES_32);
+ tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
+ }
+ zero_vec(get_field(s->fields, v1));
+ write_vec_element_i32(sum, get_field(s->fields, v1), 1, ES_32);
+
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i32(sum);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 10/41] s390x/tcg: Implement VECTOR ELEMENT COMPARE *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Fairly easy to implement, we can make use of the existing CC helpers
cmps64 and cmpu64 - we siply have to sign extend the elements.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 20 ++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 64459465c5..52e398f515 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1074,6 +1074,10 @@
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
/* VECTOR CHECKSUM */
F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
+/* VECTOR ELEMENT COMPARE */
+ F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
+/* VECTOR ELEMENT COMPARE LOGICAL */
+ F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0f90f981b6..3f29d3b67a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1365,3 +1365,23 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(sum);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
+{
+ uint8_t es = get_field(s->fields, m3);
+ const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ if (s->fields->op2 == 0xdb) {
+ es |= MO_SIGN;
+ }
+
+ o->in1 = tcg_temp_new_i64();
+ o->in2 = tcg_temp_new_i64();
+ read_vec_element_i64(o->in1, get_field(s->fields, v1), enr, es);
+ read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 10/41] s390x/tcg: Implement VECTOR ELEMENT COMPARE *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Fairly easy to implement, we can make use of the existing CC helpers
cmps64 and cmpu64 - we siply have to sign extend the elements.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 20 ++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 64459465c5..52e398f515 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1074,6 +1074,10 @@
F(0xe7f0, VAVGL, VRR_c, V, 0, 0, 0, 0, vavgl, 0, IF_VEC)
/* VECTOR CHECKSUM */
F(0xe766, VCKSM, VRR_c, V, 0, 0, 0, 0, vcksm, 0, IF_VEC)
+/* VECTOR ELEMENT COMPARE */
+ F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
+/* VECTOR ELEMENT COMPARE LOGICAL */
+ F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0f90f981b6..3f29d3b67a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1365,3 +1365,23 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(sum);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
+{
+ uint8_t es = get_field(s->fields, m3);
+ const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ if (s->fields->op2 == 0xdb) {
+ es |= MO_SIGN;
+ }
+
+ o->in1 = tcg_temp_new_i64();
+ o->in2 = tcg_temp_new_i64();
+ read_vec_element_i64(o->in1, get_field(s->fields, v1), enr, es);
+ read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 11/41] s390x/tcg: Implement VECTOR COMPARE *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
To carry out the comparison, we can reuse the existing gvec comparison
function. In case the CC is to be computed, save the result vector
and compute the CC lazily. The result is a vector consisting of all 1's
for elements that matched and 0's for elements that didn't match.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cc_helper.c | 17 +++++++++++++++++
target/s390x/helper.c | 1 +
target/s390x/insn-data.def | 6 ++++++
target/s390x/internal.h | 1 +
target/s390x/translate.c | 1 +
target/s390x/translate_vx.inc.c | 28 ++++++++++++++++++++++++++++
6 files changed, 54 insertions(+)
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 0e467bf2b6..a00294f183 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -402,6 +402,20 @@ static uint32_t cc_calc_lcbb(uint64_t dst)
return dst == 16 ? 0 : 3;
}
+static uint32_t cc_calc_vc(uint64_t low, uint64_t high)
+{
+ if (high == -1ull && low == -1ull) {
+ /* all elements match */
+ return 0;
+ } else if (high == 0 && low == 0) {
+ /* no elements match */
+ return 3;
+ } else {
+ /* some elements but not all match */
+ return 1;
+ }
+}
+
static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
uint64_t src, uint64_t dst, uint64_t vr)
{
@@ -514,6 +528,9 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
case CC_OP_LCBB:
r = cc_calc_lcbb(dst);
break;
+ case CC_OP_VC:
+ r = cc_calc_vc(src, dst);
+ break;
case CC_OP_NZ_F32:
r = set_cc_nz_f32(dst);
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 8e9573221c..946de15503 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -418,6 +418,7 @@ const char *cc_name(enum cc_op cc_op)
[CC_OP_SLA_64] = "CC_OP_SLA_64",
[CC_OP_FLOGR] = "CC_OP_FLOGR",
[CC_OP_LCBB] = "CC_OP_LCBB",
+ [CC_OP_VC] = "CC_OP_VC",
};
return cc_names[cc_op];
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 52e398f515..1d159cb201 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1078,6 +1078,12 @@
F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
/* VECTOR ELEMENT COMPARE LOGICAL */
F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
+/* VECTOR COMPARE EQUAL */
+ E(0xe7f8, VCEQ, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_EQ, IF_VEC)
+/* VECTOR COMPARE HIGH */
+ E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
+/* VECTOR COMPARE HIGH LOGICAL */
+ E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 3b4855c175..00b00fece5 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -200,6 +200,7 @@ enum cc_op {
CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
CC_OP_FLOGR, /* find leftmost one */
CC_OP_LCBB, /* load count to block boundary */
+ CC_OP_VC, /* vector compare result */
CC_OP_MAX
};
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 0afa8f7ca5..a800aa9dc9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -572,6 +572,7 @@ static void gen_op_calc_cc(DisasContext *s)
case CC_OP_SLA_32:
case CC_OP_SLA_64:
case CC_OP_NZ_F128:
+ case CC_OP_VC:
/* 2 arguments */
gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
break;
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 3f29d3b67a..3e4e28c742 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1385,3 +1385,31 @@ static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGCond cond = s->insn->data;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tcg_gen_gvec_cmp(cond, es,
+ vec_full_reg_offset(get_field(s->fields, v1)),
+ vec_full_reg_offset(get_field(s->fields, v2)),
+ vec_full_reg_offset(get_field(s->fields, v3)), 16, 16);
+ if (get_field(s->fields, m5) & 0x1) {
+ TCGv_i64 low = tcg_temp_new_i64();
+ TCGv_i64 high = tcg_temp_new_i64();
+
+ read_vec_element_i64(high, get_field(s->fields, v1), 0, ES_64);
+ read_vec_element_i64(low, get_field(s->fields, v1), 1, ES_64);
+ gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
+
+ tcg_temp_free_i64(low);
+ tcg_temp_free_i64(high);
+ }
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 11/41] s390x/tcg: Implement VECTOR COMPARE *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
To carry out the comparison, we can reuse the existing gvec comparison
function. In case the CC is to be computed, save the result vector
and compute the CC lazily. The result is a vector consisting of all 1's
for elements that matched and 0's for elements that didn't match.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/cc_helper.c | 17 +++++++++++++++++
target/s390x/helper.c | 1 +
target/s390x/insn-data.def | 6 ++++++
target/s390x/internal.h | 1 +
target/s390x/translate.c | 1 +
target/s390x/translate_vx.inc.c | 28 ++++++++++++++++++++++++++++
6 files changed, 54 insertions(+)
diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c
index 0e467bf2b6..a00294f183 100644
--- a/target/s390x/cc_helper.c
+++ b/target/s390x/cc_helper.c
@@ -402,6 +402,20 @@ static uint32_t cc_calc_lcbb(uint64_t dst)
return dst == 16 ? 0 : 3;
}
+static uint32_t cc_calc_vc(uint64_t low, uint64_t high)
+{
+ if (high == -1ull && low == -1ull) {
+ /* all elements match */
+ return 0;
+ } else if (high == 0 && low == 0) {
+ /* no elements match */
+ return 3;
+ } else {
+ /* some elements but not all match */
+ return 1;
+ }
+}
+
static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
uint64_t src, uint64_t dst, uint64_t vr)
{
@@ -514,6 +528,9 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
case CC_OP_LCBB:
r = cc_calc_lcbb(dst);
break;
+ case CC_OP_VC:
+ r = cc_calc_vc(src, dst);
+ break;
case CC_OP_NZ_F32:
r = set_cc_nz_f32(dst);
diff --git a/target/s390x/helper.c b/target/s390x/helper.c
index 8e9573221c..946de15503 100644
--- a/target/s390x/helper.c
+++ b/target/s390x/helper.c
@@ -418,6 +418,7 @@ const char *cc_name(enum cc_op cc_op)
[CC_OP_SLA_64] = "CC_OP_SLA_64",
[CC_OP_FLOGR] = "CC_OP_FLOGR",
[CC_OP_LCBB] = "CC_OP_LCBB",
+ [CC_OP_VC] = "CC_OP_VC",
};
return cc_names[cc_op];
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 52e398f515..1d159cb201 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1078,6 +1078,12 @@
F(0xe7db, VEC, VRR_a, V, 0, 0, 0, 0, vec, cmps64, IF_VEC)
/* VECTOR ELEMENT COMPARE LOGICAL */
F(0xe7d9, VECL, VRR_a, V, 0, 0, 0, 0, vec, cmpu64, IF_VEC)
+/* VECTOR COMPARE EQUAL */
+ E(0xe7f8, VCEQ, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_EQ, IF_VEC)
+/* VECTOR COMPARE HIGH */
+ E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
+/* VECTOR COMPARE HIGH LOGICAL */
+ E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index 3b4855c175..00b00fece5 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -200,6 +200,7 @@ enum cc_op {
CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
CC_OP_FLOGR, /* find leftmost one */
CC_OP_LCBB, /* load count to block boundary */
+ CC_OP_VC, /* vector compare result */
CC_OP_MAX
};
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 0afa8f7ca5..a800aa9dc9 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -572,6 +572,7 @@ static void gen_op_calc_cc(DisasContext *s)
case CC_OP_SLA_32:
case CC_OP_SLA_64:
case CC_OP_NZ_F128:
+ case CC_OP_VC:
/* 2 arguments */
gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, dummy);
break;
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 3f29d3b67a..3e4e28c742 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1385,3 +1385,31 @@ static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGCond cond = s->insn->data;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ tcg_gen_gvec_cmp(cond, es,
+ vec_full_reg_offset(get_field(s->fields, v1)),
+ vec_full_reg_offset(get_field(s->fields, v2)),
+ vec_full_reg_offset(get_field(s->fields, v3)), 16, 16);
+ if (get_field(s->fields, m5) & 0x1) {
+ TCGv_i64 low = tcg_temp_new_i64();
+ TCGv_i64 high = tcg_temp_new_i64();
+
+ read_vec_element_i64(high, get_field(s->fields, v1), 0, ES_64);
+ read_vec_element_i64(low, get_field(s->fields, v1), 1, ES_64);
+ gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
+
+ tcg_temp_free_i64(low);
+ tcg_temp_free_i64(high);
+ }
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 12/41] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
For 8/16, use the 32 bit variant and properly subtract the added
leading zero bits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 49 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 21921397fe..670677427c 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -150,6 +150,8 @@ DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 1d159cb201..be3c07aafb 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1084,6 +1084,8 @@
E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
/* VECTOR COMPARE HIGH LOGICAL */
E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
+/* VECTOR COUNT LEADING ZEROS */
+ F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 3e4e28c742..5f17dbec3f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -182,6 +182,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
tcg_temp_free_i64(tmp);
}
+#define gen_gvec_2(v1, v2, gen) \
+ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, gen)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -1413,3 +1416,31 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_clzi_i32(d, a, 32);
+}
+
+static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_clzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vclz8, },
+ { .fno = gen_helper_gvec_vclz16, },
+ { .fni4 = gen_clz_i32, },
+ { .fni8 = gen_clz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 8f97d3f466..016512547c 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -46,3 +46,17 @@ void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VAVGL(8)
DEF_VAVGL(16)
+
+#define DEF_VCLZ(BITS) \
+void HELPER(gvec_vclz##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, clz32(a) - 32 + BITS); \
+ } \
+}
+DEF_VCLZ(8)
+DEF_VCLZ(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 12/41] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
For 8/16, use the 32 bit variant and properly subtract the added
leading zero bits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 31 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 49 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 21921397fe..670677427c 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -150,6 +150,8 @@ DEF_HELPER_FLAGS_4(gvec_vavg8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavg16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 1d159cb201..be3c07aafb 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1084,6 +1084,8 @@
E(0xe7fb, VCH, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GT, IF_VEC)
/* VECTOR COMPARE HIGH LOGICAL */
E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
+/* VECTOR COUNT LEADING ZEROS */
+ F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 3e4e28c742..5f17dbec3f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -182,6 +182,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
tcg_temp_free_i64(tmp);
}
+#define gen_gvec_2(v1, v2, gen) \
+ tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, gen)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -1413,3 +1416,31 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static void gen_clz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_clzi_i32(d, a, 32);
+}
+
+static void gen_clz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_clzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vclz8, },
+ { .fno = gen_helper_gvec_vclz16, },
+ { .fni4 = gen_clz_i32, },
+ { .fni8 = gen_clz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 8f97d3f466..016512547c 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -46,3 +46,17 @@ void HELPER(gvec_vavgl##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VAVGL(8)
DEF_VAVGL(16)
+
+#define DEF_VCLZ(BITS) \
+void HELPER(gvec_vclz##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, clz32(a) - 32 + BITS); \
+ } \
+}
+DEF_VCLZ(8)
+DEF_VCLZ(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 13/41] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Implement it similar to VECTOR COUNT LEADING ZEROS.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 28 ++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 46 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 670677427c..60b8bd3c43 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -152,6 +152,8 @@ DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vctz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vctz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index be3c07aafb..a355b7f62f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1086,6 +1086,8 @@
E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
/* VECTOR COUNT LEADING ZEROS */
F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
+/* VECTOR COUNT TRAILING ZEROS */
+ F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5f17dbec3f..ac1a2d77ad 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1444,3 +1444,31 @@ static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_ctzi_i32(d, a, 32);
+}
+
+static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_ctzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vctz8, },
+ { .fno = gen_helper_gvec_vctz16, },
+ { .fni4 = gen_ctz_i32, },
+ { .fni8 = gen_ctz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 016512547c..d1b1f28509 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -60,3 +60,17 @@ void HELPER(gvec_vclz##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VCLZ(8)
DEF_VCLZ(16)
+
+#define DEF_VCTZ(BITS) \
+void HELPER(gvec_vctz##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a ? ctz32(a) : BITS); \
+ } \
+}
+DEF_VCTZ(8)
+DEF_VCTZ(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 13/41] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Implement it similar to VECTOR COUNT LEADING ZEROS.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 28 ++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 46 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 670677427c..60b8bd3c43 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -152,6 +152,8 @@ DEF_HELPER_FLAGS_4(gvec_vavgl8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vavgl16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vctz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vctz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index be3c07aafb..a355b7f62f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1086,6 +1086,8 @@
E(0xe7f9, VCHL, VRR_b, V, 0, 0, 0, 0, vc, 0, TCG_COND_GTU, IF_VEC)
/* VECTOR COUNT LEADING ZEROS */
F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
+/* VECTOR COUNT TRAILING ZEROS */
+ F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5f17dbec3f..ac1a2d77ad 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1444,3 +1444,31 @@ static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_ctz_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ tcg_gen_ctzi_i32(d, a, 32);
+}
+
+static void gen_ctz_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ tcg_gen_ctzi_i64(d, a, 64);
+}
+
+static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vctz8, },
+ { .fno = gen_helper_gvec_vctz16, },
+ { .fni4 = gen_ctz_i32, },
+ { .fni8 = gen_ctz_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 016512547c..d1b1f28509 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -60,3 +60,17 @@ void HELPER(gvec_vclz##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VCLZ(8)
DEF_VCLZ(16)
+
+#define DEF_VCTZ(BITS) \
+void HELPER(gvec_vctz##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a ? ctz32(a) : BITS); \
+ } \
+}
+DEF_VCTZ(8)
+DEF_VCTZ(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 14/41] s390x/tcg: Implement VECTOR EXCLUSIVE OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Easy, we can reuse an existing gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a355b7f62f..b8400c191a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1088,6 +1088,8 @@
F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
/* VECTOR COUNT TRAILING ZEROS */
F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
+/* VECTOR EXCLUSIVE OR */
+ F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index ac1a2d77ad..0c67f53d1c 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1472,3 +1472,10 @@ static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(xor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 14/41] s390x/tcg: Implement VECTOR EXCLUSIVE OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Easy, we can reuse an existing gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a355b7f62f..b8400c191a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1088,6 +1088,8 @@
F(0xe753, VCLZ, VRR_a, V, 0, 0, 0, 0, vclz, 0, IF_VEC)
/* VECTOR COUNT TRAILING ZEROS */
F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
+/* VECTOR EXCLUSIVE OR */
+ F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index ac1a2d77ad..0c67f53d1c 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1472,3 +1472,10 @@ static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(xor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 15/41] s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
A galois field multiplication in field 2 is like binary multiplication,
however instead of doing ordinary binary additions, xor's are performed.
So no carries are considered.
Implement all variants via helpers. s390_vec_sar() and s390_vec_shr()
will be reused later on.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 8 ++
target/s390x/insn-data.def | 4 +
target/s390x/translate_vx.inc.c | 38 ++++++++
target/s390x/vec_int_helper.c | 167 ++++++++++++++++++++++++++++++++
4 files changed, 217 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 60b8bd3c43..6e6ba9bf32 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -154,6 +154,14 @@ DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vctz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vctz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b8400c191a..add174b793 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1090,6 +1090,10 @@
F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
/* VECTOR EXCLUSIVE OR */
F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
+/* VECTOR GALOIS FIELD MULTIPLY SUM */
+ F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
+/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
+ F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0c67f53d1c..dbe0b6a560 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1479,3 +1479,41 @@ static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vgfm8, },
+ { .fno = gen_helper_gvec_vgfm16, },
+ { .fno = gen_helper_gvec_vgfm32, },
+ { .fno = gen_helper_gvec_vgfm64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ static const GVecGen4 g[4] = {
+ { .fno = gen_helper_gvec_vgfma8, },
+ { .fno = gen_helper_gvec_vgfma16, },
+ { .fno = gen_helper_gvec_vgfma32, },
+ { .fno = gen_helper_gvec_vgfma64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index d1b1f28509..20a1034dd8 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -15,6 +15,59 @@
#include "vec.h"
#include "exec/helper-proto.h"
+static bool s390_vec_is_zero(const S390Vector *v)
+{
+ return !v->doubleword[0] && !v->doubleword[1];
+}
+
+static void s390_vec_xor(S390Vector *res, const S390Vector *a,
+ const S390Vector *b)
+{
+ res->doubleword[0] = a->doubleword[0] ^ b->doubleword[0];
+ res->doubleword[1] = a->doubleword[1] ^ b->doubleword[1];
+}
+
+static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ g_assert(count < 128);
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[0] = a->doubleword[1];
+ d->doubleword[1] = 0;
+ } else if (count < 64) {
+ tmp = extract64(a->doubleword[1], 64 - count, count);
+ d->doubleword[1] = a->doubleword[1] << count;
+ d->doubleword[0] = (a->doubleword[0] << count) | tmp;
+ } else {
+ d->doubleword[0] = a->doubleword[1] << (count - 64);
+ d->doubleword[1] = 0;
+ }
+}
+
+static void s390_vec_shr(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ g_assert(count < 128);
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[1] = a->doubleword[0];
+ d->doubleword[0] = 0;
+ } else if (count < 64) {
+ tmp = a->doubleword[1] >> count;
+ d->doubleword[1] = deposit64(tmp, 64 - count, count, a->doubleword[0]);
+ d->doubleword[0] = a->doubleword[0] >> count;
+ } else {
+ d->doubleword[1] = a->doubleword[0] >> (count - 64);
+ d->doubleword[0] = 0;
+ }
+}
#define DEF_VAVG(BITS) \
void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
@@ -74,3 +127,117 @@ void HELPER(gvec_vctz##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VCTZ(8)
DEF_VCTZ(16)
+
+/* like binary multiplication, but XOR instead of addition */
+#define DEF_GALOIS_MULTIPLY(BITS, TBITS) \
+static uint##TBITS##_t galois_multiply##BITS(uint##TBITS##_t a, \
+ uint##TBITS##_t b) \
+{ \
+ uint##TBITS##_t res = 0; \
+ \
+ while (b) { \
+ if (b & 0x1) { \
+ res = res ^ a; \
+ } \
+ a = a << 1; \
+ b = b >> 1; \
+ } \
+ return res; \
+}
+DEF_GALOIS_MULTIPLY(8, 16)
+DEF_GALOIS_MULTIPLY(16, 32)
+DEF_GALOIS_MULTIPLY(32, 64)
+
+static S390Vector galois_multiply64(uint64_t a, uint64_t b)
+{
+ S390Vector res = {};
+ S390Vector va = {
+ .doubleword[1] = a,
+ };
+ S390Vector vb = {
+ .doubleword[1] = b,
+ };
+
+ while (!s390_vec_is_zero(&vb)) {
+ if (vb.doubleword[1] & 0x1) {
+ s390_vec_xor(&res, &res, &va);
+ }
+ s390_vec_shl(&va, &va, 1);
+ s390_vec_shr(&vb, &vb, 1);
+ }
+ return res;
+}
+
+#define DEF_VGFM(BITS, TBITS) \
+void HELPER(gvec_vgfm##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / TBITS); i++) { \
+ uint##BITS##_t a = s390_vec_read_element##BITS(v2, i * 2); \
+ uint##BITS##_t b = s390_vec_read_element##BITS(v3, i * 2); \
+ uint##TBITS##_t d = galois_multiply##BITS(a, b); \
+ \
+ a = s390_vec_read_element##BITS(v2, i * 2 + 1); \
+ b = s390_vec_read_element##BITS(v3, i * 2 + 1); \
+ d = d ^ galois_multiply32(a, b); \
+ s390_vec_write_element##TBITS(v1, i, d); \
+ } \
+}
+DEF_VGFM(8, 16)
+DEF_VGFM(16, 32)
+DEF_VGFM(32, 64)
+
+void HELPER(gvec_vgfm64)(void *v1, const void *v2, const void *v3,
+ uint32_t desc)
+{
+ S390Vector tmp1, tmp2;
+ uint64_t a, b;
+
+ a = s390_vec_read_element64(v2, 0);
+ b = s390_vec_read_element64(v3, 0);
+ tmp1 = galois_multiply64(a, b);
+ a = s390_vec_read_element64(v2, 1);
+ b = s390_vec_read_element64(v3, 1);
+ tmp2 = galois_multiply64(a, b);
+ s390_vec_xor(v1, &tmp1, &tmp2);
+}
+
+#define DEF_VGFMA(BITS, TBITS) \
+void HELPER(gvec_vgfma##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / TBITS); i++) { \
+ uint##BITS##_t a = s390_vec_read_element##BITS(v2, i * 2); \
+ uint##BITS##_t b = s390_vec_read_element##BITS(v3, i * 2); \
+ uint##TBITS##_t d = galois_multiply##BITS(a, b); \
+ \
+ a = s390_vec_read_element##BITS(v2, i * 2 + 1); \
+ b = s390_vec_read_element##BITS(v3, i * 2 + 1); \
+ d = d ^ galois_multiply32(a, b); \
+ d = d ^ s390_vec_read_element##TBITS(v4, i); \
+ s390_vec_write_element##TBITS(v1, i, d); \
+ } \
+}
+DEF_VGFMA(8, 16)
+DEF_VGFMA(16, 32)
+DEF_VGFMA(32, 64)
+
+void HELPER(gvec_vgfma64)(void *v1, const void *v2, const void *v3,
+ const void *v4, uint32_t desc)
+{
+ S390Vector tmp1, tmp2;
+ uint64_t a, b;
+
+ a = s390_vec_read_element64(v2, 0);
+ b = s390_vec_read_element64(v3, 0);
+ tmp1 = galois_multiply64(a, b);
+ a = s390_vec_read_element64(v2, 1);
+ b = s390_vec_read_element64(v3, 1);
+ tmp2 = galois_multiply64(a, b);
+ s390_vec_xor(&tmp1, &tmp1, &tmp2);
+ s390_vec_xor(v1, &tmp1, v4);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 15/41] s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
A galois field multiplication in field 2 is like binary multiplication,
however instead of doing ordinary binary additions, xor's are performed.
So no carries are considered.
Implement all variants via helpers. s390_vec_sar() and s390_vec_shr()
will be reused later on.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 8 ++
target/s390x/insn-data.def | 4 +
target/s390x/translate_vx.inc.c | 38 ++++++++
target/s390x/vec_int_helper.c | 167 ++++++++++++++++++++++++++++++++
4 files changed, 217 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 60b8bd3c43..6e6ba9bf32 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -154,6 +154,14 @@ DEF_HELPER_FLAGS_3(gvec_vclz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vclz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vctz8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vctz16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vgfm64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b8400c191a..add174b793 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1090,6 +1090,10 @@
F(0xe752, VCTZ, VRR_a, V, 0, 0, 0, 0, vctz, 0, IF_VEC)
/* VECTOR EXCLUSIVE OR */
F(0xe76d, VX, VRR_c, V, 0, 0, 0, 0, vx, 0, IF_VEC)
+/* VECTOR GALOIS FIELD MULTIPLY SUM */
+ F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
+/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
+ F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 0c67f53d1c..dbe0b6a560 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1479,3 +1479,41 @@ static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vgfm8, },
+ { .fno = gen_helper_gvec_vgfm16, },
+ { .fno = gen_helper_gvec_vgfm32, },
+ { .fno = gen_helper_gvec_vgfm64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ static const GVecGen4 g[4] = {
+ { .fno = gen_helper_gvec_vgfma8, },
+ { .fno = gen_helper_gvec_vgfma16, },
+ { .fno = gen_helper_gvec_vgfma32, },
+ { .fno = gen_helper_gvec_vgfma64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index d1b1f28509..20a1034dd8 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -15,6 +15,59 @@
#include "vec.h"
#include "exec/helper-proto.h"
+static bool s390_vec_is_zero(const S390Vector *v)
+{
+ return !v->doubleword[0] && !v->doubleword[1];
+}
+
+static void s390_vec_xor(S390Vector *res, const S390Vector *a,
+ const S390Vector *b)
+{
+ res->doubleword[0] = a->doubleword[0] ^ b->doubleword[0];
+ res->doubleword[1] = a->doubleword[1] ^ b->doubleword[1];
+}
+
+static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ g_assert(count < 128);
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[0] = a->doubleword[1];
+ d->doubleword[1] = 0;
+ } else if (count < 64) {
+ tmp = extract64(a->doubleword[1], 64 - count, count);
+ d->doubleword[1] = a->doubleword[1] << count;
+ d->doubleword[0] = (a->doubleword[0] << count) | tmp;
+ } else {
+ d->doubleword[0] = a->doubleword[1] << (count - 64);
+ d->doubleword[1] = 0;
+ }
+}
+
+static void s390_vec_shr(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ g_assert(count < 128);
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[1] = a->doubleword[0];
+ d->doubleword[0] = 0;
+ } else if (count < 64) {
+ tmp = a->doubleword[1] >> count;
+ d->doubleword[1] = deposit64(tmp, 64 - count, count, a->doubleword[0]);
+ d->doubleword[0] = a->doubleword[0] >> count;
+ } else {
+ d->doubleword[1] = a->doubleword[0] >> (count - 64);
+ d->doubleword[0] = 0;
+ }
+}
#define DEF_VAVG(BITS) \
void HELPER(gvec_vavg##BITS)(void *v1, const void *v2, const void *v3, \
uint32_t desc) \
@@ -74,3 +127,117 @@ void HELPER(gvec_vctz##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VCTZ(8)
DEF_VCTZ(16)
+
+/* like binary multiplication, but XOR instead of addition */
+#define DEF_GALOIS_MULTIPLY(BITS, TBITS) \
+static uint##TBITS##_t galois_multiply##BITS(uint##TBITS##_t a, \
+ uint##TBITS##_t b) \
+{ \
+ uint##TBITS##_t res = 0; \
+ \
+ while (b) { \
+ if (b & 0x1) { \
+ res = res ^ a; \
+ } \
+ a = a << 1; \
+ b = b >> 1; \
+ } \
+ return res; \
+}
+DEF_GALOIS_MULTIPLY(8, 16)
+DEF_GALOIS_MULTIPLY(16, 32)
+DEF_GALOIS_MULTIPLY(32, 64)
+
+static S390Vector galois_multiply64(uint64_t a, uint64_t b)
+{
+ S390Vector res = {};
+ S390Vector va = {
+ .doubleword[1] = a,
+ };
+ S390Vector vb = {
+ .doubleword[1] = b,
+ };
+
+ while (!s390_vec_is_zero(&vb)) {
+ if (vb.doubleword[1] & 0x1) {
+ s390_vec_xor(&res, &res, &va);
+ }
+ s390_vec_shl(&va, &va, 1);
+ s390_vec_shr(&vb, &vb, 1);
+ }
+ return res;
+}
+
+#define DEF_VGFM(BITS, TBITS) \
+void HELPER(gvec_vgfm##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / TBITS); i++) { \
+ uint##BITS##_t a = s390_vec_read_element##BITS(v2, i * 2); \
+ uint##BITS##_t b = s390_vec_read_element##BITS(v3, i * 2); \
+ uint##TBITS##_t d = galois_multiply##BITS(a, b); \
+ \
+ a = s390_vec_read_element##BITS(v2, i * 2 + 1); \
+ b = s390_vec_read_element##BITS(v3, i * 2 + 1); \
+ d = d ^ galois_multiply32(a, b); \
+ s390_vec_write_element##TBITS(v1, i, d); \
+ } \
+}
+DEF_VGFM(8, 16)
+DEF_VGFM(16, 32)
+DEF_VGFM(32, 64)
+
+void HELPER(gvec_vgfm64)(void *v1, const void *v2, const void *v3,
+ uint32_t desc)
+{
+ S390Vector tmp1, tmp2;
+ uint64_t a, b;
+
+ a = s390_vec_read_element64(v2, 0);
+ b = s390_vec_read_element64(v3, 0);
+ tmp1 = galois_multiply64(a, b);
+ a = s390_vec_read_element64(v2, 1);
+ b = s390_vec_read_element64(v3, 1);
+ tmp2 = galois_multiply64(a, b);
+ s390_vec_xor(v1, &tmp1, &tmp2);
+}
+
+#define DEF_VGFMA(BITS, TBITS) \
+void HELPER(gvec_vgfma##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / TBITS); i++) { \
+ uint##BITS##_t a = s390_vec_read_element##BITS(v2, i * 2); \
+ uint##BITS##_t b = s390_vec_read_element##BITS(v3, i * 2); \
+ uint##TBITS##_t d = galois_multiply##BITS(a, b); \
+ \
+ a = s390_vec_read_element##BITS(v2, i * 2 + 1); \
+ b = s390_vec_read_element##BITS(v3, i * 2 + 1); \
+ d = d ^ galois_multiply32(a, b); \
+ d = d ^ s390_vec_read_element##TBITS(v4, i); \
+ s390_vec_write_element##TBITS(v1, i, d); \
+ } \
+}
+DEF_VGFMA(8, 16)
+DEF_VGFMA(16, 32)
+DEF_VGFMA(32, 64)
+
+void HELPER(gvec_vgfma64)(void *v1, const void *v2, const void *v3,
+ const void *v4, uint32_t desc)
+{
+ S390Vector tmp1, tmp2;
+ uint64_t a, b;
+
+ a = s390_vec_read_element64(v2, 0);
+ b = s390_vec_read_element64(v3, 0);
+ tmp1 = galois_multiply64(a, b);
+ a = s390_vec_read_element64(v2, 1);
+ b = s390_vec_read_element64(v3, 1);
+ tmp2 = galois_multiply64(a, b);
+ s390_vec_xor(&tmp1, &tmp1, &tmp2);
+ s390_vec_xor(v1, &tmp1, v4);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 16/41] s390x/tcg: Implement VECTOR LOAD COMPLEMENT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
We can reuse an existing gvec helper for negating the values.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index add174b793..07868ff082 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1094,6 +1094,8 @@
F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
+/* VECTOR LOAD COMPLEMENT */
+ F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index dbe0b6a560..b3d7f3c667 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -209,6 +209,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_fn_2(fn, es, v1, v2) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16)
#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16)
@@ -1517,3 +1520,17 @@ static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), get_field(s->fields, v4), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_fn_2(neg, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 16/41] s390x/tcg: Implement VECTOR LOAD COMPLEMENT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
We can reuse an existing gvec helper for negating the values.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index add174b793..07868ff082 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1094,6 +1094,8 @@
F(0xe7b4, VGFM, VRR_c, V, 0, 0, 0, 0, vgfm, 0, IF_VEC)
/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
+/* VECTOR LOAD COMPLEMENT */
+ F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index dbe0b6a560..b3d7f3c667 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -209,6 +209,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
16)
#define gen_gvec_dup64i(v1, c) \
tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
+#define gen_gvec_fn_2(fn, es, v1, v2) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16)
#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16)
@@ -1517,3 +1520,17 @@ static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), get_field(s->fields, v4), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_fn_2(neg, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 17/41] s390x/tcg: Implement VECTOR LOAD POSITIVE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR LOAD COMPLEMENT but unfortunately we don't have a
gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 40 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 6e6ba9bf32..361b1a2077 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -162,6 +162,8 @@ DEF_HELPER_FLAGS_5(gvec_vgfma8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i3
DEF_HELPER_FLAGS_5(gvec_vgfma16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vlp8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vlp16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 07868ff082..fc8886ff42 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1096,6 +1096,8 @@
F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
/* VECTOR LOAD COMPLEMENT */
F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
+/* VECTOR LOAD POSITIVE */
+ F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b3d7f3c667..91854ab4a4 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1534,3 +1534,43 @@ static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
get_field(s->fields, v2));
return DISAS_NEXT;
}
+
+static void gen_lp_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 neg = tcg_temp_new_i32();
+
+ tcg_gen_neg_i32(neg, a);
+ tcg_gen_movcond_i32(TCG_COND_LT, d, a, zero, neg, a);
+ tcg_temp_free_i32(neg);
+ tcg_temp_free_i32(zero);
+}
+
+static void gen_lp_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 neg = tcg_temp_new_i64();
+
+ tcg_gen_neg_i64(neg, a);
+ tcg_gen_movcond_i64(TCG_COND_LT, d, a, zero, neg, a);
+ tcg_temp_free_i64(neg);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vlp8, },
+ { .fno = gen_helper_gvec_vlp16, },
+ { .fni4 = gen_lp_i32, },
+ { .fni8 = gen_lp_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 20a1034dd8..b5d538ffcf 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -241,3 +241,17 @@ void HELPER(gvec_vgfma64)(void *v1, const void *v2, const void *v3,
s390_vec_xor(&tmp1, &tmp1, &tmp2);
s390_vec_xor(v1, &tmp1, v4);
}
+
+#define DEF_VLP(BITS) \
+void HELPER(gvec_vlp##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a < 0 ? -a : a); \
+ } \
+}
+DEF_VLP(8)
+DEF_VLP(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 17/41] s390x/tcg: Implement VECTOR LOAD POSITIVE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR LOAD COMPLEMENT but unfortunately we don't have a
gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 40 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 6e6ba9bf32..361b1a2077 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -162,6 +162,8 @@ DEF_HELPER_FLAGS_5(gvec_vgfma8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i3
DEF_HELPER_FLAGS_5(gvec_vgfma16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vlp8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vlp16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 07868ff082..fc8886ff42 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1096,6 +1096,8 @@
F(0xe7bc, VGFMA, VRR_d, V, 0, 0, 0, 0, vgfma, 0, IF_VEC)
/* VECTOR LOAD COMPLEMENT */
F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
+/* VECTOR LOAD POSITIVE */
+ F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index b3d7f3c667..91854ab4a4 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1534,3 +1534,43 @@ static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
get_field(s->fields, v2));
return DISAS_NEXT;
}
+
+static void gen_lp_i32(TCGv_i32 d, TCGv_i32 a)
+{
+ TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 neg = tcg_temp_new_i32();
+
+ tcg_gen_neg_i32(neg, a);
+ tcg_gen_movcond_i32(TCG_COND_LT, d, a, zero, neg, a);
+ tcg_temp_free_i32(neg);
+ tcg_temp_free_i32(zero);
+}
+
+static void gen_lp_i64(TCGv_i64 d, TCGv_i64 a)
+{
+ TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 neg = tcg_temp_new_i64();
+
+ tcg_gen_neg_i64(neg, a);
+ tcg_gen_movcond_i64(TCG_COND_LT, d, a, zero, neg, a);
+ tcg_temp_free_i64(neg);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vlp8, },
+ { .fno = gen_helper_gvec_vlp16, },
+ { .fni4 = gen_lp_i32, },
+ { .fni8 = gen_lp_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 20a1034dd8..b5d538ffcf 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -241,3 +241,17 @@ void HELPER(gvec_vgfma64)(void *v1, const void *v2, const void *v3,
s390_vec_xor(&tmp1, &tmp1, &tmp2);
s390_vec_xor(v1, &tmp1, v4);
}
+
+#define DEF_VLP(BITS) \
+void HELPER(gvec_vlp##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a < 0 ? -a : a); \
+ } \
+}
+DEF_VLP(8)
+DEF_VLP(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 18/41] s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Luckily, we already have gvec helpers for all four cases.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 8 ++++++++
target/s390x/translate_vx.inc.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fc8886ff42..b22d9f0f6a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1098,6 +1098,14 @@
F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
/* VECTOR LOAD POSITIVE */
F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
+/* VECTOR MAXIMUM */
+ F(0xe7ff, VMX, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MAXIMUM LOGICAL */
+ F(0xe7fd, VMXL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MINIMUM */
+ F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MINIMUM LOGICAL */
+ F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 91854ab4a4..d0577115a8 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1574,3 +1574,34 @@ static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xff:
+ gen_gvec_fn_3(smax, es, v1, v2, v3);
+ break;
+ case 0xfd:
+ gen_gvec_fn_3(umax, es, v1, v2, v3);
+ break;
+ case 0xfe:
+ gen_gvec_fn_3(smin, es, v1, v2, v3);
+ break;
+ case 0xfc:
+ gen_gvec_fn_3(umin, es, v1, v2, v3);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 18/41] s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Luckily, we already have gvec helpers for all four cases.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 8 ++++++++
target/s390x/translate_vx.inc.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fc8886ff42..b22d9f0f6a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1098,6 +1098,14 @@
F(0xe7de, VLC, VRR_a, V, 0, 0, 0, 0, vlc, 0, IF_VEC)
/* VECTOR LOAD POSITIVE */
F(0xe7df, VLP, VRR_a, V, 0, 0, 0, 0, vlp, 0, IF_VEC)
+/* VECTOR MAXIMUM */
+ F(0xe7ff, VMX, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MAXIMUM LOGICAL */
+ F(0xe7fd, VMXL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MINIMUM */
+ F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MINIMUM LOGICAL */
+ F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 91854ab4a4..d0577115a8 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1574,3 +1574,34 @@ static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
+{
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v2 = get_field(s->fields, v2);
+ const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xff:
+ gen_gvec_fn_3(smax, es, v1, v2, v3);
+ break;
+ case 0xfd:
+ gen_gvec_fn_3(umax, es, v1, v2, v3);
+ break;
+ case 0xfe:
+ gen_gvec_fn_3(smin, es, v1, v2, v3);
+ break;
+ case 0xfc:
+ gen_gvec_fn_3(umin, es, v1, v2, v3);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 19/41] s390x/tcg: Implement VECTOR MULTIPLY AND ADD *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Quite some variants to handle. At least handle some 32-bit element
variants via gvec expansion (we could also handle 16/32-bit variants
for ODD and EVEN easily via gvec expansion, but let's keep it simple
for now).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 18 +++++
target/s390x/insn-data.def | 14 ++++
target/s390x/translate_vx.inc.c | 122 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 123 ++++++++++++++++++++++++++++++++
4 files changed, 277 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 361b1a2077..924f97c59d 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -164,6 +164,24 @@ DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i
DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vlp8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vlp16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmal8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmal16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmah8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmah16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b22d9f0f6a..7ccec0544f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1106,6 +1106,20 @@
F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
/* VECTOR MINIMUM LOGICAL */
F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOW */
+ F(0xe7aa, VMAL, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD HIGH */
+ F(0xe7ab, VMAH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL HIGH */
+ F(0xe7a9, VMALH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD EVEN */
+ F(0xe7ae, VMAE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL EVEN */
+ F(0xe7ac, VMALE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD ODD */
+ F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
+ F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index d0577115a8..48abb28f91 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1605,3 +1605,125 @@ static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_mul_i32(t0, a, b);
+ tcg_gen_add_i32(d, t0, c);
+
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_ext_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_extu_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ static const GVecGen4 g_vmal[3] = {
+ { .fno = gen_helper_gvec_vmal8, },
+ { .fno = gen_helper_gvec_vmal16, },
+ { .fni4 = gen_mal_i32, },
+ };
+ static const GVecGen4 g_vmah[3] = {
+ { .fno = gen_helper_gvec_vmah8, },
+ { .fno = gen_helper_gvec_vmah16, },
+ { .fni4 = gen_mah_i32, },
+ };
+ static const GVecGen4 g_vmalh[3] = {
+ { .fno = gen_helper_gvec_vmalh8, },
+ { .fno = gen_helper_gvec_vmalh16, },
+ { .fni4 = gen_malh_i32, },
+ };
+ static const GVecGen4 g_vmae[3] = {
+ { .fno = gen_helper_gvec_vmae8, },
+ { .fno = gen_helper_gvec_vmae16, },
+ { .fno = gen_helper_gvec_vmae32, },
+ };
+ static const GVecGen4 g_vmale[3] = {
+ { .fno = gen_helper_gvec_vmale8, },
+ { .fno = gen_helper_gvec_vmale16, },
+ { .fno = gen_helper_gvec_vmale32, },
+ };
+ static const GVecGen4 g_vmao[3] = {
+ { .fno = gen_helper_gvec_vmao8, },
+ { .fno = gen_helper_gvec_vmao16, },
+ { .fno = gen_helper_gvec_vmao32, },
+ };
+ static const GVecGen4 g_vmalo[3] = {
+ { .fno = gen_helper_gvec_vmalo8, },
+ { .fno = gen_helper_gvec_vmalo16, },
+ { .fno = gen_helper_gvec_vmalo32, },
+ };
+ const GVecGen4 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xaa:
+ fn = &g_vmal[es];
+ break;
+ case 0xab:
+ fn = &g_vmah[es];
+ break;
+ case 0xa9:
+ fn = &g_vmalh[es];
+ break;
+ case 0xae:
+ fn = &g_vmae[es];
+ break;
+ case 0xac:
+ fn = &g_vmale[es];
+ break;
+ case 0xaf:
+ fn = &g_vmao[es];
+ break;
+ case 0xad:
+ fn = &g_vmalo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index b5d538ffcf..fb4c1422f3 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -255,3 +255,126 @@ void HELPER(gvec_vlp##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VLP(8)
DEF_VLP(16)
+
+#define DEF_VMAL(BITS) \
+void HELPER(gvec_vmal##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t c = s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAL(8)
+DEF_VMAL(16)
+
+#define DEF_VMAH(BITS) \
+void HELPER(gvec_vmah##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ const int32_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b + c) >> BITS); \
+ } \
+}
+DEF_VMAH(8)
+DEF_VMAH(16)
+
+#define DEF_VMALH(BITS) \
+void HELPER(gvec_vmalh##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t c = s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b + c) >> BITS); \
+ } \
+}
+DEF_VMALH(8)
+DEF_VMALH(16)
+
+#define DEF_VMAE(BITS, TBITS) \
+void HELPER(gvec_vmae##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAE(8, 16)
+DEF_VMAE(16, 32)
+DEF_VMAE(32, 64)
+
+#define DEF_VMALE(BITS, TBITS) \
+void HELPER(gvec_vmale##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMALE(8, 16)
+DEF_VMALE(16, 32)
+DEF_VMALE(32, 64)
+
+#define DEF_VMAO(BITS, TBITS) \
+void HELPER(gvec_vmao##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAO(8, 16)
+DEF_VMAO(16, 32)
+DEF_VMAO(32, 64)
+
+#define DEF_VMALO(BITS, TBITS) \
+void HELPER(gvec_vmalo##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMALO(8, 16)
+DEF_VMALO(16, 32)
+DEF_VMALO(32, 64)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 19/41] s390x/tcg: Implement VECTOR MULTIPLY AND ADD *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Quite some variants to handle. At least handle some 32-bit element
variants via gvec expansion (we could also handle 16/32-bit variants
for ODD and EVEN easily via gvec expansion, but let's keep it simple
for now).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 18 +++++
target/s390x/insn-data.def | 14 ++++
target/s390x/translate_vx.inc.c | 122 +++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 123 ++++++++++++++++++++++++++++++++
4 files changed, 277 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 361b1a2077..924f97c59d 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -164,6 +164,24 @@ DEF_HELPER_FLAGS_5(gvec_vgfma32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i
DEF_HELPER_FLAGS_5(gvec_vgfma64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vlp8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vlp16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmal8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmal16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmah8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmah16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmae32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmale32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmao32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_5(gvec_vmalo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b22d9f0f6a..7ccec0544f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1106,6 +1106,20 @@
F(0xe7fe, VMN, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
/* VECTOR MINIMUM LOGICAL */
F(0xe7fc, VMNL, VRR_c, V, 0, 0, 0, 0, vmx, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOW */
+ F(0xe7aa, VMAL, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD HIGH */
+ F(0xe7ab, VMAH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL HIGH */
+ F(0xe7a9, VMALH, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD EVEN */
+ F(0xe7ae, VMAE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL EVEN */
+ F(0xe7ac, VMALE, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD ODD */
+ F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
+ F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index d0577115a8..48abb28f91 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1605,3 +1605,125 @@ static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
}
return DISAS_NEXT;
}
+
+static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_mul_i32(t0, a, b);
+ tcg_gen_add_i32(d, t0, c);
+
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(t0, a);
+ tcg_gen_ext_i32_i64(t1, b);
+ tcg_gen_ext_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(t0, a);
+ tcg_gen_extu_i32_i64(t1, b);
+ tcg_gen_extu_i32_i64(t2, c);
+ tcg_gen_mul_i64(t0, t0, t1);
+ tcg_gen_add_i64(t0, t0, t2);
+ tcg_gen_extrh_i64_i32(d, t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+}
+
+static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ static const GVecGen4 g_vmal[3] = {
+ { .fno = gen_helper_gvec_vmal8, },
+ { .fno = gen_helper_gvec_vmal16, },
+ { .fni4 = gen_mal_i32, },
+ };
+ static const GVecGen4 g_vmah[3] = {
+ { .fno = gen_helper_gvec_vmah8, },
+ { .fno = gen_helper_gvec_vmah16, },
+ { .fni4 = gen_mah_i32, },
+ };
+ static const GVecGen4 g_vmalh[3] = {
+ { .fno = gen_helper_gvec_vmalh8, },
+ { .fno = gen_helper_gvec_vmalh16, },
+ { .fni4 = gen_malh_i32, },
+ };
+ static const GVecGen4 g_vmae[3] = {
+ { .fno = gen_helper_gvec_vmae8, },
+ { .fno = gen_helper_gvec_vmae16, },
+ { .fno = gen_helper_gvec_vmae32, },
+ };
+ static const GVecGen4 g_vmale[3] = {
+ { .fno = gen_helper_gvec_vmale8, },
+ { .fno = gen_helper_gvec_vmale16, },
+ { .fno = gen_helper_gvec_vmale32, },
+ };
+ static const GVecGen4 g_vmao[3] = {
+ { .fno = gen_helper_gvec_vmao8, },
+ { .fno = gen_helper_gvec_vmao16, },
+ { .fno = gen_helper_gvec_vmao32, },
+ };
+ static const GVecGen4 g_vmalo[3] = {
+ { .fno = gen_helper_gvec_vmalo8, },
+ { .fno = gen_helper_gvec_vmalo16, },
+ { .fno = gen_helper_gvec_vmalo32, },
+ };
+ const GVecGen4 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xaa:
+ fn = &g_vmal[es];
+ break;
+ case 0xab:
+ fn = &g_vmah[es];
+ break;
+ case 0xa9:
+ fn = &g_vmalh[es];
+ break;
+ case 0xae:
+ fn = &g_vmae[es];
+ break;
+ case 0xac:
+ fn = &g_vmale[es];
+ break;
+ case 0xaf:
+ fn = &g_vmao[es];
+ break;
+ case 0xad:
+ fn = &g_vmalo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), get_field(s->fields, v4), fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index b5d538ffcf..fb4c1422f3 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -255,3 +255,126 @@ void HELPER(gvec_vlp##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VLP(8)
DEF_VLP(16)
+
+#define DEF_VMAL(BITS) \
+void HELPER(gvec_vmal##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t c = s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAL(8)
+DEF_VMAL(16)
+
+#define DEF_VMAH(BITS) \
+void HELPER(gvec_vmah##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ const int32_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b + c) >> BITS); \
+ } \
+}
+DEF_VMAH(8)
+DEF_VMAH(16)
+
+#define DEF_VMALH(BITS) \
+void HELPER(gvec_vmalh##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t c = s390_vec_read_element##BITS(v4, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b + c) >> BITS); \
+ } \
+}
+DEF_VMALH(8)
+DEF_VMALH(16)
+
+#define DEF_VMAE(BITS, TBITS) \
+void HELPER(gvec_vmae##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAE(8, 16)
+DEF_VMAE(16, 32)
+DEF_VMAE(32, 64)
+
+#define DEF_VMALE(BITS, TBITS) \
+void HELPER(gvec_vmale##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMALE(8, 16)
+DEF_VMALE(16, 32)
+DEF_VMALE(32, 64)
+
+#define DEF_VMAO(BITS, TBITS) \
+void HELPER(gvec_vmao##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ int##TBITS##_t c = (int##BITS##_t)s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMAO(8, 16)
+DEF_VMAO(16, 32)
+DEF_VMAO(32, 64)
+
+#define DEF_VMALO(BITS, TBITS) \
+void HELPER(gvec_vmalo##BITS)(void *v1, const void *v2, const void *v3, \
+ const void *v4, uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ uint##TBITS##_t c = s390_vec_read_element##BITS(v4, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b + c); \
+ } \
+}
+DEF_VMALO(8, 16)
+DEF_VMALO(16, 32)
+DEF_VMALO(32, 64)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 20/41] s390x/tcg: Implement VECTOR MULTIPLY *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND
ADD *. At least for one variant we have a gvec helper we can reuse.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 16 +++++
target/s390x/insn-data.def | 14 +++++
target/s390x/translate_vx.inc.c | 88 ++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 100 ++++++++++++++++++++++++++++++++
4 files changed, 218 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 924f97c59d..01b2009271 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -182,6 +182,22 @@ DEF_HELPER_FLAGS_5(gvec_vmao32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i3
DEF_HELPER_FLAGS_5(gvec_vmalo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vmalo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vmalo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 7ccec0544f..2c794a2744 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1120,6 +1120,20 @@
F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY HIGH */
+ F(0xe7a3, VMH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL HIGH */
+ F(0xe7a1, VMLH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOW */
+ F(0xe7a2, VML, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY EVEN */
+ F(0xe7a6, VME, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL EVEN */
+ F(0xe7a4, VMLE, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY ODD */
+ F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL ODD */
+ F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 48abb28f91..fddab1f47e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1727,3 +1727,91 @@ static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), get_field(s->fields, v4), fn);
return DISAS_NEXT;
}
+
+static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_muls2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_mulu2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g_vmh[3] = {
+ { .fno = gen_helper_gvec_vmh8, },
+ { .fno = gen_helper_gvec_vmh16, },
+ { .fni4 = gen_mh_i32, },
+ };
+ static const GVecGen3 g_vmlh[3] = {
+ { .fno = gen_helper_gvec_vmlh8, },
+ { .fno = gen_helper_gvec_vmlh16, },
+ { .fni4 = gen_mlh_i32, },
+ };
+ static const GVecGen3 g_vme[3] = {
+ { .fno = gen_helper_gvec_vme8, },
+ { .fno = gen_helper_gvec_vme16, },
+ { .fno = gen_helper_gvec_vme32, },
+ };
+ static const GVecGen3 g_vmle[3] = {
+ { .fno = gen_helper_gvec_vmle8, },
+ { .fno = gen_helper_gvec_vmle16, },
+ { .fno = gen_helper_gvec_vmle32, },
+ };
+ static const GVecGen3 g_vmo[3] = {
+ { .fno = gen_helper_gvec_vmo8, },
+ { .fno = gen_helper_gvec_vmo16, },
+ { .fno = gen_helper_gvec_vmo32, },
+ };
+ static const GVecGen3 g_vmlo[3] = {
+ { .fno = gen_helper_gvec_vmlo8, },
+ { .fno = gen_helper_gvec_vmlo16, },
+ { .fno = gen_helper_gvec_vmlo32, },
+ };
+ const GVecGen3 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xa2:
+ gen_gvec_fn_3(mul, es, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ case 0xa3:
+ fn = &g_vmh[es];
+ break;
+ case 0xa1:
+ fn = &g_vmlh[es];
+ break;
+ case 0xa6:
+ fn = &g_vme[es];
+ break;
+ case 0xa4:
+ fn = &g_vmle[es];
+ break;
+ case 0xa7:
+ fn = &g_vmo[es];
+ break;
+ case 0xa5:
+ fn = &g_vmlo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index fb4c1422f3..9bb607af05 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -378,3 +378,103 @@ void HELPER(gvec_vmalo##BITS)(void *v1, const void *v2, const void *v3, \
DEF_VMALO(8, 16)
DEF_VMALO(16, 32)
DEF_VMALO(32, 64)
+
+#define DEF_VMH(BITS) \
+void HELPER(gvec_vmh##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b) >> BITS); \
+ } \
+}
+DEF_VMH(8)
+DEF_VMH(16)
+
+#define DEF_VMLH(BITS) \
+void HELPER(gvec_vmlh##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b) >> BITS); \
+ } \
+}
+DEF_VMLH(8)
+DEF_VMLH(16)
+
+#define DEF_VME(BITS, TBITS) \
+void HELPER(gvec_vme##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VME(8, 16)
+DEF_VME(16, 32)
+DEF_VME(32, 64)
+
+#define DEF_VMLE(BITS, TBITS) \
+void HELPER(gvec_vmle##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ const uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ const uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMLE(8, 16)
+DEF_VMLE(16, 32)
+DEF_VMLE(32, 64)
+
+#define DEF_VMO(BITS, TBITS) \
+void HELPER(gvec_vmo##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMO(8, 16)
+DEF_VMO(16, 32)
+DEF_VMO(32, 64)
+
+#define DEF_VMLO(BITS, TBITS) \
+void HELPER(gvec_vmlo##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ const uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ const uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMLO(8, 16)
+DEF_VMLO(16, 32)
+DEF_VMLO(32, 64)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 20/41] s390x/tcg: Implement VECTOR MULTIPLY *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND
ADD *. At least for one variant we have a gvec helper we can reuse.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 16 +++++
target/s390x/insn-data.def | 14 +++++
target/s390x/translate_vx.inc.c | 88 ++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 100 ++++++++++++++++++++++++++++++++
4 files changed, 218 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 924f97c59d..01b2009271 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -182,6 +182,22 @@ DEF_HELPER_FLAGS_5(gvec_vmao32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i3
DEF_HELPER_FLAGS_5(gvec_vmalo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vmalo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_5(gvec_vmalo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlh8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlh16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vme32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmle32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 7ccec0544f..2c794a2744 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1120,6 +1120,20 @@
F(0xe7af, VMAO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
/* VECTOR MULTIPLY AND ADD LOGICAL ODD */
F(0xe7ad, VMALO, VRR_d, V, 0, 0, 0, 0, vma, 0, IF_VEC)
+/* VECTOR MULTIPLY HIGH */
+ F(0xe7a3, VMH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL HIGH */
+ F(0xe7a1, VMLH, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOW */
+ F(0xe7a2, VML, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY EVEN */
+ F(0xe7a6, VME, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL EVEN */
+ F(0xe7a4, VMLE, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY ODD */
+ F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY LOGICAL ODD */
+ F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 48abb28f91..fddab1f47e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1727,3 +1727,91 @@ static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), get_field(s->fields, v4), fn);
return DISAS_NEXT;
}
+
+static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_muls2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_mulu2_i32(t, d, a, b);
+ tcg_temp_free_i32(t);
+}
+
+static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g_vmh[3] = {
+ { .fno = gen_helper_gvec_vmh8, },
+ { .fno = gen_helper_gvec_vmh16, },
+ { .fni4 = gen_mh_i32, },
+ };
+ static const GVecGen3 g_vmlh[3] = {
+ { .fno = gen_helper_gvec_vmlh8, },
+ { .fno = gen_helper_gvec_vmlh16, },
+ { .fni4 = gen_mlh_i32, },
+ };
+ static const GVecGen3 g_vme[3] = {
+ { .fno = gen_helper_gvec_vme8, },
+ { .fno = gen_helper_gvec_vme16, },
+ { .fno = gen_helper_gvec_vme32, },
+ };
+ static const GVecGen3 g_vmle[3] = {
+ { .fno = gen_helper_gvec_vmle8, },
+ { .fno = gen_helper_gvec_vmle16, },
+ { .fno = gen_helper_gvec_vmle32, },
+ };
+ static const GVecGen3 g_vmo[3] = {
+ { .fno = gen_helper_gvec_vmo8, },
+ { .fno = gen_helper_gvec_vmo16, },
+ { .fno = gen_helper_gvec_vmo32, },
+ };
+ static const GVecGen3 g_vmlo[3] = {
+ { .fno = gen_helper_gvec_vmlo8, },
+ { .fno = gen_helper_gvec_vmlo16, },
+ { .fno = gen_helper_gvec_vmlo32, },
+ };
+ const GVecGen3 *fn;
+
+ if (es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0xa2:
+ gen_gvec_fn_3(mul, es, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ case 0xa3:
+ fn = &g_vmh[es];
+ break;
+ case 0xa1:
+ fn = &g_vmlh[es];
+ break;
+ case 0xa6:
+ fn = &g_vme[es];
+ break;
+ case 0xa4:
+ fn = &g_vmle[es];
+ break;
+ case 0xa7:
+ fn = &g_vmo[es];
+ break;
+ case 0xa5:
+ fn = &g_vmlo[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index fb4c1422f3..9bb607af05 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -378,3 +378,103 @@ void HELPER(gvec_vmalo##BITS)(void *v1, const void *v2, const void *v3, \
DEF_VMALO(8, 16)
DEF_VMALO(16, 32)
DEF_VMALO(32, 64)
+
+#define DEF_VMH(BITS) \
+void HELPER(gvec_vmh##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int32_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, i); \
+ const int32_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b) >> BITS); \
+ } \
+}
+DEF_VMH(8)
+DEF_VMH(16)
+
+#define DEF_VMLH(BITS) \
+void HELPER(gvec_vmlh##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, (a * b) >> BITS); \
+ } \
+}
+DEF_VMLH(8)
+DEF_VMLH(16)
+
+#define DEF_VME(BITS, TBITS) \
+void HELPER(gvec_vme##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VME(8, 16)
+DEF_VME(16, 32)
+DEF_VME(32, 64)
+
+#define DEF_VMLE(BITS, TBITS) \
+void HELPER(gvec_vmle##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ const uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ const uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMLE(8, 16)
+DEF_VMLE(16, 32)
+DEF_VMLE(32, 64)
+
+#define DEF_VMO(BITS, TBITS) \
+void HELPER(gvec_vmo##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 1; i < (128 / TBITS); i++, j += 2) { \
+ int##TBITS##_t a = (int##BITS##_t)s390_vec_read_element##BITS(v2, j); \
+ int##TBITS##_t b = (int##BITS##_t)s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMO(8, 16)
+DEF_VMO(16, 32)
+DEF_VMO(32, 64)
+
+#define DEF_VMLO(BITS, TBITS) \
+void HELPER(gvec_vmlo##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i, j; \
+ \
+ for (i = 0, j = 0; i < (128 / TBITS); i++, j += 2) { \
+ const uint##TBITS##_t a = s390_vec_read_element##BITS(v2, j); \
+ const uint##TBITS##_t b = s390_vec_read_element##BITS(v3, j); \
+ \
+ s390_vec_write_element##TBITS(v1, i, a * b); \
+ } \
+}
+DEF_VMLO(8, 16)
+DEF_VMLO(16, 32)
+DEF_VMLO(32, 64)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 21/41] s390x/tcg: Implement VECTOR NAND
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Part of vector enhancements facility 1, but easy to implement.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c | 1 +
target/s390x/translate_vx.inc.c | 7 +++++++
3 files changed, 10 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2c794a2744..bc8b84e1c2 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1134,6 +1134,8 @@
F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL ODD */
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR NAND */
+ F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a800aa9dc9..c6378b2b53 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -6099,6 +6099,7 @@ enum DisasInsnEnum {
#define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
#define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
#define FAC_V S390_FEAT_VECTOR /* vector facility */
+#define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
static const DisasInsn insn_info[] = {
#include "insn-data.def"
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index fddab1f47e..84ff58823f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1815,3 +1815,10 @@ static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nand, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 21/41] s390x/tcg: Implement VECTOR NAND
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Part of vector enhancements facility 1, but easy to implement.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c | 1 +
target/s390x/translate_vx.inc.c | 7 +++++++
3 files changed, 10 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2c794a2744..bc8b84e1c2 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1134,6 +1134,8 @@
F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL ODD */
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR NAND */
+ F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index a800aa9dc9..c6378b2b53 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -6099,6 +6099,7 @@ enum DisasInsnEnum {
#define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
#define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
#define FAC_V S390_FEAT_VECTOR /* vector facility */
+#define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
static const DisasInsn insn_info[] = {
#include "insn-data.def"
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index fddab1f47e..84ff58823f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1815,3 +1815,10 @@ static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nand, ES_8, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 22/41] s390x/tcg: Implement VECTOR NOR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index bc8b84e1c2..4983867a44 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1136,6 +1136,8 @@
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR NAND */
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
+/* VECTOR NOR */
+ F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 84ff58823f..967da6d211 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1822,3 +1822,10 @@ static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
get_field(s->fields, v2), get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 22/41] s390x/tcg: Implement VECTOR NOR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index bc8b84e1c2..4983867a44 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1136,6 +1136,8 @@
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR NAND */
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
+/* VECTOR NOR */
+ F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 84ff58823f..967da6d211 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1822,3 +1822,10 @@ static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
get_field(s->fields, v2), get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(nor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 23/41] s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Again, part of vector enhancement facility 1. The operation corresponds
to an bitwise equality check.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 4983867a44..b549b76b96 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1138,6 +1138,8 @@
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
/* VECTOR NOR */
F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
+/* VECTOR NOT EXCLUSIVE OR */
+ F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 967da6d211..7c05af2c83 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1829,3 +1829,10 @@ static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(eqv, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 23/41] s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Again, part of vector enhancement facility 1. The operation corresponds
to an bitwise equality check.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 4983867a44..b549b76b96 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1138,6 +1138,8 @@
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
/* VECTOR NOR */
F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
+/* VECTOR NOT EXCLUSIVE OR */
+ F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 967da6d211..7c05af2c83 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1829,3 +1829,10 @@ static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(eqv, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 24/41] s390x/tcg: Implement VECTOR OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Reuse a gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b549b76b96..fb74374a0a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1140,6 +1140,8 @@
F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
/* VECTOR NOT EXCLUSIVE OR */
F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
+/* VECTOR OR */
+ F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7c05af2c83..784accd58a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1836,3 +1836,10 @@ static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(or, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 24/41] s390x/tcg: Implement VECTOR OR
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Reuse a gvec helper.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index b549b76b96..fb74374a0a 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1140,6 +1140,8 @@
F(0xe76b, VNO, VRR_c, V, 0, 0, 0, 0, vno, 0, IF_VEC)
/* VECTOR NOT EXCLUSIVE OR */
F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
+/* VECTOR OR */
+ F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7c05af2c83..784accd58a 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1836,3 +1836,10 @@ static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(or, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 25/41] s390x/tcg: Implement VECTOR OR WITH COMPLEMENT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Again, vector enhancements facility 1 material.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fb74374a0a..52171252be 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1142,6 +1142,8 @@
F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
/* VECTOR OR */
F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
+/* VECTOR OR WITH COMPLEMENT */
+ F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 784accd58a..bfc896499b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1843,3 +1843,10 @@ static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(orc, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 25/41] s390x/tcg: Implement VECTOR OR WITH COMPLEMENT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Again, vector enhancements facility 1 material.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index fb74374a0a..52171252be 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1142,6 +1142,8 @@
F(0xe76c, VNX, VRR_c, VE, 0, 0, 0, 0, vnx, 0, IF_VEC)
/* VECTOR OR */
F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
+/* VECTOR OR WITH COMPLEMENT */
+ F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 784accd58a..bfc896499b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1843,3 +1843,10 @@ static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_fn_3(orc, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 26/41] s390x/tcg: Implement VECTOR POPULATION COUNT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR COUNT TRAILING ZEROES.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 37 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 01b2009271..239d45220d 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -198,6 +198,8 @@ DEF_HELPER_FLAGS_4(gvec_vmo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 52171252be..0f786d6ab1 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1144,6 +1144,8 @@
F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
/* VECTOR OR WITH COMPLEMENT */
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
+/* VECTOR POPULATION COUNT */
+ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index bfc896499b..077da3b06e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1850,3 +1850,22 @@ static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vpopct8, },
+ { .fno = gen_helper_gvec_vpopct16, },
+ { .fni4 = tcg_gen_ctpop_i32, },
+ { .fni8 = tcg_gen_ctpop_i64, },
+ };
+
+ if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 9bb607af05..c66ec3d2f4 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -478,3 +478,17 @@ void HELPER(gvec_vmlo##BITS)(void *v1, const void *v2, const void *v3, \
DEF_VMLO(8, 16)
DEF_VMLO(16, 32)
DEF_VMLO(32, 64)
+
+#define DEF_VPOPCT(BITS) \
+void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, ctpop32(a)); \
+ } \
+}
+DEF_VPOPCT(8)
+DEF_VPOPCT(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 26/41] s390x/tcg: Implement VECTOR POPULATION COUNT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR COUNT TRAILING ZEROES.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 19 +++++++++++++++++++
target/s390x/vec_int_helper.c | 14 ++++++++++++++
4 files changed, 37 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 01b2009271..239d45220d 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -198,6 +198,8 @@ DEF_HELPER_FLAGS_4(gvec_vmo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 52171252be..0f786d6ab1 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1144,6 +1144,8 @@
F(0xe76a, VO, VRR_c, V, 0, 0, 0, 0, vo, 0, IF_VEC)
/* VECTOR OR WITH COMPLEMENT */
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
+/* VECTOR POPULATION COUNT */
+ F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index bfc896499b..077da3b06e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -1850,3 +1850,22 @@ static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m3);
+ static const GVecGen2 g[4] = {
+ { .fno = gen_helper_gvec_vpopct8, },
+ { .fno = gen_helper_gvec_vpopct16, },
+ { .fni4 = tcg_gen_ctpop_i32, },
+ { .fni8 = tcg_gen_ctpop_i64, },
+ };
+
+ if (es > ES_64 || (es != ES_8 && !s390_has_feat(S390_FEAT_VECTOR_ENH))) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 9bb607af05..c66ec3d2f4 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -478,3 +478,17 @@ void HELPER(gvec_vmlo##BITS)(void *v1, const void *v2, const void *v3, \
DEF_VMLO(8, 16)
DEF_VMLO(16, 32)
DEF_VMLO(32, 64)
+
+#define DEF_VPOPCT(BITS) \
+void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, ctpop32(a)); \
+ } \
+}
+DEF_VPOPCT(8)
+DEF_VPOPCT(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Take care of properly taking the modulo of the count. We might later
want to come back and create a variant of VERLL where the base register
is 0, resulting in an immediate.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 3 ++
target/s390x/translate_vx.inc.c | 60 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 31 +++++++++++++++++
4 files changed, 98 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 239d45220d..20b30133f9 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -200,6 +200,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 0f786d6ab1..e765c15941 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1146,6 +1146,9 @@
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
/* VECTOR POPULATION COUNT */
F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
+/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
+ F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
+ F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 077da3b06e..6282615462 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2(v1, v2, gen) \
tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, gen)
+#define gen_gvec_2s(v1, v2, c, gen) \
+ tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, c, gen)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -1869,3 +1872,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_andi_i32(t0, b, 31);
+ tcg_gen_rotl_i32(d, a, t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t0, b, 63);
+ tcg_gen_rotl_i64(d, a, t0);
+ tcg_temp_free_i64(t0);
+}
+
+static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_verllv8, },
+ { .fno = gen_helper_gvec_verllv16, },
+ { .fni4 = gen_rll_i32, },
+ { .fni8 = gen_rll_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen2s g[4] = {
+ { .fno = gen_helper_gvec_verll8, },
+ { .fno = gen_helper_gvec_verll16, },
+ { .fni4 = gen_rll_i32, },
+ { .fni8 = gen_rll_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1,
+ &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index c66ec3d2f4..3cb9119536 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -492,3 +492,34 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VPOPCT(8)
DEF_VPOPCT(16)
+
+#define DEF_VERLLV(BITS) \
+void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); \
+ } \
+}
+DEF_VERLLV(8)
+DEF_VERLLV(16)
+
+#define DEF_VERLL(BITS) \
+void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); \
+ } \
+}
+DEF_VERLL(8)
+DEF_VERLL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Take care of properly taking the modulo of the count. We might later
want to come back and create a variant of VERLL where the base register
is 0, resulting in an immediate.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 4 +++
target/s390x/insn-data.def | 3 ++
target/s390x/translate_vx.inc.c | 60 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 31 +++++++++++++++++
4 files changed, 98 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 239d45220d..20b30133f9 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -200,6 +200,10 @@ DEF_HELPER_FLAGS_4(gvec_vmlo16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vmlo32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct8, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
DEF_HELPER_FLAGS_3(gvec_vpopct16, TCG_CALL_NO_RWG, void, ptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 0f786d6ab1..e765c15941 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1146,6 +1146,9 @@
F(0xe76f, VOC, VRR_c, VE, 0, 0, 0, 0, voc, 0, IF_VEC)
/* VECTOR POPULATION COUNT */
F(0xe750, VPOPCT, VRR_a, V, 0, 0, 0, 0, vpopct, 0, IF_VEC)
+/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
+ F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
+ F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 077da3b06e..6282615462 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -185,6 +185,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2(v1, v2, gen) \
tcg_gen_gvec_2(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, gen)
+#define gen_gvec_2s(v1, v2, c, gen) \
+ tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ 16, 16, c, gen)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -1869,3 +1872,60 @@ static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_rll_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_andi_i32(t0, b, 31);
+ tcg_gen_rotl_i32(d, a, t0);
+ tcg_temp_free_i32(t0);
+}
+
+static void gen_rll_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t0, b, 63);
+ tcg_gen_rotl_i64(d, a, t0);
+ tcg_temp_free_i64(t0);
+}
+
+static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_verllv8, },
+ { .fno = gen_helper_gvec_verllv16, },
+ { .fni4 = gen_rll_i32, },
+ { .fni8 = gen_rll_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen2s g[4] = {
+ { .fno = gen_helper_gvec_verll8, },
+ { .fno = gen_helper_gvec_verll16, },
+ { .fni4 = gen_rll_i32, },
+ { .fni8 = gen_rll_i64, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+ gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1,
+ &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index c66ec3d2f4..3cb9119536 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -492,3 +492,34 @@ void HELPER(gvec_vpopct##BITS)(void *v1, const void *v2, uint32_t desc) \
}
DEF_VPOPCT(8)
DEF_VPOPCT(16)
+
+#define DEF_VERLLV(BITS) \
+void HELPER(gvec_verllv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, rol##BITS(a, b)); \
+ } \
+}
+DEF_VERLLV(8)
+DEF_VERLLV(16)
+
+#define DEF_VERLL(BITS) \
+void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, rol##BITS(a, count)); \
+ } \
+}
+DEF_VERLL(8)
+DEF_VERLL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Use the new vector expansion for GVecGen3i.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 51 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 20 +++++++++++++
4 files changed, 75 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 20b30133f9..80d82e698a 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -204,6 +204,8 @@ DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e765c15941..59c323a796 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1149,6 +1149,8 @@
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
+/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
+ F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6282615462..03f8d53d75 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -197,6 +197,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
+#define gen_gvec_3i(v1, v2, v3, c, gen) \
+ tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), c, 16, 16, gen)
#define gen_gvec_4(v1, v2, v3, v4, gen) \
tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
@@ -1929,3 +1932,51 @@ static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
&g[es]);
return DISAS_NEXT;
}
+
+static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_rotli_i32(t, a, c & 31);
+ tcg_gen_and_i32(t, t, b);
+ tcg_gen_andc_i32(d, d, b);
+ tcg_gen_or_i32(d, d, t);
+
+ tcg_temp_free_i32(t);
+}
+
+static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_rotli_i64(t, a, c & 63);
+ tcg_gen_and_i64(t, t, b);
+ tcg_gen_andc_i64(d, d, b);
+ tcg_gen_or_i64(d, d, t);
+
+ tcg_temp_free_i64(t);
+}
+
+static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ const uint8_t i4 = get_field(s->fields, i4) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ static const GVecGen3i g[4] = {
+ { .fno = gen_helper_gvec_verim8, },
+ { .fno = gen_helper_gvec_verim16, },
+ { .fni4 = gen_rim_i32,
+ .load_dest = true, },
+ { .fni8 = gen_rim_i64,
+ .load_dest = true, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_3i(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), i4, &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 3cb9119536..6bc7498572 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -14,6 +14,7 @@
#include "cpu.h"
#include "vec.h"
#include "exec/helper-proto.h"
+#include "tcg/tcg-gvec-desc.h"
static bool s390_vec_is_zero(const S390Vector *v)
{
@@ -523,3 +524,22 @@ void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
}
DEF_VERLL(8)
DEF_VERLL(16)
+
+#define DEF_VERIM(BITS) \
+void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ const uint8_t count = simd_data(desc); \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v1, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t mask = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t d = (a & ~mask) | (rol##BITS(b, count) & mask); \
+ \
+ s390_vec_write_element##BITS(v1, i, d); \
+ } \
+}
+DEF_VERIM(8)
+DEF_VERIM(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Use the new vector expansion for GVecGen3i.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 51 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 20 +++++++++++++
4 files changed, 75 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 20b30133f9..80d82e698a 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -204,6 +204,8 @@ DEF_HELPER_FLAGS_4(gvec_verllv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verllv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index e765c15941..59c323a796 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1149,6 +1149,8 @@
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */
F(0xe773, VERLLV, VRR_c, V, 0, 0, 0, 0, verllv, 0, IF_VEC)
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
+/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
+ F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6282615462..03f8d53d75 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -197,6 +197,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_3_ptr(v1, v2, v3, ptr, data, fn) \
tcg_gen_gvec_3_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
+#define gen_gvec_3i(v1, v2, v3, c, gen) \
+ tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ vec_full_reg_offset(v3), c, 16, 16, gen)
#define gen_gvec_4(v1, v2, v3, v4, gen) \
tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
@@ -1929,3 +1932,51 @@ static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
&g[es]);
return DISAS_NEXT;
}
+
+static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, int32_t c)
+{
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ tcg_gen_rotli_i32(t, a, c & 31);
+ tcg_gen_and_i32(t, t, b);
+ tcg_gen_andc_i32(d, d, b);
+ tcg_gen_or_i32(d, d, t);
+
+ tcg_temp_free_i32(t);
+}
+
+static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_rotli_i64(t, a, c & 63);
+ tcg_gen_and_i64(t, t, b);
+ tcg_gen_andc_i64(d, d, b);
+ tcg_gen_or_i64(d, d, t);
+
+ tcg_temp_free_i64(t);
+}
+
+static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m5);
+ const uint8_t i4 = get_field(s->fields, i4) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ static const GVecGen3i g[4] = {
+ { .fno = gen_helper_gvec_verim8, },
+ { .fno = gen_helper_gvec_verim16, },
+ { .fni4 = gen_rim_i32,
+ .load_dest = true, },
+ { .fni8 = gen_rim_i64,
+ .load_dest = true, },
+ };
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec_3i(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), i4, &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 3cb9119536..6bc7498572 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -14,6 +14,7 @@
#include "cpu.h"
#include "vec.h"
#include "exec/helper-proto.h"
+#include "tcg/tcg-gvec-desc.h"
static bool s390_vec_is_zero(const S390Vector *v)
{
@@ -523,3 +524,22 @@ void HELPER(gvec_verll##BITS)(void *v1, const void *v2, uint64_t count, \
}
DEF_VERLL(8)
DEF_VERLL(16)
+
+#define DEF_VERIM(BITS) \
+void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ const uint8_t count = simd_data(desc); \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v1, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t mask = s390_vec_read_element##BITS(v3, i); \
+ const uint##BITS##_t d = (a & ~mask) | (rol##BITS(b, count) & mask); \
+ \
+ s390_vec_write_element##BITS(v1, i, d); \
+ } \
+}
+DEF_VERIM(8)
+DEF_VERIM(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 29/41] s390x/tcg: Implement VECTOR ELEMENT SHIFT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Only for one special case we can reuse real gvec helpers. Mostly
rely on oom helpers.
One important thing to take care of is always to properly mask of
unused bits from the shift count.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 18 +++++
target/s390x/insn-data.def | 9 +++
target/s390x/translate_vx.inc.c | 113 ++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 99 ++++++++++++++++++++++++++++
4 files changed, 239 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 80d82e698a..26837b43c5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -206,6 +206,24 @@ DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesra8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 59c323a796..f4b67bda7e 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1151,6 +1151,15 @@
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT LEFT */
+ F(0xe770, VESLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe730, VESL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
+ F(0xe77a, VESRAV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe73a, VESRA, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
+ F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 03f8d53d75..35a9161c2b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -218,6 +218,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_fn_2(fn, es, v1, v2) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16)
+#define gen_gvec_fn_2i(fn, es, v1, v2, c) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16)
#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16)
@@ -1980,3 +1983,113 @@ static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), i4, &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g_veslv[4] = {
+ { .fno = gen_helper_gvec_veslv8, },
+ { .fno = gen_helper_gvec_veslv16, },
+ { .fno = gen_helper_gvec_veslv32, },
+ { .fno = gen_helper_gvec_veslv64, },
+ };
+ static const GVecGen3 g_vesrav[4] = {
+ { .fno = gen_helper_gvec_vesrav8, },
+ { .fno = gen_helper_gvec_vesrav16, },
+ { .fno = gen_helper_gvec_vesrav32, },
+ { .fno = gen_helper_gvec_vesrav64, },
+ };
+ static const GVecGen3 g_vesrlv[4] = {
+ { .fno = gen_helper_gvec_vesrlv8, },
+ { .fno = gen_helper_gvec_vesrlv16, },
+ { .fno = gen_helper_gvec_vesrlv32, },
+ { .fno = gen_helper_gvec_vesrlv64, },
+ };
+ const GVecGen3 *fn;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0x70:
+ fn = &g_veslv[es];
+ break;
+ case 0x7a:
+ fn = &g_vesrav[es];
+ break;
+ case 0x78:
+ fn = &g_vesrlv[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ const uint8_t d2 = get_field(s->fields, d2) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v3 = get_field(s->fields, v3);
+ static const GVecGen2s g_vesl[4] = {
+ { .fno = gen_helper_gvec_vesl8, },
+ { .fno = gen_helper_gvec_vesl16, },
+ { .fni4 = tcg_gen_shl_i32, },
+ { .fni8 = tcg_gen_shl_i64, },
+ };
+ static const GVecGen2s g_vesra[4] = {
+ { .fno = gen_helper_gvec_vesra8, },
+ { .fno = gen_helper_gvec_vesra16, },
+ { .fni4 = tcg_gen_sar_i32, },
+ { .fni8 = tcg_gen_sar_i64, },
+ };
+ static const GVecGen2s g_vesrl[4] = {
+ { .fno = gen_helper_gvec_vesrl8, },
+ { .fno = gen_helper_gvec_vesrl16, },
+ { .fni4 = tcg_gen_shr_i32, },
+ { .fni8 = tcg_gen_shr_i64, },
+ };
+ const GVecGen2s *fn;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0x30:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(shli, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesl[es];
+ break;
+ case 0x3a:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(sari, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesra[es];
+ break;
+ case 0x38:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(shri, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesrl[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ tcg_gen_andi_i64(o->addr1, o->addr1, NUM_VEC_ELEMENT_BITS(es) - 1);
+ gen_gvec_2s(v1, v3, o->addr1, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 6bc7498572..266a752b76 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -543,3 +543,102 @@ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VERIM(8)
DEF_VERIM(16)
+
+#define DEF_VESLV(BITS) \
+void HELPER(gvec_veslv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a << shift); \
+ } \
+}
+DEF_VESLV(8)
+DEF_VESLV(16)
+DEF_VESLV(32)
+DEF_VESLV(64)
+
+#define DEF_VESRAV(BITS) \
+void HELPER(gvec_vesrav##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRAV(8)
+DEF_VESRAV(16)
+DEF_VESRAV(32)
+DEF_VESRAV(64)
+
+#define DEF_VESRLV(BITS) \
+void HELPER(gvec_vesrlv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRLV(8)
+DEF_VESRLV(16)
+DEF_VESRLV(32)
+DEF_VESRLV(64)
+
+#define DEF_VESL(BITS) \
+void HELPER(gvec_vesl##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a << shift); \
+ } \
+}
+DEF_VESL(8)
+DEF_VESL(16)
+
+#define DEF_VESRA(BITS) \
+void HELPER(gvec_vesra##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRA(8)
+DEF_VESRA(16)
+
+#define DEF_VESRL(BITS) \
+void HELPER(gvec_vesrl##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRL(8)
+DEF_VESRL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 29/41] s390x/tcg: Implement VECTOR ELEMENT SHIFT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Only for one special case we can reuse real gvec helpers. Mostly
rely on oom helpers.
One important thing to take care of is always to properly mask of
unused bits from the shift count.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 18 +++++
target/s390x/insn-data.def | 9 +++
target/s390x/translate_vx.inc.c | 113 ++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 99 ++++++++++++++++++++++++++++
4 files changed, 239 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 80d82e698a..26837b43c5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -206,6 +206,24 @@ DEF_HELPER_FLAGS_4(gvec_verll8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verll16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_verim8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_verim16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_veslv64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrav64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv32, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrlv64, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vesl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesra8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 59c323a796..f4b67bda7e 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1151,6 +1151,15 @@
F(0xe733, VERLL, VRS_a, V, la2, 0, 0, 0, verll, 0, IF_VEC)
/* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
F(0xe772, VERIM, VRI_d, V, 0, 0, 0, 0, verim, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT LEFT */
+ F(0xe770, VESLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe730, VESL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
+ F(0xe77a, VESRAV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe73a, VESRA, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
+ F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
+ F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 03f8d53d75..35a9161c2b 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -218,6 +218,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_fn_2(fn, es, v1, v2) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16)
+#define gen_gvec_fn_2i(fn, es, v1, v2, c) \
+ tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16)
#define gen_gvec_fn_3(fn, es, v1, v2, v3) \
tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16)
@@ -1980,3 +1983,113 @@ static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), i4, &g[es]);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g_veslv[4] = {
+ { .fno = gen_helper_gvec_veslv8, },
+ { .fno = gen_helper_gvec_veslv16, },
+ { .fno = gen_helper_gvec_veslv32, },
+ { .fno = gen_helper_gvec_veslv64, },
+ };
+ static const GVecGen3 g_vesrav[4] = {
+ { .fno = gen_helper_gvec_vesrav8, },
+ { .fno = gen_helper_gvec_vesrav16, },
+ { .fno = gen_helper_gvec_vesrav32, },
+ { .fno = gen_helper_gvec_vesrav64, },
+ };
+ static const GVecGen3 g_vesrlv[4] = {
+ { .fno = gen_helper_gvec_vesrlv8, },
+ { .fno = gen_helper_gvec_vesrlv16, },
+ { .fno = gen_helper_gvec_vesrlv32, },
+ { .fno = gen_helper_gvec_vesrlv64, },
+ };
+ const GVecGen3 *fn;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0x70:
+ fn = &g_veslv[es];
+ break;
+ case 0x7a:
+ fn = &g_vesrav[es];
+ break;
+ case 0x78:
+ fn = &g_vesrlv[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), fn);
+ return DISAS_NEXT;
+}
+
+static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ const uint8_t d2 = get_field(s->fields, d2) &
+ (NUM_VEC_ELEMENT_BITS(es) - 1);
+ const uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v3 = get_field(s->fields, v3);
+ static const GVecGen2s g_vesl[4] = {
+ { .fno = gen_helper_gvec_vesl8, },
+ { .fno = gen_helper_gvec_vesl16, },
+ { .fni4 = tcg_gen_shl_i32, },
+ { .fni8 = tcg_gen_shl_i64, },
+ };
+ static const GVecGen2s g_vesra[4] = {
+ { .fno = gen_helper_gvec_vesra8, },
+ { .fno = gen_helper_gvec_vesra16, },
+ { .fni4 = tcg_gen_sar_i32, },
+ { .fni8 = tcg_gen_sar_i64, },
+ };
+ static const GVecGen2s g_vesrl[4] = {
+ { .fno = gen_helper_gvec_vesrl8, },
+ { .fno = gen_helper_gvec_vesrl16, },
+ { .fni4 = tcg_gen_shr_i32, },
+ { .fni8 = tcg_gen_shr_i64, },
+ };
+ const GVecGen2s *fn;
+
+ if (es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ switch (s->fields->op2) {
+ case 0x30:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(shli, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesl[es];
+ break;
+ case 0x3a:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(sari, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesra[es];
+ break;
+ case 0x38:
+ if (likely(!get_field(s->fields, b2))) {
+ gen_gvec_fn_2i(shri, es, v1, v3, d2);
+ return DISAS_NEXT;
+ }
+ fn = &g_vesrl[es];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ tcg_gen_andi_i64(o->addr1, o->addr1, NUM_VEC_ELEMENT_BITS(es) - 1);
+ gen_gvec_2s(v1, v3, o->addr1, fn);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 6bc7498572..266a752b76 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -543,3 +543,102 @@ void HELPER(gvec_verim##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VERIM(8)
DEF_VERIM(16)
+
+#define DEF_VESLV(BITS) \
+void HELPER(gvec_veslv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a << shift); \
+ } \
+}
+DEF_VESLV(8)
+DEF_VESLV(16)
+DEF_VESLV(32)
+DEF_VESLV(64)
+
+#define DEF_VESRAV(BITS) \
+void HELPER(gvec_vesrav##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRAV(8)
+DEF_VESRAV(16)
+DEF_VESRAV(32)
+DEF_VESRAV(64)
+
+#define DEF_VESRLV(BITS) \
+void HELPER(gvec_vesrlv##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint8_t shift = s390_vec_read_element##BITS(v3, i) & (BITS - 1); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRLV(8)
+DEF_VESRLV(16)
+DEF_VESRLV(32)
+DEF_VESRLV(64)
+
+#define DEF_VESL(BITS) \
+void HELPER(gvec_vesl##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a << shift); \
+ } \
+}
+DEF_VESL(8)
+DEF_VESL(16)
+
+#define DEF_VESRA(BITS) \
+void HELPER(gvec_vesra##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const int##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRA(8)
+DEF_VESRA(16)
+
+#define DEF_VESRL(BITS) \
+void HELPER(gvec_vesrl##BITS)(void *v1, const void *v3, uint64_t shift, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a >> shift); \
+ } \
+}
+DEF_VESRL(8)
+DEF_VESRL(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 30/41] s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
We can reuse the existing 128-bit shift utility function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 20 ++++++++++++++++++++
target/s390x/vec_int_helper.c | 6 ++++++
4 files changed, 31 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 26837b43c5..8da4a6d32b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -224,6 +224,7 @@ DEF_HELPER_FLAGS_4(gvec_vesra8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f4b67bda7e..2621e433cd 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1160,6 +1160,10 @@
/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR SHIFT LEFT */
+ F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
+/* VECTOR SHIFT LEFT BY BYTE */
+ F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 35a9161c2b..e7f8aca238 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -188,6 +188,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2s(v1, v2, c, gen) \
tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, c, gen)
+#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
+ tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16, data, fn)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -2093,3 +2096,20 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
gen_gvec_2s(v1, v3, o->addr1, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x74) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 266a752b76..43b3cfd12a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -642,3 +642,9 @@ void HELPER(gvec_vesrl##BITS)(void *v1, const void *v3, uint64_t shift, \
}
DEF_VESRL(8)
DEF_VESRL(16)
+
+void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_shl(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 30/41] s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
We can reuse the existing 128-bit shift utility function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 20 ++++++++++++++++++++
target/s390x/vec_int_helper.c | 6 ++++++
4 files changed, 31 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 26837b43c5..8da4a6d32b 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -224,6 +224,7 @@ DEF_HELPER_FLAGS_4(gvec_vesra8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f4b67bda7e..2621e433cd 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1160,6 +1160,10 @@
/* VECTOR ELEMENT SHIFT RIGHT LOGICAL */
F(0xe778, VESRLV, VRR_c, V, 0, 0, 0, 0, vesv, 0, IF_VEC)
F(0xe738, VESRL, VRS_a, V, la2, 0, 0, 0, ves, 0, IF_VEC)
+/* VECTOR SHIFT LEFT */
+ F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
+/* VECTOR SHIFT LEFT BY BYTE */
+ F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 35a9161c2b..e7f8aca238 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -188,6 +188,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2s(v1, v2, c, gen) \
tcg_gen_gvec_2s(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
16, 16, c, gen)
+#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
+ tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ c, 16, 16, data, fn)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -2093,3 +2096,20 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
gen_gvec_2s(v1, v3, o->addr1, fn);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x74) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 266a752b76..43b3cfd12a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -642,3 +642,9 @@ void HELPER(gvec_vesrl##BITS)(void *v1, const void *v3, uint64_t shift, \
}
DEF_VESRL(8)
DEF_VESRL(16)
+
+void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_shl(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 31/41] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Inline expansion courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2621e433cd..76aec5a21f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1164,6 +1164,8 @@
F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
/* VECTOR SHIFT LEFT BY BYTE */
F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
+/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
+ F(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsldb, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index e7f8aca238..c49c4b3618 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2113,3 +2113,32 @@ static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
+{
+ const uint8_t i4 = get_field(s->fields, i4) & 0xf;
+ const int left_shift = (i4 & 7) * 8;
+ const int right_shift = 64 - left_shift;
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ if ((i4 & 8) == 0) {
+ read_vec_element_i64(t0, get_field(s->fields, v2), 0, ES_64);
+ read_vec_element_i64(t1, get_field(s->fields, v2), 1, ES_64);
+ read_vec_element_i64(t2, get_field(s->fields, v3), 0, ES_64);
+ } else {
+ read_vec_element_i64(t0, get_field(s->fields, v2), 1, ES_64);
+ read_vec_element_i64(t1, get_field(s->fields, v3), 0, ES_64);
+ read_vec_element_i64(t2, get_field(s->fields, v3), 1, ES_64);
+ }
+ tcg_gen_extract2_i64(t0, t1, t0, right_shift);
+ tcg_gen_extract2_i64(t1, t2, t1, right_shift);
+ write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 31/41] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Inline expansion courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2621e433cd..76aec5a21f 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1164,6 +1164,8 @@
F(0xe774, VSL, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
/* VECTOR SHIFT LEFT BY BYTE */
F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
+/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
+ F(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsldb, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index e7f8aca238..c49c4b3618 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2113,3 +2113,32 @@ static DisasJumpType op_vsl(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
+{
+ const uint8_t i4 = get_field(s->fields, i4) & 0xf;
+ const int left_shift = (i4 & 7) * 8;
+ const int right_shift = 64 - left_shift;
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ if ((i4 & 8) == 0) {
+ read_vec_element_i64(t0, get_field(s->fields, v2), 0, ES_64);
+ read_vec_element_i64(t1, get_field(s->fields, v2), 1, ES_64);
+ read_vec_element_i64(t2, get_field(s->fields, v3), 0, ES_64);
+ } else {
+ read_vec_element_i64(t0, get_field(s->fields, v2), 1, ES_64);
+ read_vec_element_i64(t1, get_field(s->fields, v3), 0, ES_64);
+ read_vec_element_i64(t2, get_field(s->fields, v3), 1, ES_64);
+ }
+ tcg_gen_extract2_i64(t0, t1, t0, right_shift);
+ tcg_gen_extract2_i64(t1, t2, t1, right_shift);
+ write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 32/41] s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to
s390_vec_shr().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
target/s390x/vec_int_helper.c | 26 ++++++++++++++++++++++++++
4 files changed, 48 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 8da4a6d32b..53c8b6f4bd 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -225,6 +225,7 @@ DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 76aec5a21f..587de3eaac 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1166,6 +1166,10 @@
F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
F(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsldb, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT ARITHMETIC */
+ F(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
+ F(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index c49c4b3618..7b5f484359 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2142,3 +2142,20 @@ static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
tcg_temp_free(t2);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x7e) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsra);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 43b3cfd12a..056e17d3c7 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -49,6 +49,26 @@ static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
}
}
+static void s390_vec_sar(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[1] = a->doubleword[0];
+ d->doubleword[0] = 0;
+ } else if (count < 64) {
+ tmp = a->doubleword[1] >> count;
+ d->doubleword[1] = deposit64(tmp, 64 - count, count, a->doubleword[0]);
+ d->doubleword[0] = (int64_t)a->doubleword[0] >> count;
+ } else {
+ d->doubleword[1] = (int64_t)a->doubleword[0] >> (count - 64);
+ d->doubleword[0] = 0;
+ }
+}
+
static void s390_vec_shr(S390Vector *d, const S390Vector *a, uint64_t count)
{
uint64_t tmp;
@@ -648,3 +668,9 @@ void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count,
{
s390_vec_shl(v1, v2, count);
}
+
+void HELPER(gvec_vsra)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_sar(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 32/41] s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to
s390_vec_shr().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
target/s390x/vec_int_helper.c | 26 ++++++++++++++++++++++++++
4 files changed, 48 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 8da4a6d32b..53c8b6f4bd 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -225,6 +225,7 @@ DEF_HELPER_FLAGS_4(gvec_vesra16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 76aec5a21f..587de3eaac 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1166,6 +1166,10 @@
F(0xe775, VSLB, VRR_c, V, 0, 0, 0, 0, vsl, 0, IF_VEC)
/* VECTOR SHIFT LEFT DOUBLE BY BYTE */
F(0xe777, VSLDB, VRI_d, V, 0, 0, 0, 0, vsldb, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT ARITHMETIC */
+ F(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
+ F(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index c49c4b3618..7b5f484359 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2142,3 +2142,20 @@ static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
tcg_temp_free(t2);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x7e) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsra);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 43b3cfd12a..056e17d3c7 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -49,6 +49,26 @@ static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
}
}
+static void s390_vec_sar(S390Vector *d, const S390Vector *a, uint64_t count)
+{
+ uint64_t tmp;
+
+ if (count == 0) {
+ d->doubleword[0] = a->doubleword[0];
+ d->doubleword[1] = a->doubleword[1];
+ } else if (count == 64) {
+ d->doubleword[1] = a->doubleword[0];
+ d->doubleword[0] = 0;
+ } else if (count < 64) {
+ tmp = a->doubleword[1] >> count;
+ d->doubleword[1] = deposit64(tmp, 64 - count, count, a->doubleword[0]);
+ d->doubleword[0] = (int64_t)a->doubleword[0] >> count;
+ } else {
+ d->doubleword[1] = (int64_t)a->doubleword[0] >> (count - 64);
+ d->doubleword[0] = 0;
+ }
+}
+
static void s390_vec_shr(S390Vector *d, const S390Vector *a, uint64_t count)
{
uint64_t tmp;
@@ -648,3 +668,9 @@ void HELPER(gvec_vsl)(void *v1, const void *v2, uint64_t count,
{
s390_vec_shl(v1, v2, count);
}
+
+void HELPER(gvec_vsra)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_sar(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 33/41] s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR SHIFT RIGHT ARITHMETICAL.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
target/s390x/vec_int_helper.c | 6 ++++++
4 files changed, 28 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 53c8b6f4bd..e6d86736e2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -226,6 +226,7 @@ DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 587de3eaac..f3bf9edfca 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1170,6 +1170,10 @@
F(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
F(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT LOGICAL */
+ F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
+ F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7b5f484359..6188f5b11e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2159,3 +2159,20 @@ static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x7c) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsrl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 056e17d3c7..04ee2be4f9 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -674,3 +674,9 @@ void HELPER(gvec_vsra)(void *v1, const void *v2, uint64_t count,
{
s390_vec_sar(v1, v2, count);
}
+
+void HELPER(gvec_vsrl)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_shr(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 33/41] s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR SHIFT RIGHT ARITHMETICAL.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 4 ++++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
target/s390x/vec_int_helper.c | 6 ++++++
4 files changed, 28 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 53c8b6f4bd..e6d86736e2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -226,6 +226,7 @@ DEF_HELPER_FLAGS_4(gvec_vesrl8, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 587de3eaac..f3bf9edfca 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1170,6 +1170,10 @@
F(0xe77e, VSRA, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
/* VECTOR SHIFT RIGHT ARITHMETIC BY BYTE */
F(0xe77f, VSRAB, VRR_c, V, 0, 0, 0, 0, vsra, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT LOGICAL */
+ F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
+/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
+ F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 7b5f484359..6188f5b11e 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2159,3 +2159,20 @@ static DisasJumpType op_vsra(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 shift = tcg_temp_new_i64();
+
+ read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ if (s->fields->op2 == 0x7c) {
+ tcg_gen_andi_i64(shift, shift, 0x7);
+ } else {
+ tcg_gen_andi_i64(shift, shift, 0x78);
+ }
+
+ gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ shift, 0, gen_helper_gvec_vsrl);
+ tcg_temp_free_i64(shift);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 056e17d3c7..04ee2be4f9 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -674,3 +674,9 @@ void HELPER(gvec_vsra)(void *v1, const void *v2, uint64_t count,
{
s390_vec_sar(v1, v2, count);
}
+
+void HELPER(gvec_vsrl)(void *v1, const void *v2, uint64_t count,
+ uint32_t desc)
+{
+ s390_vec_shr(v1, v2, count);
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 34/41] s390x/tcg: Implement VECTOR SUBTRACT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise
existing gvec helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f3bf9edfca..58a61f41ef 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1174,6 +1174,8 @@
F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
+/* VECTOR SUBTRACT */
+ F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6188f5b11e..2df03baf07 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2176,3 +2176,20 @@ static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(sub, es, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 34/41] s390x/tcg: Implement VECTOR SUBTRACT
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise
existing gvec helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 17 +++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index f3bf9edfca..58a61f41ef 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1174,6 +1174,8 @@
F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
+/* VECTOR SUBTRACT */
+ F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6188f5b11e..2df03baf07 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2176,3 +2176,20 @@ static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(shift);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_fn_3(sub, es, get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 35/41] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Let's keep it simple for now and handle 8/16 bit elements via helpers.
Especially for 8/16, we could come up with some bit tricks.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 16 ++++++++++
4 files changed, 72 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index e6d86736e2..431e0a8084 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -227,6 +227,8 @@ DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 58a61f41ef..94de3c9c7d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1176,6 +1176,8 @@
F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
/* VECTOR SUBTRACT */
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
+/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
+ F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 2df03baf07..8e51b6e607 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2193,3 +2193,55 @@ static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_setcond_i32(TCG_COND_LTU, d, a, b);
+}
+
+static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_setcond_i64(TCG_COND_LTU, d, a, b);
+}
+
+static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_sub2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_andi_i64(th, th, 1);
+ tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
+ tcg_gen_andi_i64(dl, th, 1);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vscbi8, },
+ { .fno = gen_helper_gvec_vscbi16, },
+ { .fni4 = gen_scbi_i32, },
+ { .fni8 = gen_scbi_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_scbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 04ee2be4f9..5b007adc26 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -680,3 +680,19 @@ void HELPER(gvec_vsrl)(void *v1, const void *v2, uint64_t count,
{
s390_vec_shr(v1, v2, count);
}
+
+#define DEF_VSCBI(BITS) \
+void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a < b); \
+ } \
+}
+DEF_VSCBI(8)
+DEF_VSCBI(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 35/41] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Let's keep it simple for now and handle 8/16 bit elements via helpers.
Especially for 8/16, we could come up with some bit tricks.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
target/s390x/vec_int_helper.c | 16 ++++++++++
4 files changed, 72 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index e6d86736e2..431e0a8084 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -227,6 +227,8 @@ DEF_HELPER_FLAGS_4(gvec_vesrl16, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
+DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 58a61f41ef..94de3c9c7d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1176,6 +1176,8 @@
F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC)
/* VECTOR SUBTRACT */
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
+/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
+ F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 2df03baf07..8e51b6e607 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2193,3 +2193,55 @@ static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
get_field(s->fields, v3));
return DISAS_NEXT;
}
+
+static void gen_scbi_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_setcond_i32(TCG_COND_LTU, d, a, b);
+}
+
+static void gen_scbi_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_setcond_i64(TCG_COND_LTU, d, a, b);
+}
+
+static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al,
+ TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_sub2_i64(tl, th, al, zero, bl, zero);
+ tcg_gen_andi_i64(th, th, 1);
+ tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
+ tcg_gen_andi_i64(dl, th, 1);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ static const GVecGen3 g[4] = {
+ { .fno = gen_helper_gvec_vscbi8, },
+ { .fno = gen_helper_gvec_vscbi16, },
+ { .fni4 = gen_scbi_i32, },
+ { .fni8 = gen_scbi_i64, },
+ };
+
+ if (es > ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ } else if (es == ES_128) {
+ gen_gvec128_3_i64(gen_scbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3));
+ return DISAS_NEXT;
+ }
+ gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
+ get_field(s->fields, v3), &g[es]);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 04ee2be4f9..5b007adc26 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -680,3 +680,19 @@ void HELPER(gvec_vsrl)(void *v1, const void *v2, uint64_t count,
{
s390_vec_shr(v1, v2, count);
}
+
+#define DEF_VSCBI(BITS) \
+void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \
+ uint32_t desc) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < (128 / BITS); i++) { \
+ const uint##BITS##_t a = s390_vec_read_element##BITS(v2, i); \
+ const uint##BITS##_t b = s390_vec_read_element##BITS(v3, i); \
+ \
+ s390_vec_write_element##BITS(v1, i, a < b); \
+ } \
+}
+DEF_VSCBI(8)
+DEF_VSCBI(16)
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 36/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Fairly easy as only 128-bit handling is required. Simply perform the
subtraction and then subtract the borrow.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 26 ++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 94de3c9c7d..a60d8531dc 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1178,6 +1178,8 @@
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
+/* VECTOR SUBTRACT WITH BORROW INDICATION */
+ F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 8e51b6e607..794588ae96 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2245,3 +2245,29 @@ static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_sub2_i64(dl, dh, al, ah, bl, bh);
+ tcg_gen_sub2_i64(dl, dh, dl, dh, tl, zero);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 36/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Fairly easy as only 128-bit handling is required. Simply perform the
subtraction and then subtract the borrow.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 26 ++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 94de3c9c7d..a60d8531dc 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1178,6 +1178,8 @@
F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC)
/* VECTOR SUBTRACT COMPUTE BORROW INDICATION */
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
+/* VECTOR SUBTRACT WITH BORROW INDICATION */
+ F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 8e51b6e607..794588ae96 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2245,3 +2245,29 @@ static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v3), &g[es]);
return DISAS_NEXT;
}
+
+static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_sub2_i64(dl, dh, al, ah, bl, bh);
+ tcg_gen_sub2_i64(dl, dh, dl, dh, tl, zero);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 37/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand
Mostly courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34 +++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a60d8531dc..a8d90517f6 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1180,6 +1180,8 @@
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
/* VECTOR SUBTRACT WITH BORROW INDICATION */
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
+/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
+ F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 794588ae96..170605c7ed 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2271,3 +2271,37 @@ static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_sub2_i64(tl, th, al, zero, tl, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bl, zero);
+ tcg_gen_andi_i64(th, th, 1);
+ tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
+ tcg_gen_andi_i64(dl, th, 1);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 37/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Cornelia Huck, David Hildenbrand, Thomas Huth,
Richard Henderson
Mostly courtesy of Richard H.
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 34 +++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a60d8531dc..a8d90517f6 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1180,6 +1180,8 @@
F(0xe7f5, VSCBI, VRR_c, V, 0, 0, 0, 0, vscbi, 0, IF_VEC)
/* VECTOR SUBTRACT WITH BORROW INDICATION */
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
+/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
+ F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 794588ae96..170605c7ed 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2271,3 +2271,37 @@ static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
+ TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch)
+{
+ TCGv_i64 th = tcg_temp_new_i64();
+ TCGv_i64 tl = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tl, cl, 1);
+ tcg_gen_sub2_i64(tl, th, al, zero, tl, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bl, zero);
+ tcg_gen_andi_i64(th, th, 1);
+ tcg_gen_sub2_i64(tl, th, ah, zero, th, zero);
+ tcg_gen_sub2_i64(tl, th, tl, th, bh, zero);
+ tcg_gen_andi_i64(dl, th, 1);
+ tcg_gen_mov_i64(dh, zero);
+
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(zero);
+}
+
+static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
+{
+ if (get_field(s->fields, m5) != ES_128) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s->fields, v1),
+ get_field(s->fields, v2), get_field(s->fields, v3),
+ get_field(s->fields, v4));
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 38/41] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Perform the calculations without a helper. Only 16 bit or 32 bit values
have to be added.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a8d90517f6..dd37003082 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1182,6 +1182,8 @@
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
+/* VECTOR SUM ACROSS DOUBLEWORD */
+ F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 170605c7ed..1c781bcd68 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2305,3 +2305,32 @@ static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_i64 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es == ES_8 || es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+ for (dst_idx = 0; dst_idx < 2; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ read_vec_element_i64(sum, get_field(s->fields, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmp, get_field(s->fields, v2), idx, es);
+ tcg_gen_add_i64(sum, sum, tmp);
+ }
+ write_vec_element_i64(sum, get_field(s->fields, v1), dst_idx, ES_64);
+ }
+ tcg_temp_free_i64(sum);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 38/41] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Perform the calculations without a helper. Only 16 bit or 32 bit values
have to be added.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a8d90517f6..dd37003082 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1182,6 +1182,8 @@
F(0xe7bf, VSBI, VRR_d, V, 0, 0, 0, 0, vsbi, 0, IF_VEC)
/* VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION */
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
+/* VECTOR SUM ACROSS DOUBLEWORD */
+ F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 170605c7ed..1c781bcd68 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2305,3 +2305,32 @@ static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
get_field(s->fields, v4));
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_i64 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es == ES_8 || es > ES_32) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+ for (dst_idx = 0; dst_idx < 2; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1;
+
+ read_vec_element_i64(sum, get_field(s->fields, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmp, get_field(s->fields, v2), idx, es);
+ tcg_gen_add_i64(sum, sum, tmp);
+ }
+ write_vec_element_i64(sum, get_field(s->fields, v1), dst_idx, ES_64);
+ }
+ tcg_temp_free_i64(sum);
+ tcg_temp_free_i64(tmp);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 39/41] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and
using 128-bit calculations.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index dd37003082..2483ee01d7 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1184,6 +1184,8 @@
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
/* VECTOR SUM ACROSS DOUBLEWORD */
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
+/* VECTOR SUM ACROSS QUADWORD */
+ F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 1c781bcd68..82ab42d2d9 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2334,3 +2334,35 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1;
+ TCGv_i64 sumh, suml, zero, tmpl;
+ uint8_t idx;
+
+ if (es < ES_32 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sumh = tcg_const_i64(0);
+ suml = tcg_temp_new_i64();
+ zero = tcg_const_i64(0);
+ tmpl = tcg_temp_new_i64();
+
+ read_vec_element_i64(suml, get_field(s->fields, v3), max_idx, es);
+ for (idx = 0; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmpl, get_field(s->fields, v2), idx, es);
+ tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero);
+ }
+ write_vec_element_i64(sumh, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(suml, get_field(s->fields, v1), 1, ES_64);
+
+ tcg_temp_free_i64(sumh);
+ tcg_temp_free_i64(suml);
+ tcg_temp_free_i64(zero);
+ tcg_temp_free_i64(tmpl);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 39/41] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD
@ 2019-04-16 18:52 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:52 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and
using 128-bit calculations.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index dd37003082..2483ee01d7 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1184,6 +1184,8 @@
F(0xe7bd, VSBCBI, VRR_d, V, 0, 0, 0, 0, vsbcbi, 0, IF_VEC)
/* VECTOR SUM ACROSS DOUBLEWORD */
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
+/* VECTOR SUM ACROSS QUADWORD */
+ F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 1c781bcd68..82ab42d2d9 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2334,3 +2334,35 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1;
+ TCGv_i64 sumh, suml, zero, tmpl;
+ uint8_t idx;
+
+ if (es < ES_32 || es > ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sumh = tcg_const_i64(0);
+ suml = tcg_temp_new_i64();
+ zero = tcg_const_i64(0);
+ tmpl = tcg_temp_new_i64();
+
+ read_vec_element_i64(suml, get_field(s->fields, v3), max_idx, es);
+ for (idx = 0; idx <= max_idx; idx++) {
+ read_vec_element_i64(tmpl, get_field(s->fields, v2), idx, es);
+ tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero);
+ }
+ write_vec_element_i64(sumh, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(suml, get_field(s->fields, v1), 1, ES_64);
+
+ tcg_temp_free_i64(sumh);
+ tcg_temp_free_i64(suml);
+ tcg_temp_free_i64(zero);
+ tcg_temp_free_i64(tmpl);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 40/41] s390x/tcg: Implement VECTOR SUM ACROSS WORD
@ 2019-04-16 18:53 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:53 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Similar to VECTOR SUM ACROSS DOUBLEWORD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2483ee01d7..a52db41388 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1186,6 +1186,8 @@
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
/* VECTOR SUM ACROSS QUADWORD */
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
+/* VECTOR SUM ACROSS WORD */
+ F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 82ab42d2d9..1273bb5ded 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2366,3 +2366,32 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmpl);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_i32 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es > ES_16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
+ for (dst_idx = 0; dst_idx < 4; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1;
+
+ read_vec_element_i32(sum, get_field(s->fields, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i32(tmp, get_field(s->fields, v2), idx, es);
+ tcg_gen_add_i32(sum, sum, tmp);
+ }
+ write_vec_element_i32(sum, get_field(s->fields, v1), dst_idx, ES_32);
+ }
+ tcg_temp_free_i32(sum);
+ tcg_temp_free_i32(tmp);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 40/41] s390x/tcg: Implement VECTOR SUM ACROSS WORD
@ 2019-04-16 18:53 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:53 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Similar to VECTOR SUM ACROSS DOUBLEWORD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 2483ee01d7..a52db41388 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1186,6 +1186,8 @@
F(0xe765, VSUMG, VRR_c, V, 0, 0, 0, 0, vsumg, 0, IF_VEC)
/* VECTOR SUM ACROSS QUADWORD */
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
+/* VECTOR SUM ACROSS WORD */
+ F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 82ab42d2d9..1273bb5ded 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2366,3 +2366,32 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
tcg_temp_free_i64(tmpl);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
+{
+ const uint8_t es = get_field(s->fields, m4);
+ TCGv_i32 sum, tmp;
+ uint8_t dst_idx;
+
+ if (es > ES_16) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ sum = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
+ for (dst_idx = 0; dst_idx < 4; dst_idx++) {
+ uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4;
+ const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1;
+
+ read_vec_element_i32(sum, get_field(s->fields, v3), max_idx, es);
+ for (; idx <= max_idx; idx++) {
+ read_vec_element_i32(tmp, get_field(s->fields, v2), idx, es);
+ tcg_gen_add_i32(sum, sum, tmp);
+ }
+ write_vec_element_i32(sum, get_field(s->fields, v1), dst_idx, ES_32);
+ }
+ tcg_temp_free_i32(sum);
+ tcg_temp_free_i32(tmp);
+ return DISAS_NEXT;
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 41/41] s390x/tcg: Implement VECTOR TEST UNDER MASK
@ 2019-04-16 18:53 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:53 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Thomas Huth, Cornelia Huck, Richard Henderson,
David Hildenbrand, Richard Henderson
Let's return the cc value directly via cpu_env. Unfortunately there
isn't a simple way to calculate the value lazily - one would have to
calculate and store e.g. the population count of the mask and the
result so it can be evaluated in a cc helper.
But as VTM only sets the cc, we can assume the value will be needed soon
either way.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 11 +++++++++++
target/s390x/vec_int_helper.c | 18 ++++++++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 431e0a8084..eb511b8aaf 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -229,6 +229,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a52db41388..e61475bdc4 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1188,6 +1188,8 @@
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
/* VECTOR SUM ACROSS WORD */
F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
+/* VECTOR TEST UNDER MASK */
+ F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 1273bb5ded..fe52e08a3f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
c, 16, 16, data, fn)
+#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ ptr, 16, 16, data, fn)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -2395,3 +2398,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ cpu_env, 0, gen_helper_gvec_vtm);
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 5b007adc26..866ecaee4a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -696,3 +696,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VSCBI(8)
DEF_VSCBI(16)
+
+void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ S390Vector tmp;
+
+ s390_vec_and(&tmp, v1, v2);
+ if (s390_vec_is_zero(&tmp)) {
+ /* Selected bits all zeros; or all mask bits zero */
+ env->cc_op = 0;
+ } else if (s390_vec_equal(&tmp, v2)) {
+ /* Selected bits all ones */
+ env->cc_op = 3;
+ } else {
+ /* Selected bits a mix of zeros and ones */
+ env->cc_op = 1;
+ }
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* [Qemu-devel] [PATCH v2 41/41] s390x/tcg: Implement VECTOR TEST UNDER MASK
@ 2019-04-16 18:53 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-16 18:53 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, David Hildenbrand, Cornelia Huck, Richard Henderson,
qemu-s390x, Richard Henderson
Let's return the cc value directly via cpu_env. Unfortunately there
isn't a simple way to calculate the value lazily - one would have to
calculate and store e.g. the population count of the mask and the
result so it can be evaluated in a cc helper.
But as VTM only sets the cc, we can assume the value will be needed soon
either way.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 11 +++++++++++
target/s390x/vec_int_helper.c | 18 ++++++++++++++++++
4 files changed, 32 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 431e0a8084..eb511b8aaf 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -229,6 +229,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a52db41388..e61475bdc4 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1188,6 +1188,8 @@
F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
/* VECTOR SUM ACROSS WORD */
F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
+/* VECTOR TEST UNDER MASK */
+ F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 1273bb5ded..fe52e08a3f 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
c, 16, 16, data, fn)
+#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+ ptr, 16, 16, data, fn)
#define gen_gvec_3(v1, v2, v3, gen) \
tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
vec_full_reg_offset(v3), 16, 16, gen)
@@ -2395,3 +2398,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
tcg_temp_free_i32(tmp);
return DISAS_NEXT;
}
+
+static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
+{
+ gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ cpu_env, 0, gen_helper_gvec_vtm);
+ set_cc_static(s);
+ return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 5b007adc26..866ecaee4a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -696,3 +696,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \
}
DEF_VSCBI(8)
DEF_VSCBI(16)
+
+void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ S390Vector tmp;
+
+ s390_vec_and(&tmp, v1, v2);
+ if (s390_vec_is_zero(&tmp)) {
+ /* Selected bits all zeros; or all mask bits zero */
+ env->cc_op = 0;
+ } else if (s390_vec_equal(&tmp, v2)) {
+ /* Selected bits all ones */
+ env->cc_op = 3;
+ } else {
+ /* Selected bits a mix of zeros and ones */
+ env->cc_op = 1;
+ }
+}
--
2.20.1
^ permalink raw reply related [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:30 ` Richard Henderson
2019-04-17 7:42 ` David Hildenbrand
-1 siblings, 1 reply; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:30 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
> without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
> for now.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
> tcg/tcg-op-gvec.h | 24 ++++++++
> 2 files changed, 163 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 03/41] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:34 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:34 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> 128-bit handling courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/insn-data.def | 2 +
> target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++
> 2 files changed, 96 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:37 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:37 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only.
> Courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 13/41] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:41 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:41 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Implement it similar to VECTOR COUNT LEADING ZEROS.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 28 ++++++++++++++++++++++++++++
> target/s390x/vec_int_helper.c | 14 ++++++++++++++
> 4 files changed, 46 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:47 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:47 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Use the new vector expansion for GVecGen3i.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 51 +++++++++++++++++++++++++++++++++
> target/s390x/vec_int_helper.c | 20 +++++++++++++
> 4 files changed, 75 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 31/41] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:53 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:53 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Inline expansion courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 29 +++++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 35/41] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:55 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:55 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Let's keep it simple for now and handle 8/16 bit elements via helpers.
> Especially for 8/16, we could come up with some bit tricks.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/helper.h | 2 ++
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 52 +++++++++++++++++++++++++++++++++
> target/s390x/vec_int_helper.c | 16 ++++++++++
> 4 files changed, 72 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 37/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION
2019-04-16 18:52 ` David Hildenbrand
(?)
@ 2019-04-17 4:55 ` Richard Henderson
-1 siblings, 0 replies; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 4:55 UTC (permalink / raw)
To: David Hildenbrand, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 4/16/19 8:52 AM, David Hildenbrand wrote:
> Mostly courtesy of Richard H.
>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate_vx.inc.c | 34 +++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
2019-04-17 4:30 ` Richard Henderson
@ 2019-04-17 7:42 ` David Hildenbrand
2019-04-17 9:14 ` Richard Henderson
0 siblings, 1 reply; 99+ messages in thread
From: David Hildenbrand @ 2019-04-17 7:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth, Richard Henderson
On 17.04.19 06:30, Richard Henderson wrote:
> On 4/16/19 8:52 AM, David Hildenbrand wrote:
>> Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
>> without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
>> for now.
>>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
>> tcg/tcg-op-gvec.h | 24 ++++++++
>> 2 files changed, 163 insertions(+)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
>
Thanks, can this go via Conny's tree or do you want to include this one
in your next TCG pull request?
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-17 7:54 ` Cornelia Huck
0 siblings, 0 replies; 99+ messages in thread
From: Cornelia Huck @ 2019-04-17 7:54 UTC (permalink / raw)
To: David Hildenbrand; +Cc: qemu-devel, qemu-s390x, Thomas Huth, Richard Henderson
On Tue, 16 Apr 2019 20:52:20 +0200
David Hildenbrand <david@redhat.com> wrote:
> This is the second part of vector instruction support for s390x. It is
> based on the series soon to land upstream:
> [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
>
> Part 1: Vector Support Instructions
> Part 2: Vector Integer Instructions
> Part 3: Vector String Instructions
> Part 4: Vector Floating-Point Instructions
>
> The current state can be found at (kept updated):
> https://github.com/davidhildenbrand/qemu/tree/vx
>
> With the current state I can boot Linux kernel + user space compiled with
> SIMD support. This allows to boot distributions compiled exclusively for
> z13, requiring SIMD support. Also, it is now possible to build a complete
> kernel using rpmbuild as quite some issues have been sorted out.
>
> In this part, all Vector Integer Instructions introduced with the
> "Vector Facility" are added. Some instructions part of the Vector Extension
> Facilities are also added.
>
> v1 -> v2:
> - Many suggestions and fixes as outlined by Richard H.
> -- Mostly avoid oom helpers for 128-bit add/sub variants
> -- New vector helpers are not considered for now
FWIW, I'd prefer a pull request for that over picking 41 patches :)
(I'm unlikely to be able to provide more insightful review anyway ;)
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-17 7:54 ` Cornelia Huck
0 siblings, 0 replies; 99+ messages in thread
From: Cornelia Huck @ 2019-04-17 7:54 UTC (permalink / raw)
To: David Hildenbrand; +Cc: Thomas Huth, qemu-s390x, qemu-devel, Richard Henderson
On Tue, 16 Apr 2019 20:52:20 +0200
David Hildenbrand <david@redhat.com> wrote:
> This is the second part of vector instruction support for s390x. It is
> based on the series soon to land upstream:
> [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
>
> Part 1: Vector Support Instructions
> Part 2: Vector Integer Instructions
> Part 3: Vector String Instructions
> Part 4: Vector Floating-Point Instructions
>
> The current state can be found at (kept updated):
> https://github.com/davidhildenbrand/qemu/tree/vx
>
> With the current state I can boot Linux kernel + user space compiled with
> SIMD support. This allows to boot distributions compiled exclusively for
> z13, requiring SIMD support. Also, it is now possible to build a complete
> kernel using rpmbuild as quite some issues have been sorted out.
>
> In this part, all Vector Integer Instructions introduced with the
> "Vector Facility" are added. Some instructions part of the Vector Extension
> Facilities are also added.
>
> v1 -> v2:
> - Many suggestions and fixes as outlined by Richard H.
> -- Mostly avoid oom helpers for 128-bit add/sub variants
> -- New vector helpers are not considered for now
FWIW, I'd prefer a pull request for that over picking 41 patches :)
(I'm unlikely to be able to provide more insightful review anyway ;)
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
2019-04-17 7:42 ` David Hildenbrand
@ 2019-04-17 9:14 ` Richard Henderson
2019-04-17 11:05 ` David Hildenbrand
0 siblings, 1 reply; 99+ messages in thread
From: Richard Henderson @ 2019-04-17 9:14 UTC (permalink / raw)
To: David Hildenbrand, Richard Henderson, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth
On 4/16/19 9:42 PM, David Hildenbrand wrote:
> On 17.04.19 06:30, Richard Henderson wrote:
>> On 4/16/19 8:52 AM, David Hildenbrand wrote:
>>> Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
>>> without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
>>> for now.
>>>
>>> Signed-off-by: David Hildenbrand <david@redhat.com>
>>> ---
>>> tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
>>> tcg/tcg-op-gvec.h | 24 ++++++++
>>> 2 files changed, 163 insertions(+)
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>
>>
>> r~
>>
>
> Thanks, can this go via Conny's tree or do you want to include this one
> in your next TCG pull request?
>
Hmm. Lemme take it through my tree, so that I can handle the
conflict that's certain to arise with the .opc adjustment.
There's only one patch in this set that depends on this, I think?
Connie may be able to take the other 39 in the meantime.
r~
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i()
2019-04-17 9:14 ` Richard Henderson
@ 2019-04-17 11:05 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-17 11:05 UTC (permalink / raw)
To: Richard Henderson, Richard Henderson, qemu-devel
Cc: qemu-s390x, Cornelia Huck, Thomas Huth
On 17.04.19 11:14, Richard Henderson wrote:
> On 4/16/19 9:42 PM, David Hildenbrand wrote:
>> On 17.04.19 06:30, Richard Henderson wrote:
>>> On 4/16/19 8:52 AM, David Hildenbrand wrote:
>>>> Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
>>>> without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
>>>> for now.
>>>>
>>>> Signed-off-by: David Hildenbrand <david@redhat.com>
>>>> ---
>>>> tcg/tcg-op-gvec.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
>>>> tcg/tcg-op-gvec.h | 24 ++++++++
>>>> 2 files changed, 163 insertions(+)
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>
>>>
>>> r~
>>>
>>
>> Thanks, can this go via Conny's tree or do you want to include this one
>> in your next TCG pull request?
>>
>
> Hmm. Lemme take it through my tree, so that I can handle the
> conflict that's certain to arise with the .opc adjustment.
>
> There's only one patch in this set that depends on this, I think?
Yes,
[PATCH v2 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT
UNDER MASK
> Connie may be able to take the other 39 in the meantime.
>
I'll have to wait for extract2 either way, so I can also wait until this
patch reaches upstream.
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-17 11:06 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-17 11:06 UTC (permalink / raw)
To: Cornelia Huck; +Cc: qemu-devel, qemu-s390x, Thomas Huth, Richard Henderson
On 17.04.19 09:54, Cornelia Huck wrote:
> On Tue, 16 Apr 2019 20:52:20 +0200
> David Hildenbrand <david@redhat.com> wrote:
>
>> This is the second part of vector instruction support for s390x. It is
>> based on the series soon to land upstream:
>> [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
>>
>> Part 1: Vector Support Instructions
>> Part 2: Vector Integer Instructions
>> Part 3: Vector String Instructions
>> Part 4: Vector Floating-Point Instructions
>>
>> The current state can be found at (kept updated):
>> https://github.com/davidhildenbrand/qemu/tree/vx
>>
>> With the current state I can boot Linux kernel + user space compiled with
>> SIMD support. This allows to boot distributions compiled exclusively for
>> z13, requiring SIMD support. Also, it is now possible to build a complete
>> kernel using rpmbuild as quite some issues have been sorted out.
>>
>> In this part, all Vector Integer Instructions introduced with the
>> "Vector Facility" are added. Some instructions part of the Vector Extension
>> Facilities are also added.
>>
>> v1 -> v2:
>> - Many suggestions and fixes as outlined by Richard H.
>> -- Mostly avoid oom helpers for 128-bit add/sub variants
>> -- New vector helpers are not considered for now
>
> FWIW, I'd prefer a pull request for that over picking 41 patches :)
> (I'm unlikely to be able to provide more insightful review anyway ;)
Will do once the required patches are upstream and you rebased your
branch. Thanks!
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 99+ messages in thread
* Re: [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2
@ 2019-04-17 11:06 ` David Hildenbrand
0 siblings, 0 replies; 99+ messages in thread
From: David Hildenbrand @ 2019-04-17 11:06 UTC (permalink / raw)
To: Cornelia Huck; +Cc: Thomas Huth, qemu-s390x, qemu-devel, Richard Henderson
On 17.04.19 09:54, Cornelia Huck wrote:
> On Tue, 16 Apr 2019 20:52:20 +0200
> David Hildenbrand <david@redhat.com> wrote:
>
>> This is the second part of vector instruction support for s390x. It is
>> based on the series soon to land upstream:
>> [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64}
>>
>> Part 1: Vector Support Instructions
>> Part 2: Vector Integer Instructions
>> Part 3: Vector String Instructions
>> Part 4: Vector Floating-Point Instructions
>>
>> The current state can be found at (kept updated):
>> https://github.com/davidhildenbrand/qemu/tree/vx
>>
>> With the current state I can boot Linux kernel + user space compiled with
>> SIMD support. This allows to boot distributions compiled exclusively for
>> z13, requiring SIMD support. Also, it is now possible to build a complete
>> kernel using rpmbuild as quite some issues have been sorted out.
>>
>> In this part, all Vector Integer Instructions introduced with the
>> "Vector Facility" are added. Some instructions part of the Vector Extension
>> Facilities are also added.
>>
>> v1 -> v2:
>> - Many suggestions and fixes as outlined by Richard H.
>> -- Mostly avoid oom helpers for 128-bit add/sub variants
>> -- New vector helpers are not considered for now
>
> FWIW, I'd prefer a pull request for that over picking 41 patches :)
> (I'm unlikely to be able to provide more insightful review anyway ;)
Will do once the required patches are upstream and you rebased your
branch. Thanks!
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 99+ messages in thread
end of thread, other threads:[~2019-04-17 11:07 UTC | newest]
Thread overview: 99+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-16 18:52 [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2 David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 01/41] tcg: Implement tcg_gen_gvec_3i() David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:30 ` Richard Henderson
2019-04-17 7:42 ` David Hildenbrand
2019-04-17 9:14 ` Richard Henderson
2019-04-17 11:05 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 02/41] s390x/tcg: Implement VECTOR ADD David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 03/41] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:34 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 04/41] s390x/tcg: Implement VECTOR ADD WITH CARRY David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 05/41] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:37 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 06/41] s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT) David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 07/41] s390x/tcg: Implement VECTOR AVERAGE David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 08/41] s390x/tcg: Implement VECTOR AVERAGE LOGICAL David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 09/41] s390x/tcg: Implement VECTOR CHECKSUM David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 10/41] s390x/tcg: Implement VECTOR ELEMENT COMPARE * David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 11/41] s390x/tcg: Implement VECTOR " David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 12/41] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 13/41] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:41 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 14/41] s390x/tcg: Implement VECTOR EXCLUSIVE OR David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 15/41] s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE) David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 16/41] s390x/tcg: Implement VECTOR LOAD COMPLEMENT David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 17/41] s390x/tcg: Implement VECTOR LOAD POSITIVE David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 18/41] s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL) David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 19/41] s390x/tcg: Implement VECTOR MULTIPLY AND ADD * David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 20/41] s390x/tcg: Implement VECTOR MULTIPLY * David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 21/41] s390x/tcg: Implement VECTOR NAND David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 22/41] s390x/tcg: Implement VECTOR NOR David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 23/41] s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 24/41] s390x/tcg: Implement VECTOR OR David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 25/41] s390x/tcg: Implement VECTOR OR WITH COMPLEMENT David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 26/41] s390x/tcg: Implement VECTOR POPULATION COUNT David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 27/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 28/41] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:47 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 29/41] s390x/tcg: Implement VECTOR ELEMENT SHIFT David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 30/41] s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 31/41] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:53 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 32/41] s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 33/41] s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 34/41] s390x/tcg: Implement VECTOR SUBTRACT David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 35/41] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:55 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 36/41] s390x/tcg: Implement VECTOR SUBTRACT WITH " David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 37/41] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE " David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-17 4:55 ` Richard Henderson
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 38/41] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:52 ` [Qemu-devel] [PATCH v2 39/41] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD David Hildenbrand
2019-04-16 18:52 ` David Hildenbrand
2019-04-16 18:53 ` [Qemu-devel] [PATCH v2 40/41] s390x/tcg: Implement VECTOR SUM ACROSS WORD David Hildenbrand
2019-04-16 18:53 ` David Hildenbrand
2019-04-16 18:53 ` [Qemu-devel] [PATCH v2 41/41] s390x/tcg: Implement VECTOR TEST UNDER MASK David Hildenbrand
2019-04-16 18:53 ` David Hildenbrand
2019-04-17 7:54 ` [Qemu-devel] [PATCH v2 00/41] s390x/tcg: Vector Instruction Support Part 2 Cornelia Huck
2019-04-17 7:54 ` Cornelia Huck
2019-04-17 11:06 ` David Hildenbrand
2019-04-17 11:06 ` David Hildenbrand
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