* [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node @ 2019-04-17 7:48 Peng Ma 2019-04-17 7:48 ` [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code Peng Ma 2019-05-22 12:32 ` [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Prabhakar Kushwaha 0 siblings, 2 replies; 6+ messages in thread From: Peng Ma @ 2019-04-17 7:48 UTC (permalink / raw) To: u-boot Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> --- changed for v2: - Add reg-names to improve driver code. arch/arm/dts/fsl-ls1012a.dtsi | 4 +++- arch/arm/dts/fsl-ls1043a.dtsi | 4 +++- arch/arm/dts/fsl-ls1046a.dtsi | 4 +++- arch/arm/dts/fsl-ls1088a.dtsi | 3 +++ arch/arm/dts/ls1021a.dtsi | 4 +++- 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index f22cbf4..30af2e1 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -136,7 +136,9 @@ sata: sata at 3200000 { compatible = "fsl,ls1012a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index bb70992..c7fa9e2 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -290,7 +290,9 @@ sata: sata at 3200000 { compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 0>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 5ac10e0..d56ecd6 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -294,7 +294,9 @@ sata: sata at 3200000 { compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 69 4>; clocks = <&clockgen 4 1>; status = "disabled"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 9455e03..7ba0683 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -154,6 +154,9 @@ sata: sata at 3200000 { compatible = "fsl,ls1088a-ahci"; reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 133 4>; status = "disabled"; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7670a39..cc5d56c 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -406,7 +406,9 @@ sata: sata at 3200000 { compatible = "fsl,ls1021a-ahci"; - reg = <0x3200000 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x0 0x20220520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 101 4>; status = "disabled"; }; -- 1.7.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code 2019-04-17 7:48 [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Peng Ma @ 2019-04-17 7:48 ` Peng Ma 2019-04-17 8:50 ` Michal Simek 2019-05-22 12:32 ` Prabhakar Kushwaha 2019-05-22 12:32 ` [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Prabhakar Kushwaha 1 sibling, 2 replies; 6+ messages in thread From: Peng Ma @ 2019-04-17 7:48 UTC (permalink / raw) To: u-boot Distinguish the ecc val by chassis version and move the ecc addr to dts. Add ls1028a soc support. Signed-off-by: Peng Ma <peng.ma@nxp.com> --- changed for v2: - Use the reg-names to get secondary reg base - Return error while some socs not set the ecc address at DT drivers/ata/sata_ceva.c | 50 +++++++++++++++++++++++++++++++---------------- 1 files changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 8887be9..2d49630 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -8,6 +8,7 @@ #include <ahci.h> #include <scsi.h> #include <asm/io.h> +#include <linux/ioport.h> /* Vendor Specific Register Offsets */ #define AHCI_VEND_PCFG 0xA4 @@ -88,20 +89,16 @@ #define LS1021_CEVA_PHY4_CFG 0x064a080b #define LS1021_CEVA_PHY5_CFG 0x2aa86470 -/* for ls1088a */ -#define LS1088_ECC_DIS_ADDR_CH2 0x100520 -#define LS1088_ECC_DIS_VAL_CH2 0x40000000 - -/* ecc addr-val pair */ -#define ECC_DIS_ADDR_CH2 0x20140520 +/* ecc val pair */ +#define ECC_DIS_VAL_CH1 0x00020000 #define ECC_DIS_VAL_CH2 0x80000000 -#define SATA_ECC_REG_ADDR 0x20220520 -#define SATA_ECC_DISABLE 0x00020000 +#define ECC_DIS_VAL_CH3 0x40000000 enum ceva_soc { CEVA_1V84, CEVA_LS1012A, CEVA_LS1021A, + CEVA_LS1028A, CEVA_LS1043A, CEVA_LS1046A, CEVA_LS1088A, @@ -110,12 +107,14 @@ enum ceva_soc { struct ceva_sata_priv { ulong base; + ulong ecc_base; enum ceva_soc soc; ulong flag; }; static int ceva_init_sata(struct ceva_sata_priv *priv) { + ulong ecc_addr = priv->ecc_base; ulong base = priv->base; ulong tmp; @@ -132,38 +131,42 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) break; case CEVA_LS1021A: - writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR); + if (!ecc_addr) + return -EINVAL; + writel(ECC_DIS_VAL_CH1, ecc_addr); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C); writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C); writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C); writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC); break; case CEVA_LS1012A: case CEVA_LS1043A: case CEVA_LS1046A: - writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); + if (!ecc_addr) + return -EINVAL; + writel(ECC_DIS_VAL_CH2, ecc_addr); /* fallthrough */ case CEVA_LS2080A: writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); break; + case CEVA_LS1028A: case CEVA_LS1088A: - writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2); + if (!ecc_addr) + return -EINVAL; + writel(ECC_DIS_VAL_CH3, ecc_addr); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); - if (priv->flag & FLAG_COHERENT) - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); break; } + if (priv->flag & FLAG_COHERENT) + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); + return 0; } @@ -187,6 +190,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, + { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, @@ -197,6 +201,8 @@ static const struct udevice_id sata_ceva_ids[] = { static int sata_ceva_ofdata_to_platdata(struct udevice *dev) { struct ceva_sata_priv *priv = dev_get_priv(dev); + struct resource res_regs; + int ret; if (dev_read_bool(dev, "dma-coherent")) priv->flag |= FLAG_COHERENT; @@ -205,8 +211,18 @@ static int sata_ceva_ofdata_to_platdata(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; + ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs); + if (ret) + priv->ecc_base = 0; + else + priv->ecc_base = res_regs.start; + priv->soc = dev_get_driver_data(dev); + debug("ccsr-sata-base %lx\t ecc-base %lx\n", + priv->base, + priv->ecc_base); + return 0; } -- 1.7.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code 2019-04-17 7:48 ` [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code Peng Ma @ 2019-04-17 8:50 ` Michal Simek 2019-05-22 12:32 ` Prabhakar Kushwaha 1 sibling, 0 replies; 6+ messages in thread From: Michal Simek @ 2019-04-17 8:50 UTC (permalink / raw) To: u-boot On 17. 04. 19 9:48, Peng Ma wrote: > Distinguish the ecc val by chassis version and move the ecc addr to dts. > Add ls1028a soc support. > > Signed-off-by: Peng Ma <peng.ma@nxp.com> > --- > changed for v2: > - Use the reg-names to get secondary reg base > - Return error while some socs not set the ecc address at DT > > drivers/ata/sata_ceva.c | 50 +++++++++++++++++++++++++++++++---------------- > 1 files changed, 33 insertions(+), 17 deletions(-) > > diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c > index 8887be9..2d49630 100644 > --- a/drivers/ata/sata_ceva.c > +++ b/drivers/ata/sata_ceva.c > @@ -8,6 +8,7 @@ > #include <ahci.h> > #include <scsi.h> > #include <asm/io.h> > +#include <linux/ioport.h> > > /* Vendor Specific Register Offsets */ > #define AHCI_VEND_PCFG 0xA4 > @@ -88,20 +89,16 @@ > #define LS1021_CEVA_PHY4_CFG 0x064a080b > #define LS1021_CEVA_PHY5_CFG 0x2aa86470 > > -/* for ls1088a */ > -#define LS1088_ECC_DIS_ADDR_CH2 0x100520 > -#define LS1088_ECC_DIS_VAL_CH2 0x40000000 > - > -/* ecc addr-val pair */ > -#define ECC_DIS_ADDR_CH2 0x20140520 > +/* ecc val pair */ > +#define ECC_DIS_VAL_CH1 0x00020000 > #define ECC_DIS_VAL_CH2 0x80000000 > -#define SATA_ECC_REG_ADDR 0x20220520 > -#define SATA_ECC_DISABLE 0x00020000 > +#define ECC_DIS_VAL_CH3 0x40000000 > > enum ceva_soc { > CEVA_1V84, > CEVA_LS1012A, > CEVA_LS1021A, > + CEVA_LS1028A, > CEVA_LS1043A, > CEVA_LS1046A, > CEVA_LS1088A, > @@ -110,12 +107,14 @@ enum ceva_soc { > > struct ceva_sata_priv { > ulong base; > + ulong ecc_base; > enum ceva_soc soc; > ulong flag; > }; > > static int ceva_init_sata(struct ceva_sata_priv *priv) > { > + ulong ecc_addr = priv->ecc_base; > ulong base = priv->base; > ulong tmp; > > @@ -132,38 +131,42 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) > break; > > case CEVA_LS1021A: > - writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR); > + if (!ecc_addr) > + return -EINVAL; > + writel(ECC_DIS_VAL_CH1, ecc_addr); > writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); > writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C); > writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C); > writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C); > writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C); > writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); > - if (priv->flag & FLAG_COHERENT) > - writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC); > break; > > case CEVA_LS1012A: > case CEVA_LS1043A: > case CEVA_LS1046A: > - writel(ECC_DIS_VAL_CH2, ECC_DIS_ADDR_CH2); > + if (!ecc_addr) > + return -EINVAL; > + writel(ECC_DIS_VAL_CH2, ecc_addr); > /* fallthrough */ > case CEVA_LS2080A: > writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); > writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); > - if (priv->flag & FLAG_COHERENT) > - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); > break; > > + case CEVA_LS1028A: > case CEVA_LS1088A: > - writel(LS1088_ECC_DIS_VAL_CH2, LS1088_ECC_DIS_ADDR_CH2); > + if (!ecc_addr) > + return -EINVAL; > + writel(ECC_DIS_VAL_CH3, ecc_addr); > writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); > writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); > - if (priv->flag & FLAG_COHERENT) > - writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); > break; > } > > + if (priv->flag & FLAG_COHERENT) > + writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC); > + > return 0; > } > > @@ -187,6 +190,7 @@ static const struct udevice_id sata_ceva_ids[] = { > { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 }, > { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, > { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, > + { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A }, > { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, > { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, > { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A }, > @@ -197,6 +201,8 @@ static const struct udevice_id sata_ceva_ids[] = { > static int sata_ceva_ofdata_to_platdata(struct udevice *dev) > { > struct ceva_sata_priv *priv = dev_get_priv(dev); > + struct resource res_regs; > + int ret; > > if (dev_read_bool(dev, "dma-coherent")) > priv->flag |= FLAG_COHERENT; > @@ -205,8 +211,18 @@ static int sata_ceva_ofdata_to_platdata(struct udevice *dev) > if (priv->base == FDT_ADDR_T_NONE) > return -EINVAL; > > + ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs); > + if (ret) > + priv->ecc_base = 0; > + else > + priv->ecc_base = res_regs.start; > + > priv->soc = dev_get_driver_data(dev); > > + debug("ccsr-sata-base %lx\t ecc-base %lx\n", > + priv->base, > + priv->ecc_base); > + > return 0; > } > > Reviewed-by: Michal Simek <michal.simek@xilinx.com> Thanks, Michal ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code 2019-04-17 7:48 ` [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code Peng Ma 2019-04-17 8:50 ` Michal Simek @ 2019-05-22 12:32 ` Prabhakar Kushwaha 1 sibling, 0 replies; 6+ messages in thread From: Prabhakar Kushwaha @ 2019-05-22 12:32 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Peng Ma <peng.ma@nxp.com> > Sent: Wednesday, April 17, 2019 1:19 PM > To: albert.u.boot at aribaud.net; sjg at chromium.org; Fabio Estevam > <fabio.estevam@nxp.com>; York Sun <york.sun@nxp.com>; Prabhakar > Kushwaha <prabhakar.kushwaha@nxp.com> > Cc: Andy Tang <andy.tang@nxp.com>; Yinbo Zhu <yinbo.zhu@nxp.com>; > michal.simek at xilinx.com; u-boot at lists.denx.de; Peng Ma > <peng.ma@nxp.com> > Subject: [v2 2/2] scsi: ceva: Clean up the driver code > > Distinguish the ecc val by chassis version and move the ecc addr to dts. > Add ls1028a soc support. > > Signed-off-by: Peng Ma <peng.ma@nxp.com> > --- > changed for v2: > - Use the reg-names to get secondary reg base > - Return error while some socs not set the ecc address at DT > > drivers/ata/sata_ceva.c | 50 +++++++++++++++++++++++++++++++-------------- > -- This patch has been applied to fsl-qoriq master, awaiting upstream. --pk ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node 2019-04-17 7:48 [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Peng Ma 2019-04-17 7:48 ` [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code Peng Ma @ 2019-05-22 12:32 ` Prabhakar Kushwaha 2019-05-23 4:10 ` Peng Ma 1 sibling, 1 reply; 6+ messages in thread From: Prabhakar Kushwaha @ 2019-05-22 12:32 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Peng Ma <peng.ma@nxp.com> > Sent: Wednesday, April 17, 2019 1:19 PM > To: albert.u.boot at aribaud.net; sjg at chromium.org; Fabio Estevam > <fabio.estevam@nxp.com>; York Sun <york.sun@nxp.com>; Prabhakar > Kushwaha <prabhakar.kushwaha@nxp.com> > Cc: Andy Tang <andy.tang@nxp.com>; Yinbo Zhu <yinbo.zhu@nxp.com>; > michal.simek at xilinx.com; u-boot at lists.denx.de; Peng Ma > <peng.ma@nxp.com> > Subject: [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node > > Move the ecc addr from driver to dts. > > Signed-off-by: Peng Ma <peng.ma@nxp.com> > --- > changed for v2: > - Add reg-names to improve driver code. > fix chechpatch warning i.e. updated subject and applied to fsl-qoriq master, awaiting upstream Can you send patches for ls2088a and ls1028a also --pk ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node 2019-05-22 12:32 ` [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Prabhakar Kushwaha @ 2019-05-23 4:10 ` Peng Ma 0 siblings, 0 replies; 6+ messages in thread From: Peng Ma @ 2019-05-23 4:10 UTC (permalink / raw) To: u-boot Hi prabhakar, >-----Original Message----- >From: Prabhakar Kushwaha >Sent: 2019年5月22日 20:33 >To: Peng Ma <peng.ma@nxp.com>; albert.u.boot at aribaud.net; >sjg at chromium.org; Fabio Estevam <fabio.estevam@nxp.com>; York Sun ><york.sun@nxp.com> >Cc: Andy Tang <andy.tang@nxp.com>; Yinbo Zhu <yinbo.zhu@nxp.com>; >michal.simek at xilinx.com; u-boot at lists.denx.de; Peng Ma ><peng.ma@nxp.com> >Subject: RE: [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node > > >> -----Original Message----- >> From: Peng Ma <peng.ma@nxp.com> >> Sent: Wednesday, April 17, 2019 1:19 PM >> To: albert.u.boot at aribaud.net; sjg at chromium.org; Fabio Estevam >> <fabio.estevam@nxp.com>; York Sun <york.sun@nxp.com>; Prabhakar >> Kushwaha <prabhakar.kushwaha@nxp.com> >> Cc: Andy Tang <andy.tang@nxp.com>; Yinbo Zhu <yinbo.zhu@nxp.com>; >> michal.simek at xilinx.com; u-boot at lists.denx.de; Peng Ma >> <peng.ma@nxp.com> >> Subject: [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node >> >> Move the ecc addr from driver to dts. >> >> Signed-off-by: Peng Ma <peng.ma@nxp.com> >> --- >> changed for v2: >> - Add reg-names to improve driver code. >> > >fix chechpatch warning i.e. updated subject and applied to fsl-qoriq master, >awaiting upstream > >Can you send patches for ls2088a and ls1028a also [Peng Ma] ls2088a is not need to ecc address, I will add ls1028 patch to upstream. Best Regards, Peng > >--pk ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-05-23 4:10 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-17 7:48 [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Peng Ma 2019-04-17 7:48 ` [U-Boot] [v2 2/2] scsi: ceva: Clean up the driver code Peng Ma 2019-04-17 8:50 ` Michal Simek 2019-05-22 12:32 ` Prabhakar Kushwaha 2019-05-22 12:32 ` [U-Boot] [v2 1/2] ARM: dts: Freescale: Add ecc addr for sata node Prabhakar Kushwaha 2019-05-23 4:10 ` Peng Ma
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