[PATCH 0/7] mmc: meson-gx: clean up and tuning update

[PATCH 0/7] mmc: meson-gx: clean up and tuning update

[Jerome Brunet]

The purpose of this series is too improve reliability of the amlogic mmc
driver on new (g12a) and old ones (axg, gxl, gxbb, etc...)

* The 3 first patches are just harmless clean ups.
* Patch 4 makes sure HS400 can't be enabled, we still have not been able
  to crack this modes.
* Patch 5 removes some clock glitches when switching to DDR modes
* Patch 6 and 7 changes the tuning method from Rx phase to signal
  resampling. It could have been done in a single patch but the unified
  diff was extremely ugly. The change has been split in two patches to
  ease review.

The last tuning update that went through was meant to improve the axg
support. Since then, it was reported to break some other boards, like the
s912 vim2.

Also with the current tuning method, it was impossible to find phase
settings which would work on all the SoC, including the new ones.

After redoing all the tests from scratch, it appeared that Rx phase made
(strangely) almost no difference, especially on g12a and axg.
It is important to have a phase shift between the Core and Tx clock, 180
works best.

I discussed the test results with Amlogic. They suggested to use 180/0 or
0/180 for the Core and Tx phase. For tuning, they suggested to use
signal resampling.

So far, so good ... here the platform and modes tested:

NanoPi-K2 (S905): SD UHS SDR50/DDR50, SDIO HS
Odroid-C2 (S905): SD UHS SDR50/DDR50, eMMC DDR52/HS200
Khadas Vim (S905X): SD HS, SDIO HS, eMMC HS200
Libretech CC (S905X): SD HS, eMMC HS200
Khadas Vim2 (S912): SD HS, SDIO HS, eMMC HS200
S400 (A113D): SDIO UHS SDR104, eMMC DDR52/HS200
U200 (S905D2): SD HS, eMMC DDR52/HS200
SEI510 (S905X2): SD HS, eMMC DDR52/HS200

Jerome Brunet (7):
  mmc: meson-gx: remove open coded read with timeout
  mmc: meson-gx: ack only raised irq
  mmc: meson-gx: irq is not shared
  mmc: meson-gx: disable HS400
  mmc: meson-gx: avoid clock glitch when switching to DDR modes
  mmc: meson-gx: remove Rx phase tuning
  mmc: meson-gx: add signal resampling tuning

 drivers/mmc/host/meson-gx-mmc.c | 418 +++++++++-----------------------
 1 file changed, 113 insertions(+), 305 deletions(-)

-- 
2.20.1

[PATCH 0/7] mmc: meson-gx: clean up and tuning update

[Jerome Brunet]

The purpose of this series is too improve reliability of the amlogic mmc
driver on new (g12a) and old ones (axg, gxl, gxbb, etc...)

* The 3 first patches are just harmless clean ups.
* Patch 4 makes sure HS400 can't be enabled, we still have not been able
  to crack this modes.
* Patch 5 removes some clock glitches when switching to DDR modes
* Patch 6 and 7 changes the tuning method from Rx phase to signal
  resampling. It could have been done in a single patch but the unified
  diff was extremely ugly. The change has been split in two patches to
  ease review.

The last tuning update that went through was meant to improve the axg
support. Since then, it was reported to break some other boards, like the
s912 vim2.

Also with the current tuning method, it was impossible to find phase
settings which would work on all the SoC, including the new ones.

After redoing all the tests from scratch, it appeared that Rx phase made
(strangely) almost no difference, especially on g12a and axg.
It is important to have a phase shift between the Core and Tx clock, 180
works best.

I discussed the test results with Amlogic. They suggested to use 180/0 or
0/180 for the Core and Tx phase. For tuning, they suggested to use
signal resampling.

So far, so good ... here the platform and modes tested:

NanoPi-K2 (S905): SD UHS SDR50/DDR50, SDIO HS
Odroid-C2 (S905): SD UHS SDR50/DDR50, eMMC DDR52/HS200
Khadas Vim (S905X): SD HS, SDIO HS, eMMC HS200
Libretech CC (S905X): SD HS, eMMC HS200
Khadas Vim2 (S912): SD HS, SDIO HS, eMMC HS200
S400 (A113D): SDIO UHS SDR104, eMMC DDR52/HS200
U200 (S905D2): SD HS, eMMC DDR52/HS200
SEI510 (S905X2): SD HS, eMMC DDR52/HS200

Jerome Brunet (7):
  mmc: meson-gx: remove open coded read with timeout
  mmc: meson-gx: ack only raised irq
  mmc: meson-gx: irq is not shared
  mmc: meson-gx: disable HS400
  mmc: meson-gx: avoid clock glitch when switching to DDR modes
  mmc: meson-gx: remove Rx phase tuning
  mmc: meson-gx: add signal resampling tuning

 drivers/mmc/host/meson-gx-mmc.c | 418 +++++++++-----------------------
 1 file changed, 113 insertions(+), 305 deletions(-)

-- 
2.20.1


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[PATCH 1/7] mmc: meson-gx: remove open coded read with timeout

[Jerome Brunet]

There is already a function available to poll a register until a
condition is met. Let's use it instead of open coding it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 2eba507790e4..2deeacc051b1 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/iopoll.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/ioport.h>
@@ -1100,7 +1101,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 
 static int meson_mmc_wait_desc_stop(struct meson_host *host)
 {
-	int loop;
 	u32 status;
 
 	/*
@@ -1110,20 +1110,10 @@ static int meson_mmc_wait_desc_stop(struct meson_host *host)
 	 * If we don't confirm the descriptor is stopped, it might raise new
 	 * IRQs after we have called mmc_request_done() which is bad.
 	 */
-	for (loop = 50; loop; loop--) {
-		status = readl(host->regs + SD_EMMC_STATUS);
-		if (status & (STATUS_BUSY | STATUS_DESC_BUSY))
-			udelay(100);
-		else
-			break;
-	}
 
-	if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) {
-		dev_err(host->dev, "Timed out waiting for host to stop\n");
-		return -ETIMEDOUT;
-	}
-
-	return 0;
+	return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
+				  !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
+				  100, 5000);
 }
 
 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
-- 
2.20.1

[PATCH 1/7] mmc: meson-gx: remove open coded read with timeout

[Jerome Brunet]

There is already a function available to poll a register until a
condition is met. Let's use it instead of open coding it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 2eba507790e4..2deeacc051b1 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/iopoll.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/ioport.h>
@@ -1100,7 +1101,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 
 static int meson_mmc_wait_desc_stop(struct meson_host *host)
 {
-	int loop;
 	u32 status;
 
 	/*
@@ -1110,20 +1110,10 @@ static int meson_mmc_wait_desc_stop(struct meson_host *host)
 	 * If we don't confirm the descriptor is stopped, it might raise new
 	 * IRQs after we have called mmc_request_done() which is bad.
 	 */
-	for (loop = 50; loop; loop--) {
-		status = readl(host->regs + SD_EMMC_STATUS);
-		if (status & (STATUS_BUSY | STATUS_DESC_BUSY))
-			udelay(100);
-		else
-			break;
-	}
 
-	if (status & (STATUS_BUSY | STATUS_DESC_BUSY)) {
-		dev_err(host->dev, "Timed out waiting for host to stop\n");
-		return -ETIMEDOUT;
-	}
-
-	return 0;
+	return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
+				  !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
+				  100, 5000);
 }
 
 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
-- 
2.20.1


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[PATCH 2/7] mmc: meson-gx: ack only raised irq

[Jerome Brunet]

This is merely a clean up. It makes sense to only ack raised irqs
instead of acking everything all the time.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 2deeacc051b1..8b690ecde4c5 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -1082,9 +1082,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 	}
 
 out:
-	/* ack all enabled interrupts */
-	writel(irq_en, host->regs + SD_EMMC_STATUS);
-
 	if (cmd->error) {
 		/* Stop desc in case of errors */
 		u32 start = readl(host->regs + SD_EMMC_START);
@@ -1096,6 +1093,9 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 	if (ret == IRQ_HANDLED)
 		meson_mmc_request_done(host->mmc, cmd->mrq);
 
+	/* ack all raised interrupts */
+	writel(status, host->regs + SD_EMMC_STATUS);
+
 	return ret;
 }
 
-- 
2.20.1

[PATCH 2/7] mmc: meson-gx: ack only raised irq

[Jerome Brunet]

This is merely a clean up. It makes sense to only ack raised irqs
instead of acking everything all the time.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 2deeacc051b1..8b690ecde4c5 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -1082,9 +1082,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 	}
 
 out:
-	/* ack all enabled interrupts */
-	writel(irq_en, host->regs + SD_EMMC_STATUS);
-
 	if (cmd->error) {
 		/* Stop desc in case of errors */
 		u32 start = readl(host->regs + SD_EMMC_START);
@@ -1096,6 +1093,9 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
 	if (ret == IRQ_HANDLED)
 		meson_mmc_request_done(host->mmc, cmd->mrq);
 
+	/* ack all raised interrupts */
+	writel(status, host->regs + SD_EMMC_STATUS);
+
 	return ret;
 }
 
-- 
2.20.1


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[PATCH 3/7] mmc: meson-gx: irq is not shared

[Jerome Brunet]

There is no reason for another device to request the MMC irq. It should
only be used the MMC device.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 8b690ecde4c5..3df50b53f834 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
 	       host->regs + SD_EMMC_IRQ_EN);
 
 	ret = request_threaded_irq(host->irq, meson_mmc_irq,
-				   meson_mmc_irq_thread, IRQF_SHARED,
+				   meson_mmc_irq_thread, IRQF_ONESHOT,
 				   dev_name(&pdev->dev), host);
 	if (ret)
 		goto err_init_clk;
-- 
2.20.1

[PATCH 3/7] mmc: meson-gx: irq is not shared

[Jerome Brunet]

There is no reason for another device to request the MMC irq. It should
only be used the MMC device.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 8b690ecde4c5..3df50b53f834 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
 	       host->regs + SD_EMMC_IRQ_EN);
 
 	ret = request_threaded_irq(host->irq, meson_mmc_irq,
-				   meson_mmc_irq_thread, IRQF_SHARED,
+				   meson_mmc_irq_thread, IRQF_ONESHOT,
 				   dev_name(&pdev->dev), host);
 	if (ret)
 		goto err_init_clk;
-- 
2.20.1


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[PATCH 4/7] mmc: meson-gx: disable HS400

[Jerome Brunet]

At the moment, all our attempts to enable HS400 on Amlogic chipsets have
been unsuccessful or unreliable. Until we can figure out how to enable this
mode safely and reliably, let's force it off.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 3df50b53f834..118f09da8dfb 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -823,10 +823,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	if (meson_mmc_timing_is_ddr(ios))
 		val |= CFG_DDR;
 
-	val &= ~CFG_CHK_DS;
-	if (ios->timing == MMC_TIMING_MMC_HS400)
-		val |= CFG_CHK_DS;
-
 	err = meson_mmc_clk_set(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
@@ -1339,6 +1335,13 @@ static int meson_mmc_probe(struct platform_device *pdev)
 	mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
 	mmc->max_seg_size = mmc->max_req_size;
 
+	/*
+	 * At the moment, we don't know how to reliably enable HS400.
+	 * From the different datasheets, it is not even clear if this mode
+	 * is officially supported by any of the SoCs
+	 */
+	mmc->caps2 &= ~MMC_CAP2_HS400;
+
 	/* data bounce buffer */
 	host->bounce_buf_size = mmc->max_req_size;
 	host->bounce_buf =
-- 
2.20.1

[PATCH 4/7] mmc: meson-gx: disable HS400

[Jerome Brunet]

At the moment, all our attempts to enable HS400 on Amlogic chipsets have
been unsuccessful or unreliable. Until we can figure out how to enable this
mode safely and reliably, let's force it off.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 3df50b53f834..118f09da8dfb 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -823,10 +823,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	if (meson_mmc_timing_is_ddr(ios))
 		val |= CFG_DDR;
 
-	val &= ~CFG_CHK_DS;
-	if (ios->timing == MMC_TIMING_MMC_HS400)
-		val |= CFG_CHK_DS;
-
 	err = meson_mmc_clk_set(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
@@ -1339,6 +1335,13 @@ static int meson_mmc_probe(struct platform_device *pdev)
 	mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
 	mmc->max_seg_size = mmc->max_req_size;
 
+	/*
+	 * At the moment, we don't know how to reliably enable HS400.
+	 * From the different datasheets, it is not even clear if this mode
+	 * is officially supported by any of the SoCs
+	 */
+	mmc->caps2 &= ~MMC_CAP2_HS400;
+
 	/* data bounce buffer */
 	host->bounce_buf_size = mmc->max_req_size;
 	host->bounce_buf =
-- 
2.20.1


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[PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

Activating DDR in the Amlogic mmc controller, among other things, will
divide the output clock by 2. So by activating it with clock on, we are
creating a glitch on the output.

Instead, let's deal with DDR when the clock output is off, when setting
the clock.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 72 +++++++++++++++++++--------------
 1 file changed, 42 insertions(+), 30 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 118f09da8dfb..f77b9327a590 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -169,6 +169,7 @@ struct meson_host {
 	struct clk *rx_clk;
 	struct clk *tx_clk;
 	unsigned long req_rate;
+	bool ddr;
 
 	struct pinctrl *pinctrl;
 	struct pinctrl_state *pins_default;
@@ -384,16 +385,6 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 			     mmc_get_dma_dir(data));
 }
 
-static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
-{
-	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
-	    ios->timing == MMC_TIMING_UHS_DDR50 ||
-	    ios->timing == MMC_TIMING_MMC_HS400)
-		return true;
-
-	return false;
-}
-
 /*
  * Gating the clock on this controller is tricky.  It seems the mmc clock
  * is also used by the controller.  It may crash during some operation if the
@@ -430,36 +421,41 @@ static void meson_mmc_clk_ungate(struct meson_host *host)
 	writel(cfg, host->regs + SD_EMMC_CFG);
 }
 
-static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
+static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
+			     bool ddr)
 {
 	struct mmc_host *mmc = host->mmc;
-	unsigned long rate = ios->clock;
 	int ret;
 	u32 cfg;
 
-	/* DDR modes require higher module clock */
-	if (meson_mmc_timing_is_ddr(ios))
-		rate <<= 1;
-
 	/* Same request - bail-out */
-	if (host->req_rate == rate)
+	if (host->ddr == ddr && host->req_rate == rate)
 		return 0;
 
 	/* stop clock */
 	meson_mmc_clk_gate(host);
 	host->req_rate = 0;
+	mmc->actual_clock = 0;
 
-	if (!rate) {
-		mmc->actual_clock = 0;
-		/* return with clock being stopped */
+	/* return with clock being stopped */
+	if (!rate)
 		return 0;
-	}
 
 	/* Stop the clock during rate change to avoid glitches */
 	cfg = readl(host->regs + SD_EMMC_CFG);
 	cfg |= CFG_STOP_CLOCK;
 	writel(cfg, host->regs + SD_EMMC_CFG);
 
+	if (ddr) {
+		/* DDR modes require higher module clock */
+		rate <<= 1;
+		cfg |= CFG_DDR;
+	} else {
+		cfg &= ~CFG_DDR;
+	}
+	writel(cfg, host->regs + SD_EMMC_CFG);
+	host->ddr = ddr;
+
 	ret = clk_set_rate(host->mmc_clk, rate);
 	if (ret) {
 		dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
@@ -471,12 +467,14 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
 	mmc->actual_clock = clk_get_rate(host->mmc_clk);
 
 	/* We should report the real output frequency of the controller */
-	if (meson_mmc_timing_is_ddr(ios))
+	if (ddr) {
+		host->req_rate >>= 1;
 		mmc->actual_clock >>= 1;
+	}
 
 	dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
-	if (ios->clock != mmc->actual_clock)
-		dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
+	if (rate != mmc->actual_clock)
+		dev_dbg(host->dev, "requested rate was %lu\n", rate);
 
 	/* (re)start clock */
 	meson_mmc_clk_ungate(host);
@@ -750,6 +748,25 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
 }
 
+static int meson_mmc_prepare_ios_clock(struct meson_host *host,
+				       struct mmc_ios *ios)
+{
+	bool ddr;
+
+	switch (ios->timing) {
+	case MMC_TIMING_MMC_DDR52:
+	case MMC_TIMING_UHS_DDR50:
+		ddr = true;
+		break;
+
+	default:
+		ddr = false;
+		break;
+	}
+
+	return meson_mmc_clk_set(host, ios->clock, ddr);
+}
+
 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct meson_host *host = mmc_priv(mmc);
@@ -819,15 +836,10 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	val &= ~CFG_BUS_WIDTH_MASK;
 	val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
 
-	val &= ~CFG_DDR;
-	if (meson_mmc_timing_is_ddr(ios))
-		val |= CFG_DDR;
-
-	err = meson_mmc_clk_set(host, ios);
+	err = meson_mmc_prepare_ios_clock(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
 
-	writel(val, host->regs + SD_EMMC_CFG);
 	dev_dbg(host->dev, "SD_EMMC_CFG:  0x%08x\n", val);
 }
 
-- 
2.20.1

[PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

Activating DDR in the Amlogic mmc controller, among other things, will
divide the output clock by 2. So by activating it with clock on, we are
creating a glitch on the output.

Instead, let's deal with DDR when the clock output is off, when setting
the clock.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 72 +++++++++++++++++++--------------
 1 file changed, 42 insertions(+), 30 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 118f09da8dfb..f77b9327a590 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -169,6 +169,7 @@ struct meson_host {
 	struct clk *rx_clk;
 	struct clk *tx_clk;
 	unsigned long req_rate;
+	bool ddr;
 
 	struct pinctrl *pinctrl;
 	struct pinctrl_state *pins_default;
@@ -384,16 +385,6 @@ static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 			     mmc_get_dma_dir(data));
 }
 
-static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
-{
-	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
-	    ios->timing == MMC_TIMING_UHS_DDR50 ||
-	    ios->timing == MMC_TIMING_MMC_HS400)
-		return true;
-
-	return false;
-}
-
 /*
  * Gating the clock on this controller is tricky.  It seems the mmc clock
  * is also used by the controller.  It may crash during some operation if the
@@ -430,36 +421,41 @@ static void meson_mmc_clk_ungate(struct meson_host *host)
 	writel(cfg, host->regs + SD_EMMC_CFG);
 }
 
-static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
+static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
+			     bool ddr)
 {
 	struct mmc_host *mmc = host->mmc;
-	unsigned long rate = ios->clock;
 	int ret;
 	u32 cfg;
 
-	/* DDR modes require higher module clock */
-	if (meson_mmc_timing_is_ddr(ios))
-		rate <<= 1;
-
 	/* Same request - bail-out */
-	if (host->req_rate == rate)
+	if (host->ddr == ddr && host->req_rate == rate)
 		return 0;
 
 	/* stop clock */
 	meson_mmc_clk_gate(host);
 	host->req_rate = 0;
+	mmc->actual_clock = 0;
 
-	if (!rate) {
-		mmc->actual_clock = 0;
-		/* return with clock being stopped */
+	/* return with clock being stopped */
+	if (!rate)
 		return 0;
-	}
 
 	/* Stop the clock during rate change to avoid glitches */
 	cfg = readl(host->regs + SD_EMMC_CFG);
 	cfg |= CFG_STOP_CLOCK;
 	writel(cfg, host->regs + SD_EMMC_CFG);
 
+	if (ddr) {
+		/* DDR modes require higher module clock */
+		rate <<= 1;
+		cfg |= CFG_DDR;
+	} else {
+		cfg &= ~CFG_DDR;
+	}
+	writel(cfg, host->regs + SD_EMMC_CFG);
+	host->ddr = ddr;
+
 	ret = clk_set_rate(host->mmc_clk, rate);
 	if (ret) {
 		dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
@@ -471,12 +467,14 @@ static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
 	mmc->actual_clock = clk_get_rate(host->mmc_clk);
 
 	/* We should report the real output frequency of the controller */
-	if (meson_mmc_timing_is_ddr(ios))
+	if (ddr) {
+		host->req_rate >>= 1;
 		mmc->actual_clock >>= 1;
+	}
 
 	dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
-	if (ios->clock != mmc->actual_clock)
-		dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
+	if (rate != mmc->actual_clock)
+		dev_dbg(host->dev, "requested rate was %lu\n", rate);
 
 	/* (re)start clock */
 	meson_mmc_clk_ungate(host);
@@ -750,6 +748,25 @@ static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
 }
 
+static int meson_mmc_prepare_ios_clock(struct meson_host *host,
+				       struct mmc_ios *ios)
+{
+	bool ddr;
+
+	switch (ios->timing) {
+	case MMC_TIMING_MMC_DDR52:
+	case MMC_TIMING_UHS_DDR50:
+		ddr = true;
+		break;
+
+	default:
+		ddr = false;
+		break;
+	}
+
+	return meson_mmc_clk_set(host, ios->clock, ddr);
+}
+
 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct meson_host *host = mmc_priv(mmc);
@@ -819,15 +836,10 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	val &= ~CFG_BUS_WIDTH_MASK;
 	val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
 
-	val &= ~CFG_DDR;
-	if (meson_mmc_timing_is_ddr(ios))
-		val |= CFG_DDR;
-
-	err = meson_mmc_clk_set(host, ios);
+	err = meson_mmc_prepare_ios_clock(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
 
-	writel(val, host->regs + SD_EMMC_CFG);
 	dev_dbg(host->dev, "SD_EMMC_CFG:  0x%08x\n", val);
 }
 
-- 
2.20.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH 6/7] mmc: meson-gx: remove Rx phase tuning

[Jerome Brunet]

This remove all the code related to phase settings. Using the Rx phase
for tuning has not been reliable. We had several issues over the past
months, on both v2 and v3 mmc chips After discussing the issue matter
with Amlogic, They suggested to set a phase shift of 180 between Core and
Tx and use signal resampling for the tuning.

Since we won't be playing with the phase anymore, let's remove all the
clock code related to it and set the appropriate value on init.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 290 ++------------------------------
 1 file changed, 13 insertions(+), 277 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index f77b9327a590..50b03c167435 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -49,6 +49,8 @@
 #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
 #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
+#define   CLK_PHASE_0 0
+#define   CLK_PHASE_180 2
 #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
 #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
 #define   CLK_V2_ALWAYS_ON BIT(24)
@@ -57,10 +59,6 @@
 #define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
 #define   CLK_V3_ALWAYS_ON BIT(28)
 
-#define   CLK_DELAY_STEP_PS 200
-#define   CLK_PHASE_STEP 30
-#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
-
 #define   CLK_TX_DELAY_MASK(h)		(h->data->tx_delay_mask)
 #define   CLK_RX_DELAY_MASK(h)		(h->data->rx_delay_mask)
 #define   CLK_ALWAYS_ON(h)		(h->data->always_on)
@@ -165,9 +163,8 @@ struct meson_host {
 
 	void __iomem *regs;
 	struct clk *core_clk;
+	struct clk *mux_clk;
 	struct clk *mmc_clk;
-	struct clk *rx_clk;
-	struct clk *tx_clk;
 	unsigned long req_rate;
 	bool ddr;
 
@@ -209,90 +206,6 @@ struct meson_host {
 #define CMD_RESP_MASK GENMASK(31, 1)
 #define CMD_RESP_SRAM BIT(0)
 
-struct meson_mmc_phase {
-	struct clk_hw hw;
-	void __iomem *reg;
-	unsigned long phase_mask;
-	unsigned long delay_mask;
-	unsigned int delay_step_ps;
-};
-
-#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
-
-static int meson_mmc_clk_get_phase(struct clk_hw *hw)
-{
-	struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
-	unsigned int phase_num = 1 <<  hweight_long(mmc->phase_mask);
-	unsigned long period_ps, p, d;
-		int degrees;
-	u32 val;
-
-	val = readl(mmc->reg);
-	p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
-	degrees = p * 360 / phase_num;
-
-	if (mmc->delay_mask) {
-		period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
-					 clk_get_rate(hw->clk));
-		d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
-		degrees += d * mmc->delay_step_ps * 360 / period_ps;
-		degrees %= 360;
-	}
-
-	return degrees;
-}
-
-static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
-					unsigned int phase,
-					unsigned int delay)
-{
-	u32 val;
-
-	val = readl(mmc->reg);
-	val &= ~mmc->phase_mask;
-	val |= phase << __ffs(mmc->phase_mask);
-
-	if (mmc->delay_mask) {
-		val &= ~mmc->delay_mask;
-		val |= delay << __ffs(mmc->delay_mask);
-	}
-
-	writel(val, mmc->reg);
-}
-
-static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
-{
-	struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
-	unsigned int phase_num = 1 <<  hweight_long(mmc->phase_mask);
-	unsigned long period_ps, d = 0, r;
-	uint64_t p;
-
-	p = degrees % 360;
-
-	if (!mmc->delay_mask) {
-		p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
-	} else {
-		period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
-					 clk_get_rate(hw->clk));
-
-		/* First compute the phase index (p), the remainder (r) is the
-		 * part we'll try to acheive using the delays (d).
-		 */
-		r = do_div(p, 360 / phase_num);
-		d = DIV_ROUND_CLOSEST(r * period_ps,
-				      360 * mmc->delay_step_ps);
-		d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
-	}
-
-	meson_mmc_apply_phase_delay(mmc, p, d);
-	return 0;
-}
-
-static const struct clk_ops meson_mmc_clk_phase_ops = {
-	.get_phase = meson_mmc_clk_get_phase,
-	.set_phase = meson_mmc_clk_set_phase,
-};
-
 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
 {
 	unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
@@ -492,8 +405,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	struct clk_init_data init;
 	struct clk_mux *mux;
 	struct clk_divider *div;
-	struct meson_mmc_phase *core, *tx, *rx;
-	struct clk *clk;
 	char clk_name[32];
 	int i, ret = 0;
 	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
@@ -501,9 +412,11 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	u32 clk_reg;
 
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
-	clk_reg = 0;
-	clk_reg |= CLK_ALWAYS_ON(host);
+	clk_reg = CLK_ALWAYS_ON(host);
 	clk_reg |= CLK_DIV_MASK;
+	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
+	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
 	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
 
 	/* get the mux parents */
@@ -539,9 +452,9 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	mux->mask = CLK_SRC_MASK >> mux->shift;
 	mux->hw.init = &init;
 
-	clk = devm_clk_register(host->dev, &mux->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return PTR_ERR(clk);
+	host->mux_clk = devm_clk_register(host->dev, &mux->hw);
+	if (WARN_ON(IS_ERR(host->mux_clk)))
+		return PTR_ERR(host->mux_clk);
 
 	/* create the divider */
 	div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
@@ -552,7 +465,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	init.name = clk_name;
 	init.ops = &clk_divider_ops;
 	init.flags = CLK_SET_RATE_PARENT;
-	clk_parent[0] = __clk_get_name(clk);
+	clk_parent[0] = __clk_get_name(host->mux_clk);
 	init.parent_names = clk_parent;
 	init.num_parents = 1;
 
@@ -562,192 +475,19 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	div->hw.init = &init;
 	div->flags = CLK_DIVIDER_ONE_BASED;
 
-	clk = devm_clk_register(host->dev, &div->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return PTR_ERR(clk);
-
-	/* create the mmc core clock */
-	core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
-	if (!core)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = CLK_SET_RATE_PARENT;
-	clk_parent[0] = __clk_get_name(clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	core->reg = host->regs + SD_EMMC_CLOCK;
-	core->phase_mask = CLK_CORE_PHASE_MASK;
-	core->hw.init = &init;
-
-	host->mmc_clk = devm_clk_register(host->dev, &core->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
+	host->mmc_clk = devm_clk_register(host->dev, &div->hw);
+	if (WARN_ON(IS_ERR(host->mmc_clk)))
 		return PTR_ERR(host->mmc_clk);
 
-	/* create the mmc tx clock */
-	tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
-	if (!tx)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = 0;
-	clk_parent[0] = __clk_get_name(host->mmc_clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	tx->reg = host->regs + SD_EMMC_CLOCK;
-	tx->phase_mask = CLK_TX_PHASE_MASK;
-	tx->delay_mask = CLK_TX_DELAY_MASK(host);
-	tx->delay_step_ps = CLK_DELAY_STEP_PS;
-	tx->hw.init = &init;
-
-	host->tx_clk = devm_clk_register(host->dev, &tx->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
-		return PTR_ERR(host->tx_clk);
-
-	/* create the mmc rx clock */
-	rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
-	if (!rx)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = 0;
-	clk_parent[0] = __clk_get_name(host->mmc_clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	rx->reg = host->regs + SD_EMMC_CLOCK;
-	rx->phase_mask = CLK_RX_PHASE_MASK;
-	rx->delay_mask = CLK_RX_DELAY_MASK(host);
-	rx->delay_step_ps = CLK_DELAY_STEP_PS;
-	rx->hw.init = &init;
-
-	host->rx_clk = devm_clk_register(host->dev, &rx->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
-		return PTR_ERR(host->rx_clk);
-
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
 	host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
 	ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
 	if (ret)
 		return ret;
 
-	clk_set_phase(host->mmc_clk, 180);
-	clk_set_phase(host->tx_clk, 0);
-	clk_set_phase(host->rx_clk, 0);
-
 	return clk_prepare_enable(host->mmc_clk);
 }
 
-static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
-{
-	DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
-	DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
-
-	/*
-	 * shift the bitmap right and reintroduce the dropped bits on the left
-	 * of the bitmap
-	 */
-	bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
-	bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
-			  CLK_PHASE_POINT_NUM);
-	bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
-}
-
-static void meson_mmc_find_next_region(unsigned long *map,
-				       unsigned long *start,
-				       unsigned long *stop)
-{
-	*start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
-	*stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
-}
-
-static int meson_mmc_find_tuning_point(unsigned long *test)
-{
-	unsigned long shift, stop, offset = 0, start = 0, size = 0;
-
-	/* Get the all good/all bad situation out the way */
-	if (bitmap_full(test, CLK_PHASE_POINT_NUM))
-		return 0; /* All points are good so point 0 will do */
-	else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
-		return -EIO; /* No successful tuning point */
-
-	/*
-	 * Now we know there is a least one region find. Make sure it does
-	 * not wrap by the shifting the bitmap if necessary
-	 */
-	shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
-	if (shift != 0)
-		meson_mmc_shift_map(test, shift);
-
-	while (start < CLK_PHASE_POINT_NUM) {
-		meson_mmc_find_next_region(test, &start, &stop);
-
-		if ((stop - start) > size) {
-			offset = start;
-			size = stop - start;
-		}
-
-		start = stop;
-	}
-
-	/* Get the center point of the region */
-	offset += (size / 2);
-
-	/* Shift the result back */
-	offset = (offset + shift) % CLK_PHASE_POINT_NUM;
-
-	return offset;
-}
-
-static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
-				      struct clk *clk)
-{
-	int point, ret;
-	DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
-
-	dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
-		__clk_get_name(clk));
-	bitmap_zero(test, CLK_PHASE_POINT_NUM);
-
-	/* Explore tuning points */
-	for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
-		clk_set_phase(clk, point * CLK_PHASE_STEP);
-		ret = mmc_send_tuning(mmc, opcode, NULL);
-		if (!ret)
-			set_bit(point, test);
-	}
-
-	/* Find the optimal tuning point and apply it */
-	point = meson_mmc_find_tuning_point(test);
-	if (point < 0)
-		return point; /* tuning failed */
-
-	clk_set_phase(clk, point * CLK_PHASE_STEP);
-	dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
-		clk_get_phase(clk));
-	return 0;
-}
-
-static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
-{
-	struct meson_host *host = mmc_priv(mmc);
-	int adj = 0;
-
-	/* enable signal resampling w/o delay */
-	adj = ADJUST_ADJ_EN;
-	writel(adj, host->regs + host->data->adjust);
-
-	return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
-}
-
 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 				       struct mmc_ios *ios)
 {
@@ -796,9 +536,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		/* disable signal resampling */
 		writel(0, host->regs + host->data->adjust);
 
-		/* Reset rx phase */
-		clk_set_phase(host->rx_clk, 0);
-
 		break;
 
 	case MMC_POWER_ON:
@@ -1225,7 +962,6 @@ static const struct mmc_host_ops meson_mmc_ops = {
 	.get_cd         = meson_mmc_get_cd,
 	.pre_req	= meson_mmc_pre_req,
 	.post_req	= meson_mmc_post_req,
-	.execute_tuning = meson_mmc_execute_tuning,
 	.card_busy	= meson_mmc_card_busy,
 	.start_signal_voltage_switch = meson_mmc_voltage_switch,
 };
-- 
2.20.1

[PATCH 6/7] mmc: meson-gx: remove Rx phase tuning

[Jerome Brunet]

This remove all the code related to phase settings. Using the Rx phase
for tuning has not been reliable. We had several issues over the past
months, on both v2 and v3 mmc chips After discussing the issue matter
with Amlogic, They suggested to set a phase shift of 180 between Core and
Tx and use signal resampling for the tuning.

Since we won't be playing with the phase anymore, let's remove all the
clock code related to it and set the appropriate value on init.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 290 ++------------------------------
 1 file changed, 13 insertions(+), 277 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index f77b9327a590..50b03c167435 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -49,6 +49,8 @@
 #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
 #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
+#define   CLK_PHASE_0 0
+#define   CLK_PHASE_180 2
 #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
 #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
 #define   CLK_V2_ALWAYS_ON BIT(24)
@@ -57,10 +59,6 @@
 #define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
 #define   CLK_V3_ALWAYS_ON BIT(28)
 
-#define   CLK_DELAY_STEP_PS 200
-#define   CLK_PHASE_STEP 30
-#define   CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
-
 #define   CLK_TX_DELAY_MASK(h)		(h->data->tx_delay_mask)
 #define   CLK_RX_DELAY_MASK(h)		(h->data->rx_delay_mask)
 #define   CLK_ALWAYS_ON(h)		(h->data->always_on)
@@ -165,9 +163,8 @@ struct meson_host {
 
 	void __iomem *regs;
 	struct clk *core_clk;
+	struct clk *mux_clk;
 	struct clk *mmc_clk;
-	struct clk *rx_clk;
-	struct clk *tx_clk;
 	unsigned long req_rate;
 	bool ddr;
 
@@ -209,90 +206,6 @@ struct meson_host {
 #define CMD_RESP_MASK GENMASK(31, 1)
 #define CMD_RESP_SRAM BIT(0)
 
-struct meson_mmc_phase {
-	struct clk_hw hw;
-	void __iomem *reg;
-	unsigned long phase_mask;
-	unsigned long delay_mask;
-	unsigned int delay_step_ps;
-};
-
-#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
-
-static int meson_mmc_clk_get_phase(struct clk_hw *hw)
-{
-	struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
-	unsigned int phase_num = 1 <<  hweight_long(mmc->phase_mask);
-	unsigned long period_ps, p, d;
-		int degrees;
-	u32 val;
-
-	val = readl(mmc->reg);
-	p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
-	degrees = p * 360 / phase_num;
-
-	if (mmc->delay_mask) {
-		period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
-					 clk_get_rate(hw->clk));
-		d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
-		degrees += d * mmc->delay_step_ps * 360 / period_ps;
-		degrees %= 360;
-	}
-
-	return degrees;
-}
-
-static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
-					unsigned int phase,
-					unsigned int delay)
-{
-	u32 val;
-
-	val = readl(mmc->reg);
-	val &= ~mmc->phase_mask;
-	val |= phase << __ffs(mmc->phase_mask);
-
-	if (mmc->delay_mask) {
-		val &= ~mmc->delay_mask;
-		val |= delay << __ffs(mmc->delay_mask);
-	}
-
-	writel(val, mmc->reg);
-}
-
-static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
-{
-	struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
-	unsigned int phase_num = 1 <<  hweight_long(mmc->phase_mask);
-	unsigned long period_ps, d = 0, r;
-	uint64_t p;
-
-	p = degrees % 360;
-
-	if (!mmc->delay_mask) {
-		p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
-	} else {
-		period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
-					 clk_get_rate(hw->clk));
-
-		/* First compute the phase index (p), the remainder (r) is the
-		 * part we'll try to acheive using the delays (d).
-		 */
-		r = do_div(p, 360 / phase_num);
-		d = DIV_ROUND_CLOSEST(r * period_ps,
-				      360 * mmc->delay_step_ps);
-		d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
-	}
-
-	meson_mmc_apply_phase_delay(mmc, p, d);
-	return 0;
-}
-
-static const struct clk_ops meson_mmc_clk_phase_ops = {
-	.get_phase = meson_mmc_clk_get_phase,
-	.set_phase = meson_mmc_clk_set_phase,
-};
-
 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
 {
 	unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
@@ -492,8 +405,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	struct clk_init_data init;
 	struct clk_mux *mux;
 	struct clk_divider *div;
-	struct meson_mmc_phase *core, *tx, *rx;
-	struct clk *clk;
 	char clk_name[32];
 	int i, ret = 0;
 	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
@@ -501,9 +412,11 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	u32 clk_reg;
 
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
-	clk_reg = 0;
-	clk_reg |= CLK_ALWAYS_ON(host);
+	clk_reg = CLK_ALWAYS_ON(host);
 	clk_reg |= CLK_DIV_MASK;
+	clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
+	clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
+	clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
 	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
 
 	/* get the mux parents */
@@ -539,9 +452,9 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	mux->mask = CLK_SRC_MASK >> mux->shift;
 	mux->hw.init = &init;
 
-	clk = devm_clk_register(host->dev, &mux->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return PTR_ERR(clk);
+	host->mux_clk = devm_clk_register(host->dev, &mux->hw);
+	if (WARN_ON(IS_ERR(host->mux_clk)))
+		return PTR_ERR(host->mux_clk);
 
 	/* create the divider */
 	div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
@@ -552,7 +465,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	init.name = clk_name;
 	init.ops = &clk_divider_ops;
 	init.flags = CLK_SET_RATE_PARENT;
-	clk_parent[0] = __clk_get_name(clk);
+	clk_parent[0] = __clk_get_name(host->mux_clk);
 	init.parent_names = clk_parent;
 	init.num_parents = 1;
 
@@ -562,192 +475,19 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	div->hw.init = &init;
 	div->flags = CLK_DIVIDER_ONE_BASED;
 
-	clk = devm_clk_register(host->dev, &div->hw);
-	if (WARN_ON(IS_ERR(clk)))
-		return PTR_ERR(clk);
-
-	/* create the mmc core clock */
-	core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
-	if (!core)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = CLK_SET_RATE_PARENT;
-	clk_parent[0] = __clk_get_name(clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	core->reg = host->regs + SD_EMMC_CLOCK;
-	core->phase_mask = CLK_CORE_PHASE_MASK;
-	core->hw.init = &init;
-
-	host->mmc_clk = devm_clk_register(host->dev, &core->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
+	host->mmc_clk = devm_clk_register(host->dev, &div->hw);
+	if (WARN_ON(IS_ERR(host->mmc_clk)))
 		return PTR_ERR(host->mmc_clk);
 
-	/* create the mmc tx clock */
-	tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
-	if (!tx)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = 0;
-	clk_parent[0] = __clk_get_name(host->mmc_clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	tx->reg = host->regs + SD_EMMC_CLOCK;
-	tx->phase_mask = CLK_TX_PHASE_MASK;
-	tx->delay_mask = CLK_TX_DELAY_MASK(host);
-	tx->delay_step_ps = CLK_DELAY_STEP_PS;
-	tx->hw.init = &init;
-
-	host->tx_clk = devm_clk_register(host->dev, &tx->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
-		return PTR_ERR(host->tx_clk);
-
-	/* create the mmc rx clock */
-	rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
-	if (!rx)
-		return -ENOMEM;
-
-	snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
-	init.name = clk_name;
-	init.ops = &meson_mmc_clk_phase_ops;
-	init.flags = 0;
-	clk_parent[0] = __clk_get_name(host->mmc_clk);
-	init.parent_names = clk_parent;
-	init.num_parents = 1;
-
-	rx->reg = host->regs + SD_EMMC_CLOCK;
-	rx->phase_mask = CLK_RX_PHASE_MASK;
-	rx->delay_mask = CLK_RX_DELAY_MASK(host);
-	rx->delay_step_ps = CLK_DELAY_STEP_PS;
-	rx->hw.init = &init;
-
-	host->rx_clk = devm_clk_register(host->dev, &rx->hw);
-	if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
-		return PTR_ERR(host->rx_clk);
-
 	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
 	host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
 	ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
 	if (ret)
 		return ret;
 
-	clk_set_phase(host->mmc_clk, 180);
-	clk_set_phase(host->tx_clk, 0);
-	clk_set_phase(host->rx_clk, 0);
-
 	return clk_prepare_enable(host->mmc_clk);
 }
 
-static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
-{
-	DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
-	DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
-
-	/*
-	 * shift the bitmap right and reintroduce the dropped bits on the left
-	 * of the bitmap
-	 */
-	bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
-	bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
-			  CLK_PHASE_POINT_NUM);
-	bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
-}
-
-static void meson_mmc_find_next_region(unsigned long *map,
-				       unsigned long *start,
-				       unsigned long *stop)
-{
-	*start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
-	*stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
-}
-
-static int meson_mmc_find_tuning_point(unsigned long *test)
-{
-	unsigned long shift, stop, offset = 0, start = 0, size = 0;
-
-	/* Get the all good/all bad situation out the way */
-	if (bitmap_full(test, CLK_PHASE_POINT_NUM))
-		return 0; /* All points are good so point 0 will do */
-	else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
-		return -EIO; /* No successful tuning point */
-
-	/*
-	 * Now we know there is a least one region find. Make sure it does
-	 * not wrap by the shifting the bitmap if necessary
-	 */
-	shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
-	if (shift != 0)
-		meson_mmc_shift_map(test, shift);
-
-	while (start < CLK_PHASE_POINT_NUM) {
-		meson_mmc_find_next_region(test, &start, &stop);
-
-		if ((stop - start) > size) {
-			offset = start;
-			size = stop - start;
-		}
-
-		start = stop;
-	}
-
-	/* Get the center point of the region */
-	offset += (size / 2);
-
-	/* Shift the result back */
-	offset = (offset + shift) % CLK_PHASE_POINT_NUM;
-
-	return offset;
-}
-
-static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
-				      struct clk *clk)
-{
-	int point, ret;
-	DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
-
-	dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
-		__clk_get_name(clk));
-	bitmap_zero(test, CLK_PHASE_POINT_NUM);
-
-	/* Explore tuning points */
-	for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
-		clk_set_phase(clk, point * CLK_PHASE_STEP);
-		ret = mmc_send_tuning(mmc, opcode, NULL);
-		if (!ret)
-			set_bit(point, test);
-	}
-
-	/* Find the optimal tuning point and apply it */
-	point = meson_mmc_find_tuning_point(test);
-	if (point < 0)
-		return point; /* tuning failed */
-
-	clk_set_phase(clk, point * CLK_PHASE_STEP);
-	dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
-		clk_get_phase(clk));
-	return 0;
-}
-
-static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
-{
-	struct meson_host *host = mmc_priv(mmc);
-	int adj = 0;
-
-	/* enable signal resampling w/o delay */
-	adj = ADJUST_ADJ_EN;
-	writel(adj, host->regs + host->data->adjust);
-
-	return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
-}
-
 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 				       struct mmc_ios *ios)
 {
@@ -796,9 +536,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		/* disable signal resampling */
 		writel(0, host->regs + host->data->adjust);
 
-		/* Reset rx phase */
-		clk_set_phase(host->rx_clk, 0);
-
 		break;
 
 	case MMC_POWER_ON:
@@ -1225,7 +962,6 @@ static const struct mmc_host_ops meson_mmc_ops = {
 	.get_cd         = meson_mmc_get_cd,
 	.pre_req	= meson_mmc_pre_req,
 	.post_req	= meson_mmc_post_req,
-	.execute_tuning = meson_mmc_execute_tuning,
 	.card_busy	= meson_mmc_card_busy,
 	.start_signal_voltage_switch = meson_mmc_voltage_switch,
 };
-- 
2.20.1


_______________________________________________
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linux-amlogic@lists.infradead.org
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[PATCH 7/7] mmc: meson-gx: add signal resampling tuning

[Jerome Brunet]

Use signal resampling tuning for the UHS and HS200 modes.
Instead of trying to get the *best* resampling setting with complex
window calculation, we just stop on the first working setting.

If the tuning setting later proves unstable, we will just continue the
tuning where we left it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++++++++++++++--
 1 file changed, 70 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 50b03c167435..207c65b3ddf1 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -488,6 +488,61 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	return clk_prepare_enable(host->mmc_clk);
 }
 
+static void meson_mmc_disable_resampling(struct meson_host *host)
+{
+	unsigned int val = readl(host->regs + host->data->adjust);
+
+	val &= ~ADJUST_ADJ_EN;
+	writel(val, host->regs + host->data->adjust);
+}
+
+static void meson_mmc_reset_resampling(struct meson_host *host)
+{
+	unsigned int val;
+
+	meson_mmc_disable_resampling(host);
+
+	val = readl(host->regs + host->data->adjust);
+	val &= ~ADJUST_ADJ_DELAY_MASK;
+	writel(val, host->regs + host->data->adjust);
+}
+
+static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct meson_host *host = mmc_priv(mmc);
+	unsigned int val, dly, max_dly, i;
+	int ret;
+
+	/* Resampling is done using the source clock */
+	max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
+			       clk_get_rate(host->mmc_clk));
+
+	val = readl(host->regs + host->data->adjust);
+	val |= ADJUST_ADJ_EN;
+	writel(val, host->regs + host->data->adjust);
+
+	if (mmc->doing_retune)
+		dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
+	else
+		dly = 0;
+
+	for (i = 0; i < max_dly; i++) {
+		val &= ~ADJUST_ADJ_DELAY_MASK;
+		val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
+		writel(val, host->regs + host->data->adjust);
+
+		ret = mmc_send_tuning(mmc, opcode, NULL);
+		if (!ret) {
+			dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
+				(dly + i) % max_dly);
+			return 0;
+		}
+	}
+
+	meson_mmc_reset_resampling(host);
+	return -EIO;
+}
+
 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 				       struct mmc_ios *ios)
 {
@@ -507,6 +562,19 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 	return meson_mmc_clk_set(host, ios->clock, ddr);
 }
 
+static void meson_mmc_check_resampling(struct meson_host *host,
+				       struct mmc_ios *ios)
+{
+	switch (ios->timing) {
+	case MMC_TIMING_LEGACY:
+	case MMC_TIMING_MMC_HS:
+	case MMC_TIMING_SD_HS:
+	case MMC_TIMING_MMC_DDR52:
+		meson_mmc_disable_resampling(host);
+		break;
+	}
+}
+
 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct meson_host *host = mmc_priv(mmc);
@@ -533,9 +601,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		if (!IS_ERR(mmc->supply.vmmc))
 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
 
-		/* disable signal resampling */
-		writel(0, host->regs + host->data->adjust);
-
 		break;
 
 	case MMC_POWER_ON:
@@ -573,6 +638,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	val &= ~CFG_BUS_WIDTH_MASK;
 	val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
 
+	meson_mmc_check_resampling(host, ios);
 	err = meson_mmc_prepare_ios_clock(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
@@ -962,6 +1028,7 @@ static const struct mmc_host_ops meson_mmc_ops = {
 	.get_cd         = meson_mmc_get_cd,
 	.pre_req	= meson_mmc_pre_req,
 	.post_req	= meson_mmc_post_req,
+	.execute_tuning = meson_mmc_resampling_tuning,
 	.card_busy	= meson_mmc_card_busy,
 	.start_signal_voltage_switch = meson_mmc_voltage_switch,
 };
-- 
2.20.1

[PATCH 7/7] mmc: meson-gx: add signal resampling tuning

[Jerome Brunet]

Use signal resampling tuning for the UHS and HS200 modes.
Instead of trying to get the *best* resampling setting with complex
window calculation, we just stop on the first working setting.

If the tuning setting later proves unstable, we will just continue the
tuning where we left it.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++++++++++++++--
 1 file changed, 70 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 50b03c167435..207c65b3ddf1 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -488,6 +488,61 @@ static int meson_mmc_clk_init(struct meson_host *host)
 	return clk_prepare_enable(host->mmc_clk);
 }
 
+static void meson_mmc_disable_resampling(struct meson_host *host)
+{
+	unsigned int val = readl(host->regs + host->data->adjust);
+
+	val &= ~ADJUST_ADJ_EN;
+	writel(val, host->regs + host->data->adjust);
+}
+
+static void meson_mmc_reset_resampling(struct meson_host *host)
+{
+	unsigned int val;
+
+	meson_mmc_disable_resampling(host);
+
+	val = readl(host->regs + host->data->adjust);
+	val &= ~ADJUST_ADJ_DELAY_MASK;
+	writel(val, host->regs + host->data->adjust);
+}
+
+static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
+{
+	struct meson_host *host = mmc_priv(mmc);
+	unsigned int val, dly, max_dly, i;
+	int ret;
+
+	/* Resampling is done using the source clock */
+	max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
+			       clk_get_rate(host->mmc_clk));
+
+	val = readl(host->regs + host->data->adjust);
+	val |= ADJUST_ADJ_EN;
+	writel(val, host->regs + host->data->adjust);
+
+	if (mmc->doing_retune)
+		dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
+	else
+		dly = 0;
+
+	for (i = 0; i < max_dly; i++) {
+		val &= ~ADJUST_ADJ_DELAY_MASK;
+		val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
+		writel(val, host->regs + host->data->adjust);
+
+		ret = mmc_send_tuning(mmc, opcode, NULL);
+		if (!ret) {
+			dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
+				(dly + i) % max_dly);
+			return 0;
+		}
+	}
+
+	meson_mmc_reset_resampling(host);
+	return -EIO;
+}
+
 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 				       struct mmc_ios *ios)
 {
@@ -507,6 +562,19 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host,
 	return meson_mmc_clk_set(host, ios->clock, ddr);
 }
 
+static void meson_mmc_check_resampling(struct meson_host *host,
+				       struct mmc_ios *ios)
+{
+	switch (ios->timing) {
+	case MMC_TIMING_LEGACY:
+	case MMC_TIMING_MMC_HS:
+	case MMC_TIMING_SD_HS:
+	case MMC_TIMING_MMC_DDR52:
+		meson_mmc_disable_resampling(host);
+		break;
+	}
+}
+
 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 {
 	struct meson_host *host = mmc_priv(mmc);
@@ -533,9 +601,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		if (!IS_ERR(mmc->supply.vmmc))
 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
 
-		/* disable signal resampling */
-		writel(0, host->regs + host->data->adjust);
-
 		break;
 
 	case MMC_POWER_ON:
@@ -573,6 +638,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	val &= ~CFG_BUS_WIDTH_MASK;
 	val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
 
+	meson_mmc_check_resampling(host, ios);
 	err = meson_mmc_prepare_ios_clock(host, ios);
 	if (err)
 		dev_err(host->dev, "Failed to set clock: %d\n,", err);
@@ -962,6 +1028,7 @@ static const struct mmc_host_ops meson_mmc_ops = {
 	.get_cd         = meson_mmc_get_cd,
 	.pre_req	= meson_mmc_pre_req,
 	.post_req	= meson_mmc_post_req,
+	.execute_tuning = meson_mmc_resampling_tuning,
 	.card_busy	= meson_mmc_card_busy,
 	.start_signal_voltage_switch = meson_mmc_voltage_switch,
 };
-- 
2.20.1


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Re: [PATCH 3/7] mmc: meson-gx: irq is not shared

[Martin Blumenstingl]

Hi Jerome,

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> There is no reason for another device to request the MMC irq. It should
> only be used the MMC device.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/mmc/host/meson-gx-mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 8b690ecde4c5..3df50b53f834 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
>                host->regs + SD_EMMC_IRQ_EN);
>
>         ret = request_threaded_irq(host->irq, meson_mmc_irq,
> -                                  meson_mmc_irq_thread, IRQF_SHARED,
> +                                  meson_mmc_irq_thread, IRQF_ONESHOT,
>                                    dev_name(&pdev->dev), host);
the commit message reads as if the intention is to remove the IRQF_SHARED flag.
however, the commit message doesn't mention IRQF_ONESHOT (which was
not set before).

if you used IRQF_ONESHOT on purpose then please mention it in the
patch description.


Martin

Re: [PATCH 3/7] mmc: meson-gx: irq is not shared

[Martin Blumenstingl]

Hi Jerome,

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> There is no reason for another device to request the MMC irq. It should
> only be used the MMC device.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  drivers/mmc/host/meson-gx-mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 8b690ecde4c5..3df50b53f834 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
>                host->regs + SD_EMMC_IRQ_EN);
>
>         ret = request_threaded_irq(host->irq, meson_mmc_irq,
> -                                  meson_mmc_irq_thread, IRQF_SHARED,
> +                                  meson_mmc_irq_thread, IRQF_ONESHOT,
>                                    dev_name(&pdev->dev), host);
the commit message reads as if the intention is to remove the IRQF_SHARED flag.
however, the commit message doesn't mention IRQF_ONESHOT (which was
not set before).

if you used IRQF_ONESHOT on purpose then please mention it in the
patch description.


Martin

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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

[-- Attachment #1: Type: text/plain, Size: 780 bytes --]

Hi Jerome,

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> Activating DDR in the Amlogic mmc controller, among other things, will
> divide the output clock by 2. So by activating it with clock on, we are
> creating a glitch on the output.
>
> Instead, let's deal with DDR when the clock output is off, when setting
> the clock.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
I used git bisect within this series to find that issue.
applying your .dts patches on top doesn't fix it

two boot logs attached:
* kvim-broken.txt has patches 1-5 (= including this patch) applied
* kvim-working.txt has only patches 1-4 (= excluding this patch) applied


Regards
Martin

[-- Attachment #2: kvim-broken.txt --]
[-- Type: text/plain, Size: 22112 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.1.0-rc5+ (xdarklight@blackbox) (gcc version 8.3.0 (GCC)) #504 SMP PREEMPT Thu Apr 18 22:09:17 CEST 2019
[    0.000000] Machine model: Khadas VIM
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000068000000, size 256 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv0.2 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] random: get_random_bytes called from start_kernel+0x9c/0x444 with crng_init=0
[    0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s55576 r8192 d30440 u94208
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 478528
[    0.000000] Kernel command line: console=ttyAML0,115200 root=/dev/mmcblk0p2 rootwait=1 rootdelay=2 init=/usr/bin/init
[    0.000000] printk: log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] printk: log_buf_len total cpu_extra contributions: 12288 bytes
[    0.000000] printk: log_buf_len min size: 16384 bytes
[    0.000000] printk: log_buf_len: 32768 bytes
[    0.000000] printk: early log buf free: 14580(88%)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Memory: 1621808K/1944576K available (12284K kernel code, 876K rwdata, 4272K rodata, 640K init, 320K bss, 60624K reserved, 262144K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
[    0.000000]  Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq_meson_gpio: 110 to 8 gpio interrupt mux initialized
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000004] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.000358] Console: colour dummy device 80x25
[    0.000390] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[    0.000399] pid_max: default: 32768 minimum: 301
[    0.000467] LSM: Security Framework initializing
[    0.000533] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000546] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000890] *** VALIDATE proc ***
[    0.000998] *** VALIDATE cgroup1 ***
[    0.001006] *** VALIDATE cgroup2 ***
[    0.024007] ASID allocator initialised with 32768 entries
[    0.031995] rcu: Hierarchical SRCU implementation.
[    0.040350] EFI services will not be available.
[    0.052037] smp: Bringing up secondary CPUs ...
[    0.084246] Detected VIPT I-cache on CPU1
[    0.084296] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.116279] Detected VIPT I-cache on CPU2
[    0.116319] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.148329] Detected VIPT I-cache on CPU3
[    0.148367] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.148437] smp: Brought up 1 node, 4 CPUs
[    0.148455] SMP: Total of 4 processors activated.
[    0.148460] CPU features: detected: 32-bit EL0 Support
[    0.148466] CPU features: detected: CRC32 instructions
[    0.148766] CPU: All CPU(s) started at EL2
[    0.148781] alternatives: patching kernel code
[    0.149523] devtmpfs: initialized
[    0.153643] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.153661] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.160521] xor: measuring software checksum speed
[    0.200286]    8regs     :  2375.000 MB/sec
[    0.240315]    32regs    :  2725.000 MB/sec
[    0.280346]    arm64_neon:  2374.000 MB/sec
[    0.280351] xor: using function: 32regs (2725.000 MB/sec)
[    0.280410] pinctrl core: initialized pinctrl subsystem
[    0.281197] DMI not present or invalid.
[    0.281468] NET: Registered protocol family 16
[    0.281838] audit: initializing netlink subsys (disabled)
[    0.281955] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
[    0.282679] cpuidle: using governor menu
[    0.282918] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.282929] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.283961] DMA: preallocated 256 KiB pool for atomic allocations
[    0.284093] Serial: AMBA PL011 UART driver
[    0.303250] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.303261] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.303267] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.303272] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.303660] cryptd: max_cpu_qlen set to 1000
[    0.368591] raid6: neonx8   gen()  1595 MB/s
[    0.436616] raid6: neonx8   xor()  1488 MB/s
[    0.504732] raid6: neonx4   gen()  1560 MB/s
[    0.572773] raid6: neonx4   xor()  1435 MB/s
[    0.640797] raid6: neonx2   gen()  1173 MB/s
[    0.708859] raid6: neonx2   xor()  1149 MB/s
[    0.776909] raid6: neonx1   gen()   760 MB/s
[    0.844983] raid6: neonx1   xor()   774 MB/s
[    0.913039] raid6: int64x8  gen()  1194 MB/s
[    0.981094] raid6: int64x8  xor()   765 MB/s
[    1.049203] raid6: int64x4  gen()  1011 MB/s
[    1.117215] raid6: int64x4  xor()   727 MB/s
[    1.185291] raid6: int64x2  gen()   710 MB/s
[    1.253364] raid6: int64x2  xor()   555 MB/s
[    1.321440] raid6: int64x1  gen()   465 MB/s
[    1.389479] raid6: int64x1  xor()   381 MB/s
[    1.389484] raid6: using algorithm neonx8 gen() 1595 MB/s
[    1.389488] raid6: .... xor() 1488 MB/s, rmw enabled
[    1.389492] raid6: using neon recovery algorithm
[    1.389702] ACPI: Interpreter disabled.
[    1.391154] vgaarb: loaded
[    1.391417] SCSI subsystem initialized
[    1.391890] usbcore: registered new interface driver usbfs
[    1.391933] usbcore: registered new interface driver hub
[    1.392009] usbcore: registered new device driver usb
[    1.392569] media: Linux media interface: v0.10
[    1.392604] videodev: Linux video capture interface: v2.00
[    1.392800] pps_core: LinuxPPS API ver. 1 registered
[    1.392808] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.392828] PTP clock support registered
[    1.393212] Advanced Linux Sound Architecture Driver Initialized.
[    1.393646] Bluetooth: Core ver 2.22
[    1.393715] NET: Registered protocol family 31
[    1.393720] Bluetooth: HCI device and connection manager initialized
[    1.393734] Bluetooth: HCI socket layer initialized
[    1.393740] Bluetooth: L2CAP socket layer initialized
[    1.393755] Bluetooth: SCO socket layer initialized
[    1.394236] clocksource: Switched to clocksource arch_sys_counter
[    1.394374] VFS: Disk quotas dquot_6.6.0
[    1.394425] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.394462] *** VALIDATE hugetlbfs ***
[    1.394616] pnp: PnP ACPI: disabled
[    1.400190] NET: Registered protocol family 2
[    1.400590] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[    1.400619] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    1.400726] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[    1.400923] TCP: Hash tables configured (established 16384 bind 16384)
[    1.401030] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.401073] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.401222] NET: Registered protocol family 1
[    1.401581] RPC: Registered named UNIX socket transport module.
[    1.401589] RPC: Registered udp transport module.
[    1.401593] RPC: Registered tcp transport module.
[    1.401597] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.402950] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    1.403272] kvm [1]: IPA Size Limit: 40bits
[    1.403753] kvm [1]: vgic interrupt IRQ1
[    1.403836] kvm [1]: Hyp mode initialized successfully
[    1.412564] Initialise system trusted keyrings
[    1.412689] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    1.419046] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.419717] NFS: Registering the id_resolver key type
[    1.419743] Key type id_resolver registered
[    1.419747] Key type id_legacy registered
[    1.419916] fuse init (API version 7.29)
[    1.420296] 9p: Installing v9fs 9p2000 file system support
[    1.427233] Key type asymmetric registered
[    1.427245] Asymmetric key parser 'x509' registered
[    1.427263] io scheduler mq-deadline registered
[    1.427269] io scheduler kyber registered
[    1.427496] io scheduler bfq registered
[    1.446522] soc soc0: Amlogic Meson GXL (S905X) Revision 21:a (82:2) Detected
[    1.450206] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.452547] c11084c0.serial: ttyAML1 at MMIO 0xc11084c0 (irq = 10, base_baud = 1500000) is a meson_uart
[    1.452701] serial serial0: tty port ttyAML1 registered
[    1.452995] c81004c0.serial: ttyAML0 at MMIO 0xc81004c0 (irq = 15, base_baud = 1500000) is a meson_uart
[    2.323225] printk: console [ttyAML0] enabled
[    2.328110] c81004e0.serial: ttyAML2 at MMIO 0xc81004e0 (irq = 16, base_baud = 1500000) is a meson_uart
[    2.345041] loop: module loaded
[    2.347396] libphy: Fixed MDIO Bus: probed
[    2.348286] tun: Universal TUN/TAP device driver, 1.6
[    2.352124] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[    2.357411] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    2.363327] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k
[    2.370168] igb: Copyright (c) 2007-2014 Intel Corporation.
[    2.375747] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[    2.383447] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    2.389354] sky2: driver version 1.30
[    2.393672] meson8b-dwmac c9410000.ethernet: PTP uses main clock
[    2.398905] meson8b-dwmac c9410000.ethernet: no reset control found
[    2.405534] meson8b-dwmac c9410000.ethernet: User ID: 0x11, Synopsys ID: 0x37
[    2.412178] meson8b-dwmac c9410000.ethernet:         DWMAC1000
[    2.417341] meson8b-dwmac c9410000.ethernet: DMA HW capability register supported
[    2.424758] meson8b-dwmac c9410000.ethernet: RX Checksum Offload Engine supported
[    2.432175] meson8b-dwmac c9410000.ethernet: COE Type 2
[    2.437349] meson8b-dwmac c9410000.ethernet: TX Checksum insertion supported
[    2.444336] meson8b-dwmac c9410000.ethernet: Wake-Up On Lan supported
[    2.450746] meson8b-dwmac c9410000.ethernet: Normal descriptors
[    2.456584] meson8b-dwmac c9410000.ethernet: Ring mode enabled
[    2.462363] meson8b-dwmac c9410000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.470426] libphy: stmmac: probed
[    2.475086] VFIO - User Level meta-driver version: 0.3
[    2.480049] dwc3 c9000000.dwc3: Failed to get clk 'ref': -2
[    2.486094] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.490757] ehci-pci: EHCI PCI platform driver
[    2.495203] ehci-platform: EHCI generic platform driver
[    2.500549] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    2.506459] ohci-pci: OHCI PCI platform driver
[    2.510900] ohci-platform: OHCI generic platform driver
[    2.516804] usbcore: registered new interface driver usb-storage
[    2.523550] mousedev: PS/2 mouse device common for all mice
[    2.528242] input: gpio-keys-polled as /devices/platform/gpio-keys-polled/input/input0
[    2.536246] i2c /dev entries driver
[    2.540702] IR NEC protocol handler initialized
[    2.543281] IR RC5(x/sz) protocol handler initialized
[    2.548267] IR RC6 protocol handler initialized
[    2.552752] IR JVC protocol handler initialized
[    2.557236] IR Sony protocol handler initialized
[    2.561807] IR SANYO protocol handler initialized
[    2.566465] IR Sharp protocol handler initialized
[    2.571122] IR MCE Keyboard/mouse protocol handler initialized
[    2.576901] IR XMP protocol handler initialized
[    2.581725] Registered IR keymap rc-geekbox
[    2.585625] rc rc0: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0
[    2.593408] input: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0/input1
[    2.601806] rc rc0: lirc_dev: driver meson-ir registered at minor = 0, raw IR receiver, no transmitter
[    2.610926] meson-ir c8100580.ir: receiver initialized
[    2.617203] Registered IR keymap rc-cec
[    2.619844] rc rc1: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1
[    2.628051] input: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1/input2
[    2.637127] usbcore: registered new interface driver dvb_usb_rtl28xxu
[    2.644793] Bluetooth: HCI UART driver ver 2.3
[    2.647390] Bluetooth: HCI UART protocol H4 registered
[    2.652468] Bluetooth: HCI UART protocol BCSP registered
[    2.657763] Bluetooth: HCI UART protocol LL registered
[    2.662811] Bluetooth: HCI UART protocol ATH3K registered
[    2.668188] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.674512] Bluetooth: HCI UART protocol Intel registered
[    2.679864] Bluetooth: HCI UART protocol Broadcom registered
[    2.680045] hci_uart_bcm serial0-0: serial0-0 supply vbat not found, using dummy regulator
[    2.685377] Bluetooth: HCI UART protocol QCA registered
[    2.693593] hci_uart_bcm serial0-0: serial0-0 supply vddio not found, using dummy regulator
[    2.698687] Bluetooth: HCI UART protocol AG6XX registered
[    2.698762] usbcore: registered new interface driver bcm203x
[    2.717924] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.724323] sdhci: Secure Digital Host Controller Interface driver
[    2.729679] sdhci: Copyright(c) Pierre Ossman
[    2.734016] Synopsys Designware Multimedia Card Interface Driver
[    2.741525] meson-gx-mmc d0072000.mmc: Got CD GPIO
[    2.771477] meson-gx-mmc d0074000.mmc: allocated mmc-pwrseq
[    2.798513] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.799658] ledtrig-cpu: registered to indicate activity on CPUs
[    2.805232] meson-sm: secure-monitor enabled
[    2.809656] usbcore: registered new interface driver usbhid
[    2.814272] usbhid: USB HID core driver
[    2.818416] platform-mhu c883c404.mailbox: Platform MHU Mailbox registered
[BL31]: tee size: 0
[    2.829037] gnss: GNSS driver registered with major 240
[    2.834326] NET: Registered protocol family 17
[    2.836507] Bluetooth: RFCOMM TTY layer initialized
[    2.841112] Bluetooth: RFCOMM socket layer initialized
[    2.846253] Bluetooth: RFCOMM ver 1.11
[    2.849865] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.855136] Bluetooth: BNEP filters: protocol multicast
[    2.860377] Bluetooth: BNEP socket layer initialized
[    2.865217] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.871079] Bluetooth: HIDP socket layer initialized
[    2.876536] 9pnet: Installing 9P2000 support
[    2.880374] Key type dns_resolver registered
[    2.885363] registered taskstats version 1
[    2.888599] Loading compiled-in X.509 certificates
[    2.894354] Btrfs loaded, crc32c=crc32c-generic
[    2.909268] meson-drm d0100000.vpu: Queued 2 outputs on vpu
[    2.909665] meson-drm d0100000.vpu: Falling back to parsing the 'hhi' registers
[    2.909752] mmc1: switch to bus width 8 failed
[    2.916726] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.927421] [drm] No driver support for vblank timestamp query.
[    2.932506] mmc1: switch to bus width 4 failed
[    2.933394] meson-drm d0100000.vpu: CVBS Output connector not available
[    2.937757] mmc1: mmc_select_hs200 failed, error -84
[    2.949151] mmc1: error -84 whilst initialising MMC card
[    2.970365] meson-dw-hdmi c883a000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
[    2.975069] meson-dw-hdmi c883a000.hdmi-tx: registered DesignWare HDMI I2C bus driver
[    2.983078] Registered IR keymap rc-cec
[    2.986189] rc rc2: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2
[    2.993313] input: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2/input3
[    3.001054] meson-drm d0100000.vpu: bound c883a000.hdmi-tx (ops meson_dw_hdmi_ops)
[    3.008443] [drm] Initialized meson 1.0.0 20161109 for d0100000.vpu on minor 0
[    3.015364] [drm] Cannot find any crtc or sizes
[    3.020332] libphy: mdio_mux: probed
[    3.023354] [drm] Cannot find any crtc or sizes
[    3.028053] libphy: mdio_mux: probed
[    3.031796] phy phy-d0078080.phy.2: unsupported PHY mode 5
[    3.038831] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.042157] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    3.050742] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010
[    3.059178] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0xc9000000
[    3.065825] hub 1-0:1.0: USB hub found
[    3.068744] hub 1-0:1.0: 2 ports detected
[    3.072919] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.078126] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[    3.085667] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed
[    3.092250] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    3.100723] hub 2-0:1.0: USB hub found
[    3.104124] mmc0: new high speed SDHC card at address 1234
[    3.109604] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
[    3.117068] mmcblk0: mmc0:1234 SA32G 28.9 GiB 
[    3.122175] input: adc-keys as /devices/platform/adc-keys/input/input4
[    3.128691] meson-gx-mmc d0070000.mmc: allocated mmc-pwrseq
[    3.160142] scpi_protocol scpi: SCP Protocol legacy pre-1.0 firmware
domain-0 init dvfs: 4
[    3.169177] cpu cpu0: failed to add opp 100000000Hz 910mV
[    3.169336] cpu cpu0: failed to add opps to the device
[    3.172105] print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
[    3.174274] cpu cpu1: failed to add opp 100000000Hz 910mV
[    3.180529] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[    3.185895] cpu cpu1: failed to add opps to the device
[    3.198196] cpu cpu2: failed to add opp 100000000Hz 910mV
[    3.201761] print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
[    3.203411] cpu cpu2: failed to add opps to the device
[    3.209752] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[    3.214919] cpu cpu3: failed to add opp 100000000Hz 910mV
[    3.227294]  mmcblk0: unable to read partition table
[    3.232761] cpu cpu3: failed to add opps to the device
[    3.239142] hctosys: unable to open rtc device (rtc0)
[    3.242432] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    3.251750] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    3.256578] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    3.264973] cfg80211: failed to load regulatory.db
[    3.265295] VCC_3V3: disabling
[    3.272759] ALSA device list:
[    3.275678]   No soundcards found.
[    3.284692] Waiting 2 sec before mounting root device...
[    3.285790] mmc2: queuing unknown CIS tuple 0x80 (2 bytes)
[    3.291864] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.297303] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.304384] mmc2: queuing unknown CIS tuple 0x80 (7 bytes)
[    3.316407] random: fast init done
[    3.381083] mmc2: new high speed SDIO card at address 0001
[    3.382026] brcmfmac: brcmf_chip_recognition: chip backplane type 15 is not supported
[    3.388704] brcmfmac: brcmf_sdio_probe_attach: brcmf_chip_attach failed!
[    3.395339] brcmfmac: brcmf_sdio_probe: brcmf_sdio_probe_attach failed
[    3.401879] brcmfmac: brcmf_ops_sdio_probe: F2 error, probe failed -19...
[    3.470256] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[    3.555122] random: crng init done
[    3.668466] hub 1-1:1.0: USB hub found
[    3.668532] hub 1-1:1.0: 4 ports detected
[    4.862276] Bluetooth: hci0: command 0x1001 tx timeout
[    5.310447] VFS: Cannot open root device "mmcblk0p2" or unknown-block(179,2): error -6
[    5.312704] Please append a correct "root=" boot option; here are the available partitions:
[    5.321015] b300        30318592 mmcblk0 
[    5.321018]  driver: mmcblk
[    5.327718] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)
[    5.336080] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.1.0-rc5+ #504
[    5.342459] Hardware name: Khadas VIM (DT)
[    5.346513] Call trace:
[    5.348939]  dump_backtrace+0x0/0x130
[    5.352553]  show_stack+0x14/0x20
[    5.355833]  dump_stack+0xac/0xd4
[    5.359110]  panic+0x148/0x2d0
[    5.362128]  mount_block_root+0x1bc/0x26c
[    5.366092]  mount_root+0x11c/0x148
[    5.369543]  prepare_namespace+0x128/0x16c
[    5.373597]  kernel_init_freeable+0x1b8/0x1d4
[    5.377910]  kernel_init+0x10/0xfc
[    5.381274]  ret_from_fork+0x10/0x1c
[    5.384813] SMP: stopping secondary CPUs
[    5.388694] Kernel Offset: disabled
[    5.392141] CPU features: 0x002,20002004
[    5.396020] Memory Limit: none
[    5.399045] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2) ]---

[-- Attachment #3: kvin-working.txt --]
[-- Type: text/plain, Size: 20594 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.1.0-rc5+ (xdarklight@blackbox) (gcc version 8.3.0 (GCC)) #507 SMP PREEMPT Thu Apr 18 22:11:29 CEST 2019
[    0.000000] Machine model: Khadas VIM
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000068000000, size 256 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv0.2 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] random: get_random_bytes called from start_kernel+0x9c/0x444 with crng_init=0
[    0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s55576 r8192 d30440 u94208
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 478528
[    0.000000] Kernel command line: console=ttyAML0,115200 root=/dev/mmcblk0p2 rootwait=1 rootdelay=2 init=/usr/bin/init rw
[    0.000000] printk: log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] printk: log_buf_len total cpu_extra contributions: 12288 bytes
[    0.000000] printk: log_buf_len min size: 16384 bytes
[    0.000000] printk: log_buf_len: 32768 bytes
[    0.000000] printk: early log buf free: 14580(88%)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Memory: 1621808K/1944576K available (12284K kernel code, 876K rwdata, 4272K rodata, 640K init, 320K bss, 60624K reserved, 262144K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
[    0.000000]  Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq_meson_gpio: 110 to 8 gpio interrupt mux initialized
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000003] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.000357] Console: colour dummy device 80x25
[    0.000388] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[    0.000396] pid_max: default: 32768 minimum: 301
[    0.000465] LSM: Security Framework initializing
[    0.000529] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000542] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000880] *** VALIDATE proc ***
[    0.000989] *** VALIDATE cgroup1 ***
[    0.000996] *** VALIDATE cgroup2 ***
[    0.024003] ASID allocator initialised with 32768 entries
[    0.031992] rcu: Hierarchical SRCU implementation.
[    0.040350] EFI services will not be available.
[    0.052036] smp: Bringing up secondary CPUs ...
[    0.084245] Detected VIPT I-cache on CPU1
[    0.084293] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.116276] Detected VIPT I-cache on CPU2
[    0.116317] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.148324] Detected VIPT I-cache on CPU3
[    0.148364] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.148432] smp: Brought up 1 node, 4 CPUs
[    0.148449] SMP: Total of 4 processors activated.
[    0.148455] CPU features: detected: 32-bit EL0 Support
[    0.148461] CPU features: detected: CRC32 instructions
[    0.148763] CPU: All CPU(s) started at EL2
[    0.148778] alternatives: patching kernel code
[    0.149518] devtmpfs: initialized
[    0.153673] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.153691] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.160549] xor: measuring software checksum speed
[    0.200279]    8regs     :  2375.000 MB/sec
[    0.240307]    32regs    :  2725.000 MB/sec
[    0.280338]    arm64_neon:  2374.000 MB/sec
[    0.280342] xor: using function: 32regs (2725.000 MB/sec)
[    0.280401] pinctrl core: initialized pinctrl subsystem
[    0.281326] DMI not present or invalid.
[    0.281599] NET: Registered protocol family 16
[    0.281989] audit: initializing netlink subsys (disabled)
[    0.282130] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
[    0.282995] cpuidle: using governor menu
[    0.283243] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.283252] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.284267] DMA: preallocated 256 KiB pool for atomic allocations
[    0.284428] Serial: AMBA PL011 UART driver
[    0.303157] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.303169] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.303174] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.303179] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.303536] cryptd: max_cpu_qlen set to 1000
[    0.368579] raid6: neonx8   gen()  1600 MB/s
[    0.436675] raid6: neonx8   xor()  1474 MB/s
[    0.504732] raid6: neonx4   gen()  1559 MB/s
[    0.572737] raid6: neonx4   xor()  1445 MB/s
[    0.640837] raid6: neonx2   gen()  1175 MB/s
[    0.708865] raid6: neonx2   xor()  1148 MB/s
[    0.776926] raid6: neonx1   gen()   760 MB/s
[    0.844969] raid6: neonx1   xor()   771 MB/s
[    0.913013] raid6: int64x8  gen()  1194 MB/s
[    0.981050] raid6: int64x8  xor()   765 MB/s
[    1.049137] raid6: int64x4  gen()  1011 MB/s
[    1.117164] raid6: int64x4  xor()   727 MB/s
[    1.185260] raid6: int64x2  gen()   711 MB/s
[    1.253253] raid6: int64x2  xor()   554 MB/s
[    1.321331] raid6: int64x1  gen()   465 MB/s
[    1.389340] raid6: int64x1  xor()   381 MB/s
[    1.389345] raid6: using algorithm neonx8 gen() 1600 MB/s
[    1.389349] raid6: .... xor() 1474 MB/s, rmw enabled
[    1.389354] raid6: using neon recovery algorithm
[    1.389578] ACPI: Interpreter disabled.
[    1.390980] vgaarb: loaded
[    1.391231] SCSI subsystem initialized
[    1.391696] usbcore: registered new interface driver usbfs
[    1.391742] usbcore: registered new interface driver hub
[    1.391823] usbcore: registered new device driver usb
[    1.392316] media: Linux media interface: v0.10
[    1.392349] videodev: Linux video capture interface: v2.00
[    1.392502] pps_core: LinuxPPS API ver. 1 registered
[    1.392510] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.392530] PTP clock support registered
[    1.392840] Advanced Linux Sound Architecture Driver Initialized.
[    1.393213] Bluetooth: Core ver 2.22
[    1.393273] NET: Registered protocol family 31
[    1.393278] Bluetooth: HCI device and connection manager initialized
[    1.393292] Bluetooth: HCI socket layer initialized
[    1.393298] Bluetooth: L2CAP socket layer initialized
[    1.393311] Bluetooth: SCO socket layer initialized
[    1.393824] clocksource: Switched to clocksource arch_sys_counter
[    1.393962] VFS: Disk quotas dquot_6.6.0
[    1.394011] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.394047] *** VALIDATE hugetlbfs ***
[    1.394197] pnp: PnP ACPI: disabled
[    1.399936] NET: Registered protocol family 2
[    1.400322] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[    1.400350] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    1.400458] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[    1.400656] TCP: Hash tables configured (established 16384 bind 16384)
[    1.400764] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.400807] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.400951] NET: Registered protocol family 1
[    1.401296] RPC: Registered named UNIX socket transport module.
[    1.401302] RPC: Registered udp transport module.
[    1.401307] RPC: Registered tcp transport module.
[    1.401310] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.402436] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    1.402758] kvm [1]: IPA Size Limit: 40bits
[    1.403224] kvm [1]: vgic interrupt IRQ1
[    1.403310] kvm [1]: Hyp mode initialized successfully
[    1.411956] Initialise system trusted keyrings
[    1.412097] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    1.418104] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.418716] NFS: Registering the id_resolver key type
[    1.418741] Key type id_resolver registered
[    1.418745] Key type id_legacy registered
[    1.418922] fuse init (API version 7.29)
[    1.419305] 9p: Installing v9fs 9p2000 file system support
[    1.425769] Key type asymmetric registered
[    1.425781] Asymmetric key parser 'x509' registered
[    1.425799] io scheduler mq-deadline registered
[    1.425804] io scheduler kyber registered
[    1.426205] io scheduler bfq registered
[    1.444199] soc soc0: Amlogic Meson GXL (S905X) Revision 21:a (82:2) Detected
[    1.447783] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.450027] c11084c0.serial: ttyAML1 at MMIO 0xc11084c0 (irq = 10, base_baud = 1500000) is a meson_uart
[    1.450202] serial serial0: tty port ttyAML1 registered
[    1.450495] c81004c0.serial: ttyAML0 at MMIO 0xc81004c0 (irq = 15, base_baud = 1500000) is a meson_uart
[    2.320981] printk: console [ttyAML0] enabled
[    2.325864] c81004e0.serial: ttyAML2 at MMIO 0xc81004e0 (irq = 16, base_baud = 1500000) is a meson_uart
[    2.342744] loop: module loaded
[    2.344917] libphy: Fixed MDIO Bus: probed
[    2.345684] tun: Universal TUN/TAP device driver, 1.6
[    2.349876] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[    2.355104] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    2.361012] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k
[    2.367869] igb: Copyright (c) 2007-2014 Intel Corporation.
[    2.373425] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[    2.381149] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    2.387050] sky2: driver version 1.30
[    2.391379] meson8b-dwmac c9410000.ethernet: PTP uses main clock
[    2.396604] meson8b-dwmac c9410000.ethernet: no reset control found
[    2.403236] meson8b-dwmac c9410000.ethernet: User ID: 0x11, Synopsys ID: 0x37
[    2.409886] meson8b-dwmac c9410000.ethernet:         DWMAC1000
[    2.415053] meson8b-dwmac c9410000.ethernet: DMA HW capability register supported
[    2.422462] meson8b-dwmac c9410000.ethernet: RX Checksum Offload Engine supported
[    2.429879] meson8b-dwmac c9410000.ethernet: COE Type 2
[    2.435053] meson8b-dwmac c9410000.ethernet: TX Checksum insertion supported
[    2.442040] meson8b-dwmac c9410000.ethernet: Wake-Up On Lan supported
[    2.448451] meson8b-dwmac c9410000.ethernet: Normal descriptors
[    2.454289] meson8b-dwmac c9410000.ethernet: Ring mode enabled
[    2.460067] meson8b-dwmac c9410000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.468129] libphy: stmmac: probed
[    2.472676] VFIO - User Level meta-driver version: 0.3
[    2.477731] dwc3 c9000000.dwc3: Failed to get clk 'ref': -2
[    2.483802] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.488464] ehci-pci: EHCI PCI platform driver
[    2.492906] ehci-platform: EHCI generic platform driver
[    2.498263] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    2.504163] ohci-pci: OHCI PCI platform driver
[    2.508608] ohci-platform: OHCI generic platform driver
[    2.514512] usbcore: registered new interface driver usb-storage
[    2.521222] mousedev: PS/2 mouse device common for all mice
[    2.525971] input: gpio-keys-polled as /devices/platform/gpio-keys-polled/input/input0
[    2.533951] i2c /dev entries driver
[    2.538072] IR NEC protocol handler initialized
[    2.540965] IR RC5(x/sz) protocol handler initialized
[    2.545982] IR RC6 protocol handler initialized
[    2.550455] IR JVC protocol handler initialized
[    2.554940] IR Sony protocol handler initialized
[    2.559511] IR SANYO protocol handler initialized
[    2.564168] IR Sharp protocol handler initialized
[    2.568826] IR MCE Keyboard/mouse protocol handler initialized
[    2.574605] IR XMP protocol handler initialized
[    2.579421] Registered IR keymap rc-geekbox
[    2.583323] rc rc0: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0
[    2.591107] input: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0/input1
[    2.599506] rc rc0: lirc_dev: driver meson-ir registered at minor = 0, raw IR receiver, no transmitter
[    2.608621] meson-ir c8100580.ir: receiver initialized
[    2.614973] Registered IR keymap rc-cec
[    2.617514] rc rc1: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1
[    2.625880] input: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1/input2
[    2.634892] usbcore: registered new interface driver dvb_usb_rtl28xxu
[    2.642439] Bluetooth: HCI UART driver ver 2.3
[    2.645070] Bluetooth: HCI UART protocol H4 registered
[    2.650176] Bluetooth: HCI UART protocol BCSP registered
[    2.655494] Bluetooth: HCI UART protocol LL registered
[    2.660516] Bluetooth: HCI UART protocol ATH3K registered
[    2.665884] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.672204] Bluetooth: HCI UART protocol Intel registered
[    2.677562] Bluetooth: HCI UART protocol Broadcom registered
[    2.677745] hci_uart_bcm serial0-0: serial0-0 supply vbat not found, using dummy regulator
[    2.683086] Bluetooth: HCI UART protocol QCA registered
[    2.691327] hci_uart_bcm serial0-0: serial0-0 supply vddio not found, using dummy regulator
[    2.696391] Bluetooth: HCI UART protocol AG6XX registered
[    2.696466] usbcore: registered new interface driver bcm203x
[    2.715627] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.722060] sdhci: Secure Digital Host Controller Interface driver
[    2.727369] sdhci: Copyright(c) Pierre Ossman
[    2.731707] Synopsys Designware Multimedia Card Interface Driver
[    2.739200] meson-gx-mmc d0072000.mmc: Got CD GPIO
[    2.769627] meson-gx-mmc d0074000.mmc: allocated mmc-pwrseq
[    2.794677] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.795807] ledtrig-cpu: registered to indicate activity on CPUs
[    2.802003] meson-sm: secure-monitor enabled
[    2.806268] usbcore: registered new interface driver usbhid
[    2.810601] usbhid: USB HID core driver
[    2.814798] platform-mhu c883c404.mailbox: Platform MHU Mailbox registered
[BL31]: tee size: 0
[    2.825356] gnss: GNSS driver registered with major 240
[    2.828398] mmc0: new high speed SDHC card at address 1234
[    2.831490] NET: Registered protocol family 17
[    2.834753] mmcblk0: mmc0:1234 SA32G 28.9 GiB 
[    2.838138] Bluetooth: RFCOMM TTY layer initialized
[    2.847268] Bluetooth: RFCOMM socket layer initialized
[    2.852174] Bluetooth: RFCOMM ver 1.11
[    2.853068]  mmcblk0: p1 p2
[    2.855863] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.863876] Bluetooth: BNEP filters: protocol multicast
[    2.869060] Bluetooth: BNEP socket layer initialized
[    2.873965] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.879829] Bluetooth: HIDP socket layer initialized
[    2.885075] 9pnet: Installing 9P2000 support
[    2.889033] Key type dns_resolver registered
[    2.893892] registered taskstats version 1
[    2.897246] Loading compiled-in X.509 certificates
[    2.902933] Btrfs loaded, crc32c=crc32c-generic
[    2.917756] meson-drm d0100000.vpu: Queued 2 outputs on vpu
[    2.918151] meson-drm d0100000.vpu: Falling back to parsing the 'hhi' registers
[    2.925071] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.931494] [drm] No driver support for vblank timestamp query.
[    2.937441] meson-drm d0100000.vpu: CVBS Output connector not available
[    2.969879] meson-dw-hdmi c883a000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
[    2.974639] meson-dw-hdmi c883a000.hdmi-tx: registered DesignWare HDMI I2C bus driver
[    2.982594] Registered IR keymap rc-cec
[    2.985707] rc rc2: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2
[    2.992729] input: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2/input3
[    3.000411] meson-drm d0100000.vpu: bound c883a000.hdmi-tx (ops meson_dw_hdmi_ops)
[    3.007958] [drm] Initialized meson 1.0.0 20161109 for d0100000.vpu on minor 0
[    3.014796] [drm] Cannot find any crtc or sizes
[    3.019698] libphy: mdio_mux: probed
[    3.022865] [drm] Cannot find any crtc or sizes
[    3.027579] libphy: mdio_mux: probed
[    3.031088] phy phy-d0078080.phy.2: unsupported PHY mode 5
[    3.038256] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.041671] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    3.049982] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010
[    3.058619] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0xc9000000
[    3.065097] hub 1-0:1.0: USB hub found
[    3.068180] hub 1-0:1.0: 2 ports detected
[    3.072408] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.077556] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[    3.085141] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed
[    3.091730] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    3.100202] hub 2-0:1.0: USB hub found
[    3.103457] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
[    3.111158] input: adc-keys as /devices/platform/adc-keys/input/input4
[    3.118353] meson-gx-mmc d0070000.mmc: allocated mmc-pwrseq
[    3.150018] scpi_protocol scpi: SCP Protocol legacy pre-1.0 firmware
domain-0 init dvfs: 4
[    3.159000] cpu cpu0: failed to add opp 100000000Hz 910mV
[    3.159028] cpu cpu0: failed to add opps to the device
[    3.163982] cpu cpu1: failed to add opp 100000000Hz 910mV
[    3.169292] cpu cpu1: failed to add opps to the device
[    3.174412] cpu cpu2: failed to add opp 100000000Hz 910mV
[    3.179725] cpu cpu2: failed to add opps to the device
[    3.184847] cpu cpu3: failed to add opp 100000000Hz 910mV
[    3.190165] cpu cpu3: failed to add opps to the device
[    3.198186] hctosys: unable to open rtc device (rtc0)
[    3.200302] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    3.204258] mmc2: queuing unknown CIS tuple 0x80 (2 bytes)
[    3.209374] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    3.215343] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.219849] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    3.227234] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.230088] ALSA device list:
[    3.230090]   No soundcards found.
[    3.233721] cfg80211: failed to load regulatory.db
[    3.242859] mmc2: queuing unknown CIS tuple 0x80 (7 bytes)
[    3.261368] Waiting 2 sec before mounting root device...
[    3.310098] random: fast init done
[    3.336037] mmc2: new high speed SDIO card at address 0001
[    3.339456] brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43455-sdio for chip BCM4345/6
[    3.344645] brcmfmac mmc2:0001:1: Direct firmware load for brcm/brcmfmac43455-sdio.bin failed with error -2
[    3.429844] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[    3.484280] random: crng init done
[    3.635931] hub 1-1:1.0: USB hub found
[    3.635995] hub 1-1:1.0: 4 ports detected
[    4.861843] Bluetooth: hci0: command 0x1001 tx timeout
[    5.389954] F2FS-fs (mmcblk0p2): Mounted with checkpoint version = 11f
[    5.390902] VFS: Mounted root (f2fs filesystem) on device 179:2.
[    5.398980] devtmpfs: mounted
[    5.399935] Freeing unused kernel memory: 640K
[    5.404197] Run /usr/bin/init as init process
[    5.915641] systemd[1]: System time before build time, advancing clock.

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

[-- Attachment #1: Type: text/plain, Size: 780 bytes --]

Hi Jerome,

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> Activating DDR in the Amlogic mmc controller, among other things, will
> divide the output clock by 2. So by activating it with clock on, we are
> creating a glitch on the output.
>
> Instead, let's deal with DDR when the clock output is off, when setting
> the clock.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
I used git bisect within this series to find that issue.
applying your .dts patches on top doesn't fix it

two boot logs attached:
* kvim-broken.txt has patches 1-5 (= including this patch) applied
* kvim-working.txt has only patches 1-4 (= excluding this patch) applied


Regards
Martin

[-- Attachment #2: kvim-broken.txt --]
[-- Type: text/plain, Size: 22112 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.1.0-rc5+ (xdarklight@blackbox) (gcc version 8.3.0 (GCC)) #504 SMP PREEMPT Thu Apr 18 22:09:17 CEST 2019
[    0.000000] Machine model: Khadas VIM
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000068000000, size 256 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv0.2 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] random: get_random_bytes called from start_kernel+0x9c/0x444 with crng_init=0
[    0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s55576 r8192 d30440 u94208
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 478528
[    0.000000] Kernel command line: console=ttyAML0,115200 root=/dev/mmcblk0p2 rootwait=1 rootdelay=2 init=/usr/bin/init
[    0.000000] printk: log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] printk: log_buf_len total cpu_extra contributions: 12288 bytes
[    0.000000] printk: log_buf_len min size: 16384 bytes
[    0.000000] printk: log_buf_len: 32768 bytes
[    0.000000] printk: early log buf free: 14580(88%)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Memory: 1621808K/1944576K available (12284K kernel code, 876K rwdata, 4272K rodata, 640K init, 320K bss, 60624K reserved, 262144K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
[    0.000000]  Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq_meson_gpio: 110 to 8 gpio interrupt mux initialized
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000004] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.000358] Console: colour dummy device 80x25
[    0.000390] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[    0.000399] pid_max: default: 32768 minimum: 301
[    0.000467] LSM: Security Framework initializing
[    0.000533] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000546] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000890] *** VALIDATE proc ***
[    0.000998] *** VALIDATE cgroup1 ***
[    0.001006] *** VALIDATE cgroup2 ***
[    0.024007] ASID allocator initialised with 32768 entries
[    0.031995] rcu: Hierarchical SRCU implementation.
[    0.040350] EFI services will not be available.
[    0.052037] smp: Bringing up secondary CPUs ...
[    0.084246] Detected VIPT I-cache on CPU1
[    0.084296] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.116279] Detected VIPT I-cache on CPU2
[    0.116319] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.148329] Detected VIPT I-cache on CPU3
[    0.148367] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.148437] smp: Brought up 1 node, 4 CPUs
[    0.148455] SMP: Total of 4 processors activated.
[    0.148460] CPU features: detected: 32-bit EL0 Support
[    0.148466] CPU features: detected: CRC32 instructions
[    0.148766] CPU: All CPU(s) started at EL2
[    0.148781] alternatives: patching kernel code
[    0.149523] devtmpfs: initialized
[    0.153643] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.153661] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.160521] xor: measuring software checksum speed
[    0.200286]    8regs     :  2375.000 MB/sec
[    0.240315]    32regs    :  2725.000 MB/sec
[    0.280346]    arm64_neon:  2374.000 MB/sec
[    0.280351] xor: using function: 32regs (2725.000 MB/sec)
[    0.280410] pinctrl core: initialized pinctrl subsystem
[    0.281197] DMI not present or invalid.
[    0.281468] NET: Registered protocol family 16
[    0.281838] audit: initializing netlink subsys (disabled)
[    0.281955] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
[    0.282679] cpuidle: using governor menu
[    0.282918] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.282929] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.283961] DMA: preallocated 256 KiB pool for atomic allocations
[    0.284093] Serial: AMBA PL011 UART driver
[    0.303250] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.303261] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.303267] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.303272] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.303660] cryptd: max_cpu_qlen set to 1000
[    0.368591] raid6: neonx8   gen()  1595 MB/s
[    0.436616] raid6: neonx8   xor()  1488 MB/s
[    0.504732] raid6: neonx4   gen()  1560 MB/s
[    0.572773] raid6: neonx4   xor()  1435 MB/s
[    0.640797] raid6: neonx2   gen()  1173 MB/s
[    0.708859] raid6: neonx2   xor()  1149 MB/s
[    0.776909] raid6: neonx1   gen()   760 MB/s
[    0.844983] raid6: neonx1   xor()   774 MB/s
[    0.913039] raid6: int64x8  gen()  1194 MB/s
[    0.981094] raid6: int64x8  xor()   765 MB/s
[    1.049203] raid6: int64x4  gen()  1011 MB/s
[    1.117215] raid6: int64x4  xor()   727 MB/s
[    1.185291] raid6: int64x2  gen()   710 MB/s
[    1.253364] raid6: int64x2  xor()   555 MB/s
[    1.321440] raid6: int64x1  gen()   465 MB/s
[    1.389479] raid6: int64x1  xor()   381 MB/s
[    1.389484] raid6: using algorithm neonx8 gen() 1595 MB/s
[    1.389488] raid6: .... xor() 1488 MB/s, rmw enabled
[    1.389492] raid6: using neon recovery algorithm
[    1.389702] ACPI: Interpreter disabled.
[    1.391154] vgaarb: loaded
[    1.391417] SCSI subsystem initialized
[    1.391890] usbcore: registered new interface driver usbfs
[    1.391933] usbcore: registered new interface driver hub
[    1.392009] usbcore: registered new device driver usb
[    1.392569] media: Linux media interface: v0.10
[    1.392604] videodev: Linux video capture interface: v2.00
[    1.392800] pps_core: LinuxPPS API ver. 1 registered
[    1.392808] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.392828] PTP clock support registered
[    1.393212] Advanced Linux Sound Architecture Driver Initialized.
[    1.393646] Bluetooth: Core ver 2.22
[    1.393715] NET: Registered protocol family 31
[    1.393720] Bluetooth: HCI device and connection manager initialized
[    1.393734] Bluetooth: HCI socket layer initialized
[    1.393740] Bluetooth: L2CAP socket layer initialized
[    1.393755] Bluetooth: SCO socket layer initialized
[    1.394236] clocksource: Switched to clocksource arch_sys_counter
[    1.394374] VFS: Disk quotas dquot_6.6.0
[    1.394425] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.394462] *** VALIDATE hugetlbfs ***
[    1.394616] pnp: PnP ACPI: disabled
[    1.400190] NET: Registered protocol family 2
[    1.400590] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[    1.400619] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    1.400726] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[    1.400923] TCP: Hash tables configured (established 16384 bind 16384)
[    1.401030] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.401073] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.401222] NET: Registered protocol family 1
[    1.401581] RPC: Registered named UNIX socket transport module.
[    1.401589] RPC: Registered udp transport module.
[    1.401593] RPC: Registered tcp transport module.
[    1.401597] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.402950] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    1.403272] kvm [1]: IPA Size Limit: 40bits
[    1.403753] kvm [1]: vgic interrupt IRQ1
[    1.403836] kvm [1]: Hyp mode initialized successfully
[    1.412564] Initialise system trusted keyrings
[    1.412689] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    1.419046] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.419717] NFS: Registering the id_resolver key type
[    1.419743] Key type id_resolver registered
[    1.419747] Key type id_legacy registered
[    1.419916] fuse init (API version 7.29)
[    1.420296] 9p: Installing v9fs 9p2000 file system support
[    1.427233] Key type asymmetric registered
[    1.427245] Asymmetric key parser 'x509' registered
[    1.427263] io scheduler mq-deadline registered
[    1.427269] io scheduler kyber registered
[    1.427496] io scheduler bfq registered
[    1.446522] soc soc0: Amlogic Meson GXL (S905X) Revision 21:a (82:2) Detected
[    1.450206] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.452547] c11084c0.serial: ttyAML1 at MMIO 0xc11084c0 (irq = 10, base_baud = 1500000) is a meson_uart
[    1.452701] serial serial0: tty port ttyAML1 registered
[    1.452995] c81004c0.serial: ttyAML0 at MMIO 0xc81004c0 (irq = 15, base_baud = 1500000) is a meson_uart
[    2.323225] printk: console [ttyAML0] enabled
[    2.328110] c81004e0.serial: ttyAML2 at MMIO 0xc81004e0 (irq = 16, base_baud = 1500000) is a meson_uart
[    2.345041] loop: module loaded
[    2.347396] libphy: Fixed MDIO Bus: probed
[    2.348286] tun: Universal TUN/TAP device driver, 1.6
[    2.352124] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[    2.357411] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    2.363327] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k
[    2.370168] igb: Copyright (c) 2007-2014 Intel Corporation.
[    2.375747] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[    2.383447] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    2.389354] sky2: driver version 1.30
[    2.393672] meson8b-dwmac c9410000.ethernet: PTP uses main clock
[    2.398905] meson8b-dwmac c9410000.ethernet: no reset control found
[    2.405534] meson8b-dwmac c9410000.ethernet: User ID: 0x11, Synopsys ID: 0x37
[    2.412178] meson8b-dwmac c9410000.ethernet:         DWMAC1000
[    2.417341] meson8b-dwmac c9410000.ethernet: DMA HW capability register supported
[    2.424758] meson8b-dwmac c9410000.ethernet: RX Checksum Offload Engine supported
[    2.432175] meson8b-dwmac c9410000.ethernet: COE Type 2
[    2.437349] meson8b-dwmac c9410000.ethernet: TX Checksum insertion supported
[    2.444336] meson8b-dwmac c9410000.ethernet: Wake-Up On Lan supported
[    2.450746] meson8b-dwmac c9410000.ethernet: Normal descriptors
[    2.456584] meson8b-dwmac c9410000.ethernet: Ring mode enabled
[    2.462363] meson8b-dwmac c9410000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.470426] libphy: stmmac: probed
[    2.475086] VFIO - User Level meta-driver version: 0.3
[    2.480049] dwc3 c9000000.dwc3: Failed to get clk 'ref': -2
[    2.486094] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.490757] ehci-pci: EHCI PCI platform driver
[    2.495203] ehci-platform: EHCI generic platform driver
[    2.500549] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    2.506459] ohci-pci: OHCI PCI platform driver
[    2.510900] ohci-platform: OHCI generic platform driver
[    2.516804] usbcore: registered new interface driver usb-storage
[    2.523550] mousedev: PS/2 mouse device common for all mice
[    2.528242] input: gpio-keys-polled as /devices/platform/gpio-keys-polled/input/input0
[    2.536246] i2c /dev entries driver
[    2.540702] IR NEC protocol handler initialized
[    2.543281] IR RC5(x/sz) protocol handler initialized
[    2.548267] IR RC6 protocol handler initialized
[    2.552752] IR JVC protocol handler initialized
[    2.557236] IR Sony protocol handler initialized
[    2.561807] IR SANYO protocol handler initialized
[    2.566465] IR Sharp protocol handler initialized
[    2.571122] IR MCE Keyboard/mouse protocol handler initialized
[    2.576901] IR XMP protocol handler initialized
[    2.581725] Registered IR keymap rc-geekbox
[    2.585625] rc rc0: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0
[    2.593408] input: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0/input1
[    2.601806] rc rc0: lirc_dev: driver meson-ir registered at minor = 0, raw IR receiver, no transmitter
[    2.610926] meson-ir c8100580.ir: receiver initialized
[    2.617203] Registered IR keymap rc-cec
[    2.619844] rc rc1: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1
[    2.628051] input: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1/input2
[    2.637127] usbcore: registered new interface driver dvb_usb_rtl28xxu
[    2.644793] Bluetooth: HCI UART driver ver 2.3
[    2.647390] Bluetooth: HCI UART protocol H4 registered
[    2.652468] Bluetooth: HCI UART protocol BCSP registered
[    2.657763] Bluetooth: HCI UART protocol LL registered
[    2.662811] Bluetooth: HCI UART protocol ATH3K registered
[    2.668188] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.674512] Bluetooth: HCI UART protocol Intel registered
[    2.679864] Bluetooth: HCI UART protocol Broadcom registered
[    2.680045] hci_uart_bcm serial0-0: serial0-0 supply vbat not found, using dummy regulator
[    2.685377] Bluetooth: HCI UART protocol QCA registered
[    2.693593] hci_uart_bcm serial0-0: serial0-0 supply vddio not found, using dummy regulator
[    2.698687] Bluetooth: HCI UART protocol AG6XX registered
[    2.698762] usbcore: registered new interface driver bcm203x
[    2.717924] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.724323] sdhci: Secure Digital Host Controller Interface driver
[    2.729679] sdhci: Copyright(c) Pierre Ossman
[    2.734016] Synopsys Designware Multimedia Card Interface Driver
[    2.741525] meson-gx-mmc d0072000.mmc: Got CD GPIO
[    2.771477] meson-gx-mmc d0074000.mmc: allocated mmc-pwrseq
[    2.798513] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.799658] ledtrig-cpu: registered to indicate activity on CPUs
[    2.805232] meson-sm: secure-monitor enabled
[    2.809656] usbcore: registered new interface driver usbhid
[    2.814272] usbhid: USB HID core driver
[    2.818416] platform-mhu c883c404.mailbox: Platform MHU Mailbox registered
[BL31]: tee size: 0
[    2.829037] gnss: GNSS driver registered with major 240
[    2.834326] NET: Registered protocol family 17
[    2.836507] Bluetooth: RFCOMM TTY layer initialized
[    2.841112] Bluetooth: RFCOMM socket layer initialized
[    2.846253] Bluetooth: RFCOMM ver 1.11
[    2.849865] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.855136] Bluetooth: BNEP filters: protocol multicast
[    2.860377] Bluetooth: BNEP socket layer initialized
[    2.865217] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.871079] Bluetooth: HIDP socket layer initialized
[    2.876536] 9pnet: Installing 9P2000 support
[    2.880374] Key type dns_resolver registered
[    2.885363] registered taskstats version 1
[    2.888599] Loading compiled-in X.509 certificates
[    2.894354] Btrfs loaded, crc32c=crc32c-generic
[    2.909268] meson-drm d0100000.vpu: Queued 2 outputs on vpu
[    2.909665] meson-drm d0100000.vpu: Falling back to parsing the 'hhi' registers
[    2.909752] mmc1: switch to bus width 8 failed
[    2.916726] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.927421] [drm] No driver support for vblank timestamp query.
[    2.932506] mmc1: switch to bus width 4 failed
[    2.933394] meson-drm d0100000.vpu: CVBS Output connector not available
[    2.937757] mmc1: mmc_select_hs200 failed, error -84
[    2.949151] mmc1: error -84 whilst initialising MMC card
[    2.970365] meson-dw-hdmi c883a000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
[    2.975069] meson-dw-hdmi c883a000.hdmi-tx: registered DesignWare HDMI I2C bus driver
[    2.983078] Registered IR keymap rc-cec
[    2.986189] rc rc2: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2
[    2.993313] input: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2/input3
[    3.001054] meson-drm d0100000.vpu: bound c883a000.hdmi-tx (ops meson_dw_hdmi_ops)
[    3.008443] [drm] Initialized meson 1.0.0 20161109 for d0100000.vpu on minor 0
[    3.015364] [drm] Cannot find any crtc or sizes
[    3.020332] libphy: mdio_mux: probed
[    3.023354] [drm] Cannot find any crtc or sizes
[    3.028053] libphy: mdio_mux: probed
[    3.031796] phy phy-d0078080.phy.2: unsupported PHY mode 5
[    3.038831] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.042157] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    3.050742] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010
[    3.059178] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0xc9000000
[    3.065825] hub 1-0:1.0: USB hub found
[    3.068744] hub 1-0:1.0: 2 ports detected
[    3.072919] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.078126] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[    3.085667] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed
[    3.092250] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    3.100723] hub 2-0:1.0: USB hub found
[    3.104124] mmc0: new high speed SDHC card at address 1234
[    3.109604] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
[    3.117068] mmcblk0: mmc0:1234 SA32G 28.9 GiB 
[    3.122175] input: adc-keys as /devices/platform/adc-keys/input/input4
[    3.128691] meson-gx-mmc d0070000.mmc: allocated mmc-pwrseq
[    3.160142] scpi_protocol scpi: SCP Protocol legacy pre-1.0 firmware
domain-0 init dvfs: 4
[    3.169177] cpu cpu0: failed to add opp 100000000Hz 910mV
[    3.169336] cpu cpu0: failed to add opps to the device
[    3.172105] print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
[    3.174274] cpu cpu1: failed to add opp 100000000Hz 910mV
[    3.180529] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[    3.185895] cpu cpu1: failed to add opps to the device
[    3.198196] cpu cpu2: failed to add opp 100000000Hz 910mV
[    3.201761] print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
[    3.203411] cpu cpu2: failed to add opps to the device
[    3.209752] Buffer I/O error on dev mmcblk0, logical block 0, async page read
[    3.214919] cpu cpu3: failed to add opp 100000000Hz 910mV
[    3.227294]  mmcblk0: unable to read partition table
[    3.232761] cpu cpu3: failed to add opps to the device
[    3.239142] hctosys: unable to open rtc device (rtc0)
[    3.242432] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    3.251750] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    3.256578] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    3.264973] cfg80211: failed to load regulatory.db
[    3.265295] VCC_3V3: disabling
[    3.272759] ALSA device list:
[    3.275678]   No soundcards found.
[    3.284692] Waiting 2 sec before mounting root device...
[    3.285790] mmc2: queuing unknown CIS tuple 0x80 (2 bytes)
[    3.291864] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.297303] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.304384] mmc2: queuing unknown CIS tuple 0x80 (7 bytes)
[    3.316407] random: fast init done
[    3.381083] mmc2: new high speed SDIO card at address 0001
[    3.382026] brcmfmac: brcmf_chip_recognition: chip backplane type 15 is not supported
[    3.388704] brcmfmac: brcmf_sdio_probe_attach: brcmf_chip_attach failed!
[    3.395339] brcmfmac: brcmf_sdio_probe: brcmf_sdio_probe_attach failed
[    3.401879] brcmfmac: brcmf_ops_sdio_probe: F2 error, probe failed -19...
[    3.470256] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[    3.555122] random: crng init done
[    3.668466] hub 1-1:1.0: USB hub found
[    3.668532] hub 1-1:1.0: 4 ports detected
[    4.862276] Bluetooth: hci0: command 0x1001 tx timeout
[    5.310447] VFS: Cannot open root device "mmcblk0p2" or unknown-block(179,2): error -6
[    5.312704] Please append a correct "root=" boot option; here are the available partitions:
[    5.321015] b300        30318592 mmcblk0 
[    5.321018]  driver: mmcblk
[    5.327718] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)
[    5.336080] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.1.0-rc5+ #504
[    5.342459] Hardware name: Khadas VIM (DT)
[    5.346513] Call trace:
[    5.348939]  dump_backtrace+0x0/0x130
[    5.352553]  show_stack+0x14/0x20
[    5.355833]  dump_stack+0xac/0xd4
[    5.359110]  panic+0x148/0x2d0
[    5.362128]  mount_block_root+0x1bc/0x26c
[    5.366092]  mount_root+0x11c/0x148
[    5.369543]  prepare_namespace+0x128/0x16c
[    5.373597]  kernel_init_freeable+0x1b8/0x1d4
[    5.377910]  kernel_init+0x10/0xfc
[    5.381274]  ret_from_fork+0x10/0x1c
[    5.384813] SMP: stopping secondary CPUs
[    5.388694] Kernel Offset: disabled
[    5.392141] CPU features: 0x002,20002004
[    5.396020] Memory Limit: none
[    5.399045] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2) ]---

[-- Attachment #3: kvin-working.txt --]
[-- Type: text/plain, Size: 20594 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.1.0-rc5+ (xdarklight@blackbox) (gcc version 8.3.0 (GCC)) #507 SMP PREEMPT Thu Apr 18 22:11:29 CEST 2019
[    0.000000] Machine model: Khadas VIM
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000068000000, size 256 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv0.2 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] random: get_random_bytes called from start_kernel+0x9c/0x444 with crng_init=0
[    0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s55576 r8192 d30440 u94208
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 478528
[    0.000000] Kernel command line: console=ttyAML0,115200 root=/dev/mmcblk0p2 rootwait=1 rootdelay=2 init=/usr/bin/init rw
[    0.000000] printk: log_buf_len individual max cpu contribution: 4096 bytes
[    0.000000] printk: log_buf_len total cpu_extra contributions: 12288 bytes
[    0.000000] printk: log_buf_len min size: 16384 bytes
[    0.000000] printk: log_buf_len: 32768 bytes
[    0.000000] printk: early log buf free: 14580(88%)
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.000000] Memory: 1621808K/1944576K available (12284K kernel code, 876K rwdata, 4272K rodata, 640K init, 320K bss, 60624K reserved, 262144K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
[    0.000000]  Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq_meson_gpio: 110 to 8 gpio interrupt mux initialized
[    0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000003] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.000357] Console: colour dummy device 80x25
[    0.000388] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[    0.000396] pid_max: default: 32768 minimum: 301
[    0.000465] LSM: Security Framework initializing
[    0.000529] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000542] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000880] *** VALIDATE proc ***
[    0.000989] *** VALIDATE cgroup1 ***
[    0.000996] *** VALIDATE cgroup2 ***
[    0.024003] ASID allocator initialised with 32768 entries
[    0.031992] rcu: Hierarchical SRCU implementation.
[    0.040350] EFI services will not be available.
[    0.052036] smp: Bringing up secondary CPUs ...
[    0.084245] Detected VIPT I-cache on CPU1
[    0.084293] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.116276] Detected VIPT I-cache on CPU2
[    0.116317] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.148324] Detected VIPT I-cache on CPU3
[    0.148364] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.148432] smp: Brought up 1 node, 4 CPUs
[    0.148449] SMP: Total of 4 processors activated.
[    0.148455] CPU features: detected: 32-bit EL0 Support
[    0.148461] CPU features: detected: CRC32 instructions
[    0.148763] CPU: All CPU(s) started at EL2
[    0.148778] alternatives: patching kernel code
[    0.149518] devtmpfs: initialized
[    0.153673] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.153691] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.160549] xor: measuring software checksum speed
[    0.200279]    8regs     :  2375.000 MB/sec
[    0.240307]    32regs    :  2725.000 MB/sec
[    0.280338]    arm64_neon:  2374.000 MB/sec
[    0.280342] xor: using function: 32regs (2725.000 MB/sec)
[    0.280401] pinctrl core: initialized pinctrl subsystem
[    0.281326] DMI not present or invalid.
[    0.281599] NET: Registered protocol family 16
[    0.281989] audit: initializing netlink subsys (disabled)
[    0.282130] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
[    0.282995] cpuidle: using governor menu
[    0.283243] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.283252] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.284267] DMA: preallocated 256 KiB pool for atomic allocations
[    0.284428] Serial: AMBA PL011 UART driver
[    0.303157] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.303169] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.303174] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.303179] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.303536] cryptd: max_cpu_qlen set to 1000
[    0.368579] raid6: neonx8   gen()  1600 MB/s
[    0.436675] raid6: neonx8   xor()  1474 MB/s
[    0.504732] raid6: neonx4   gen()  1559 MB/s
[    0.572737] raid6: neonx4   xor()  1445 MB/s
[    0.640837] raid6: neonx2   gen()  1175 MB/s
[    0.708865] raid6: neonx2   xor()  1148 MB/s
[    0.776926] raid6: neonx1   gen()   760 MB/s
[    0.844969] raid6: neonx1   xor()   771 MB/s
[    0.913013] raid6: int64x8  gen()  1194 MB/s
[    0.981050] raid6: int64x8  xor()   765 MB/s
[    1.049137] raid6: int64x4  gen()  1011 MB/s
[    1.117164] raid6: int64x4  xor()   727 MB/s
[    1.185260] raid6: int64x2  gen()   711 MB/s
[    1.253253] raid6: int64x2  xor()   554 MB/s
[    1.321331] raid6: int64x1  gen()   465 MB/s
[    1.389340] raid6: int64x1  xor()   381 MB/s
[    1.389345] raid6: using algorithm neonx8 gen() 1600 MB/s
[    1.389349] raid6: .... xor() 1474 MB/s, rmw enabled
[    1.389354] raid6: using neon recovery algorithm
[    1.389578] ACPI: Interpreter disabled.
[    1.390980] vgaarb: loaded
[    1.391231] SCSI subsystem initialized
[    1.391696] usbcore: registered new interface driver usbfs
[    1.391742] usbcore: registered new interface driver hub
[    1.391823] usbcore: registered new device driver usb
[    1.392316] media: Linux media interface: v0.10
[    1.392349] videodev: Linux video capture interface: v2.00
[    1.392502] pps_core: LinuxPPS API ver. 1 registered
[    1.392510] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.392530] PTP clock support registered
[    1.392840] Advanced Linux Sound Architecture Driver Initialized.
[    1.393213] Bluetooth: Core ver 2.22
[    1.393273] NET: Registered protocol family 31
[    1.393278] Bluetooth: HCI device and connection manager initialized
[    1.393292] Bluetooth: HCI socket layer initialized
[    1.393298] Bluetooth: L2CAP socket layer initialized
[    1.393311] Bluetooth: SCO socket layer initialized
[    1.393824] clocksource: Switched to clocksource arch_sys_counter
[    1.393962] VFS: Disk quotas dquot_6.6.0
[    1.394011] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.394047] *** VALIDATE hugetlbfs ***
[    1.394197] pnp: PnP ACPI: disabled
[    1.399936] NET: Registered protocol family 2
[    1.400322] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes)
[    1.400350] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[    1.400458] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[    1.400656] TCP: Hash tables configured (established 16384 bind 16384)
[    1.400764] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    1.400807] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    1.400951] NET: Registered protocol family 1
[    1.401296] RPC: Registered named UNIX socket transport module.
[    1.401302] RPC: Registered udp transport module.
[    1.401307] RPC: Registered tcp transport module.
[    1.401310] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.402436] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
[    1.402758] kvm [1]: IPA Size Limit: 40bits
[    1.403224] kvm [1]: vgic interrupt IRQ1
[    1.403310] kvm [1]: Hyp mode initialized successfully
[    1.411956] Initialise system trusted keyrings
[    1.412097] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    1.418104] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.418716] NFS: Registering the id_resolver key type
[    1.418741] Key type id_resolver registered
[    1.418745] Key type id_legacy registered
[    1.418922] fuse init (API version 7.29)
[    1.419305] 9p: Installing v9fs 9p2000 file system support
[    1.425769] Key type asymmetric registered
[    1.425781] Asymmetric key parser 'x509' registered
[    1.425799] io scheduler mq-deadline registered
[    1.425804] io scheduler kyber registered
[    1.426205] io scheduler bfq registered
[    1.444199] soc soc0: Amlogic Meson GXL (S905X) Revision 21:a (82:2) Detected
[    1.447783] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.450027] c11084c0.serial: ttyAML1 at MMIO 0xc11084c0 (irq = 10, base_baud = 1500000) is a meson_uart
[    1.450202] serial serial0: tty port ttyAML1 registered
[    1.450495] c81004c0.serial: ttyAML0 at MMIO 0xc81004c0 (irq = 15, base_baud = 1500000) is a meson_uart
[    2.320981] printk: console [ttyAML0] enabled
[    2.325864] c81004e0.serial: ttyAML2 at MMIO 0xc81004e0 (irq = 16, base_baud = 1500000) is a meson_uart
[    2.342744] loop: module loaded
[    2.344917] libphy: Fixed MDIO Bus: probed
[    2.345684] tun: Universal TUN/TAP device driver, 1.6
[    2.349876] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[    2.355104] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    2.361012] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k
[    2.367869] igb: Copyright (c) 2007-2014 Intel Corporation.
[    2.373425] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[    2.381149] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    2.387050] sky2: driver version 1.30
[    2.391379] meson8b-dwmac c9410000.ethernet: PTP uses main clock
[    2.396604] meson8b-dwmac c9410000.ethernet: no reset control found
[    2.403236] meson8b-dwmac c9410000.ethernet: User ID: 0x11, Synopsys ID: 0x37
[    2.409886] meson8b-dwmac c9410000.ethernet:         DWMAC1000
[    2.415053] meson8b-dwmac c9410000.ethernet: DMA HW capability register supported
[    2.422462] meson8b-dwmac c9410000.ethernet: RX Checksum Offload Engine supported
[    2.429879] meson8b-dwmac c9410000.ethernet: COE Type 2
[    2.435053] meson8b-dwmac c9410000.ethernet: TX Checksum insertion supported
[    2.442040] meson8b-dwmac c9410000.ethernet: Wake-Up On Lan supported
[    2.448451] meson8b-dwmac c9410000.ethernet: Normal descriptors
[    2.454289] meson8b-dwmac c9410000.ethernet: Ring mode enabled
[    2.460067] meson8b-dwmac c9410000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.468129] libphy: stmmac: probed
[    2.472676] VFIO - User Level meta-driver version: 0.3
[    2.477731] dwc3 c9000000.dwc3: Failed to get clk 'ref': -2
[    2.483802] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.488464] ehci-pci: EHCI PCI platform driver
[    2.492906] ehci-platform: EHCI generic platform driver
[    2.498263] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[    2.504163] ohci-pci: OHCI PCI platform driver
[    2.508608] ohci-platform: OHCI generic platform driver
[    2.514512] usbcore: registered new interface driver usb-storage
[    2.521222] mousedev: PS/2 mouse device common for all mice
[    2.525971] input: gpio-keys-polled as /devices/platform/gpio-keys-polled/input/input0
[    2.533951] i2c /dev entries driver
[    2.538072] IR NEC protocol handler initialized
[    2.540965] IR RC5(x/sz) protocol handler initialized
[    2.545982] IR RC6 protocol handler initialized
[    2.550455] IR JVC protocol handler initialized
[    2.554940] IR Sony protocol handler initialized
[    2.559511] IR SANYO protocol handler initialized
[    2.564168] IR Sharp protocol handler initialized
[    2.568826] IR MCE Keyboard/mouse protocol handler initialized
[    2.574605] IR XMP protocol handler initialized
[    2.579421] Registered IR keymap rc-geekbox
[    2.583323] rc rc0: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0
[    2.591107] input: meson-ir as /devices/platform/soc/c8100000.bus/c8100580.ir/rc/rc0/input1
[    2.599506] rc rc0: lirc_dev: driver meson-ir registered at minor = 0, raw IR receiver, no transmitter
[    2.608621] meson-ir c8100580.ir: receiver initialized
[    2.614973] Registered IR keymap rc-cec
[    2.617514] rc rc1: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1
[    2.625880] input: meson_ao_cec as /devices/platform/soc/c8100000.bus/c8100100.cec/rc/rc1/input2
[    2.634892] usbcore: registered new interface driver dvb_usb_rtl28xxu
[    2.642439] Bluetooth: HCI UART driver ver 2.3
[    2.645070] Bluetooth: HCI UART protocol H4 registered
[    2.650176] Bluetooth: HCI UART protocol BCSP registered
[    2.655494] Bluetooth: HCI UART protocol LL registered
[    2.660516] Bluetooth: HCI UART protocol ATH3K registered
[    2.665884] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.672204] Bluetooth: HCI UART protocol Intel registered
[    2.677562] Bluetooth: HCI UART protocol Broadcom registered
[    2.677745] hci_uart_bcm serial0-0: serial0-0 supply vbat not found, using dummy regulator
[    2.683086] Bluetooth: HCI UART protocol QCA registered
[    2.691327] hci_uart_bcm serial0-0: serial0-0 supply vddio not found, using dummy regulator
[    2.696391] Bluetooth: HCI UART protocol AG6XX registered
[    2.696466] usbcore: registered new interface driver bcm203x
[    2.715627] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.722060] sdhci: Secure Digital Host Controller Interface driver
[    2.727369] sdhci: Copyright(c) Pierre Ossman
[    2.731707] Synopsys Designware Multimedia Card Interface Driver
[    2.739200] meson-gx-mmc d0072000.mmc: Got CD GPIO
[    2.769627] meson-gx-mmc d0074000.mmc: allocated mmc-pwrseq
[    2.794677] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.795807] ledtrig-cpu: registered to indicate activity on CPUs
[    2.802003] meson-sm: secure-monitor enabled
[    2.806268] usbcore: registered new interface driver usbhid
[    2.810601] usbhid: USB HID core driver
[    2.814798] platform-mhu c883c404.mailbox: Platform MHU Mailbox registered
[BL31]: tee size: 0
[    2.825356] gnss: GNSS driver registered with major 240
[    2.828398] mmc0: new high speed SDHC card at address 1234
[    2.831490] NET: Registered protocol family 17
[    2.834753] mmcblk0: mmc0:1234 SA32G 28.9 GiB 
[    2.838138] Bluetooth: RFCOMM TTY layer initialized
[    2.847268] Bluetooth: RFCOMM socket layer initialized
[    2.852174] Bluetooth: RFCOMM ver 1.11
[    2.853068]  mmcblk0: p1 p2
[    2.855863] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.863876] Bluetooth: BNEP filters: protocol multicast
[    2.869060] Bluetooth: BNEP socket layer initialized
[    2.873965] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.879829] Bluetooth: HIDP socket layer initialized
[    2.885075] 9pnet: Installing 9P2000 support
[    2.889033] Key type dns_resolver registered
[    2.893892] registered taskstats version 1
[    2.897246] Loading compiled-in X.509 certificates
[    2.902933] Btrfs loaded, crc32c=crc32c-generic
[    2.917756] meson-drm d0100000.vpu: Queued 2 outputs on vpu
[    2.918151] meson-drm d0100000.vpu: Falling back to parsing the 'hhi' registers
[    2.925071] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.931494] [drm] No driver support for vblank timestamp query.
[    2.937441] meson-drm d0100000.vpu: CVBS Output connector not available
[    2.969879] meson-dw-hdmi c883a000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
[    2.974639] meson-dw-hdmi c883a000.hdmi-tx: registered DesignWare HDMI I2C bus driver
[    2.982594] Registered IR keymap rc-cec
[    2.985707] rc rc2: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2
[    2.992729] input: dw_hdmi as /devices/platform/soc/c883a000.hdmi-tx/rc/rc2/input3
[    3.000411] meson-drm d0100000.vpu: bound c883a000.hdmi-tx (ops meson_dw_hdmi_ops)
[    3.007958] [drm] Initialized meson 1.0.0 20161109 for d0100000.vpu on minor 0
[    3.014796] [drm] Cannot find any crtc or sizes
[    3.019698] libphy: mdio_mux: probed
[    3.022865] [drm] Cannot find any crtc or sizes
[    3.027579] libphy: mdio_mux: probed
[    3.031088] phy phy-d0078080.phy.2: unsupported PHY mode 5
[    3.038256] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.041671] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[    3.049982] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228f664 hci version 0x100 quirks 0x0000000002010010
[    3.058619] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0xc9000000
[    3.065097] hub 1-0:1.0: USB hub found
[    3.068180] hub 1-0:1.0: 2 ports detected
[    3.072408] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[    3.077556] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[    3.085141] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed
[    3.091730] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    3.100202] hub 2-0:1.0: USB hub found
[    3.103457] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
[    3.111158] input: adc-keys as /devices/platform/adc-keys/input/input4
[    3.118353] meson-gx-mmc d0070000.mmc: allocated mmc-pwrseq
[    3.150018] scpi_protocol scpi: SCP Protocol legacy pre-1.0 firmware
domain-0 init dvfs: 4
[    3.159000] cpu cpu0: failed to add opp 100000000Hz 910mV
[    3.159028] cpu cpu0: failed to add opps to the device
[    3.163982] cpu cpu1: failed to add opp 100000000Hz 910mV
[    3.169292] cpu cpu1: failed to add opps to the device
[    3.174412] cpu cpu2: failed to add opp 100000000Hz 910mV
[    3.179725] cpu cpu2: failed to add opps to the device
[    3.184847] cpu cpu3: failed to add opp 100000000Hz 910mV
[    3.190165] cpu cpu3: failed to add opps to the device
[    3.198186] hctosys: unable to open rtc device (rtc0)
[    3.200302] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    3.204258] mmc2: queuing unknown CIS tuple 0x80 (2 bytes)
[    3.209374] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    3.215343] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.219849] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    3.227234] mmc2: queuing unknown CIS tuple 0x80 (3 bytes)
[    3.230088] ALSA device list:
[    3.230090]   No soundcards found.
[    3.233721] cfg80211: failed to load regulatory.db
[    3.242859] mmc2: queuing unknown CIS tuple 0x80 (7 bytes)
[    3.261368] Waiting 2 sec before mounting root device...
[    3.310098] random: fast init done
[    3.336037] mmc2: new high speed SDIO card at address 0001
[    3.339456] brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43455-sdio for chip BCM4345/6
[    3.344645] brcmfmac mmc2:0001:1: Direct firmware load for brcm/brcmfmac43455-sdio.bin failed with error -2
[    3.429844] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[    3.484280] random: crng init done
[    3.635931] hub 1-1:1.0: USB hub found
[    3.635995] hub 1-1:1.0: 4 ports detected
[    4.861843] Bluetooth: hci0: command 0x1001 tx timeout
[    5.389954] F2FS-fs (mmcblk0p2): Mounted with checkpoint version = 11f
[    5.390902] VFS: Mounted root (f2fs filesystem) on device 179:2.
[    5.398980] devtmpfs: mounted
[    5.399935] Freeing unused kernel memory: 640K
[    5.404197] Run /usr/bin/init as init process
[    5.915641] systemd[1]: System time before build time, advancing clock.

[-- Attachment #4: Type: text/plain, Size: 167 bytes --]

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Re: [PATCH 1/7] mmc: meson-gx: remove open coded read with timeout

[Martin Blumenstingl]

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> There is already a function available to poll a register until a
> condition is met. Let's use it instead of open coding it.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>

and on my Khadas VIM with patches 1-4 from this series applied:
Tested-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>

Re: [PATCH 1/7] mmc: meson-gx: remove open coded read with timeout

[Martin Blumenstingl]

On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> There is already a function available to poll a register until a
> condition is met. Let's use it instead of open coding it.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>

and on my Khadas VIM with patches 1-4 from this series applied:
Tested-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>

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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > Activating DDR in the Amlogic mmc controller, among other things, will
> > divide the output clock by 2. So by activating it with clock on, we are
> > creating a glitch on the output.
> > 
> > Instead, let's deal with DDR when the clock output is off, when setting
> > the clock.
> > 
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.

The error I see in your logs is with eMMC and hs200, not SD card.

Either way, There is something I don't really get. eMMC should not go through
any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
HS.

All this does is flipping the DDR bit (when necessary) when clock if off for
the mmc device, avoiding a glitch on clk line. 

This patch should not make any difference for SDR only setup, Maybe I missed
something, but I don't see how it could make anything different for SDR only.

I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
debug this. I'll need more detail to progress, something does not make sense here.

> I used git bisect within this series to find that issue.
> applying your .dts patches on top doesn't fix it
> 
> two boot logs attached:
> * kvim-broken.txt has patches 1-5 (= including this patch) applied
> * kvim-working.txt has only patches 1-4 (= excluding this patch) applied
> 
> 
> Regards
> Martin

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > Activating DDR in the Amlogic mmc controller, among other things, will
> > divide the output clock by 2. So by activating it with clock on, we are
> > creating a glitch on the output.
> > 
> > Instead, let's deal with DDR when the clock output is off, when setting
> > the clock.
> > 
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.

The error I see in your logs is with eMMC and hs200, not SD card.

Either way, There is something I don't really get. eMMC should not go through
any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
HS.

All this does is flipping the DDR bit (when necessary) when clock if off for
the mmc device, avoiding a glitch on clk line. 

This patch should not make any difference for SDR only setup, Maybe I missed
something, but I don't see how it could make anything different for SDR only.

I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
debug this. I'll need more detail to progress, something does not make sense here.

> I used git bisect within this series to find that issue.
> applying your .dts patches on top doesn't fix it
> 
> two boot logs attached:
> * kvim-broken.txt has patches 1-5 (= including this patch) applied
> * kvim-working.txt has only patches 1-4 (= excluding this patch) applied
> 
> 
> Regards
> Martin



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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

Hi Jerome,

On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > Hi Jerome,
> >
> > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > divide the output clock by 2. So by activating it with clock on, we are
> > > creating a glitch on the output.
> > >
> > > Instead, let's deal with DDR when the clock output is off, when setting
> > > the clock.
> > >
> > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
>
> The error I see in your logs is with eMMC and hs200, not SD card.
sorry, I should have been more clear that there are two errors:
eMMC, this is what I have been seeing for a while on my Khadas VIM2
(it's probably not related to this patch):
  mmc1: mmc_select_hs200 failed, error -84
  mmc1: error -84 whilst initialising MMC card

however, then there's this other error:
  print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
  Buffer I/O error on dev mmcblk0, logical block 0, async page read
as result of this the partition table cannot be read and my kernel
cannot find the rootfs.

> Either way, There is something I don't really get. eMMC should not go through
> any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
> HS.
>
> All this does is flipping the DDR bit (when necessary) when clock if off for
> the mmc device, avoiding a glitch on clk line.
>
> This patch should not make any difference for SDR only setup, Maybe I missed
> something, but I don't see how it could make anything different for SDR only.
>
> I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
> debug this. I'll need more detail to progress, something does not make sense here.
please let me know from which part of the driver do you want debug logs


Regards
Martin

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

Hi Jerome,

On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > Hi Jerome,
> >
> > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > divide the output clock by 2. So by activating it with clock on, we are
> > > creating a glitch on the output.
> > >
> > > Instead, let's deal with DDR when the clock output is off, when setting
> > > the clock.
> > >
> > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
>
> The error I see in your logs is with eMMC and hs200, not SD card.
sorry, I should have been more clear that there are two errors:
eMMC, this is what I have been seeing for a while on my Khadas VIM2
(it's probably not related to this patch):
  mmc1: mmc_select_hs200 failed, error -84
  mmc1: error -84 whilst initialising MMC card

however, then there's this other error:
  print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
  Buffer I/O error on dev mmcblk0, logical block 0, async page read
as result of this the partition table cannot be read and my kernel
cannot find the rootfs.

> Either way, There is something I don't really get. eMMC should not go through
> any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
> HS.
>
> All this does is flipping the DDR bit (when necessary) when clock if off for
> the mmc device, avoiding a glitch on clk line.
>
> This patch should not make any difference for SDR only setup, Maybe I missed
> something, but I don't see how it could make anything different for SDR only.
>
> I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
> debug this. I'll need more detail to progress, something does not make sense here.
please let me know from which part of the driver do you want debug logs


Regards
Martin

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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > > 
> > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > creating a glitch on the output.
> > > > 
> > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > the clock.
> > > > 
> > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > 
> > The error I see in your logs is with eMMC and hs200, not SD card.
> sorry, I should have been more clear that there are two errors:
> eMMC, this is what I have been seeing for a while on my Khadas VIM2
> (it's probably not related to this patch):
>   mmc1: mmc_select_hs200 failed, error -84
>   mmc1: error -84 whilst initialising MMC card

Following patches were also supposed to help the vim2. 
... something I tested numerous time on this particular board.

> 
> however, then there's this other error:
>   print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
>   Buffer I/O error on dev mmcblk0, logical block 0, async page read
> as result of this the partition table cannot be read and my kernel
> cannot find the rootfs.

I don't know what the problem is (probably some CRC error - you can check the log
in interrupt for this) but I'm pretty sure it is not related to this patch.

I see in the log SD is indeed in HS mode, so not in any DDR mode.
I also see that the SDIO fails as well. There something really weird, which can't
be explained by this patch alone AFAICT.

> 
> > Either way, There is something I don't really get. eMMC should not go through
> > any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
> > HS.
> > 
> > All this does is flipping the DDR bit (when necessary) when clock if off for
> > the mmc device, avoiding a glitch on clk line.
> > 
> > This patch should not make any difference for SDR only setup, Maybe I missed
> > something, but I don't see how it could make anything different for SDR only.
> > 
> > I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
> > debug this. I'll need more detail to progress, something does not make sense here.
> please let me know from which part of the driver do you want debug logs
> 
> 
> Regards
> Martin

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> Hi Jerome,
> 
> On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > > 
> > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > creating a glitch on the output.
> > > > 
> > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > the clock.
> > > > 
> > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > 
> > The error I see in your logs is with eMMC and hs200, not SD card.
> sorry, I should have been more clear that there are two errors:
> eMMC, this is what I have been seeing for a while on my Khadas VIM2
> (it's probably not related to this patch):
>   mmc1: mmc_select_hs200 failed, error -84
>   mmc1: error -84 whilst initialising MMC card

Following patches were also supposed to help the vim2. 
... something I tested numerous time on this particular board.

> 
> however, then there's this other error:
>   print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
>   Buffer I/O error on dev mmcblk0, logical block 0, async page read
> as result of this the partition table cannot be read and my kernel
> cannot find the rootfs.

I don't know what the problem is (probably some CRC error - you can check the log
in interrupt for this) but I'm pretty sure it is not related to this patch.

I see in the log SD is indeed in HS mode, so not in any DDR mode.
I also see that the SDIO fails as well. There something really weird, which can't
be explained by this patch alone AFAICT.

> 
> > Either way, There is something I don't really get. eMMC should not go through
> > any DDR mode to reach HS200 (which is an SDR mode), neither should SD to reach
> > HS.
> > 
> > All this does is flipping the DDR bit (when necessary) when clock if off for
> > the mmc device, avoiding a glitch on clk line.
> > 
> > This patch should not make any difference for SDR only setup, Maybe I missed
> > something, but I don't see how it could make anything different for SDR only.
> > 
> > I (repeatedly) tested both vim1 and vim2, without seeing this issue, so I can't
> > debug this. I'll need more detail to progress, something does not make sense here.
> please let me know from which part of the driver do you want debug logs
> 
> 
> Regards
> Martin



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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 23:15 +0200, Jerome Brunet wrote:
> On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> > Hi Jerome,
> > 
> > On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > > Hi Jerome,
> > > > 
> > > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > > creating a glitch on the output.
> > > > > 
> > > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > > the clock.
> > > > > 
> > > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > > 
> > > The error I see in your logs is with eMMC and hs200, not SD card.
> > sorry, I should have been more clear that there are two errors:
> > eMMC, this is what I have been seeing for a while on my Khadas VIM2
> > (it's probably not related to this patch):
> >    mmc1: mmc_select_hs200 failed, error -84
> >    mmc1: error -84 whilst initialising MMC card
> 
> Following patches were also supposed to help the vim2. 
> ... something I tested numerous time on this particular board.
> 
> > however, then there's this other error:
> >    print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
> >    Buffer I/O error on dev mmcblk0, logical block 0, async page read
> > as result of this the partition table cannot be read and my kernel
> > cannot find the rootfs.
> 
> I don't know what the problem is (probably some CRC error - you can check the log
> in interrupt for this) but I'm pretty sure it is not related to this patch.
> 
> I see in the log SD is indeed in HS mode, so not in any DDR mode.
> I also see that the SDIO fails as well. There something really weird, which can't
> be explained by this patch alone AFAICT.

Ok, I think I got it. It is indeed not linked to DDR, but a more trivial mistake.
It looks like a writel went AWOL during the final rebase (and after the test campaign).

in meson_mmc_set_ios, after:
val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);

Could you try adding
writel(val, host->regs + SD_EMMC_CFG);

Without this, the bus width is not changed, which explains why eMMC, SD and SDIO fail
on init.

Let me know if this helps.

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Jerome Brunet]

On Thu, 2019-04-18 at 23:15 +0200, Jerome Brunet wrote:
> On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> > Hi Jerome,
> > 
> > On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > > Hi Jerome,
> > > > 
> > > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > > creating a glitch on the output.
> > > > > 
> > > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > > the clock.
> > > > > 
> > > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > > 
> > > The error I see in your logs is with eMMC and hs200, not SD card.
> > sorry, I should have been more clear that there are two errors:
> > eMMC, this is what I have been seeing for a while on my Khadas VIM2
> > (it's probably not related to this patch):
> >    mmc1: mmc_select_hs200 failed, error -84
> >    mmc1: error -84 whilst initialising MMC card
> 
> Following patches were also supposed to help the vim2. 
> ... something I tested numerous time on this particular board.
> 
> > however, then there's this other error:
> >    print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
> >    Buffer I/O error on dev mmcblk0, logical block 0, async page read
> > as result of this the partition table cannot be read and my kernel
> > cannot find the rootfs.
> 
> I don't know what the problem is (probably some CRC error - you can check the log
> in interrupt for this) but I'm pretty sure it is not related to this patch.
> 
> I see in the log SD is indeed in HS mode, so not in any DDR mode.
> I also see that the SDIO fails as well. There something really weird, which can't
> be explained by this patch alone AFAICT.

Ok, I think I got it. It is indeed not linked to DDR, but a more trivial mistake.
It looks like a writel went AWOL during the final rebase (and after the test campaign).

in meson_mmc_set_ios, after:
val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);

Could you try adding
writel(val, host->regs + SD_EMMC_CFG);

Without this, the bus width is not changed, which explains why eMMC, SD and SDIO fail
on init.

Let me know if this helps.


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Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

Hi Jerome,

On Fri, Apr 19, 2019 at 10:53 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Thu, 2019-04-18 at 23:15 +0200, Jerome Brunet wrote:
> > On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > >
> > > On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > > > Hi Jerome,
> > > > >
> > > > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > > > creating a glitch on the output.
> > > > > >
> > > > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > > > the clock.
> > > > > >
> > > > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > > >
> > > > The error I see in your logs is with eMMC and hs200, not SD card.
> > > sorry, I should have been more clear that there are two errors:
> > > eMMC, this is what I have been seeing for a while on my Khadas VIM2
> > > (it's probably not related to this patch):
> > >    mmc1: mmc_select_hs200 failed, error -84
> > >    mmc1: error -84 whilst initialising MMC card
> >
> > Following patches were also supposed to help the vim2.
> > ... something I tested numerous time on this particular board.
> >
> > > however, then there's this other error:
> > >    print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
> > >    Buffer I/O error on dev mmcblk0, logical block 0, async page read
> > > as result of this the partition table cannot be read and my kernel
> > > cannot find the rootfs.
> >
> > I don't know what the problem is (probably some CRC error - you can check the log
> > in interrupt for this) but I'm pretty sure it is not related to this patch.
> >
> > I see in the log SD is indeed in HS mode, so not in any DDR mode.
> > I also see that the SDIO fails as well. There something really weird, which can't
> > be explained by this patch alone AFAICT.
>
> Ok, I think I got it. It is indeed not linked to DDR, but a more trivial mistake.
> It looks like a writel went AWOL during the final rebase (and after the test campaign).
>
> in meson_mmc_set_ios, after:
> val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
>
> Could you try adding
> writel(val, host->regs + SD_EMMC_CFG);
good catch!

> Without this, the bus width is not changed, which explains why eMMC, SD and SDIO fail
> on init.
I have added that missing writel on top of the whole series and now:
- SD card is detected again (same as without this series)
- SDIO wifi is detected again (same as without this series)
- eMMC is detected (was not working before)

I will give my Tested-by on v2 of these patches


Martin

Re: [PATCH 5/7] mmc: meson-gx: avoid clock glitch when switching to DDR modes

[Martin Blumenstingl]

Hi Jerome,

On Fri, Apr 19, 2019 at 10:53 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Thu, 2019-04-18 at 23:15 +0200, Jerome Brunet wrote:
> > On Thu, 2019-04-18 at 22:53 +0200, Martin Blumenstingl wrote:
> > > Hi Jerome,
> > >
> > > On Thu, Apr 18, 2019 at 10:46 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > On Thu, 2019-04-18 at 22:16 +0200, Martin Blumenstingl wrote:
> > > > > Hi Jerome,
> > > > >
> > > > > On Wed, Apr 17, 2019 at 10:44 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> > > > > > Activating DDR in the Amlogic mmc controller, among other things, will
> > > > > > divide the output clock by 2. So by activating it with clock on, we are
> > > > > > creating a glitch on the output.
> > > > > >
> > > > > > Instead, let's deal with DDR when the clock output is off, when setting
> > > > > > the clock.
> > > > > >
> > > > > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > > > > it seems that this patch breaks SD card on my Khadas VIM and Khadas VIM2.
> > > >
> > > > The error I see in your logs is with eMMC and hs200, not SD card.
> > > sorry, I should have been more clear that there are two errors:
> > > eMMC, this is what I have been seeing for a while on my Khadas VIM2
> > > (it's probably not related to this patch):
> > >    mmc1: mmc_select_hs200 failed, error -84
> > >    mmc1: error -84 whilst initialising MMC card
> >
> > Following patches were also supposed to help the vim2.
> > ... something I tested numerous time on this particular board.
> >
> > > however, then there's this other error:
> > >    print_req_error: I/O error, dev mmcblk0, sector 0 flags 0
> > >    Buffer I/O error on dev mmcblk0, logical block 0, async page read
> > > as result of this the partition table cannot be read and my kernel
> > > cannot find the rootfs.
> >
> > I don't know what the problem is (probably some CRC error - you can check the log
> > in interrupt for this) but I'm pretty sure it is not related to this patch.
> >
> > I see in the log SD is indeed in HS mode, so not in any DDR mode.
> > I also see that the SDIO fails as well. There something really weird, which can't
> > be explained by this patch alone AFAICT.
>
> Ok, I think I got it. It is indeed not linked to DDR, but a more trivial mistake.
> It looks like a writel went AWOL during the final rebase (and after the test campaign).
>
> in meson_mmc_set_ios, after:
> val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
>
> Could you try adding
> writel(val, host->regs + SD_EMMC_CFG);
good catch!

> Without this, the bus width is not changed, which explains why eMMC, SD and SDIO fail
> on init.
I have added that missing writel on top of the whole series and now:
- SD card is detected again (same as without this series)
- SDIO wifi is detected again (same as without this series)
- eMMC is detected (was not working before)

I will give my Tested-by on v2 of these patches


Martin

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