* [RFC 0/8] Start some re-org around IRQ.
@ 2019-04-18 20:53 Rodrigo Vivi
2019-04-18 20:53 ` [RFC 1/8] drm/i915: Introduce intel_irq Rodrigo Vivi
` (10 more replies)
0 siblings, 11 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
When playing with IRQ code here I noticed many IRQ stuff
are spreaded all around our code. So I'm starting the
organization by consolidating as much as possible on a
new intel_irq.
So we could use this intel_irq to pass around as argument
instead of dev_priv, i915 or uncore.
So, besides starting that change we need to continue
working towards the conversion of intel_uncore_*().
Another possibilities to exploer after that is to fully
split rps and hotplug code out of irq.
Latest but not least it may be possible to split gt_irq
from de_irq later.
But well, for now please give feed back on intel_irq
struct idea.
Thanks,
Rodrigo.
Rodrigo Vivi (8):
drm/i915: Introduce intel_irq
drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
drm/i915: Move display_irqs_enabled to intel_irq
drm/i915: Consolidated iir, imr and ier.
drm/i915: Move all irq related masks to intel_irq
drm/i915: Prefer passing intel_irq instead of intel_core
drm/i915: Start the conversion from passing intel_irq instead of
dev_priv/i915
drm/i915: Migrate more gen11 irq functions towards intel_irq and
uncore funcs.
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 39 +-
drivers/gpu/drm/i915/i915_irq.c | 642 +++++++++++----------
drivers/gpu/drm/i915/intel_breadcrumbs.c | 8 +-
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 30 +-
drivers/gpu/drm/i915/intel_hotplug.c | 48 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
drivers/gpu/drm/i915/intel_tv.c | 8 +-
13 files changed, 417 insertions(+), 404 deletions(-)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFC 1/8] drm/i915: Introduce intel_irq
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq Rodrigo Vivi
` (9 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Let's start the re-org of irqs with the introduction of intel_irq
structure.
Since irq_lock is used everywhere let's start intel_irq with
this lock first.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_irq.c | 182 ++++++++++-----------
drivers/gpu/drm/i915/intel_breadcrumbs.c | 8 +-
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 30 ++--
drivers/gpu/drm/i915/intel_hotplug.c | 38 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
drivers/gpu/drm/i915/intel_tv.c | 8 +-
12 files changed, 155 insertions(+), 151 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..e2fd3250760e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4336,12 +4336,12 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
else
DRM_DEBUG_KMS("Disabling HPD storm detection\n");
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
hotplug->hpd_storm_threshold = new_threshold;
/* Reset the HPD storm stats so we don't accidentally trigger a storm */
for_each_hpd_pin(i)
hotplug->stats[i].count = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/* Re-enable hpd immediately if we were in an irq storm */
flush_delayed_work(&dev_priv->hotplug.reenable_work);
@@ -4414,12 +4414,12 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
DRM_DEBUG_KMS("%sabling HPD short storm detection\n",
new_state ? "En" : "Dis");
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
hotplug->hpd_short_storm_enabled = new_state;
/* Reset the HPD storm stats so we don't accidentally trigger a storm */
for_each_hpd_pin(i)
hotplug->stats[i].count = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/* Re-enable hpd immediately if we were in an irq storm */
flush_delayed_work(&dev_priv->hotplug.reenable_work);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ad88e6d7c04..fe5c2138a725 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -879,7 +879,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
intel_uncore_init_early(&dev_priv->uncore);
- spin_lock_init(&dev_priv->irq_lock);
+ spin_lock_init(&dev_priv->irq.lock);
spin_lock_init(&dev_priv->gpu_error.lock);
mutex_init(&dev_priv->backlight_lock);
@@ -2219,10 +2219,10 @@ static int i915_drm_resume(struct drm_device *dev)
intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
intel_dp_mst_resume(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 066fd2a12851..0b4aa818d66b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -647,10 +647,15 @@ struct intel_rps_ei {
u32 media_c0;
};
+struct intel_irq {
+ /* protects the irq masks */
+ spinlock_t lock;
+};
+
struct intel_rps {
/*
* work, interrupts_enabled and pm_iir are protected by
- * dev_priv->irq_lock
+ * dev_priv->irq.lock
*/
struct work_struct work;
bool interrupts_enabled;
@@ -1551,8 +1556,7 @@ struct drm_i915_private {
struct resource mch_res;
- /* protects the irq masks */
- spinlock_t irq_lock;
+ struct intel_irq irq;
bool display_irqs_enabled;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b92cfd69134b..679dc63244d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -262,7 +262,7 @@ i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
{
u32 val;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(bits & ~mask);
val = I915_READ(PORT_HOTPLUG_EN);
@@ -287,9 +287,9 @@ void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
u32 mask,
u32 bits)
{
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
static u32
@@ -303,7 +303,7 @@ static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
void __iomem * const regs = i915->uncore.regs;
u32 dw;
- lockdep_assert_held(&i915->irq_lock);
+ lockdep_assert_held(&i915->irq.lock);
dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
if (dw & BIT(bit)) {
@@ -339,7 +339,7 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
{
u32 new_val;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(enabled_irq_mask & ~interrupt_mask);
@@ -367,7 +367,7 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
u32 interrupt_mask,
u32 enabled_irq_mask)
{
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(enabled_irq_mask & ~interrupt_mask);
@@ -448,7 +448,7 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
WARN_ON(enabled_irq_mask & ~interrupt_mask);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
new_val = dev_priv->pm_imr;
new_val &= ~interrupt_mask;
@@ -485,7 +485,7 @@ static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
{
i915_reg_t reg = gen6_pm_iir(dev_priv);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
I915_WRITE(reg, reset_mask);
I915_WRITE(reg, reset_mask);
@@ -494,7 +494,7 @@ static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
{
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
dev_priv->pm_ier |= enable_mask;
write_pm_ier(dev_priv);
@@ -504,7 +504,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
{
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
dev_priv->pm_ier &= ~disable_mask;
__gen6_mask_pm_irq(dev_priv, disable_mask);
@@ -514,22 +514,22 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
;
dev_priv->gt_pm.rps.pm_iir = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
dev_priv->gt_pm.rps.pm_iir = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
@@ -539,7 +539,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
if (READ_ONCE(rps->interrupts_enabled))
return;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
WARN_ON_ONCE(rps->pm_iir);
if (INTEL_GEN(dev_priv) >= 11)
@@ -550,7 +550,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
rps->interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
@@ -560,14 +560,14 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
if (!READ_ONCE(rps->interrupts_enabled))
return;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
rps->interrupts_enabled = false;
I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
synchronize_irq(dev_priv->drm.irq);
/* Now that we will not be generating any more work, flush any
@@ -586,35 +586,35 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
dev_priv->guc.interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
dev_priv->guc.interrupts_enabled = false;
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
synchronize_irq(dev_priv->drm.irq);
gen9_reset_guc_interrupts(dev_priv);
@@ -633,7 +633,7 @@ static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
u32 new_val;
u32 old_val;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(enabled_irq_mask & ~interrupt_mask);
@@ -666,7 +666,7 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
{
u32 new_val;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(enabled_irq_mask & ~interrupt_mask);
@@ -700,7 +700,7 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
WARN_ON(enabled_irq_mask & ~interrupt_mask);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
@@ -715,7 +715,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
u32 enable_mask = status_mask << 16;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if (INTEL_GEN(dev_priv) < 5)
goto out;
@@ -760,7 +760,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
"pipe %c: status_mask=0x%x\n",
pipe_name(pipe), status_mask);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(!intel_irqs_enabled(dev_priv));
if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
@@ -783,7 +783,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
"pipe %c: status_mask=0x%x\n",
pipe_name(pipe), status_mask);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(!intel_irqs_enabled(dev_priv));
if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
@@ -813,14 +813,14 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
if (!i915_has_asle(dev_priv))
return;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
if (INTEL_GEN(dev_priv) >= 4)
i915_enable_pipestat(dev_priv, PIPE_A,
PIPE_LEGACY_BLC_EVENT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
/*
@@ -1289,12 +1289,12 @@ static void gen6_pm_rps_work(struct work_struct *work)
int new_delay, adj, min, max;
u32 pm_iir = 0;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (rps->interrupts_enabled) {
pm_iir = fetch_and_zero(&rps->pm_iir);
client_boost = atomic_read(&rps->num_waiters);
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/* Make sure we didn't queue anything we're not going to process. */
WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
@@ -1371,10 +1371,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
out:
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (rps->interrupts_enabled)
gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -1452,9 +1452,9 @@ static void ivybridge_parity_work(struct work_struct *work)
out:
WARN_ON(dev_priv->l3_parity.which_slice);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
@@ -1465,9 +1465,9 @@ static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv
if (!HAS_L3_DPF(dev_priv))
return;
- spin_lock(&dev_priv->irq_lock);
+ spin_lock(&dev_priv->irq.lock);
gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
- spin_unlock(&dev_priv->irq_lock);
+ spin_unlock(&dev_priv->irq.lock);
iir &= GT_PARITY_ERROR(dev_priv);
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
@@ -1845,7 +1845,7 @@ static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
struct intel_rps *rps = &i915->gt_pm.rps;
const u32 events = i915->pm_rps_events & pm_iir;
- lockdep_assert_held(&i915->irq_lock);
+ lockdep_assert_held(&i915->irq.lock);
if (unlikely(!events))
return;
@@ -1864,13 +1864,13 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
if (pm_iir & dev_priv->pm_rps_events) {
- spin_lock(&dev_priv->irq_lock);
+ spin_lock(&dev_priv->irq.lock);
gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
if (rps->interrupts_enabled) {
rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
schedule_work(&rps->work);
}
- spin_unlock(&dev_priv->irq_lock);
+ spin_unlock(&dev_priv->irq.lock);
}
if (INTEL_GEN(dev_priv) >= 8)
@@ -1907,10 +1907,10 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
{
int pipe;
- spin_lock(&dev_priv->irq_lock);
+ spin_lock(&dev_priv->irq.lock);
if (!dev_priv->display_irqs_enabled) {
- spin_unlock(&dev_priv->irq_lock);
+ spin_unlock(&dev_priv->irq.lock);
return;
}
@@ -1964,7 +1964,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
I915_WRITE(reg, enable_mask);
}
}
- spin_unlock(&dev_priv->irq_lock);
+ spin_unlock(&dev_priv->irq.lock);
}
static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
@@ -2981,7 +2981,7 @@ gen11_gt_engine_identity(struct drm_i915_private * const i915,
u32 timeout_ts;
u32 ident;
- lockdep_assert_held(&i915->irq_lock);
+ lockdep_assert_held(&i915->irq.lock);
raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
@@ -3065,7 +3065,7 @@ gen11_gt_bank_handler(struct drm_i915_private * const i915,
unsigned long intr_dw;
unsigned int bit;
- lockdep_assert_held(&i915->irq_lock);
+ lockdep_assert_held(&i915->irq.lock);
intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
@@ -3085,14 +3085,14 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915,
{
unsigned int bank;
- spin_lock(&i915->irq_lock);
+ spin_lock(&i915->irq.lock);
for (bank = 0; bank < 2; bank++) {
if (master_ctl & GEN11_GT_DW_IRQ(bank))
gen11_gt_bank_handler(i915, bank);
}
- spin_unlock(&i915->irq_lock);
+ spin_unlock(&i915->irq.lock);
}
static u32
@@ -3185,9 +3185,9 @@ static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
return 0;
}
@@ -3207,10 +3207,10 @@ static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
return 0;
}
@@ -3222,9 +3222,9 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
u32 bit = INTEL_GEN(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
ilk_enable_display_irq(dev_priv, bit);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
/* Even though there is no DMC, frame counter can get stuck when
* PSR is active as no frames are generated.
@@ -3240,9 +3240,9 @@ static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
/* Even if there is no DMC, frame counter can get stuck when
* PSR is active as no frames are generated, so check only for PSR.
@@ -3261,9 +3261,9 @@ static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
}
static void i945gm_disable_vblank(struct drm_device *dev, unsigned int pipe)
@@ -3281,10 +3281,10 @@ static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
i915_disable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_STATUS);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
}
static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
@@ -3294,9 +3294,9 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
u32 bit = INTEL_GEN(dev_priv) >= 7 ?
DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
ilk_disable_display_irq(dev_priv, bit);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
}
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
@@ -3304,9 +3304,9 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ spin_lock_irqsave(&dev_priv->irq.lock, irqflags);
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
- spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, irqflags);
}
static void i945gm_vblank_work_func(struct work_struct *work)
@@ -3484,10 +3484,10 @@ static void valleyview_irq_reset(struct drm_device *dev)
gen5_gt_irq_reset(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
@@ -3581,10 +3581,10 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (!intel_irqs_enabled(dev_priv)) {
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
return;
}
@@ -3593,7 +3593,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
dev_priv->de_irq_mask[pipe],
~dev_priv->de_irq_mask[pipe] | extra_ier);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
@@ -3602,17 +3602,17 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
struct intel_uncore *uncore = &dev_priv->uncore;
enum pipe pipe;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (!intel_irqs_enabled(dev_priv)) {
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
return;
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/* make sure we're done processing display irqs */
synchronize_irq(dev_priv->drm.irq);
@@ -3630,10 +3630,10 @@ static void cherryview_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_reset(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
@@ -3995,9 +3995,9 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
* spinlocking not required here for correctness since interrupt
* setup is guaranteed to run in single-threaded context. But we
* need it to make the assert_spin_locked happy. */
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
return 0;
@@ -4005,7 +4005,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
return;
@@ -4020,7 +4020,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if (!dev_priv->display_irqs_enabled)
return;
@@ -4038,10 +4038,10 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
gen5_gt_irq_postinstall(dev);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_postinstall(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
POSTING_READ(VLV_MASTER_IER);
@@ -4241,10 +4241,10 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
gen8_gt_irq_postinstall(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
vlv_display_irq_postinstall(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
@@ -4287,10 +4287,10 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
return 0;
}
@@ -4465,10 +4465,10 @@ static int i915_irq_postinstall(struct drm_device *dev)
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
i915_enable_asle_pipestat(dev_priv);
@@ -4587,11 +4587,11 @@ static int i965_irq_postinstall(struct drm_device *dev)
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
i915_enable_asle_pipestat(dev_priv);
@@ -4602,7 +4602,7 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_en;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
/* Note HDMI and DP share hotplug bits */
/* enable bits are the same for all generations */
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 3cbffd400b1b..98a55f0a16eb 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -33,9 +33,9 @@ static void irq_enable(struct intel_engine_cs *engine)
return;
/* Caller disables interrupts */
- spin_lock(&engine->i915->irq_lock);
+ spin_lock(&engine->i915->irq.lock);
engine->irq_enable(engine);
- spin_unlock(&engine->i915->irq_lock);
+ spin_unlock(&engine->i915->irq.lock);
}
static void irq_disable(struct intel_engine_cs *engine)
@@ -44,9 +44,9 @@ static void irq_disable(struct intel_engine_cs *engine)
return;
/* Caller disables interrupts */
- spin_lock(&engine->i915->irq_lock);
+ spin_lock(&engine->i915->irq.lock);
engine->irq_disable(engine);
- spin_unlock(&engine->i915->irq_lock);
+ spin_unlock(&engine->i915->irq.lock);
}
static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3bd40a4a6739..7c8c179146a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3975,10 +3975,10 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
intel_modeset_init_hw(dev);
intel_init_clock_gating(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
ret = __intel_display_resume(dev, state, ctx);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a38b9cff5cd0..417dba7d0a06 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1099,7 +1099,7 @@ struct intel_crtc {
struct intel_crtc_state *config;
- /* Access to these should be protected by dev_priv->irq_lock. */
+ /* Access to these should be protected by dev_priv->irq.lock. */
bool cpu_fifo_underrun_disabled;
bool pch_fifo_underrun_disabled;
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h
index 1f970c76b6a6..599991a0067f 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -308,7 +308,7 @@ struct intel_engine_cs {
spinlock_t irq_lock;
struct list_head signalers;
- struct irq_work irq_work; /* for use from inside irq_lock */
+ struct irq_work irq_work; /* for use from inside irq.lock */
unsigned int irq_enabled;
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 74c8b0528294..3dd5c8453f20 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -55,7 +55,7 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
struct intel_crtc *crtc;
enum pipe pipe;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
for_each_pipe(dev_priv, pipe) {
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
@@ -73,7 +73,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
enum pipe pipe;
struct intel_crtc *crtc;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
for_each_pipe(dev_priv, pipe) {
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
@@ -91,7 +91,7 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
i915_reg_t reg = PIPESTAT(crtc->pipe);
u32 enable_mask;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
return;
@@ -111,7 +111,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t reg = PIPESTAT(pipe);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if (enable) {
u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
@@ -143,7 +143,7 @@ static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
enum pipe pipe = crtc->pipe;
u32 err_int = I915_READ(GEN7_ERR_INT);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
return;
@@ -209,7 +209,7 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
enum pipe pch_transcoder = crtc->pipe;
u32 serr_int = I915_READ(SERR_INT);
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
return;
@@ -254,7 +254,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
bool old;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
old = !crtc->cpu_fifo_underrun_disabled;
crtc->cpu_fifo_underrun_disabled = !enable;
@@ -293,10 +293,10 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
unsigned long flags;
bool ret;
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
+ spin_lock_irqsave(&dev_priv->irq.lock, flags);
ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
enable);
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, flags);
return ret;
}
@@ -333,7 +333,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
* crtc on LPT won't cause issues.
*/
- spin_lock_irqsave(&dev_priv->irq_lock, flags);
+ spin_lock_irqsave(&dev_priv->irq.lock, flags);
old = !crtc->pch_fifo_underrun_disabled;
crtc->pch_fifo_underrun_disabled = !enable;
@@ -347,7 +347,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
pch_transcoder,
enable, old);
- spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+ spin_unlock_irqrestore(&dev_priv->irq.lock, flags);
return old;
}
@@ -416,7 +416,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
for_each_intel_crtc(&dev_priv->drm, crtc) {
if (crtc->cpu_fifo_underrun_disabled)
@@ -428,7 +428,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
ivybridge_check_fifo_underruns(crtc);
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
/**
@@ -443,7 +443,7 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
{
struct intel_crtc *crtc;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
for_each_intel_crtc(&dev_priv->drm, crtc) {
if (crtc->pch_fifo_underrun_disabled)
@@ -453,5 +453,5 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
cpt_check_pch_fifo_underruns(crtc);
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index b8937c788f03..8260e81f88e7 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -184,7 +184,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
enum hpd_pin pin;
bool hpd_disabled = false;
- lockdep_assert_held(&dev_priv->irq_lock);
+ lockdep_assert_held(&dev_priv->irq.lock);
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
@@ -231,7 +231,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
wakeref = intel_runtime_pm_get(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
for_each_hpd_pin(pin) {
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
@@ -260,7 +260,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
}
if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
intel_runtime_pm_put(dev_priv, wakeref);
}
@@ -303,12 +303,12 @@ static void i915_digport_work_func(struct work_struct *work)
struct intel_encoder *encoder;
u32 old_bits = 0;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
long_port_mask = dev_priv->hotplug.long_port_mask;
dev_priv->hotplug.long_port_mask = 0;
short_port_mask = dev_priv->hotplug.short_port_mask;
dev_priv->hotplug.short_port_mask = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
for_each_intel_encoder(&dev_priv->drm, encoder) {
struct intel_digital_port *dig_port;
@@ -335,9 +335,9 @@ static void i915_digport_work_func(struct work_struct *work)
}
if (old_bits) {
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
dev_priv->hotplug.event_bits |= old_bits;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
schedule_work(&dev_priv->hotplug.hotplug_work);
}
}
@@ -360,7 +360,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
mutex_lock(&dev->mode_config.mutex);
DRM_DEBUG_KMS("running encoder hotplug functions\n");
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
hpd_event_bits = dev_priv->hotplug.event_bits;
dev_priv->hotplug.event_bits = 0;
@@ -368,7 +368,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
/* Enable polling for connectors which had HPD IRQ storms */
intel_hpd_irq_storm_switch_to_polling(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
@@ -421,7 +421,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!pin_mask)
return;
- spin_lock(&dev_priv->irq_lock);
+ spin_lock(&dev_priv->irq.lock);
/*
* Determine whether ->hpd_pulse() exists for each pin, and
@@ -504,7 +504,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
*/
if (storm_detected && dev_priv->display_irqs_enabled)
dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock(&dev_priv->irq_lock);
+ spin_unlock(&dev_priv->irq.lock);
/*
* Our hotplug handler can grab modeset locks (by calling down into the
@@ -549,10 +549,10 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
* just to make the assert_spin_locked checks happy.
*/
if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->display_irqs_enabled)
dev_priv->display.hpd_irq_setup(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
}
@@ -644,13 +644,13 @@ void intel_hpd_init_work(struct drm_i915_private *dev_priv)
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
dev_priv->hotplug.long_port_mask = 0;
dev_priv->hotplug.short_port_mask = 0;
dev_priv->hotplug.event_bits = 0;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
cancel_work_sync(&dev_priv->hotplug.dig_port_work);
cancel_work_sync(&dev_priv->hotplug.hotplug_work);
@@ -665,12 +665,12 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
if (pin == HPD_NONE)
return false;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
ret = true;
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
return ret;
}
@@ -680,7 +680,7 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
if (pin == HPD_NONE)
return;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d4f4262d0fee..5a2d7f2f799d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1335,9 +1335,9 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
vlv_init_display_clock_gating(dev_priv);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
valleyview_enable_display_irqs(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/*
* During driver initialization/resume we can avoid restoring the
@@ -1361,9 +1361,9 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
{
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
valleyview_disable_display_irqs(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
/* make sure we're done processing display irqs */
synchronize_irq(dev_priv->drm.irq);
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 5dbba33f4202..04081f029023 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1574,11 +1574,11 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
/* Disable TV interrupts around load detect or we'll recurse */
if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_disable_pipestat(dev_priv, 0,
PIPE_HOTPLUG_INTERRUPT_STATUS |
PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
save_tv_dac = tv_dac = I915_READ(TV_DAC);
@@ -1646,11 +1646,11 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
/* Restore interrupt config */
if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&dev_priv->irq.lock);
i915_enable_pipestat(dev_priv, 0,
PIPE_HOTPLUG_INTERRUPT_STATUS |
PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&dev_priv->irq.lock);
}
return type;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
2019-04-18 20:53 ` [RFC 1/8] drm/i915: Introduce intel_irq Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 21:15 ` Chris Wilson
2019-04-18 20:53 ` [RFC 3/8] drm/i915: Move display_irqs_enabled to intel_irq Rodrigo Vivi
` (8 subsequent siblings)
10 siblings, 1 reply; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
The plan is to consolidate all IRQ related stuff together
under the new intel_irq.
So let's continue with RPS stuff.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 ++-----
drivers/gpu/drm/i915/i915_irq.c | 41 ++++++++++++++++++---------------
2 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0b4aa818d66b..06617a67002c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -650,16 +650,12 @@ struct intel_rps_ei {
struct intel_irq {
/* protects the irq masks */
spinlock_t lock;
+ bool rps_interrupts_enabled;
+ u32 pm_iir;
};
struct intel_rps {
- /*
- * work, interrupts_enabled and pm_iir are protected by
- * dev_priv->irq.lock
- */
struct work_struct work;
- bool interrupts_enabled;
- u32 pm_iir;
/* PM interrupt bits that should never be masked */
u32 pm_intrmsk_mbz;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 679dc63244d9..487ea27ea152 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -519,7 +519,7 @@ void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
;
- dev_priv->gt_pm.rps.pm_iir = 0;
+ dev_priv->irq.pm_iir = 0;
spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -528,46 +528,47 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq.lock);
gen6_reset_pm_iir(dev_priv, GEN6_PM_RPS_EVENTS);
- dev_priv->gt_pm.rps.pm_iir = 0;
+ dev_priv->irq.pm_iir = 0;
spin_unlock_irq(&dev_priv->irq.lock);
}
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ struct intel_irq *irq = &dev_priv->irq;
- if (READ_ONCE(rps->interrupts_enabled))
+ if (READ_ONCE(irq->rps_interrupts_enabled))
return;
- spin_lock_irq(&dev_priv->irq.lock);
- WARN_ON_ONCE(rps->pm_iir);
+ spin_lock_irq(&irq->lock);
+ WARN_ON_ONCE(irq->pm_iir);
if (INTEL_GEN(dev_priv) >= 11)
WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
else
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
- rps->interrupts_enabled = true;
+ irq->rps_interrupts_enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
- spin_unlock_irq(&dev_priv->irq.lock);
+ spin_unlock_irq(&irq->lock);
}
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ struct intel_irq *irq = &dev_priv->irq;
- if (!READ_ONCE(rps->interrupts_enabled))
+ if (!READ_ONCE(irq->rps_interrupts_enabled))
return;
- spin_lock_irq(&dev_priv->irq.lock);
- rps->interrupts_enabled = false;
+ spin_lock_irq(&irq->lock);
+ irq->rps_interrupts_enabled = false;
I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
- spin_unlock_irq(&dev_priv->irq.lock);
+ spin_unlock_irq(&irq->lock);
synchronize_irq(dev_priv->drm.irq);
/* Now that we will not be generating any more work, flush any
@@ -1290,8 +1291,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
u32 pm_iir = 0;
spin_lock_irq(&dev_priv->irq.lock);
- if (rps->interrupts_enabled) {
- pm_iir = fetch_and_zero(&rps->pm_iir);
+ if (dev_priv->irq.rps_interrupts_enabled) {
+ pm_iir = fetch_and_zero(&dev_priv->irq.pm_iir);
client_boost = atomic_read(&rps->num_waiters);
}
spin_unlock_irq(&dev_priv->irq.lock);
@@ -1372,7 +1373,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
out:
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
spin_lock_irq(&dev_priv->irq.lock);
- if (rps->interrupts_enabled)
+ if (dev_priv->irq.rps_interrupts_enabled)
gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -1843,6 +1844,7 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
{
struct intel_rps *rps = &i915->gt_pm.rps;
+ struct intel_irq *irq = &i915->irq;
const u32 events = i915->pm_rps_events & pm_iir;
lockdep_assert_held(&i915->irq.lock);
@@ -1852,22 +1854,23 @@ static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
gen6_mask_pm_irq(i915, events);
- if (!rps->interrupts_enabled)
+ if (!irq->rps_interrupts_enabled)
return;
- rps->pm_iir |= events;
+ irq->pm_iir |= events;
schedule_work(&rps->work);
}
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ struct intel_irq *irq = &dev_priv->irq;
if (pm_iir & dev_priv->pm_rps_events) {
spin_lock(&dev_priv->irq.lock);
gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
- if (rps->interrupts_enabled) {
- rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
+ if (irq->rps_interrupts_enabled) {
+ irq->pm_iir |= pm_iir & dev_priv->pm_rps_events;
schedule_work(&rps->work);
}
spin_unlock(&dev_priv->irq.lock);
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 3/8] drm/i915: Move display_irqs_enabled to intel_irq
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
2019-04-18 20:53 ` [RFC 1/8] drm/i915: Introduce intel_irq Rodrigo Vivi
2019-04-18 20:53 ` [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 4/8] drm/i915: Consolidated iir, imr and ier Rodrigo Vivi
` (7 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Let's continue the IRQ consolidation with display_irqs_enabled.
Another possibility was a full split on gt_irq vs de_irq,
but for now display_irqs_enabled is already protected
buy the same lock. So, at least for now, let's keep
them together.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/i915_irq.c | 22 +++++++++++-----------
drivers/gpu/drm/i915/intel_hotplug.c | 10 ++++++----
3 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 06617a67002c..874668b5da57 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -651,6 +651,7 @@ struct intel_irq {
/* protects the irq masks */
spinlock_t lock;
bool rps_interrupts_enabled;
+ bool display_interrupts_enabled;
u32 pm_iir;
};
@@ -1554,8 +1555,6 @@ struct drm_i915_private {
struct intel_irq irq;
- bool display_irqs_enabled;
-
/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
struct pm_qos_request pm_qos;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 487ea27ea152..019472c98aac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1912,7 +1912,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
spin_lock(&dev_priv->irq.lock);
- if (!dev_priv->display_irqs_enabled) {
+ if (!dev_priv->irq.display_interrupts_enabled) {
spin_unlock(&dev_priv->irq.lock);
return;
}
@@ -3488,7 +3488,7 @@ static void valleyview_irq_reset(struct drm_device *dev)
gen5_gt_irq_reset(dev_priv);
spin_lock_irq(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
vlv_display_irq_reset(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -3634,7 +3634,7 @@ static void cherryview_irq_reset(struct drm_device *dev)
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
spin_lock_irq(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
vlv_display_irq_reset(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -4010,10 +4010,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
return;
- dev_priv->display_irqs_enabled = true;
+ dev_priv->irq.display_interrupts_enabled = true;
if (intel_irqs_enabled(dev_priv)) {
vlv_display_irq_reset(dev_priv);
@@ -4025,10 +4025,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
{
lockdep_assert_held(&dev_priv->irq.lock);
- if (!dev_priv->display_irqs_enabled)
+ if (!dev_priv->irq.display_interrupts_enabled)
return;
- dev_priv->display_irqs_enabled = false;
+ dev_priv->irq.display_interrupts_enabled = false;
if (intel_irqs_enabled(dev_priv))
vlv_display_irq_reset(dev_priv);
@@ -4042,7 +4042,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
gen5_gt_irq_postinstall(dev);
spin_lock_irq(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
vlv_display_irq_postinstall(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
@@ -4245,7 +4245,7 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
gen8_gt_irq_postinstall(dev_priv);
spin_lock_irq(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
vlv_display_irq_postinstall(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
@@ -4749,9 +4749,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
* outside of the power domain. We defer setting up the display irqs
* in this case to the runtime pm.
*/
- dev_priv->display_irqs_enabled = true;
+ dev_priv->irq.display_interrupts_enabled = true;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->display_irqs_enabled = false;
+ dev_priv->irq.display_interrupts_enabled = false;
dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
/* If we have MST support, we want to avoid doing short HPD IRQ storm
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c
index 8260e81f88e7..89ee666eb78c 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -258,7 +258,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
}
drm_connector_list_iter_end(&conn_iter);
}
- if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
+ if (dev_priv->irq.display_interrupts_enabled &&
+ dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
@@ -502,7 +503,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
* Disable any IRQs that storms were detected on. Polling enablement
* happens later in our hotplug work.
*/
- if (storm_detected && dev_priv->display_irqs_enabled)
+ if (storm_detected && dev_priv->irq.display_interrupts_enabled)
dev_priv->display.hpd_irq_setup(dev_priv);
spin_unlock(&dev_priv->irq.lock);
@@ -548,9 +549,10 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked checks happy.
*/
- if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
+ if (dev_priv->irq.display_interrupts_enabled &&
+ dev_priv->display.hpd_irq_setup) {
spin_lock_irq(&dev_priv->irq.lock);
- if (dev_priv->display_irqs_enabled)
+ if (dev_priv->irq.display_interrupts_enabled)
dev_priv->display.hpd_irq_setup(dev_priv);
spin_unlock_irq(&dev_priv->irq.lock);
}
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 4/8] drm/i915: Consolidated iir, imr and ier.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (2 preceding siblings ...)
2019-04-18 20:53 ` [RFC 3/8] drm/i915: Move display_irqs_enabled to intel_irq Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 5/8] drm/i915: Move all irq related masks to intel_irq Rodrigo Vivi
` (6 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Get all friends back together.
For gen8 gt_ prefix would be better than pm_ on them
since these regs include more stuff then PM, but let's
keep for legacy reasons.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++---------------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 874668b5da57..cb51cf335226 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -653,6 +653,8 @@ struct intel_irq {
bool rps_interrupts_enabled;
bool display_interrupts_enabled;
u32 pm_iir;
+ u32 pm_imr;
+ u32 pm_ier;
};
struct intel_rps {
@@ -1567,8 +1569,6 @@ struct drm_i915_private {
u32 de_irq_mask[I915_MAX_PIPES];
};
u32 gt_irq_mask;
- u32 pm_imr;
- u32 pm_ier;
u32 pm_rps_events;
u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 019472c98aac..667bbcc01513 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -400,7 +400,7 @@ static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
static void write_pm_imr(struct drm_i915_private *dev_priv)
{
i915_reg_t reg;
- u32 mask = dev_priv->pm_imr;
+ u32 mask = dev_priv->irq.pm_imr;
if (INTEL_GEN(dev_priv) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
@@ -419,7 +419,7 @@ static void write_pm_imr(struct drm_i915_private *dev_priv)
static void write_pm_ier(struct drm_i915_private *dev_priv)
{
i915_reg_t reg;
- u32 mask = dev_priv->pm_ier;
+ u32 mask = dev_priv->irq.pm_ier;
if (INTEL_GEN(dev_priv) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
@@ -450,12 +450,12 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
lockdep_assert_held(&dev_priv->irq.lock);
- new_val = dev_priv->pm_imr;
+ new_val = dev_priv->irq.pm_imr;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->pm_imr) {
- dev_priv->pm_imr = new_val;
+ if (new_val != dev_priv->irq.pm_imr) {
+ dev_priv->irq.pm_imr = new_val;
write_pm_imr(dev_priv);
}
}
@@ -496,7 +496,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
{
lockdep_assert_held(&dev_priv->irq.lock);
- dev_priv->pm_ier |= enable_mask;
+ dev_priv->irq.pm_ier |= enable_mask;
write_pm_ier(dev_priv);
gen6_unmask_pm_irq(dev_priv, enable_mask);
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
@@ -506,7 +506,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
{
lockdep_assert_held(&dev_priv->irq.lock);
- dev_priv->pm_ier &= ~disable_mask;
+ dev_priv->irq.pm_ier &= ~disable_mask;
__gen6_mask_pm_irq(dev_priv, disable_mask);
write_pm_ier(dev_priv);
/* though a barrier is missing here, but don't really need a one */
@@ -3944,11 +3944,11 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
*/
if (HAS_ENGINE(dev_priv, VECS0)) {
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
- dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
+ dev_priv->irq.pm_ier |= PM_VEBOX_USER_INTERRUPT;
}
- dev_priv->pm_imr = 0xffffffff;
- GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
+ dev_priv->irq.pm_imr = 0xffffffff;
+ GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
}
}
@@ -4074,15 +4074,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
};
- dev_priv->pm_ier = 0x0;
- dev_priv->pm_imr = ~dev_priv->pm_ier;
+ dev_priv->irq.pm_ier = 0x0;
+ dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled. Same wil be the case for GuC interrupts.
*/
- GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->irq.pm_imr, dev_priv->irq.pm_ier);
GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
@@ -4195,8 +4195,8 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
- dev_priv->pm_ier = 0x0;
- dev_priv->pm_imr = ~dev_priv->pm_ier;
+ dev_priv->irq.pm_ier = 0x0;
+ dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
}
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 5/8] drm/i915: Move all irq related masks to intel_irq
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (3 preceding siblings ...)
2019-04-18 20:53 ` [RFC 4/8] drm/i915: Consolidated iir, imr and ier Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 6/8] drm/i915: Prefer passing intel_irq instead of intel_core Rodrigo Vivi
` (5 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Another step towards the consolidation of all irq
related stuff under new intel_irq
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++---
drivers/gpu/drm/i915/i915_irq.c | 76 ++++++++++++-------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 +++---
3 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb51cf335226..8368daecf478 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -655,6 +655,13 @@ struct intel_irq {
u32 pm_iir;
u32 pm_imr;
u32 pm_ier;
+ /** Cached value of IMR to avoid reads in updating the bitfield */
+ union {
+ u32 mask;
+ u32 de_mask[I915_MAX_PIPES];
+ };
+ u32 gt_mask;
+ u32 pipestat_mask[I915_MAX_PIPES];
};
struct intel_rps {
@@ -1563,15 +1570,8 @@ struct drm_i915_private {
/* Sideband mailbox protection */
struct mutex sb_lock;
- /** Cached value of IMR to avoid reads in updating the bitfield */
- union {
- u32 irq_mask;
- u32 de_irq_mask[I915_MAX_PIPES];
- };
- u32 gt_irq_mask;
u32 pm_rps_events;
u32 pm_guc_events;
- u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
struct intel_fbc fbc;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 667bbcc01513..0468fbea70af 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -346,13 +346,13 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
- new_val = dev_priv->irq_mask;
+ new_val = dev_priv->irq.mask;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->irq_mask) {
- dev_priv->irq_mask = new_val;
- I915_WRITE(DEIMR, dev_priv->irq_mask);
+ if (new_val != dev_priv->irq.mask) {
+ dev_priv->irq.mask = new_val;
+ I915_WRITE(DEIMR, dev_priv->irq.mask);
POSTING_READ(DEIMR);
}
}
@@ -374,9 +374,9 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
- dev_priv->gt_irq_mask &= ~interrupt_mask;
- dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
- I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+ dev_priv->irq.gt_mask &= ~interrupt_mask;
+ dev_priv->irq.gt_mask |= (~enabled_irq_mask & interrupt_mask);
+ I915_WRITE(GTIMR, dev_priv->irq.gt_mask);
}
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask)
@@ -674,13 +674,13 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
return;
- new_val = dev_priv->de_irq_mask[pipe];
+ new_val = dev_priv->irq.de_mask[pipe];
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->de_irq_mask[pipe]) {
- dev_priv->de_irq_mask[pipe] = new_val;
- I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+ if (new_val != dev_priv->irq.de_mask[pipe]) {
+ dev_priv->irq.de_mask[pipe] = new_val;
+ I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->irq.de_mask[pipe]);
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
}
}
@@ -713,7 +713,7 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
+ u32 status_mask = dev_priv->irq.pipestat_mask[pipe];
u32 enable_mask = status_mask << 16;
lockdep_assert_held(&dev_priv->irq.lock);
@@ -764,10 +764,10 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(!intel_irqs_enabled(dev_priv));
- if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
+ if ((dev_priv->irq.pipestat_mask[pipe] & status_mask) == status_mask)
return;
- dev_priv->pipestat_irq_mask[pipe] |= status_mask;
+ dev_priv->irq.pipestat_mask[pipe] |= status_mask;
enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
I915_WRITE(reg, enable_mask | status_mask);
@@ -787,10 +787,10 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
lockdep_assert_held(&dev_priv->irq.lock);
WARN_ON(!intel_irqs_enabled(dev_priv));
- if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
+ if ((dev_priv->irq.pipestat_mask[pipe] & status_mask) == 0)
return;
- dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
+ dev_priv->irq.pipestat_mask[pipe] &= ~status_mask;
enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
I915_WRITE(reg, enable_mask | status_mask);
@@ -1901,7 +1901,7 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
PIPESTAT_INT_STATUS_MASK |
PIPE_FIFO_UNDERRUN_STATUS);
- dev_priv->pipestat_irq_mask[pipe] = 0;
+ dev_priv->irq.pipestat_mask[pipe] = 0;
}
}
@@ -1944,7 +1944,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
break;
}
if (iir & iir_bit)
- status_mask |= dev_priv->pipestat_irq_mask[pipe];
+ status_mask |= dev_priv->irq.pipestat_mask[pipe];
if (!status_mask)
continue;
@@ -3423,7 +3423,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
GEN3_IRQ_RESET(uncore, VLV_);
- dev_priv->irq_mask = ~0u;
+ dev_priv->irq.mask = ~0u;
}
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3450,11 +3450,11 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
I915_LPE_PIPE_C_INTERRUPT;
- WARN_ON(dev_priv->irq_mask != ~0u);
+ WARN_ON(dev_priv->irq.mask != ~0u);
- dev_priv->irq_mask = ~enable_mask;
+ dev_priv->irq.mask = ~enable_mask;
- GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq.mask, enable_mask);
}
/* drm_dma.h hooks
@@ -3593,8 +3593,8 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
- dev_priv->de_irq_mask[pipe],
- ~dev_priv->de_irq_mask[pipe] | extra_ier);
+ dev_priv->irq.de_mask[pipe],
+ ~dev_priv->irq.de_mask[pipe] | extra_ier);
spin_unlock_irq(&dev_priv->irq.lock);
}
@@ -3921,10 +3921,10 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
pm_irqs = gt_irqs = 0;
- dev_priv->gt_irq_mask = ~0;
+ dev_priv->irq.gt_mask = ~0;
if (HAS_L3_DPF(dev_priv)) {
/* L3 parity interrupt is always unmasked. */
- dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
+ dev_priv->irq.gt_mask = ~GT_PARITY_ERROR(dev_priv);
gt_irqs |= GT_PARITY_ERROR(dev_priv);
}
@@ -3935,7 +3935,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs);
+ GEN3_IRQ_INIT(uncore, GT, dev_priv->irq.gt_mask, gt_irqs);
if (INTEL_GEN(dev_priv) >= 6) {
/*
@@ -3979,11 +3979,11 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
display_mask |= DE_EDP_PSR_INT_HSW;
}
- dev_priv->irq_mask = ~display_mask;
+ dev_priv->irq.mask = ~display_mask;
ibx_irq_pre_postinstall(dev);
- GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
+ GEN3_IRQ_INIT(uncore, DE, dev_priv->irq.mask,
display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
@@ -4129,12 +4129,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
- dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
+ dev_priv->irq.de_mask[pipe] = ~de_pipe_masked;
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
- dev_priv->de_irq_mask[pipe],
+ dev_priv->irq.de_mask[pipe],
de_pipe_enables);
}
@@ -4275,7 +4275,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */
- dev_priv->irq_mask =
+ dev_priv->irq.mask =
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
I915_MASTER_ERROR_INTERRUPT);
@@ -4286,7 +4286,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
+ GEN2_IRQ_INIT(uncore, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4444,7 +4444,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
I915_ERROR_MEMORY_REFRESH));
/* Unmask the interrupts that we always want on. */
- dev_priv->irq_mask =
+ dev_priv->irq.mask =
~(I915_ASLE_INTERRUPT |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
@@ -4461,10 +4461,10 @@ static int i915_irq_postinstall(struct drm_device *dev)
/* Enable in IER... */
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
/* and unmask in IMR */
- dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
+ dev_priv->irq.mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4568,7 +4568,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
I915_WRITE(EMR, error_mask);
/* Unmask the interrupts that we always want on. */
- dev_priv->irq_mask =
+ dev_priv->irq.mask =
~(I915_ASLE_INTERRUPT |
I915_DISPLAY_PORT_INTERRUPT |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -4586,7 +4586,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
+ GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3844581f622c..db966d9106dc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -970,16 +970,16 @@ gen5_irq_disable(struct intel_engine_cs *engine)
static void
i9xx_irq_enable(struct intel_engine_cs *engine)
{
- engine->i915->irq_mask &= ~engine->irq_enable_mask;
- intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
+ engine->i915->irq.mask &= ~engine->irq_enable_mask;
+ intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq.mask);
intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
}
static void
i9xx_irq_disable(struct intel_engine_cs *engine)
{
- engine->i915->irq_mask |= engine->irq_enable_mask;
- intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
+ engine->i915->irq.mask |= engine->irq_enable_mask;
+ intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq.mask);
}
static void
@@ -987,8 +987,8 @@ i8xx_irq_enable(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- dev_priv->irq_mask &= ~engine->irq_enable_mask;
- I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
+ dev_priv->irq.mask &= ~engine->irq_enable_mask;
+ I915_WRITE16(GEN2_IMR, dev_priv->irq.mask);
POSTING_READ16(RING_IMR(engine->mmio_base));
}
@@ -997,8 +997,8 @@ i8xx_irq_disable(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- dev_priv->irq_mask |= engine->irq_enable_mask;
- I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);
+ dev_priv->irq.mask |= engine->irq_enable_mask;
+ I915_WRITE16(GEN2_IMR, dev_priv->irq.mask);
}
static int
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 6/8] drm/i915: Prefer passing intel_irq instead of intel_core
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (4 preceding siblings ...)
2019-04-18 20:53 ` [RFC 5/8] drm/i915: Move all irq related masks to intel_irq Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 7/8] drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915 Rodrigo Vivi
` (4 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
The plan is to convert most of arguments to use intel_irq
instead of intel_core or i915.
Note that dev_priv is not getting replaced by i915 because
the plan also include to move dev_priv to intel_irq.
The caveat is that we will need the uncore for tracking
the mmio region that we need, but at least code keeps "clean"
and less dependent on other components.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_irq.c | 238 ++++++++++++++++----------------
2 files changed, 122 insertions(+), 118 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8368daecf478..f783d63b686f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,6 +662,8 @@ struct intel_irq {
};
u32 gt_mask;
u32 pipestat_mask[I915_MAX_PIPES];
+
+ struct intel_uncore *uncore;
};
struct intel_rps {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0468fbea70af..27cae1e7f2cc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -136,120 +136,120 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
};
-static void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
+static void gen3_irq_reset(struct intel_irq *irq, i915_reg_t imr,
i915_reg_t iir, i915_reg_t ier)
{
- intel_uncore_write(uncore, imr, 0xffffffff);
- intel_uncore_posting_read(uncore, imr);
+ intel_uncore_write(irq->uncore, imr, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, imr);
- intel_uncore_write(uncore, ier, 0);
+ intel_uncore_write(irq->uncore, ier, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- intel_uncore_write(uncore, iir, 0xffffffff);
- intel_uncore_posting_read(uncore, iir);
- intel_uncore_write(uncore, iir, 0xffffffff);
- intel_uncore_posting_read(uncore, iir);
+ intel_uncore_write(irq->uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, iir);
+ intel_uncore_write(irq->uncore, iir, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, iir);
}
-static void gen2_irq_reset(struct intel_uncore *uncore)
+static void gen2_irq_reset(struct intel_irq *irq)
{
- intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IMR);
+ intel_uncore_write16(irq->uncore, GEN2_IMR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IMR);
- intel_uncore_write16(uncore, GEN2_IER, 0);
+ intel_uncore_write16(irq->uncore, GEN2_IER, 0);
/* IIR can theoretically queue up two events. Be paranoid. */
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
}
-#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
+#define GEN8_IRQ_RESET_NDX(irq, type, which) \
({ \
unsigned int which_ = which; \
- gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
+ gen3_irq_reset((irq), GEN8_##type##_IMR(which_), \
GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
})
-#define GEN3_IRQ_RESET(uncore, type) \
- gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
+#define GEN3_IRQ_RESET(irq, type) \
+ gen3_irq_reset((irq), type##IMR, type##IIR, type##IER)
-#define GEN2_IRQ_RESET(uncore) \
- gen2_irq_reset(uncore)
+#define GEN2_IRQ_RESET(irq) \
+ gen2_irq_reset(irq)
/*
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
*/
-static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
+static void gen3_assert_iir_is_zero(struct intel_irq *irq, i915_reg_t reg)
{
- u32 val = intel_uncore_read(uncore, reg);
+ u32 val = intel_uncore_read(irq->uncore, reg);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(reg), val);
- intel_uncore_write(uncore, reg, 0xffffffff);
- intel_uncore_posting_read(uncore, reg);
- intel_uncore_write(uncore, reg, 0xffffffff);
- intel_uncore_posting_read(uncore, reg);
+ intel_uncore_write(irq->uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, reg);
+ intel_uncore_write(irq->uncore, reg, 0xffffffff);
+ intel_uncore_posting_read(irq->uncore, reg);
}
-static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
+static void gen2_assert_iir_is_zero(struct intel_irq *irq)
{
- u16 val = intel_uncore_read16(uncore, GEN2_IIR);
+ u16 val = intel_uncore_read16(irq->uncore, GEN2_IIR);
if (val == 0)
return;
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
i915_mmio_reg_offset(GEN2_IIR), val);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
- intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
- intel_uncore_posting_read16(uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
+ intel_uncore_write16(irq->uncore, GEN2_IIR, 0xffff);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IIR);
}
-static void gen3_irq_init(struct intel_uncore *uncore,
+static void gen3_irq_init(struct intel_irq *irq,
i915_reg_t imr, u32 imr_val,
i915_reg_t ier, u32 ier_val,
i915_reg_t iir)
{
- gen3_assert_iir_is_zero(uncore, iir);
+ gen3_assert_iir_is_zero(irq, iir);
- intel_uncore_write(uncore, ier, ier_val);
- intel_uncore_write(uncore, imr, imr_val);
- intel_uncore_posting_read(uncore, imr);
+ intel_uncore_write(irq->uncore, ier, ier_val);
+ intel_uncore_write(irq->uncore, imr, imr_val);
+ intel_uncore_posting_read(irq->uncore, imr);
}
-static void gen2_irq_init(struct intel_uncore *uncore,
+static void gen2_irq_init(struct intel_irq *irq,
u32 imr_val, u32 ier_val)
{
- gen2_assert_iir_is_zero(uncore);
+ gen2_assert_iir_is_zero(irq);
- intel_uncore_write16(uncore, GEN2_IER, ier_val);
- intel_uncore_write16(uncore, GEN2_IMR, imr_val);
- intel_uncore_posting_read16(uncore, GEN2_IMR);
+ intel_uncore_write16(irq->uncore, GEN2_IER, ier_val);
+ intel_uncore_write16(irq->uncore, GEN2_IMR, imr_val);
+ intel_uncore_posting_read16(irq->uncore, GEN2_IMR);
}
-#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
+#define GEN8_IRQ_INIT_NDX(irq, type, which, imr_val, ier_val) \
({ \
unsigned int which_ = which; \
- gen3_irq_init((uncore), \
+ gen3_irq_init((irq), \
GEN8_##type##_IMR(which_), imr_val, \
GEN8_##type##_IER(which_), ier_val, \
GEN8_##type##_IIR(which_)); \
})
-#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
- gen3_irq_init((uncore), \
+#define GEN3_IRQ_INIT(irq, type, imr_val, ier_val) \
+ gen3_irq_init((irq), \
type##IMR, imr_val, \
type##IER, ier_val, \
type##IIR)
-#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
- gen2_irq_init((uncore), imr_val, ier_val)
+#define GEN2_IRQ_INIT(irq, imr_val, ier_val) \
+ gen2_irq_init((irq), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
@@ -3368,12 +3368,12 @@ static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (HAS_PCH_NOP(dev_priv))
return;
- GEN3_IRQ_RESET(uncore, SDE);
+ GEN3_IRQ_RESET(irq, SDE);
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
I915_WRITE(SERR_INT, 0xffffffff);
@@ -3401,16 +3401,16 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN3_IRQ_RESET(uncore, GT);
+ GEN3_IRQ_RESET(irq, GT);
if (INTEL_GEN(dev_priv) >= 6)
- GEN3_IRQ_RESET(uncore, GEN6_PM);
+ GEN3_IRQ_RESET(irq, GEN6_PM);
}
static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
@@ -3422,13 +3422,13 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, VLV_);
+ GEN3_IRQ_RESET(irq, VLV_);
dev_priv->irq.mask = ~0u;
}
static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 pipestat_mask;
u32 enable_mask;
@@ -3454,7 +3454,7 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq.mask = ~enable_mask;
- GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, VLV_, dev_priv->irq.mask, enable_mask);
}
/* drm_dma.h hooks
@@ -3462,9 +3462,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
static void ironlake_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN3_IRQ_RESET(uncore, DE);
+ GEN3_IRQ_RESET(irq, DE);
if (IS_GEN(dev_priv, 7))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
@@ -3495,18 +3495,18 @@ static void valleyview_irq_reset(struct drm_device *dev)
static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
- GEN8_IRQ_RESET_NDX(uncore, GT, 0);
- GEN8_IRQ_RESET_NDX(uncore, GT, 1);
- GEN8_IRQ_RESET_NDX(uncore, GT, 2);
- GEN8_IRQ_RESET_NDX(uncore, GT, 3);
+ GEN8_IRQ_RESET_NDX(irq, GT, 0);
+ GEN8_IRQ_RESET_NDX(irq, GT, 1);
+ GEN8_IRQ_RESET_NDX(irq, GT, 2);
+ GEN8_IRQ_RESET_NDX(irq, GT, 3);
}
static void gen8_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
int pipe;
gen8_master_intr_disable(dev_priv->uncore.regs);
@@ -3519,11 +3519,11 @@ static void gen8_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
@@ -3549,7 +3549,7 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
static void gen11_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
int pipe;
gen11_master_intr_disable(dev_priv->uncore.regs);
@@ -3564,22 +3564,22 @@ static void gen11_irq_reset(struct drm_device *dev)
for_each_pipe(dev_priv, pipe)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
- GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
- GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_PORT_);
+ GEN3_IRQ_RESET(irq, GEN8_DE_MISC_);
+ GEN3_IRQ_RESET(irq, GEN11_DE_HPD_);
+ GEN3_IRQ_RESET(irq, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- GEN3_IRQ_RESET(uncore, SDE);
+ GEN3_IRQ_RESET(irq, SDE);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
@@ -3592,7 +3592,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(irq, DE_PIPE, pipe,
dev_priv->irq.de_mask[pipe],
~dev_priv->irq.de_mask[pipe] | extra_ier);
@@ -3602,7 +3602,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
enum pipe pipe;
spin_lock_irq(&dev_priv->irq.lock);
@@ -3613,7 +3613,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
}
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
- GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
+ GEN8_IRQ_RESET_NDX(irq, DE_PIPE, pipe);
spin_unlock_irq(&dev_priv->irq.lock);
@@ -3624,14 +3624,14 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
static void cherryview_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
I915_WRITE(GEN8_MASTER_IRQ, 0);
POSTING_READ(GEN8_MASTER_IRQ);
gen8_gt_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(irq, GEN8_PCU_);
spin_lock_irq(&dev_priv->irq.lock);
if (dev_priv->irq.display_interrupts_enabled)
@@ -3903,7 +3903,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
else
mask = SDE_GMBUS_CPT;
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->irq, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
@@ -3916,7 +3916,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
static void gen5_gt_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 pm_irqs, gt_irqs;
pm_irqs = gt_irqs = 0;
@@ -3935,7 +3935,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GT, dev_priv->irq.gt_mask, gt_irqs);
+ GEN3_IRQ_INIT(irq, GT, dev_priv->irq.gt_mask, gt_irqs);
if (INTEL_GEN(dev_priv) >= 6) {
/*
@@ -3948,14 +3948,14 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
}
dev_priv->irq.pm_imr = 0xffffffff;
- GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
+ GEN3_IRQ_INIT(irq, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
}
}
static int ironlake_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 display_mask, extra_mask;
if (INTEL_GEN(dev_priv) >= 7) {
@@ -3974,7 +3974,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
}
if (IS_HASWELL(dev_priv)) {
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(irq, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
@@ -3983,7 +3983,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_pre_postinstall(dev);
- GEN3_IRQ_INIT(uncore, DE, dev_priv->irq.mask,
+ GEN3_IRQ_INIT(irq, DE, dev_priv->irq.mask,
display_mask | extra_mask);
gen5_gt_irq_postinstall(dev);
@@ -4054,7 +4054,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
/* These are interrupts we'll toggle with the ring mask register */
u32 gt_interrupts[] = {
@@ -4076,19 +4076,19 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
dev_priv->irq.pm_ier = 0x0;
dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
- GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
- GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled. Same wil be the case for GuC interrupts.
*/
- GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->irq.pm_imr, dev_priv->irq.pm_ier);
- GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
+ GEN8_IRQ_INIT_NDX(irq, GT, 2, dev_priv->irq.pm_imr, dev_priv->irq.pm_ier);
+ GEN8_IRQ_INIT_NDX(irq, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
u32 de_pipe_enables;
@@ -4125,7 +4125,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
- gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
+ gen3_assert_iir_is_zero(irq, EDP_PSR_IIR);
intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
for_each_pipe(dev_priv, pipe) {
@@ -4133,20 +4133,20 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (intel_display_power_is_enabled(dev_priv,
POWER_DOMAIN_PIPE(pipe)))
- GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
+ GEN8_IRQ_INIT_NDX(irq, DE_PIPE, pipe,
dev_priv->irq.de_mask[pipe],
de_pipe_enables);
}
- GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
- GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
+ GEN3_IRQ_INIT(irq, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
+ GEN3_IRQ_INIT(irq, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
if (INTEL_GEN(dev_priv) >= 11) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
- GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
+ GEN3_IRQ_INIT(irq, GEN11_DE_HPD_, ~de_hpd_masked,
de_hpd_enables);
gen11_hpd_detection_setup(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
@@ -4210,7 +4210,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
I915_WRITE(SDEIER, 0xffffffff);
POSTING_READ(SDEIER);
- gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
+ gen3_assert_iir_is_zero(&dev_priv->irq, SDEIIR);
I915_WRITE(SDEIMR, ~mask);
icp_hpd_detection_setup(dev_priv);
@@ -4219,7 +4219,7 @@ static void icp_irq_postinstall(struct drm_device *dev)
static int gen11_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
@@ -4228,7 +4228,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
gen11_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(irq, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
@@ -4258,17 +4258,17 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
static void i8xx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
i9xx_pipestat_irq_reset(dev_priv);
- GEN2_IRQ_RESET(uncore);
+ GEN2_IRQ_RESET(irq);
}
static int i8xx_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u16 enable_mask;
I915_WRITE16(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4286,7 +4286,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
I915_MASTER_ERROR_INTERRUPT |
I915_USER_INTERRUPT;
- GEN2_IRQ_INIT(uncore, dev_priv->irq.mask, enable_mask);
+ GEN2_IRQ_INIT(irq, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4422,7 +4422,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
static void i915_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
if (I915_HAS_HOTPLUG(dev_priv)) {
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
@@ -4431,13 +4431,13 @@ static void i915_irq_reset(struct drm_device *dev)
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN2_);
+ GEN3_IRQ_RESET(irq, GEN2_);
}
static int i915_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 enable_mask;
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
@@ -4464,7 +4464,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
dev_priv->irq.mask &= ~I915_DISPLAY_PORT_INTERRUPT;
}
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4535,20 +4535,20 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
static void i965_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
i9xx_pipestat_irq_reset(dev_priv);
- GEN3_IRQ_RESET(uncore, GEN2_);
+ GEN3_IRQ_RESET(irq, GEN2_);
}
static int i965_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_irq *irq = &dev_priv->irq;
u32 enable_mask;
u32 error_mask;
@@ -4586,7 +4586,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
if (IS_G4X(dev_priv))
enable_mask |= I915_BSD_USER_INTERRUPT;
- GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask);
+ GEN3_IRQ_INIT(irq, GEN2_, dev_priv->irq.mask, enable_mask);
/* Interrupt setup is already guaranteed to be single-threaded, this is
* just to make the assert_spin_locked check happy. */
@@ -4698,6 +4698,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (IS_I945GM(dev_priv))
i945gm_vblank_work_init(dev_priv);
+ dev_priv->irq.uncore = &dev_priv->uncore;
+
intel_hpd_init_work(dev_priv);
INIT_WORK(&rps->work, gen6_pm_rps_work);
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 7/8] drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (5 preceding siblings ...)
2019-04-18 20:53 ` [RFC 6/8] drm/i915: Prefer passing intel_irq instead of intel_core Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 8/8] drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs Rodrigo Vivi
` (3 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Now that we are free from passing uncore around let's free ourselves
from passing the whole i915 reference and only passing the struct
with all information that we need for handling the interrupts.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++----------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 27cae1e7f2cc..f142fe23bf10 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -293,17 +293,17 @@ void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
}
static u32
-gen11_gt_engine_identity(struct drm_i915_private * const i915,
+gen11_gt_engine_identity(struct intel_irq * const irq,
const unsigned int bank, const unsigned int bit);
-static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
+static bool gen11_reset_one_iir(struct intel_irq * const irq,
const unsigned int bank,
const unsigned int bit)
{
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = irq->uncore->regs;
u32 dw;
- lockdep_assert_held(&i915->irq.lock);
+ lockdep_assert_held(&irq->lock);
dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
if (dw & BIT(bit)) {
@@ -311,7 +311,7 @@ static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
* According to the BSpec, DW_IIR bits cannot be cleared without
* first servicing the Selector & Shared IIR registers.
*/
- gen11_gt_engine_identity(i915, bank, bit);
+ gen11_gt_engine_identity(irq, bank, bit);
/*
* We locked GT INT DW by reading it. If we want to (try
@@ -516,7 +516,7 @@ void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
{
spin_lock_irq(&dev_priv->irq.lock);
- while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
+ while (gen11_reset_one_iir(&dev_priv->irq, 0, GEN11_GTPM))
;
dev_priv->irq.pm_iir = 0;
@@ -543,7 +543,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
WARN_ON_ONCE(irq->pm_iir);
if (INTEL_GEN(dev_priv) >= 11)
- WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
+ WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->irq, 0, GEN11_GTPM));
else
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
@@ -1841,10 +1841,10 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
/* The RPS events need forcewake, so we add them to a work queue and mask their
* IMR bits until the work is done. Other interrupts can be processed without
* the work queue. */
-static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
+static void gen11_rps_irq_handler(struct intel_irq *irq, u32 pm_iir)
{
+ struct drm_i915_private *i915 = uncore_to_i915(irq->uncore);
struct intel_rps *rps = &i915->gt_pm.rps;
- struct intel_irq *irq = &i915->irq;
const u32 events = i915->pm_rps_events & pm_iir;
lockdep_assert_held(&i915->irq.lock);
@@ -2977,14 +2977,14 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
}
static u32
-gen11_gt_engine_identity(struct drm_i915_private * const i915,
+gen11_gt_engine_identity(struct intel_irq * const irq,
const unsigned int bank, const unsigned int bit)
{
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = irq->uncore->regs;
u32 timeout_ts;
u32 ident;
- lockdep_assert_held(&i915->irq.lock);
+ lockdep_assert_held(&irq->lock);
raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
@@ -3011,20 +3011,21 @@ gen11_gt_engine_identity(struct drm_i915_private * const i915,
}
static void
-gen11_other_irq_handler(struct drm_i915_private * const i915,
+gen11_other_irq_handler(struct intel_irq * const irq,
const u8 instance, const u16 iir)
{
if (instance == OTHER_GTPM_INSTANCE)
- return gen11_rps_irq_handler(i915, iir);
+ return gen11_rps_irq_handler(irq, iir);
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
static void
-gen11_engine_irq_handler(struct drm_i915_private * const i915,
+gen11_engine_irq_handler(struct intel_irq * const irq,
const u8 class, const u8 instance, const u16 iir)
{
+ struct drm_i915_private *i915 = uncore_to_i915(irq->uncore);
struct intel_engine_cs *engine;
if (instance <= MAX_ENGINE_INSTANCE)
@@ -3040,7 +3041,7 @@ gen11_engine_irq_handler(struct drm_i915_private * const i915,
}
static void
-gen11_gt_identity_handler(struct drm_i915_private * const i915,
+gen11_gt_identity_handler(struct intel_irq * const irq,
const u32 identity)
{
const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
@@ -3051,31 +3052,31 @@ gen11_gt_identity_handler(struct drm_i915_private * const i915,
return;
if (class <= COPY_ENGINE_CLASS)
- return gen11_engine_irq_handler(i915, class, instance, intr);
+ return gen11_engine_irq_handler(irq, class, instance, intr);
if (class == OTHER_CLASS)
- return gen11_other_irq_handler(i915, instance, intr);
+ return gen11_other_irq_handler(irq, instance, intr);
WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
class, instance, intr);
}
static void
-gen11_gt_bank_handler(struct drm_i915_private * const i915,
+gen11_gt_bank_handler(struct intel_irq * const irq,
const unsigned int bank)
{
- void __iomem * const regs = i915->uncore.regs;
+ void __iomem * const regs = irq->uncore->regs;
unsigned long intr_dw;
unsigned int bit;
- lockdep_assert_held(&i915->irq.lock);
+ lockdep_assert_held(&irq->lock);
intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
for_each_set_bit(bit, &intr_dw, 32) {
- const u32 ident = gen11_gt_engine_identity(i915, bank, bit);
+ const u32 ident = gen11_gt_engine_identity(irq, bank, bit);
- gen11_gt_identity_handler(i915, ident);
+ gen11_gt_identity_handler(irq, ident);
}
/* Clear must be after shared has been served for engine */
@@ -3083,19 +3084,19 @@ gen11_gt_bank_handler(struct drm_i915_private * const i915,
}
static void
-gen11_gt_irq_handler(struct drm_i915_private * const i915,
+gen11_gt_irq_handler(struct intel_irq * const irq,
const u32 master_ctl)
{
unsigned int bank;
- spin_lock(&i915->irq.lock);
+ spin_lock(&irq->lock);
for (bank = 0; bank < 2; bank++) {
if (master_ctl & GEN11_GT_DW_IRQ(bank))
- gen11_gt_bank_handler(i915, bank);
+ gen11_gt_bank_handler(irq, bank);
}
- spin_unlock(&i915->irq.lock);
+ spin_unlock(&irq->lock);
}
static u32
@@ -3156,7 +3157,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
}
/* Find, clear, then process each source of interrupt. */
- gen11_gt_irq_handler(i915, master_ctl);
+ gen11_gt_irq_handler(&i915->irq, master_ctl);
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ) {
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [RFC 8/8] drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (6 preceding siblings ...)
2019-04-18 20:53 ` [RFC 7/8] drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915 Rodrigo Vivi
@ 2019-04-18 20:53 ` Rodrigo Vivi
2019-04-18 21:31 ` ✗ Fi.CI.SPARSE: warning for Start some re-org around IRQ Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 20:53 UTC (permalink / raw)
To: intel-gfx
Let's continue the migration starting from newer to old platforms.
The goal is to use intel_irq struct and intel_uncore_* functions
along all i915_irq.c as much as possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++++---------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f142fe23bf10..cdb079459d29 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3100,9 +3100,9 @@ gen11_gt_irq_handler(struct intel_irq * const irq,
}
static u32
-gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
+gen11_gu_misc_irq_ack(struct intel_irq *irq, const u32 master_ctl)
{
- void __iomem * const regs = dev_priv->uncore.regs;
+ void __iomem * const regs = irq->uncore->regs;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -3172,7 +3172,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(i915);
}
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(&i915->irq, master_ctl);
gen11_master_intr_enable(regs);
@@ -4175,31 +4175,35 @@ static int gen8_irq_postinstall(struct drm_device *dev)
return 0;
}
-static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+static void gen11_gt_irq_postinstall(struct intel_irq *irq)
{
+ struct intel_uncore *uncore = irq->uncore;
const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
BUILD_BUG_ON(irqs & 0xffff0000);
/* Enable RCS, BCS, VCS and VECS class interrupts. */
- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
+ intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
+ intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
+ intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
+ intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,
+ ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,
+ ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,
+ ~(irqs | irqs << 16));
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
- dev_priv->irq.pm_ier = 0x0;
- dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+ irq->pm_ier = 0x0;
+ irq->pm_imr = ~irq->pm_ier;
+ intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
}
static void icp_irq_postinstall(struct drm_device *dev)
@@ -4226,7 +4230,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_postinstall(dev);
- gen11_gt_irq_postinstall(dev_priv);
+ gen11_gt_irq_postinstall(irq);
gen8_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(irq, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
--
2.20.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
2019-04-18 20:53 ` [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq Rodrigo Vivi
@ 2019-04-18 21:15 ` Chris Wilson
2019-04-18 22:48 ` Rodrigo Vivi
0 siblings, 1 reply; 14+ messages in thread
From: Chris Wilson @ 2019-04-18 21:15 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Quoting Rodrigo Vivi (2019-04-18 21:53:41)
> The plan is to consolidate all IRQ related stuff together
> under the new intel_irq.
>
> So let's continue with RPS stuff.
Nah, this is the wrong direction as we don't have to pull this under a
more global lock but push it under a local one. If you are touching this
code, you could review the bug fixes first... :)
-Chris
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^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Start some re-org around IRQ.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (7 preceding siblings ...)
2019-04-18 20:53 ` [RFC 8/8] drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs Rodrigo Vivi
@ 2019-04-18 21:31 ` Patchwork
2019-04-18 21:50 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-19 0:25 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-04-18 21:31 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Start some re-org around IRQ.
URL : https://patchwork.freedesktop.org/series/59735/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce intel_irq
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3620:16: warning: expression using sizeof(void)
Commit: drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3620:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)
Commit: drm/i915: Move display_irqs_enabled to intel_irq
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3616:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3615:16: warning: expression using sizeof(void)
Commit: drm/i915: Consolidated iir, imr and ier.
Okay!
Commit: drm/i915: Move all irq related masks to intel_irq
Okay!
Commit: drm/i915: Prefer passing intel_irq instead of intel_core
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3615:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3617:16: warning: expression using sizeof(void)
Commit: drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915
Okay!
Commit: drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs.
Okay!
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for Start some re-org around IRQ.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (8 preceding siblings ...)
2019-04-18 21:31 ` ✗ Fi.CI.SPARSE: warning for Start some re-org around IRQ Patchwork
@ 2019-04-18 21:50 ` Patchwork
2019-04-19 0:25 ` ✓ Fi.CI.IGT: " Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-04-18 21:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Start some re-org around IRQ.
URL : https://patchwork.freedesktop.org/series/59735/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5954 -> Patchwork_12836
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59735/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12836 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload:
- fi-ilk-650: PASS -> DMESG-WARN [fdo#106387]
* igt@kms_force_connector_basic@force-edid:
- fi-glk-dsi: NOTRUN -> SKIP [fdo#109271] +26
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47
* igt@kms_frontbuffer_tracking@basic:
- fi-glk-dsi: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191]
#### Possible fixes ####
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] -> PASS +1
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (48 -> 43)
------------------------------
Additional (1): fi-bxt-j4205
Missing (6): fi-ilk-m540 fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-icl-dsi fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5954 -> Patchwork_12836
CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12836: 5ff172f4ac6a0f3c5075c342f35103c374a236c0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5ff172f4ac6a drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs.
fd398ff095b0 drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915
bf5092f95158 drm/i915: Prefer passing intel_irq instead of intel_core
d7c5c0db8e68 drm/i915: Move all irq related masks to intel_irq
b665bca12700 drm/i915: Consolidated iir, imr and ier.
159bc9ff310e drm/i915: Move display_irqs_enabled to intel_irq
e7980dbafa19 drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
9ce2cb8e6c65 drm/i915: Introduce intel_irq
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12836/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq.
2019-04-18 21:15 ` Chris Wilson
@ 2019-04-18 22:48 ` Rodrigo Vivi
0 siblings, 0 replies; 14+ messages in thread
From: Rodrigo Vivi @ 2019-04-18 22:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Apr 18, 2019 at 10:15:55PM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-04-18 21:53:41)
> > The plan is to consolidate all IRQ related stuff together
> > under the new intel_irq.
> >
> > So let's continue with RPS stuff.
>
> Nah, this is the wrong direction
you mean just this rps moving to intel_irq?
or the whole idea of intel_irq is bad in your opinion?
> as we don't have to pull this under a
> more global lock but push it under a local one.
yeap, I noticed this big lock around everything and
that we need to reduce that indeed...
> If you are touching this
> code, you could review the bug fixes first... :)
:(
Thanks a lot,
Rodrigo.
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for Start some re-org around IRQ.
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
` (9 preceding siblings ...)
2019-04-18 21:50 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-19 0:25 ` Patchwork
10 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-04-19 0:25 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: Start some re-org around IRQ.
URL : https://patchwork.freedesktop.org/series/59735/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5954_full -> Patchwork_12836_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12836_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-skl: NOTRUN -> FAIL
- shard-apl: NOTRUN -> FAIL
* {igt@audio@hdmi-integrity-after-suspend}:
- shard-glk: TIMEOUT -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12836_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +2
* igt@i915_pm_rpm@pm-caching:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#107807]
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-e:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4
* igt@kms_chamelium@dp-crc-fast:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +48
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: PASS -> SKIP [fdo#109349]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +117
* igt@kms_lease@atomic_implicit_crtc:
- shard-snb: NOTRUN -> FAIL [fdo#110279]
* igt@kms_lease@setcrtc_implicit_plane:
- shard-snb: NOTRUN -> FAIL [fdo#110281]
* igt@kms_panel_fitting@atomic-fastset:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-e:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] / [fdo#110403]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +85
#### Possible fixes ####
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +5
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: FAIL [fdo#100368] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1
* igt@kms_psr@psr2_basic:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-kbl: INCOMPLETE [fdo#103665] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-skl: SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110279]: https://bugs.freedesktop.org/show_bug.cgi?id=110279
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5954 -> Patchwork_12836
CI_DRM_5954: a77e0dc060fcd1a2a09412067097685c5101589c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4957: a765aa108105804c19096554447ad0cb71f64fc3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12836: 5ff172f4ac6a0f3c5075c342f35103c374a236c0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12836/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-04-19 0:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-18 20:53 [RFC 0/8] Start some re-org around IRQ Rodrigo Vivi
2019-04-18 20:53 ` [RFC 1/8] drm/i915: Introduce intel_irq Rodrigo Vivi
2019-04-18 20:53 ` [RFC 2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq Rodrigo Vivi
2019-04-18 21:15 ` Chris Wilson
2019-04-18 22:48 ` Rodrigo Vivi
2019-04-18 20:53 ` [RFC 3/8] drm/i915: Move display_irqs_enabled to intel_irq Rodrigo Vivi
2019-04-18 20:53 ` [RFC 4/8] drm/i915: Consolidated iir, imr and ier Rodrigo Vivi
2019-04-18 20:53 ` [RFC 5/8] drm/i915: Move all irq related masks to intel_irq Rodrigo Vivi
2019-04-18 20:53 ` [RFC 6/8] drm/i915: Prefer passing intel_irq instead of intel_core Rodrigo Vivi
2019-04-18 20:53 ` [RFC 7/8] drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915 Rodrigo Vivi
2019-04-18 20:53 ` [RFC 8/8] drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs Rodrigo Vivi
2019-04-18 21:31 ` ✗ Fi.CI.SPARSE: warning for Start some re-org around IRQ Patchwork
2019-04-18 21:50 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-19 0:25 ` ✓ Fi.CI.IGT: " Patchwork
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