* [Qemu-devel] [PULL 0/2] target/hppa patch queue
@ 2019-04-26 18:22 Richard Henderson
2019-04-26 18:22 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Richard Henderson @ 2019-04-26 18:22 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 3284aa128153750f14a61e8a96fd085e6f2999b6:
Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging (2019-04-24 13:19:41 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-hppa-20190426
for you to fetch changes up to 647ad90a1eb6c016071d21e4f1e22b9cd4986417:
target/hppa: Always return EXCP_DMAR for protection id trap (2019-04-26 11:09:22 -0700)
----------------------------------------------------------------
Implement fast tlb insert insns.
Fix data tlb exception for pa 1.1.
----------------------------------------------------------------
Nick Hudson (2):
target/hppa: Implement Fast TLB Insert instructions
target/hppa: Always return EXCP_DMAR for protection id trap
target/hppa/mem_helper.c | 3 +--
target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++
target/hppa/insns.decode | 3 +++
3 files changed, 58 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread* [Qemu-devel] [PULL 1/2] target/hppa: Implement Fast TLB Insert instructions @ 2019-04-26 18:22 ` Richard Henderson 0 siblings, 0 replies; 6+ messages in thread From: Richard Henderson @ 2019-04-26 18:22 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Nick Hudson From: Nick Hudson <skrll@netbsd.org> These instructions are present on pcxl and pcxl2 machines, and are used by NetBSD and OpenBSD. See https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf page 13-9 (195/206) Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-2-nick.hudson@gmx.co.uk> [rth: Use extending loads, locally managed temporaries.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++ target/hppa/insns.decode | 3 +++ 2 files changed, 57 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 43b74367ea..aa140c6c72 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2518,6 +2518,60 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) #endif } +/* + * Implement the pcxl and pcxl2 Fast TLB Insert instructions. + * See + * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf + * page 13-9 (195/206) + */ +static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + TCGv_tl addr, atl, stl; + TCGv_reg reg; + + nullify_over(ctx); + + /* + * FIXME: + * if (not (pcxl or pcxl2)) + * return gen_illegal(ctx); + * + * Note for future: these are 32-bit systems; no hppa64. + */ + + atl = tcg_temp_new_tl(ctx); + stl = tcg_temp_new_tl(ctx); + addr = tcg_temp_new_tl(ctx); + + tcg_gen_ld32u_i64(stl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) + : offsetof(CPUHPPAState, cr[CR_IIASQ])); + tcg_gen_ld32u_i64(atl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) + : offsetof(CPUHPPAState, cr[CR_IIAOQ])); + tcg_gen_shli_i64(stl, stl, 32); + tcg_gen_or_tl(addr, atl, stl); + tcg_temp_free_tl(atl); + tcg_temp_free_tl(stl); + + reg = load_gpr(ctx, a->r); + if (a->addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + tcg_temp_free_tl(addr); + + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + } + return nullify_end(ctx); +#endif +} + static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 098370c2f0..f0dd71dd08 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -133,6 +133,9 @@ ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ sp=%assemble_sr3x data=0 +# pcxl and pcxl2 Fast TLB Insert instructions +ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=%assemble_sr3x data=0 -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PULL 1/2] target/hppa: Implement Fast TLB Insert instructions @ 2019-04-26 18:22 ` Richard Henderson 0 siblings, 0 replies; 6+ messages in thread From: Richard Henderson @ 2019-04-26 18:22 UTC (permalink / raw) To: qemu-devel; +Cc: Nick Hudson, peter.maydell From: Nick Hudson <skrll@netbsd.org> These instructions are present on pcxl and pcxl2 machines, and are used by NetBSD and OpenBSD. See https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf page 13-9 (195/206) Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-2-nick.hudson@gmx.co.uk> [rth: Use extending loads, locally managed temporaries.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++ target/hppa/insns.decode | 3 +++ 2 files changed, 57 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 43b74367ea..aa140c6c72 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2518,6 +2518,60 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) #endif } +/* + * Implement the pcxl and pcxl2 Fast TLB Insert instructions. + * See + * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf + * page 13-9 (195/206) + */ +static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + TCGv_tl addr, atl, stl; + TCGv_reg reg; + + nullify_over(ctx); + + /* + * FIXME: + * if (not (pcxl or pcxl2)) + * return gen_illegal(ctx); + * + * Note for future: these are 32-bit systems; no hppa64. + */ + + atl = tcg_temp_new_tl(ctx); + stl = tcg_temp_new_tl(ctx); + addr = tcg_temp_new_tl(ctx); + + tcg_gen_ld32u_i64(stl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) + : offsetof(CPUHPPAState, cr[CR_IIASQ])); + tcg_gen_ld32u_i64(atl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) + : offsetof(CPUHPPAState, cr[CR_IIAOQ])); + tcg_gen_shli_i64(stl, stl, 32); + tcg_gen_or_tl(addr, atl, stl); + tcg_temp_free_tl(atl); + tcg_temp_free_tl(stl); + + reg = load_gpr(ctx, a->r); + if (a->addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + tcg_temp_free_tl(addr); + + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + } + return nullify_end(ctx); +#endif +} + static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 098370c2f0..f0dd71dd08 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -133,6 +133,9 @@ ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ sp=%assemble_sr3x data=0 +# pcxl and pcxl2 Fast TLB Insert instructions +ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=%assemble_sr3x data=0 -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PULL 2/2] target/hppa: Always return EXCP_DMAR for protection id trap @ 2019-04-26 18:22 ` Richard Henderson 0 siblings, 0 replies; 6+ messages in thread From: Richard Henderson @ 2019-04-26 18:22 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, Nick Hudson From: Nick Hudson <skrll@netbsd.org> The EXCP_DMP trap is considered legacy. "In PA-RISC 1.1 (Second Edition) and later revisions, processors must use traps 26, 27,and 28 which provide equivalent functionality" Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-3-nick.hudson@gmx.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/mem_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..77fb544838 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (unlikely(!(prot & type))) { /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ - ret = (type & PAGE_EXEC ? EXCP_IMP : - prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR); + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; goto egress; } -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PULL 2/2] target/hppa: Always return EXCP_DMAR for protection id trap @ 2019-04-26 18:22 ` Richard Henderson 0 siblings, 0 replies; 6+ messages in thread From: Richard Henderson @ 2019-04-26 18:22 UTC (permalink / raw) To: qemu-devel; +Cc: Nick Hudson, peter.maydell From: Nick Hudson <skrll@netbsd.org> The EXCP_DMP trap is considered legacy. "In PA-RISC 1.1 (Second Edition) and later revisions, processors must use traps 26, 27,and 28 which provide equivalent functionality" Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-3-nick.hudson@gmx.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/mem_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..77fb544838 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (unlikely(!(prot & type))) { /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ - ret = (type & PAGE_EXEC ? EXCP_IMP : - prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR); + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; goto egress; } -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PULL 0/2] target/hppa patch queue 2019-04-26 18:22 [Qemu-devel] [PULL 0/2] target/hppa patch queue Richard Henderson 2019-04-26 18:22 ` Richard Henderson 2019-04-26 18:22 ` Richard Henderson @ 2019-04-28 14:55 ` Peter Maydell 2 siblings, 0 replies; 6+ messages in thread From: Peter Maydell @ 2019-04-28 14:55 UTC (permalink / raw) To: Richard Henderson; +Cc: QEMU Developers On Fri, 26 Apr 2019 at 19:22, Richard Henderson <richard.henderson@linaro.org> wrote: > > The following changes since commit 3284aa128153750f14a61e8a96fd085e6f2999b6: > > Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging (2019-04-24 13:19:41 +0100) > > are available in the Git repository at: > > https://github.com/rth7680/qemu.git tags/pull-hppa-20190426 > > for you to fetch changes up to 647ad90a1eb6c016071d21e4f1e22b9cd4986417: > > target/hppa: Always return EXCP_DMAR for protection id trap (2019-04-26 11:09:22 -0700) > > ---------------------------------------------------------------- > Implement fast tlb insert insns. > Fix data tlb exception for pa 1.1. > > ---------------------------------------------------------------- Hi; this doesn't seem to build: /home/pm215/qemu/target/hppa/translate.c: In function ‘trans_ixtlbxf’: /home/pm215/qemu/target/hppa/translate.c:2544:5: error: too many arguments to function ‘tcg_temp_new_i64’ atl = tcg_temp_new_tl(ctx); ^ In file included from /home/pm215/qemu/tcg/tcg-op.h:28:0, from /home/pm215/qemu/target/hppa/translate.c:25: /home/pm215/qemu/tcg/tcg.h:975:24: note: declared here static inline TCGv_i64 tcg_temp_new_i64(void) ^ /home/pm215/qemu/target/hppa/translate.c:2545:5: error: too many arguments to function ‘tcg_temp_new_i64’ stl = tcg_temp_new_tl(ctx); ^ In file included from /home/pm215/qemu/tcg/tcg-op.h:28:0, from /home/pm215/qemu/target/hppa/translate.c:25: /home/pm215/qemu/tcg/tcg.h:975:24: note: declared here static inline TCGv_i64 tcg_temp_new_i64(void) ^ /home/pm215/qemu/target/hppa/translate.c:2546:5: error: too many arguments to function ‘tcg_temp_new_i64’ addr = tcg_temp_new_tl(ctx); ^ In file included from /home/pm215/qemu/tcg/tcg-op.h:28:0, from /home/pm215/qemu/target/hppa/translate.c:25: /home/pm215/qemu/tcg/tcg.h:975:24: note: declared here static inline TCGv_i64 tcg_temp_new_i64(void) ^ (maybe a conflict with your other pullreq I just applied?) thanks -- PMM ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-04-28 14:56 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-04-26 18:22 [Qemu-devel] [PULL 0/2] target/hppa patch queue Richard Henderson 2019-04-26 18:22 ` [Qemu-devel] [PULL 1/2] target/hppa: Implement Fast TLB Insert instructions Richard Henderson 2019-04-26 18:22 ` Richard Henderson 2019-04-26 18:22 ` [Qemu-devel] [PULL 2/2] target/hppa: Always return EXCP_DMAR for protection id trap Richard Henderson 2019-04-26 18:22 ` Richard Henderson 2019-04-28 14:55 ` [Qemu-devel] [PULL 0/2] target/hppa patch queue Peter Maydell
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