* [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
@ 2019-05-06 12:04 ` Manivannan Sadhasivam
0 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-06 12:04 UTC (permalink / raw)
To: heiko
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom,
dev, Manivannan Sadhasivam
Enable SPI0 and SPI4 exposed on the Low and High speed expansion
connectors of Rock960.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
index 12285c51cceb..7498344d4a73 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
@@ -114,6 +114,18 @@
};
};
+&spi0 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
+&spi4 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
@ 2019-05-06 12:04 ` Manivannan Sadhasivam
0 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-06 12:04 UTC (permalink / raw)
To: heiko
Cc: tom, linux-kernel, dev, linux-rockchip, Manivannan Sadhasivam,
ezequiel, linux-arm-kernel
Enable SPI0 and SPI4 exposed on the Low and High speed expansion
connectors of Rock960.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
index 12285c51cceb..7498344d4a73 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
@@ -114,6 +114,18 @@
};
};
+&spi0 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
+&spi4 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "otg";
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
2019-05-06 12:04 ` Manivannan Sadhasivam
@ 2019-05-06 12:04 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-06 12:04 UTC (permalink / raw)
To: heiko
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom,
dev, Manivannan Sadhasivam
Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:
CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 027d428917b8..9baa378fc770 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -146,6 +146,12 @@
};
};
+&spi1 {
+ /* On both Low speed and High speed expansion */
+ cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
@ 2019-05-06 12:04 ` Manivannan Sadhasivam
0 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-06 12:04 UTC (permalink / raw)
To: heiko
Cc: tom, linux-kernel, dev, linux-rockchip, Manivannan Sadhasivam,
ezequiel, linux-arm-kernel
Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:
CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 027d428917b8..9baa378fc770 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -146,6 +146,12 @@
};
};
+&spi1 {
+ /* On both Low speed and High speed expansion */
+ cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
+ status = "okay";
+};
+
&usbdrd_dwc3_0 {
dr_mode = "host";
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
2019-05-06 12:04 ` Manivannan Sadhasivam
@ 2019-05-07 11:17 ` Heiko Stuebner
-1 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:17 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> connectors of Rock960.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> index 12285c51cceb..7498344d4a73 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> @@ -114,6 +114,18 @@
> };
> };
>
> +&spi0 {
> + /* On Low speed expansion */
> + label = "LS-SPI0";
where does the label property come from and what does it do?
It's not part of the rockchip-spi / general-spi binding.
Heiko
> + status = "okay";
> +};
> +
> +&spi4 {
> + /* On High speed expansion */
> + label = "HS-SPI1";
> + status = "okay";
> +};
> +
> &usbdrd_dwc3_0 {
> dr_mode = "otg";
> };
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
@ 2019-05-07 11:17 ` Heiko Stuebner
0 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:17 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> connectors of Rock960.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> index 12285c51cceb..7498344d4a73 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> @@ -114,6 +114,18 @@
> };
> };
>
> +&spi0 {
> + /* On Low speed expansion */
> + label = "LS-SPI0";
where does the label property come from and what does it do?
It's not part of the rockchip-spi / general-spi binding.
Heiko
> + status = "okay";
> +};
> +
> +&spi4 {
> + /* On High speed expansion */
> + label = "HS-SPI1";
> + status = "okay";
> +};
> +
> &usbdrd_dwc3_0 {
> dr_mode = "otg";
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
2019-05-06 12:04 ` Manivannan Sadhasivam
@ 2019-05-07 11:22 ` Heiko Stuebner
-1 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:22 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> Enable SPI1 exposed on both Low and High speed expansion connectors
> of Ficus. SPI1 has 3 different chip selects wired as below:
>
> CS0 - Serial Flash (unpopulated)
> CS1 - Low Speed expansion
> CS2 - High Speed expansion
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> index 027d428917b8..9baa378fc770 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> @@ -146,6 +146,12 @@
> };
> };
>
> +&spi1 {
> + /* On both Low speed and High speed expansion */
> + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
The flash is part of the schematics, so there might be board with
it pre-populated or people might put a flash chip on it.
Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
Heiko
> + status = "okay";
> +};
> +
> &usbdrd_dwc3_0 {
> dr_mode = "host";
> };
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
@ 2019-05-07 11:22 ` Heiko Stuebner
0 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:22 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> Enable SPI1 exposed on both Low and High speed expansion connectors
> of Ficus. SPI1 has 3 different chip selects wired as below:
>
> CS0 - Serial Flash (unpopulated)
> CS1 - Low Speed expansion
> CS2 - High Speed expansion
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> index 027d428917b8..9baa378fc770 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> @@ -146,6 +146,12 @@
> };
> };
>
> +&spi1 {
> + /* On both Low speed and High speed expansion */
> + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
The flash is part of the schematics, so there might be board with
it pre-populated or people might put a flash chip on it.
Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
Heiko
> + status = "okay";
> +};
> +
> &usbdrd_dwc3_0 {
> dr_mode = "host";
> };
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
2019-05-07 11:17 ` Heiko Stuebner
@ 2019-05-07 11:33 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-07 11:33 UTC (permalink / raw)
To: Heiko Stuebner
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
Hi Heiko,
On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > connectors of Rock960.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > index 12285c51cceb..7498344d4a73 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > @@ -114,6 +114,18 @@
> > };
> > };
> >
> > +&spi0 {
> > + /* On Low speed expansion */
> > + label = "LS-SPI0";
>
> where does the label property come from and what does it do?
> It's not part of the rockchip-spi / general-spi binding.
>
It is not part of the binding but I thought it will provide the users
the information of the SPI bus as per the specification when they
look into devicetree.
If it doesn't makes sense, I can remove that!
Thanks,
Mani
>
> Heiko
>
> > + status = "okay";
> > +};
> > +
> > +&spi4 {
> > + /* On High speed expansion */
> > + label = "HS-SPI1";
> > + status = "okay";
> > +};
> > +
> > &usbdrd_dwc3_0 {
> > dr_mode = "otg";
> > };
> >
>
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
@ 2019-05-07 11:33 ` Manivannan Sadhasivam
0 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-07 11:33 UTC (permalink / raw)
To: Heiko Stuebner
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
Hi Heiko,
On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > connectors of Rock960.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > index 12285c51cceb..7498344d4a73 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > @@ -114,6 +114,18 @@
> > };
> > };
> >
> > +&spi0 {
> > + /* On Low speed expansion */
> > + label = "LS-SPI0";
>
> where does the label property come from and what does it do?
> It's not part of the rockchip-spi / general-spi binding.
>
It is not part of the binding but I thought it will provide the users
the information of the SPI bus as per the specification when they
look into devicetree.
If it doesn't makes sense, I can remove that!
Thanks,
Mani
>
> Heiko
>
> > + status = "okay";
> > +};
> > +
> > +&spi4 {
> > + /* On High speed expansion */
> > + label = "HS-SPI1";
> > + status = "okay";
> > +};
> > +
> > &usbdrd_dwc3_0 {
> > dr_mode = "otg";
> > };
> >
>
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
2019-05-07 11:33 ` Manivannan Sadhasivam
@ 2019-05-07 11:34 ` Heiko Stuebner
-1 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:34 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
Am Dienstag, 7. Mai 2019, 13:33:39 CEST schrieb Manivannan Sadhasivam:
> Hi Heiko,
>
> On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > > connectors of Rock960.
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> > > 1 file changed, 12 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > index 12285c51cceb..7498344d4a73 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > @@ -114,6 +114,18 @@
> > > };
> > > };
> > >
> > > +&spi0 {
> > > + /* On Low speed expansion */
> > > + label = "LS-SPI0";
> >
> > where does the label property come from and what does it do?
> > It's not part of the rockchip-spi / general-spi binding.
> >
>
> It is not part of the binding but I thought it will provide the users
> the information of the SPI bus as per the specification when they
> look into devicetree.
>
> If it doesn't makes sense, I can remove that!
please do :-) ... dt-bindings are supposed to be verifyable at some
point, so we shouldn't add undocumented properties.
Heiko
>
> Thanks,
> Mani
>
> >
> > Heiko
> >
> > > + status = "okay";
> > > +};
> > > +
> > > +&spi4 {
> > > + /* On High speed expansion */
> > > + label = "HS-SPI1";
> > > + status = "okay";
> > > +};
> > > +
> > > &usbdrd_dwc3_0 {
> > > dr_mode = "otg";
> > > };
> > >
> >
> >
> >
> >
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
@ 2019-05-07 11:34 ` Heiko Stuebner
0 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:34 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
Am Dienstag, 7. Mai 2019, 13:33:39 CEST schrieb Manivannan Sadhasivam:
> Hi Heiko,
>
> On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > > connectors of Rock960.
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> > > 1 file changed, 12 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > index 12285c51cceb..7498344d4a73 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > @@ -114,6 +114,18 @@
> > > };
> > > };
> > >
> > > +&spi0 {
> > > + /* On Low speed expansion */
> > > + label = "LS-SPI0";
> >
> > where does the label property come from and what does it do?
> > It's not part of the rockchip-spi / general-spi binding.
> >
>
> It is not part of the binding but I thought it will provide the users
> the information of the SPI bus as per the specification when they
> look into devicetree.
>
> If it doesn't makes sense, I can remove that!
please do :-) ... dt-bindings are supposed to be verifyable at some
point, so we shouldn't add undocumented properties.
Heiko
>
> Thanks,
> Mani
>
> >
> > Heiko
> >
> > > + status = "okay";
> > > +};
> > > +
> > > +&spi4 {
> > > + /* On High speed expansion */
> > > + label = "HS-SPI1";
> > > + status = "okay";
> > > +};
> > > +
> > > &usbdrd_dwc3_0 {
> > > dr_mode = "otg";
> > > };
> > >
> >
> >
> >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
2019-05-07 11:22 ` Heiko Stuebner
@ 2019-05-07 11:36 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-07 11:36 UTC (permalink / raw)
To: Heiko Stuebner
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI1 exposed on both Low and High speed expansion connectors
> > of Ficus. SPI1 has 3 different chip selects wired as below:
> >
> > CS0 - Serial Flash (unpopulated)
> > CS1 - Low Speed expansion
> > CS2 - High Speed expansion
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > index 027d428917b8..9baa378fc770 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > @@ -146,6 +146,12 @@
> > };
> > };
> >
> > +&spi1 {
> > + /* On both Low speed and High speed expansion */
> > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
>
> cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> The flash is part of the schematics, so there might be board with
> it pre-populated or people might put a flash chip on it.
>
Why? CS0 is owned by the SPI controller itself, so we can't use it as
a GPIO. Otherwise, we need to change the pinctrl definition of it, which
doesn't look good to me.
> Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
>
Sure.
Thanks,
Mani
>
> Heiko
>
> > + status = "okay";
> > +};
> > +
> > &usbdrd_dwc3_0 {
> > dr_mode = "host";
> > };
> >
>
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
@ 2019-05-07 11:36 ` Manivannan Sadhasivam
0 siblings, 0 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2019-05-07 11:36 UTC (permalink / raw)
To: Heiko Stuebner
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI1 exposed on both Low and High speed expansion connectors
> > of Ficus. SPI1 has 3 different chip selects wired as below:
> >
> > CS0 - Serial Flash (unpopulated)
> > CS1 - Low Speed expansion
> > CS2 - High Speed expansion
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > index 027d428917b8..9baa378fc770 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > @@ -146,6 +146,12 @@
> > };
> > };
> >
> > +&spi1 {
> > + /* On both Low speed and High speed expansion */
> > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
>
> cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> The flash is part of the schematics, so there might be board with
> it pre-populated or people might put a flash chip on it.
>
Why? CS0 is owned by the SPI controller itself, so we can't use it as
a GPIO. Otherwise, we need to change the pinctrl definition of it, which
doesn't look good to me.
> Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
>
Sure.
Thanks,
Mani
>
> Heiko
>
> > + status = "okay";
> > +};
> > +
> > &usbdrd_dwc3_0 {
> > dr_mode = "host";
> > };
> >
>
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
2019-05-07 11:36 ` Manivannan Sadhasivam
@ 2019-05-07 11:59 ` Heiko Stuebner
-1 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:59 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-arm-kernel, linux-rockchip, linux-kernel, ezequiel, tom, dev
Am Dienstag, 7. Mai 2019, 13:36:35 CEST schrieb Manivannan Sadhasivam:
> On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI1 exposed on both Low and High speed expansion connectors
> > > of Ficus. SPI1 has 3 different chip selects wired as below:
> > >
> > > CS0 - Serial Flash (unpopulated)
> > > CS1 - Low Speed expansion
> > > CS2 - High Speed expansion
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > index 027d428917b8..9baa378fc770 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > @@ -146,6 +146,12 @@
> > > };
> > > };
> > >
> > > +&spi1 {
> > > + /* On both Low speed and High speed expansion */
> > > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
> >
> > cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> > The flash is part of the schematics, so there might be board with
> > it pre-populated or people might put a flash chip on it.
> >
>
> Why? CS0 is owned by the SPI controller itself, so we can't use it as
> a GPIO. Otherwise, we need to change the pinctrl definition of it, which
> doesn't look good to me.
Ok, but are you sure mixing both pinctrl-based chip-select with gpio-based
chip-select will actually work when the spi-flash is populated?
But it looks like you're right in that spi_set_cs() checks for a gpio-cs
first and falls back to the controller-based chip-select.
So I guess this can stay as it is.
>
> > Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
> >
>
> Sure.
Thanks
Heiko
>
> Thanks,
> Mani
>
> >
> > Heiko
> >
> > > + status = "okay";
> > > +};
> > > +
> > > &usbdrd_dwc3_0 {
> > > dr_mode = "host";
> > > };
> > >
> >
> >
> >
> >
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus
@ 2019-05-07 11:59 ` Heiko Stuebner
0 siblings, 0 replies; 16+ messages in thread
From: Heiko Stuebner @ 2019-05-07 11:59 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: tom, linux-kernel, dev, linux-rockchip, ezequiel, linux-arm-kernel
Am Dienstag, 7. Mai 2019, 13:36:35 CEST schrieb Manivannan Sadhasivam:
> On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI1 exposed on both Low and High speed expansion connectors
> > > of Ficus. SPI1 has 3 different chip selects wired as below:
> > >
> > > CS0 - Serial Flash (unpopulated)
> > > CS1 - Low Speed expansion
> > > CS2 - High Speed expansion
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > index 027d428917b8..9baa378fc770 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > @@ -146,6 +146,12 @@
> > > };
> > > };
> > >
> > > +&spi1 {
> > > + /* On both Low speed and High speed expansion */
> > > + cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
> >
> > cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> > The flash is part of the schematics, so there might be board with
> > it pre-populated or people might put a flash chip on it.
> >
>
> Why? CS0 is owned by the SPI controller itself, so we can't use it as
> a GPIO. Otherwise, we need to change the pinctrl definition of it, which
> doesn't look good to me.
Ok, but are you sure mixing both pinctrl-based chip-select with gpio-based
chip-select will actually work when the spi-flash is populated?
But it looks like you're right in that spi_set_cs() checks for a gpio-cs
first and falls back to the controller-based chip-select.
So I guess this can stay as it is.
>
> > Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
> >
>
> Sure.
Thanks
Heiko
>
> Thanks,
> Mani
>
> >
> > Heiko
> >
> > > + status = "okay";
> > > +};
> > > +
> > > &usbdrd_dwc3_0 {
> > > dr_mode = "host";
> > > };
> > >
> >
> >
> >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-05-07 11:59 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-06 12:04 [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 Manivannan Sadhasivam
2019-05-06 12:04 ` Manivannan Sadhasivam
2019-05-06 12:04 ` [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus Manivannan Sadhasivam
2019-05-06 12:04 ` Manivannan Sadhasivam
2019-05-07 11:22 ` Heiko Stuebner
2019-05-07 11:22 ` Heiko Stuebner
2019-05-07 11:36 ` Manivannan Sadhasivam
2019-05-07 11:36 ` Manivannan Sadhasivam
2019-05-07 11:59 ` Heiko Stuebner
2019-05-07 11:59 ` Heiko Stuebner
2019-05-07 11:17 ` [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 Heiko Stuebner
2019-05-07 11:17 ` Heiko Stuebner
2019-05-07 11:33 ` Manivannan Sadhasivam
2019-05-07 11:33 ` Manivannan Sadhasivam
2019-05-07 11:34 ` Heiko Stuebner
2019-05-07 11:34 ` Heiko Stuebner
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